CN108091654B - 用于垂直fet sram及逻辑单元微缩的金属层布线层级 - Google Patents

用于垂直fet sram及逻辑单元微缩的金属层布线层级 Download PDF

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CN108091654B
CN108091654B CN201711182012.0A CN201711182012A CN108091654B CN 108091654 B CN108091654 B CN 108091654B CN 201711182012 A CN201711182012 A CN 201711182012A CN 108091654 B CN108091654 B CN 108091654B
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layer
forming
fin
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metal wiring
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CN108091654A (zh
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S·本利
B·C·保罗
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GlobalFoundries US Inc
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Abstract

本发明涉及用于垂直FET SRAM及逻辑单元微缩的金属层布线层级，提供形成具有与一个晶体管对的栅极以及另一个晶体管对的底部S/D连接的鳍片下层级金属布线层的VFET SRAM或逻辑装置的方法以及所得装置。实施例包括形成于衬底上的鳍片对；围绕该鳍片在该衬底上图案化的底部S/D层；形成于该衬底上方的共形衬里层；形成于衬里层上方的ILD；金属布线层，形成于该些鳍片对之间、该第一对之间的该衬里层上以及至少该第二对之间的该底部S/D层上，上表面形成于该主动鳍片部下方；围绕该第一对的各鳍片形成于介电间隙壁上的GAA；以及分别邻近该GAA或穿过该GAA形成于该金属布线层上的底部S/D接触xc(交叉耦接)或专门xc。

Description

用于垂直FET SRAM及逻辑单元微缩的金属层布线层级
技术领域
本发明涉及形成静态随机访问存储器(static random-access memory；SRAM)阵列。本发明尤其适用于垂直场效应晶体管(vertical field-effect transistor；VFET)。
背景技术
单元微缩对于不断改进互补金属氧化物半导体(complementary metal-oxide-semiconductor；CMOS)技术至关重要。尽管历史上，经典的晶体管微缩已通过接触栅极(多晶)间距(contacted gate pitch；CPP)及金属层(MX)间距缩小提供了关键驱动力，但在激烈微缩的几何上，基本的布局限制开始从根本上限制单元微缩。此类微缩对于SRAM尤其具有挑战性，即使实施新的装置几何。尤其，环绕栅极(gate-all-around；GAA)架构保证进一步的CPP微缩；但是，通过使用传统的构造，SRAM微缩受基本规则要求阻碍。该GAA架构的一种特定实施是VFET，其中，电流流过垂直取向的沟道；由于这是基本装置的极大变化，因此针对标准单元设计也需要新的布局概念。图1中显示一种已知的VFET SRAM设计。请参照图1(顶视图)，该已知设计包括n型主动(nRX)区101(底部源/漏(S/D)区)及p型主动(pRX)区103。该VFET SRAM还包括下拉(pulldown；PD)晶体管109(与源极供应电压(VSS)连接)、上拉(pullup；PU)晶体管111(与漏极供应电压(VDD)连接)，以及通栅(pass gate；PG)晶体管113。该PD、PU及PG晶体管109、111及113分别包括鳍片115、S/D接触区(CA)117、栅极(PC)119、栅极接触(CB)121，以及底部S/D接触(TS)123。此外，PG栅极113的S/D接触区117与位线(BL)连接，且栅极接触121与字线(WL)连接。不过，此已知SRAM架构因各种接触及隔离要求而无法显着微缩该位单元区域。图2中显示包括邻接主动(RX)结构的另一种已知VFET SRAM设计，其消除pRX-pRX间隔并将两个PU晶体管对齐。请参照图2，该邻接VFET SRAM设计包括nRX区201及pRX区203。与图1的VFET SRAM类似，图2的VFET SRAM也包括PD晶体管205(与VSS连接)、PU晶体管207(与VDD连接)，以及PG晶体管209。PD、PU及PG晶体管205、207、209分别包括鳍片211、与S/D接触区213连接的顶部接触(出于说明方便未显示)、栅极215、栅极接触217，以及与底部nRX区201及pRX区203连接的交叉耦接(cross-couple；xc)接触219，在此情况下使用与栅极215绑定的底部S/D接触金属。不过，以此方式绘制的底部S/D xc接触要求(通过使用该底部S/D接触以将栅极215金属与底部nRX区201及pRX区203绑定)受接触-栅极基本规则间距要求限制，其显着增加n-p间隔，从而限制总体微缩。
因此，需要能够形成互连以实施能够微缩位单元区域而不增加n-p间隔的xc连接的方法以及所得装置。
发明内容
本发明的一个态样是一种具有与一个晶体管对的栅极以及另一个晶体管对的底部S/D区连接的鳍片下层级金属布线层的VFET SRAM或逻辑单元布局。
本发明的另一个态样是一种形成VFET SRAM或逻辑单元装置的与一个晶体管对的栅极以及另一个晶体管对的底部S/D区连接的鳍片下层级金属布线层的方法。
本发明的额外态样以及其它特征将在下面的说明中阐述，且本领域的普通技术人员在检查下文以后将在某种程度上清楚该些额外态样以及其它特征，或者该些额外态样以及其它特征可自本发明的实施中获知。本发明的优点可如所附权利要求中所特别指出的那样来实现和获得。
依据本发明，一些技术效果可通过一种装置在某种程度上实现，该装置包括：形成于衬底上的第一及第二对鳍片，各鳍片具有主动顶部及非主动底部，每对中的鳍片沿第一方向横向隔开，且该些对沿垂直于该第一方向的第二方向彼此横向隔开；底部S/D层，围绕该鳍片在该衬底上图案化；共形第一及第二衬里层，顺序形成于该衬底上方；第一层间介电质(interlayer dielectric；ILD)，形成于该共形第二衬里层上方；金属布线层，沿该第二方向形成于该些鳍片对之间、该第一对之间的该共形第二衬里层上以及至少该第二对之间的该底部S/D层上，上表面形成于该主动顶部下方；第一介电间隙壁，形成于该第一ILD上方；GAA，围绕该第一对的各鳍片形成于该第一介电间隙壁上；第二介电间隙壁，形成于该GAA及第一介电间隙壁上方；底部S/D接触xc或专门xc，分别邻近该GAA或穿过该GAA形成于该金属布线层上；以及第二ILD，形成于该衬底上方。
该装置的态样包括该第一对的该鳍片分别形成PD及第一PU晶体管的部分，且该第二对的该鳍片分别形成PG及第二PU晶体管的部分。其它态样包括形成于该金属布线层与该第一介电层之间的衬里及氧化物层。另外的态样包括该GAA经形成而有部分重叠该金属布线层的部分。另一个态样包括形成于各鳍片上的顶部S/D接触。
本发明的另一个态样是一种方法，其包括：在衬底上形成第一及第二对鳍片，各鳍片具有主动沟道部及包括部分凹入区的非主动底部，每对中的鳍片沿第一方向横向隔开，且该些对沿垂直于该第一方向的第二方向横向隔开；围绕该鳍片在该衬底上图案化底部S/D层；在该衬底上方顺序形成共形第一及第二衬里层；与该共形第二衬里层共面在该衬底上方形成第一ILD；沿该第二方向在每对之间及在该些对之间的该ILD中形成沟槽；沿该沟槽形成金属布线层，上表面形成于该主动顶部下方；在该金属布线层上方形成氧化物层，上表面位于该主动顶部的下表面下方；在该衬底上方形成第一介电间隙壁；围绕各该第一对鳍片在该第一介电间隙壁上形成GAA；在该GAA及第一介电间隙壁上方形成第二介电间隙壁；以及在该衬底上方形成第二ILD层。
本发明的态样包括通过以下方式形成该第一及第二对鳍片：在该衬底上方形成硬掩膜；蚀刻该硬掩膜及衬底，以显露该主动顶部；在该硬掩膜及主动顶部的侧壁上形成双层侧间隙壁；凹入该衬底40纳米(nm)至100纳米，以显露该非主动底部；横向凹入该非主动底部的部分；以及在该鳍片的该非主动部分中形成底部S/D层之后剥离该双层侧间隙壁。其它态样包括沿该非主动底部的侧壁形成该底部S/D层。另外的态样包括通过以下方式形成该第一及第二对鳍片及该底部S/D层：在该衬底上方形成该底部S/D层；在该底部S/D层上方形成主动鳍片层；在该主动鳍片层上方形成硬掩膜；图案化该硬掩膜；在该图案化硬掩膜的各侧上向下蚀刻该主动鳍片层至该底部S/D层，以显露该主动顶部；以及围绕该主动鳍片层凹入该底部S/D层，以显露该非主动底部。额外的态样包括通过以下方式形成该沟槽：向下蚀刻该第一ILD至该第一对鳍片的鳍片之间的该共形第二衬里层；以及向下蚀刻该第一ILD及共形第一及第二衬里层至至少位于该第二对鳍片的鳍片之间的该底部S/D层。另一个态样在形成该氧化物层之前包括：凹入该金属布线层直至该上表面位于该主动顶部下方；在该沟槽的侧壁上及该金属布线层上形成共形第三衬里层；用氧化物填充该沟槽；向下凹入该氧化物、ILD及共形第三衬里层至该非主动底部的该上表面；以及自该主动顶部剥离该共形第一及第二衬里层。其它态样包括：邻近该GAA向下穿过该第二ILD、第二介电间隙壁、第一介电间隙壁、氧化物层及SiN衬里至该金属布线层形成沟槽；以及在该沟槽中形成沟槽硅化物，该沟槽硅化物连接该金属布线层与GAA。另外的态样包括形成部分重叠该金属布线层的该GAA。额外的态样包括：在该沟槽的侧壁上及该金属布线层上形成共形第三衬里层；用氧化物填充该沟槽；向下凹入该氧化物、ILD及共形第三衬里层至该非主动底部的该上表面；以及在形成该氧化物层之前，自该主动顶部剥离该共形氧化物及SiN层；以及向下穿过该第二ILD、第二介电层、GAA、第一介电间隙壁、氧化物层及该共形第三衬里层至该金属布线层形成开口；用金属层填充该开口；向下凹入该金属层至该GAA的上表面；在该第二介电层的该开口中的该GAA上形成第三介电间隙壁层；以及与该第二ILD共面在该开口中形成第二氧化物层。
本发明的另一个态样是一种方法，其包括：在衬底上方形成S/D层；在该S/D层上方形成覆被介电层；在该覆被介电层上方形成金属布线层；图案化该金属布线层；在该S/D及金属布线层上方形成替代金属栅极(replacement metal gate；RMG)堆叠；向下穿过该RMG堆叠至该S/D层形成替代鳍片沟槽；在该替代鳍片沟槽中形成替代鳍片堆叠；在该替代鳍片上方形成比该替代鳍片宽的SiN覆盖层；在该SiN覆盖层的各侧上移除该RMG堆叠的部分；以及在该RMG堆叠的剩余部分上并围绕该替代鳍片形成GAA。
本发明的态样包括通过以下方式形成该RMG堆叠：在该S/D及金属布线层上方形成第一硅硼碳氮化物(SiBCN)、碳氧化硅(SiOC)、碳氮氧化硅(SiOCN)，或碳化硅(SiC)层；在该第一SiBCN、SiOC、SiOCN或SiC层上方形成第一氧化物层；在该第一氧化物层上方形成第二SiBCN、SiOC、SiOCN或SiC层；以及在该第二SiBCN、SiOC、SiOCN或SiC层上方形成第二氧化物层。其它态样包括通过以下方式移除该RMG堆叠的该部分：在该SiN覆盖层的各侧上向下蚀刻该RMG堆叠至该第一SiBCN、SiOC、SiOCN或SiC层且该第二SiBCN、SiOC、SiOCN或SiC层的部分保留于该SiN覆盖层下方。另外的态样包括通过以下方式形成该RMG堆叠：在该S/D及金属布线层上方形成第一SiN层；向下平坦化该第一SiN层至该金属布线层；在该第一SiN层上方形成第二SiN层；在该第二SiN层上方形成氧化物层；以及在该氧化物层上方形成第三SiN层。额外的态样包括通过以下方式移除该RMG堆叠的该部分：在该SiN覆盖层的各侧上向下蚀刻该RMG堆叠至该第二SiN层，该第三SiN层的部分保留于该SiN覆盖层下方。另一个态样包括通过以下方式形成该替代鳍片堆叠：在该替代鳍片沟槽中的该S/D层上形成第二S/D层；在该第二S/D层上形成主动鳍片层；以及在该主动鳍片层上形成第三S/D层。
本领域的技术人员从下面的详细说明中将很容易了解本发明的额外的态样以及技术效果，在该详细说明中，通过示例拟执行本发明的最佳模式来简单说明本发明的实施例。本领域的技术人员将意识到，本发明支持其它及不同的实施例，且其数个细节支持在各种显而易见的方面的修改，所有这些都不背离本发明。相应地，附图及说明将被视为示例性质而非限制。
附图说明
附图中的图形示例显示(而非限制)本发明，附图中类似的附图标记表示类似的元件，且其中：
图1示意显示垂直装置的背景SRAM设计；
图2示意显示包括底部n/p/S/D交叉耦接设计的垂直装置的背景SRAM设计；
图3至9、10A至15A、16、17、18A至22A示意显示依据一个示例实施例基于减成鳍片后期底部S/D制程形成VFET SRAM或逻辑单元装置的鳍片下金属布线层的流程的剖视图；
图10B至15B及18B至22B分别示意显示图10A至15A及18A至22A的顶视图；
图23至25示意显示依据示例实施例基于减成鳍片早期S/D制程形成VFET SRAM或逻辑单元装置的鳍片下金属布线层的部分流程的剖视图；
图26A至29A示意显示依据另一个示例实施例基于减成鳍片后期底部S/D制程形成能够增加CPP微缩的VFET SRAM或逻辑单元装置的鳍片下金属布线层的流程；
图26B至29B分别示意显示图26A至29A的顶视图；以及
图30至36示意显示依据另一个示例实施例基于后沟道替代鳍片早期底部S/D制程形成VFET SRAM或逻辑单元装置的鳍片下金属布线层的流程的剖视图。
具体实施方式
在下面的说明中，出于解释目的，阐述许多具体细节来提供有关示例实施例的充分理解。不过，应当很清楚，可在不具有这些具体细节或者具有等同布置的情况下实施该些示例实施例。在其它情况下，以方块图形式显示已知的结构及装置，以避免不必要地模糊示例实施例。此外，除非另外指出，否则说明书及权利要求中所使用的表示组分的量、比例及数值属性，反应条件等的所有数字将被理解为通过术语“大约”在所有情况下被修饰。
本发明处理并解决当前SRAM微缩所伴随的满足基本规则要求的间隔约束及阻碍问题。
依据本发明的实施例的方法及所得装置包括形成于衬底上的第一及第二对鳍片，各鳍片具有主动顶部及非主动底部，每对中的鳍片沿第一方向横向隔开，且该些对沿垂直于该第一方向的第二方向彼此横向隔开。围绕该鳍片在该衬底上图案化底部S/D层并在该衬底上方顺序形成共形第一及第二衬里层。在该共形第二衬里层上方形成第一ILD，并沿该第二方向在该些鳍片对之间、该第一对之间的该共形第二衬里层上以及至少该第二对之间的该底部S/D层上形成金属布线层，上表面形成于该主动顶部下方。在该第一ILD上方形成第一介电间隙壁。围绕该第一对的各鳍片在该第一介电间隙壁上形成GAA并在该GAA及第一介电间隙壁上方形成第二介电间隙壁。分别邻近该GAA或穿过该GAA在该金属布线层上形成底部S/D接触xc或专门xc，并在该衬底上方形成第二ILD。
本领域的技术人员从下面的详细说明中将很容易了解其它态样、特征以及技术效果，在该详细说明中，简单地通过示例所考虑的最佳模式来显示并说明优选实施例。本发明支持其它及不同的实施例，且其数个细节支持在各种显而易见的方面的修改。相应地，附图及说明将被视为示例性质而非限制。
图3至9、10A至15A、10B至15B、16、17、18A至22A以及18B至22B示意显示依据一个示例实施例基于减成鳍片后期底部S/D制程形成VFET SRAM或逻辑单元装置的鳍片下金属布线层的流程。图10B至15B及18B至22B为顶视图，且图10A至15A及18A至22A分别为沿线A-A’的剖视图。图10B至15B及18B至22B是出于说明目的进行初步显示，而非完整的顶视图。请参照图3，在衬底303上方形成例如由SiN构成的硬掩膜301。接着，蚀刻硬掩膜301及衬底303，以显露一对鳍片305及307的主动顶部。此外，同时并以后续步骤中所述的相同方式形成第二对鳍片309及311(出于说明方便未显示)，除了该第二对鳍片与鳍片305及307横向隔开形成以外，如图10B中所示。在硬掩膜301及鳍片305及307的主动顶部的侧壁上形成例如由氧化物层403及SiN层405构成的双层侧间隙壁401，如图4中所示。接着，凹入衬底303例如40纳米至100纳米，以显露鳍片305及307的非主动底部，接着横向凹入鳍片305及307的该非主动底部，例如保留1纳米至20纳米的宽度，如图5中所示。
请参照图6，在衬底303上方并沿鳍片305及307的该非主动底部的侧壁，通过外延生长或经由另一种掺杂技术形成底部S/D层601例如至10纳米至70纳米的厚度。底部S/D层601的厚度小于图5中所述的凹入深度。如果衬底303由硅(Si)或硅锗(SiGe)形成，则底部S/D层601可例如由磷(P)掺杂硅(Si:P)、碳(C)及P掺杂硅(Si:CP)、硼(B)掺杂硅(Si:B)、硼掺杂SiGe(SiGe:B)、砷(As)掺杂硅(Si:As)形成，或者衬底303及底部S/D层601可由任意其它半导体材料形成。接着，执行退火制程以热扩散该掺杂物，从而提供某些结重叠控制，并剥离双层侧间隙壁401，如图7中所示。一种可能性是在此阶段包括早期硅化物；不过，该硅化物将需要能够承受前端工艺(front end of line；FEOL)热预算。请参照图8，在衬底303上方共形形成氧化物衬里层801及SiN衬里层803例如分别至0.5纳米至4纳米及2纳米至10纳米的厚度。应当注意，作为替代，衬里层801及803可由具有与氧化物及SiN类似的相应属性的不同材料共形形成于衬底303上方。
接着，在衬底303上方沉积层间介电质ILD 901并例如通过化学机械抛光(chemical mechanical polishing；CMP)将其向下平坦化至SiN衬里层803，如图9中所示。作为替代，如需要的话，还可通过多步骤氧化物沉积/凹入/SiN沉积制程添加额外的蚀刻停止层(出于说明方便未显示)。请参照图10A及10B，在鳍片305及307与鳍片309及311之间的ILD 901中向下至SiN衬里层803，例如通过非等向性反应离子蚀刻(reactive ionetching；RIE)形成沟槽1001。沟槽1001的宽度仅通过鳍片-鳍片间隔设置，而没有任何其它约束。请参照图11A及11B，例如通过RIE移除位于鳍片309与311之间的氧化物衬里层801及SiN衬里层803的部分，以向下延伸沟槽1001至底部S/D层601，从而形成底部S/D接触区。作为替代，该底部S/D接触区可进一步延伸，而不只是在鳍片309与311之间。
请参照图12A(鳍片305与307之间的剖视图)及13A(鳍片309与311之间的剖视图)，沿沟槽1001形成金属布线层1201。在鳍片309与311之间，可选地，可使用例如由钛(Ti)或镍(Ni)形成的接触层(出于说明方便未显示)来形成硅化物(如需要的话)，结合可选的退火及剥离步骤，随后形成多层堆叠例如氮化钛(TiN)及钨(W)或TiN及铝(Al)。在非接触区，例如在鳍片305与307之间，硅化物被氧化物衬里层801阻挡。接着，凹入金属布线层1201直至上表面位于鳍片305至311的该主动部分下方，从而形成金属布线层1201’，如图14A中所示。依据鳍片305至311的尺寸，金属布线层1201’的剩余厚度可为例如10纳米至100纳米。
接着，在沟槽1001的侧壁上以及在凹入的金属布线层1201’上形成共形SiN衬里1501例如至2纳米至10纳米的厚度，如图15A中所示。接着，用氧化物层1503填充沟槽1001，然后例如通过CMP向下平坦化氧化物层1503至SiN层803。请参照图16，向下凹入氧化物层1503、ILD 901及SiN衬里1501至鳍片305至311的该非主动底部的上表面，以形成氧化物层1503’、ILD 901’，以及SiN衬里1501’。接着，自鳍片305至311的该主动顶部剥离SiN衬里层803及氧化物衬里层801，以形成SiN衬里层803’及氧化物衬里层801’。接着，例如由SiN、氧化物，或低k膜例如SiBCN/SiOCN/SiOC形成介电层1701至2纳米至15纳米的厚度，如图17中所示。
请参照图18A(沿图18B的x轴的剖视图)及19A(沿图19B的y轴的剖视图)，围绕各鳍片305及307在介电层1701上形成GAA 1801。根据需要，GAA 1801的部分可重叠金属布线层1201’。然后，在介电层1701及GAA 1801上方形成与介电层1701类似的介电层1803。接着，在该衬底上方形成ILD 1805，然后通过CMP将其向下平坦化至硬掩膜301。随后，邻近GAA 1801向下穿过ILD 1805、介电层1803、介电层1701、氧化物层1503’及SiN衬里1501’至金属布线层1201’形成底部接触沟槽1807。底部接触沟槽1807横向偏移，以使其重叠GAA 1801与金属布线层1201’两者，从而确保接触。
接着，在沟槽1807中形成沟槽硅化物2001，以连接金属布线层1201’与GAA1801，如图20A(横穿图20B的沟槽硅化物2001的剖视图)、图21A(沿图21B的鳍片309及311的剖视图)及图22A(沿图22B的y轴的剖视图)中所示。随后，该流程遵循传统的中间工艺(middle ofthe line；MOL)形成步骤，例如移除硬掩膜301并形成上方S/D层2003、S/D接触2005及ILD2007。因此，图21B中的圆圈2101内的区域可相对图1及2的已知VFET SRAM设计收缩，因为底部S/D层601可与金属布线层1201’连接而不分别干涉鳍片309及311的栅极2103及2105。
图23至25(剖视图)示意显示依据一个示例实施例基于减成鳍片早期S/D制程形成VFET SRAM或逻辑单元装置的鳍片下金属布线层的部分流程。请参照图23，以与图6的底部S/D层601类似的方式在衬底2303上方形成掺杂底部S/D层2301。接着，在底部S/D层2301上方形成例如由Si构成的主动鳍片层2305，并在主动鳍片层2305上方形成硬掩膜2307。接着，图案化硬掩膜2307并在图案化硬掩膜2307的各侧上向下蚀刻主动鳍片层2305至底部S/D层2301，以显露鳍片2309及2311的主动顶部。随后，围绕鳍片2309及2311的该主动顶部凹入底部S/D层2301，以显露鳍片2309及2311的非主动底部。如图3中所述，还同时并以相同的方式形成第二对鳍片2313及2315(出于说明方便未显示)，除了第二对鳍片2313及2315与鳍片2309及2311横向隔开形成以外，如图10B中所示。
请参照图24，在衬底2303上方共形形成氧化物衬里层2401及SiN衬里层2403例如分别至0.5纳米至4纳米以及2纳米至10纳米的厚度。接着，在该衬底上方沉积ILD 2405并例如通过CMP将其向下平坦化至SiN衬里层2403。如图12中所述，在鳍片2309与2311之间的SiN衬里层2403上以及至少在鳍片2313与2315之间的底部S/D层2301上形成金属布线层2501，如图25中所示。沿IDL 2405的侧壁以及在金属布线层2501上形成SiN衬里2503。随后，在SiN层2503上方形成氧化物层2505并例如通过CMP将其向下平坦化至SiN衬里层2403。接着，如图16、17、18A至22A以及18B至22B中所详细叙述的那样继续该流程。再次，应当注意，作为替代，衬里层2401及2403可由具有与氧化物及SiN类似的相应属性的不同材料共形形成于衬底2303上方。
图26A至29A以及26B至29B示意显示依据另一个示例实施例基于减成鳍片后期底部S/D制程形成能够增加CPP微缩的VFET SRAM或逻辑单元装置的鳍片下金属布线层的流程。图26B至29B为顶视图，且图26A至29A分别为沿线A-A’的剖视图。图26B至29B是出于说明目的进行初步显示，而非完整的顶视图。请参照图26A(沿图26B的x轴的剖视图)及图27A(沿图27B的y轴的剖视图)，在图26A及26B以及27A及27B之前的流程与图3至9、10A至15A、10B至15B、16及17中所述基本相同。不过，不是邻近GAA 1801形成底部S/D接触沟槽1807，而是利用独特的图案化步骤向下穿过ILD 1805、介电层1803、GAA 1801、介电层1701、氧化物层1503’及SiN衬里1501’至金属布线层1201’形成专门开口2601，从而能够例如利用单独的光刻曝光后续形成专门xc层。
请参照图28A及28B，用金属层2801例如W、Al等填充开口2601。接着，向下凹入金属层2801至GAA 1801的上表面，以形成专门xc层2801’，如图29A中所示。专门xc层2801’将鳍片309与311之间的底部S/D层601与鳍片305与307之间的GAA 1801连接。随后，在专门xc层2801’上方形成介电层2901，且该流程再次遵循传统的MOL形成步骤，例如移除硬掩膜301并形成上方S/D层2903、S/D接触2905以及ILD 2907。沿鳍片309与311之间的x轴的剖视图与图21A中的沿x轴的剖视图相同。因此，与当前的沟槽硅化物层2001不同，专门xc层2801’支持最大限度的CPP微缩。
图30至36(剖视图)示意显示依据另一个示例实施例基于后沟道替代鳍片早期底部S/D制程形成VFET SRAM或逻辑单元装置的鳍片下金属布线层的流程。请参照图30，在衬底3003上方形成n+/P+掺杂底部S/D层3001例如至5纳米至50纳米的厚度。接着，在底部S/D层3001上方形成覆被介电层(出于说明方便未显示)。以与向下移除氧化物衬里层801及SiN衬里层803至底部S/D层601从而在图11A及11B中形成底部S/D接触区相同的方式，在所设计的接触区域中蚀刻介电层。随后，在非接触区中的该介电层及该接触区中的底部S/D层3001上方形成金属层(出于说明方便未显示)并接着对其图案化以形成金属布线层3101，如图31中所示。金属布线层3101可由与金属布线层1201’相同的金属形成，且可被图案化例如至3纳米至50纳米的宽度，取决于想要的电路设计。
接着，在金属布线层3101及该介电层上方形成FEOL ILD RMG堆叠3103。RMG堆叠3103包括SiBCN层3105、氧化物层3107、SiBCN层3109，以及氧化物层3111。作为替代，SiBCN层3105可例如由SiOC、SiOCN、SiC或类似物形成。请参照图32，向下穿过RMG堆叠3103至底部S/D层3001形成替代鳍片沟槽3201及3203。接着，通过在替代鳍片沟槽3201及3203中的底部S/D层3001上形成可选的底部S/D层3305、在可选的底部S/D层3305上形成主动鳍片层3307以及在主动鳍片层3307上形成顶部S/D层3309来形成替代鳍片堆叠3301及3303，如图33中所示。可掺杂或不掺杂替代鳍片堆叠3301及3303。接着，在替代鳍片堆叠3301及3303上方形成SiN覆盖层3401，其具有比替代鳍片堆叠3301及3303宽的宽度，如图34中所示。
请参照图35，通过在SiN覆盖层3401的各侧上向下蚀刻RMG堆叠3103至SiBCN层3105来移除RMG堆叠3103的部分，SiBCN层3109的部分保留于SiN覆盖层3401下方。接着，围绕各替代鳍片堆叠3301及3303在SiBCN层3105上形成GAA 3601，如图36中所示。接着，邻近GAA 3601在金属布线层3101上形成沟槽硅化物(出于说明方便未显示)，从而连接金属布线层3101与GAA 3601，如图20A及图20B中所示，或者向下穿过GAA 3601至金属布线层3101形成专门xc层(出于说明方便未显示)，从而连接金属布线层3101与GAA 3601，如图29A及29B中所示。
作为替代，通过在顶部S/D层3301及金属布线层3401上方形成SiN层(出于说明方便未显示)可形成FEOL ILD RMG堆叠；向下平坦化该SiN层至金属布线层3401；在该第一SiN层上方形成第二SiN层(出于说明方便未显示)；在该第二SiN层上方形成氧化物层(出于说明方便未显示)；以及在该氧化物层上方形成第三SiN层(出于说明方便未显示)。随后，通过在该SiN覆盖层的各侧上向下蚀刻该RMG堆叠至该第二SiN层来移除该替代形成的RMG堆叠的部分，部分该第三SiN层保留于该SiN覆盖层下方。
本发明的实施例可实现数个技术效果，包括通过使用底部S/D接触互连来减少xc接触上的间隔约束，并通过使用专门xc层来促进增加CPP微缩。本发明的实施例适于各种工业应用，例如微处理器、智能电话、移动电话、蜂窝手机、机顶盒、DVD记录器及播放器、汽车导航、打印机及周边设备、网络及电信设备、游戏系统，以及数字相机。因此，本发明对于具有VFET或逻辑单元的任意IC装置具有工业适用性。
在前面的说明中，参照本发明的具体示例实施例来说明本发明。不过，显然，可对其作各种修改及变更，而不背离如权利要求中所阐述的本发明的较广泛的精神及范围。相应地，说明书及附图将被看作示例性质而非限制。应当理解，本发明能够使用各种其它组合及实施例，且支持在本文中所表示的发明性概念的范围内的任意修改或变更。

Claims (20)

1.一种半导体装置，包括：
形成于衬底上的第一及第二对鳍片，各鳍片具有主动顶部及非主动底部，每对中的鳍片沿第一方向横向隔开，且该第一及第二对沿垂直于该第一方向的第二方向彼此横向隔开；
底部源/漏(S/D)层，在该衬底上围绕该鳍片图案化；
共形第一及第二衬里层，顺序形成于该衬底上方；
第一层间介电质(ILD)，形成于该共形第二衬里层上方；
金属布线层，沿该第二方向形成于该第一及第二对鳍片之间、该第一对之间的该共形第二衬里层上以及至少该第二对之间的该底部源/漏层上，上表面形成于该主动顶部下方；
第一介电层，形成于该第一层间介电质上方；
环绕栅极(GAA)，围绕该第一对的各鳍片形成于该第一介电层上；
第二介电层，形成于该环绕栅极及第一介电层上方；
底部源/漏接触交叉耦接(xc)或专门交叉耦接，分别邻近该环绕栅极或穿过该环绕栅极形成于该金属布线层上；以及
第二层间介电质，形成于该衬底上方。
2.如权利要求1所述的半导体装置，其中，该第一对的该鳍片分别形成下拉(PD)及第一上拉(PU)晶体管的部分，且该第二对的该鳍片分别形成通栅(PG)及第二上拉晶体管的部分。
3.如权利要求1所述的半导体装置，还包括位于该金属布线层与该第一介电层之间的衬里及氧化物层。
4.如权利要求1所述的半导体装置，其中，该环绕栅极经形成而有部分重叠该金属布线层的部分。
5.如权利要求1所述的半导体装置，还包括位于各鳍片上的顶部源/漏接触。
6.一种形成半导体装置的方法，该方法包括：
在衬底上形成第一及第二对鳍片，各鳍片具有主动顶部及包括部分凹入区的非主动底部，每对中的鳍片沿第一方向横向隔开，且该第一及第二对沿垂直于该第一方向的第二方向横向隔开；
在该衬底上围绕该鳍片图案化底部源/漏(S/D)层；
在该衬底上方顺序形成共形第一及第二衬里层；
与该共形第二衬里层共面在该衬底上方形成第一层间介电质(ILD)；
沿该第二方向在每对之间及在该第一及第二对之间的该层间介电质中形成沟槽；
沿该沟槽形成金属布线层，上表面形成于该主动顶 部下方；
在该金属布线层上方形成氧化物层，上表面位于该主动顶部的下表面下方；
在该衬底上方形成第一介电层；
围绕各该第一对鳍片在该第一介电层上形成环绕栅极(GAA)；
在该环绕栅极及第一介电层上方形成第二介电层；以及
在该衬底上方形成第二层间介电质。
7.如权利要求6所述的方法，包括通过以下方式形成该第一及第二对鳍片：
在该衬底上方形成硬掩膜；
蚀刻该硬掩膜及衬底，以显露该主动顶部；
在该硬掩膜及主动顶部的侧壁上形成双层侧间隙壁；
凹入该衬底40纳米(nm)至100纳米，以显露该非主动底部；
横向凹入该非主动底部的部分；以及
在该鳍片的该非主动部分中形成该底部源/漏层之后剥离该双层侧间隙壁。
8.如权利要求6所述的方法，包括沿该非主动底部的侧壁形成该底部源/漏层。
9.如权利要求6所述的方法，包括通过以下方式形成该第一及第二对鳍片及该底部源/漏层：
在该衬底上方形成该底部源/漏层；
在该底部源/漏层上方形成主动鳍片层；
在该主动鳍片层上方形成硬掩膜；
图案化该硬掩膜；
在该图案化硬掩膜的各侧上向下蚀刻该主动鳍片层至该底部源/漏层，以显露该主动顶部；以及
围绕该主动鳍片层凹入该底部源/漏层，以显露该非主动底部。
10.如权利要求6所述的方法，包括通过以下方式形成该沟槽：
向下蚀刻该第一层间介电质至该第一对鳍片的鳍片之间的该共形第二衬里层；以及
向下蚀刻该第一层间介电质及共形第一及第二衬里层至至少位于该第二对鳍片的鳍片之间的该底部源/漏层。
11.如权利要求6所述的方法，在形成该氧化物层之前还包括：
凹入该金属布线层直至该上表面位于该主动顶 部下方；
在该沟槽的侧壁上及该金属布线层上形成共形第三衬里层；
用氧化物填充该沟槽；
向下凹入该氧化物、该第一层间介电质及共形第三衬里层至该非主动底部的该上表面；以及
自该主动顶部剥离该共形第一及第二衬里层。
12.如权利要求11所述的方法，还包括：
邻近该环绕栅极向下穿过该第二层间介电质、该第二介电层、该第一介电层、该氧化物层及该共形第三衬里层至该金属布线层形成沟槽；以及
在该沟槽中形成沟槽硅化物，该沟槽硅化物连接该金属布线层与环绕栅极。
13.如权利要求6所述的方法，包括形成部分重叠该金属布线层的该环绕栅极。
14.如权利要求13所述的方法，包括：
在该沟槽的侧壁上及该金属布线层上形成共形第三衬里层；
用氧化物填充该沟槽；
向下凹入该氧化物、该第一层间介电质及该共形第三衬里层至该非主动底部的该上表面；以及
在形成该氧化物层之前，自该主动顶部剥离该共形第一及第二衬里层；以及
向下穿过该第二层间介电质、该第二介电层、该环绕栅极、该第一介电层、该氧化物层及该共形第三衬里层至该金属布线层形成开口；
用金属层填充该开口；
向下凹入该金属层至该环绕栅极的上表面；
在该第二介电层的该开口中的该环绕栅极上形成第三介电间隙壁层；以及
与该第二层间介电质共面在该开口中形成第二氧化物层。
15.一种形成半导体装置的方法，该方法包括：
在衬底上方形成源/漏(S/D)层；
在该源/漏层上方形成覆被介电层；
在该覆被介电层上方形成金属布线层；
图案化该金属布线层；
在该源/漏及金属布线层上方形成替代金属栅极(RMG)堆叠；
向下穿过该替代金属栅极堆叠至该源/漏层形成替代鳍片沟槽；
在该替代鳍片沟槽中形成替代鳍片堆叠；
在该替代鳍片上方形成比该替代鳍片宽的氮化硅(SiN)覆盖层；
在该氮化硅覆盖层的各侧上移除该替代金属栅极堆叠的部分，该替代金属栅极堆叠的剩余部分保留于该氮化硅覆盖层的下方；以及
在该替代金属栅极堆叠的该剩余部分上并围绕该替代鳍片形成环绕栅极(GAA)。
16.如权利要求15所述的方法，包括通过以下方式形成该替代金属栅极堆叠：
在该源/漏及金属布线层上方形成第一硅硼碳氮化物(SiBCN)、碳氧化硅(SiOC)、碳氮氧化硅(SiOCN)，或碳化硅(SiC)层；
在该第一硅硼碳氮化物、碳氧化硅、碳氮氧化硅或碳化硅层上方形成第一氧化物层；
在该第一氧化物层上方形成第二硅硼碳氮化物、碳氧化硅、碳氮氧化硅或碳化硅层；以及
在该第二硅硼碳氮化物、碳氧化硅、碳氮氧化硅或碳化硅层上方形成第二氧化物层。
17.如权利要求16所述的方法，包括通过以下方式移除该替代金属栅极堆叠的该部分：
在该氮化硅覆盖层的各侧上向下蚀刻该替代金属栅极堆叠至该第一硅硼碳氮化物、碳氧化硅、碳氮氧化硅或碳化硅层，且该替代金属栅极堆叠的该剩余部分包括保留于该氮化硅覆盖层下方的该第二硅硼碳氮化物、碳氧化硅、碳氮氧化硅或碳化硅层。
18.如权利要求15所述的方法，包括通过以下方式形成该替代金属栅极堆叠：
在该源/漏及金属布线层上方形成第一氮化硅层；
向下平坦化该第一氮化硅层至该金属布线层；
在该第一氮化硅层上方形成第二氮化硅层；
在该第二氮化硅层上方形成氧化物层；以及
在该氧化物层上方形成第三氮化硅层。
19.如权利要求18所述的方法，包括通过以下方式移除该替代金属栅极堆叠的该部分：
在该氮化硅覆盖层的各侧上向下蚀刻该替代金属栅极堆叠至该第二氮化硅层，该第三氮化硅层的部分保留于该氮化硅覆盖层下方。
20.如权利要求15所述的方法，包括通过以下方式形成该替代鳍片堆叠：
在该替代鳍片沟槽中的该源/漏层上形成第二源/漏层；
在该第二源/漏层上形成主动五层；以及
在该主动鳍片层上形成第三源/漏层。
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