TWI653740B - 用於垂直ｆｅｔ ｓｒａｍ以及邏輯胞元縮放的金屬層佈線層級 - Google Patents

用於垂直ｆｅｔ ｓｒａｍ以及邏輯胞元縮放的金屬層佈線層級 Download PDF

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TWI653740B
TWI653740B TW106122578A TW106122578A TWI653740B TW I653740 B TWI653740 B TW I653740B TW 106122578 A TW106122578 A TW 106122578A TW 106122578 A TW106122578 A TW 106122578A TW I653740 B TWI653740 B TW I653740B
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layer
forming
metal wiring
fins
over
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TW106122578A
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TW201834204A (zh
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史蒂芬 賓利
必普Ｃ 保羅
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美商格羅方德美國公司
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Abstract

本發明揭示一種形成一VFET SRAM或邏輯裝置之方法，該裝置具有連接至一電晶體配對的一閘極以及另一電晶體配對的該底部S/D之副鰭片級金屬佈線層。具體實施例包括：鰭片配對，其形成於一基材上；一底部S/D層，其該基材上圍繞該等鰭片而形成圖案；順應襯墊層，其形成於該基材之上；一ILD，其形成於一襯墊層之上；一金屬佈線層，其形成於該第一配對之間該襯墊層上以及至少該第二配對之間該底部S/D層上該等鰭片配對之間，其中一上方表面形成於該活性鰭片部分之下；一GAA，其形成於該介電隔板上圍繞該第一配對的每一鰭片；以及一底部S/D接點xc或一專屬xc，其分別形成於與該GAA相鄰或穿透該GAA的該金屬佈線層上。

Description

用於垂直FET SRAM以及邏輯胞元縮放的金屬層佈線層級
本案係關於靜態隨機存取記憶體(SRAM，static random-access memory)陣列，本案尤其適用於垂直場效電晶體(VFET，vertical field-effect transistor)。
胞元縮放對於繼續改進互補金屬氧化物半導體(CMOS，complementary metal-oxide-semiconductor)技術至關重要。雖然經典的晶體管縮放歷來通過接觸柵極(poly)間距(CPP)和金屬層(MX)以顯著規模的縮放尺寸進行間距減小，而提供一個關鍵的驅動器，但基本佈局限制也開始從根本上限制胞元縮放。即使採用新裝置幾何尺寸，這種縮放對於SRAM也特別有挑戰性。尤其是，全包覆閘(GAA，gate-all-around)架構承諾進一步CPP縮放；然而在使用常規結構時，SRAM縮放受到接地規則要求的阻礙。GAA架構的一個具體實現為VFET，其中電流流過垂直定向的通道；由於這是基礎裝置的巨大變化，因此標準胞元設計也需要新的佈局概念。圖1內顯示一個已知的VFET SRAM設計。請注意圖1(俯視圖)，該已知設計包括n型活性(nRX)區域101(底部源極/汲極(S/D)區域)以及p型活性(pRX)區域103。該VFET SRAM也包括下拉(PD，pulldown)電晶體109(連接至一源極供應電壓(VSS，source supply voltage))、上拉(PU，pullup)電晶體111(連接至一汲極供應電壓(VDD，drain supply voltage))以及通道閘(PG，pass gate)電晶體113。該PD、PU和PG電晶體109、111和113分別包括鰭片115、S/D接觸區(CA)117、閘極(PC)119、閘極接點(CB)121以及底部S/D接點(TS)123。此外，PG閘極113的S/D接觸區117連接至位元線(BL，bit line)並且閘極接點121連接至字線(WL，word line)。然而，由於許多接觸與隔離要求，這已知的SRAM架構無法使得該位元胞元區之顯著縮放。包括一相鄰活性(RX)結構，免除pRX-pRX空間以及對準兩PU電晶體的另一個已知VFET SRAM設計則顯示在圖2內。請注意圖2，該相鄰VFET SRAM設計包括nRX區域201和pRX區域203。類似於圖1的VFET SRAM，圖2的VFET SRAM也包括PD電晶體205(連接至一VSS)、PU電晶體207(連接至一VDD)以及PG電晶體209。該PD、PU和PG電晶體205、207和209分別包括鰭片211、連接至S/D接觸區213的頂端接點(為了方面說明並未顯示)、閘極215、閘極接點217以及連接至底部nRX區域201和pRX區域203的交叉耦合(xc)接點219，在此案例中使用綁(strap)在閘極215上的底部S/D接點金屬。然而，以使用該底部S/D接點將閘極215綁到底部nRX區域201和pRX區域203這種方式繪製的該等底部S/D xc接點要求，受到接觸閘極接地規則間隔要求，這顯著增加了n-p空間，從而限制了總體縮放。
因此需要一種能夠形成互連以實施一xc連接的方法，該xc連接能夠縮放位元胞元區而不增加該n-p空間以及該結果裝置。
本案的態樣為一VFET SRAM或邏輯胞元佈局，其具有連接至一電晶體配對的一閘極以及另一電晶體配對的該底部S/D區域之副鰭片級金屬佈線層。
本案的另一個態樣為形成一副鰭片級金屬佈線層的方法，該層連接至一VFET SRAM或邏輯胞元裝置的一電晶體配對之一閘極以及另 一電晶體配對的該底部S/D區域。
在下列說明中將公佈本案的額外態樣與其他特徵，並且對於原本就精通此技術的人士而言，有些部分從下列試驗就可理解，或者熟習本案就可知道。本案的優點可在隨附申請專利範圍特別指出的情況下實現和獲得。
根據本案，某些技術效果可以部分由一裝置來實現，包括：鰭片的第一和第二配對，其形成於一基材上，其中每一鰭片都具有一活性頂端部分以及一非活性底端部分，每對鰭片在一第一方向內橫向分隔，並且該等配對在與該第一方向垂直的一第二方向內彼此橫向分隔；一底部S/D層，其繪製在該基材上圍繞該等鰭片；順應第一和第二襯墊層，其依序形成於該基材上；一第一層間介電質(ILD)，其形成於該順應第二襯墊層之上；一金屬佈線層，其形成於該第一配對之間該順應第二襯墊層上與至少該第二配對之間該底部S/D層上該等鰭片配對之間的該第二方向內，一上方表面形成於該活性頂端部分之下方；一第一介電隔板，其形成於該第一ILD之上；一GAA，其形成於該第一介電隔板上圍繞該第一配對的每一鰭片；一第二介電隔板，其形成於該GAA和該第一介電隔板上；一底部S/D接點xc或一專屬xc，其分別形成於與該GAA相鄰或穿透該GAA的該金屬佈線層上；以及一第二ILD，其形成於該基材上。
該裝置的態樣包括分別形成一PD和一第一PU電晶體的一部分的第一配對的鰭片，以及分別形成一PG和一第二PU電晶體的一部分的第二配對的鰭片。其他態樣包括一襯墊與氧化物層，其形成於該金屬佈線層與該第一介電層之間。進一步態樣包括形成該GAA有一部分與該金屬佈線層的一部分重疊。另一個態樣包括在每一鰭片上形成頂端S/D接點。
本發明的另一個態樣為一方法，其包括：在一基材上形成鰭片的第一和第二配對，其中每一鰭片都具有一活性通道部分以及包括一凹陷區部分的一非活性底端部分，每對鰭片在一第一方向內橫向分隔，並且 該等配對在與該第一方向垂直的一第二方向內橫向分隔；圍繞在該基材上該等鰭片形成一底部S/D層的圖案；依序在該基材上方形成順應第一和第二襯墊層；在該基材上方形成一第一ILD，其與該順應第二襯墊層共平面；在每一配對之間以及該第二方向內該等配對之間的該ILD內形成一溝渠；沿著該溝渠形成一金屬佈線層，一上方表面形成於該頂端活性部分下方；在該金屬佈線層之上方形成一氧化物層，一上方表面位於該活性頂端部分的一下表面之下方；在該基材上方形成一第一介電隔板；在該第一介電隔板上圍繞該第一配對鰭片每一者之處形成一GAA；在該GAA和該第一介電隔板上方形成一第二介電隔板；以及在該基材上方形成一第二ILD層。
本發明的態樣包括依照下列形成該等鰭片的第一和第二配對：在該基材上方形成一硬光罩；蝕刻該硬光罩與基材，露出該活性頂端部分；在該硬光罩與活性頂端部分的側壁上形成一雙層側壁隔板；將該基材凹陷40奈米(nm)至100nm，露出該非活性底端部分；橫向凹陷該非活性底端部分的一部分；以及在該鰭片的該非活性部分內形成一底部S/D層之後，將該雙層側壁隔板剝離。其他態樣包括沿著該非活性底端部分的側壁形成該底部S/D層。進一步態樣包括依照以下形成該等鰭片的第一和第二配對以及該底部S/D層：在該基材上方形成該底部S/D層；在該底部S/D層上方形成一活性鰭片層；在該活性鰭片層上形成一硬光罩；將該硬光罩形成圖案；在該已形成圖案的硬光罩之每一側上往下蝕刻該活性鰭片層至該底部S/D層，露出該活性頂端部分；以及凹陷該活性鰭片層四周的該底部S/D層，露出該非活性底端部分。額外態樣包括依照以下步驟形成該溝渠：往下蝕刻該第一ILD至該等第一配對鰭片之鰭片間之該順應第二襯墊層；以及往下蝕刻該第一ILD和順應第一和第二襯墊層到至少該等第二配對鰭片之鰭片間之該底部S/D層。另一個態樣包括在形成該氧化物層之前：凹陷該金屬佈線層，直到該上方表面低於該頂端活性部分；在該溝渠的側壁上與該金屬佈線層上形成一順應第三襯墊層；用一氧化物填入該溝渠； 往下凹陷該氧化物、ILD和順應第三襯墊層至該非活性底端部分的該上方表面；以及從該活性頂端部分將該順應第一與第二襯墊層剝離。其他態樣包括形成一溝渠，其與該GAA相鄰並往下通過該第二ILD、第二介電隔板、第一介電隔板、氧化物層以及SiN襯墊至該金屬佈線層；以及在該溝渠內形成一溝渠矽化物，該溝渠矽化物連接該金屬佈線層與GAA。進一步態樣包括形成該GAA與該金屬佈線層部分重疊。額外態樣包括在該溝渠的側壁上與該金屬佈線層上形成一順應第三襯墊層；用一氧化物填入該溝渠；往下凹陷該氧化物、ILD和順應第三襯墊層至該非活性底端部分的該上方表面；以及在形成該氧化物層之前，從該活性頂端部分將該順應氧化物與SiN層剝離；以及形成往下通過該第二ILD、第二介電層、GAA、第一介電隔板、氧化物層以及該順應第三襯墊層到該金屬佈線層的一開口；用一金屬層填入該開口；往下凹陷該金屬層至該GAA的一上方表面；在該第二介電層的該開口內該GAA上形成一第三介電隔板層；以及在該開口內形成與該第二ILD共平面的一第二氧化物層。
本發明的進一步態樣為一方法，其包括：在一基板上方形成一S/D層；在該S/D層上方形成一覆蓋介電層；在該覆蓋介電層上方形成一金屬佈線層；將該金屬佈線層形成圖案；在該S/D與金屬佈線層上方形成一置換金屬閘(RMG，replacement metal gate)堆疊；形成往下通過該RMG堆疊至該S/D層的一置換鰭片溝渠；在該置換鰭片溝渠內形成一置換鰭片堆疊；在該置換鰭片上方形成比該置換鰭片還要寬的一SiN蓋；移除該RMG堆疊在該SiN蓋每一側上的部分；以及在該RMG堆疊的剩餘部分上並圍繞該置換鰭片之處形成一GAA。
本發明的態樣包括根據以下形成該RMG堆疊：在該S/D和金屬佈線層上方形成一第一矽氮化硼(SiBCN)、一第一碳氧化矽(SiOC)、一第一矽碳氮化矽(SiOCN)或一第一碳化矽(SiC)層；在該第一SiBCN、該第一SiOC、該第一SiOCN或該第一SiC層上方形成一第一氧化物層；在該 第一氧化物層上方形成一第二SiBCN、一第二SiOC、一第二SiOCN或一第二SiC層；以及在該第二SiBCN、該第二SiOC、該第二SiOCN或該第二SiC層上方形成一第二氧化物層。其他態樣包括依照以下移除該RMG堆疊的該部分：往下蝕刻該RMG堆疊至該SiN蓋每一側上的該第一SiBCN、該第一SiOC、該第一SiOCN或該第一SiC層，並且該第二SiBCN、該第二SiOC、該第二SiOCN或該第二SiC層的一部分仍舊在該SiN蓋之下。進一步態樣包括依照以下形成該RMG堆疊：在該S/D與金屬佈線層上方形成一第一SiN層；將該第一SiN層往下平坦化到該金屬佈線層；在該第一SiN層上方形成一第二SiN層；在該第二SiN層上方形成一氧化物層；以及在該氧化物層上方形成一第三SiN層。額外態樣包括依照以下移除該RMG堆疊的該部分：往下蝕刻該RMG堆疊至該SiN蓋每一側上的該第二SiN層，而該第三SiN層的一部分仍舊在該SiN蓋之下。另一個態樣包括依照以下形成該置換鰭片堆疊：在該置換鰭片溝渠內的該S/D層上形成一第二S/D層；在該第二S/D層上形成一活性鰭片層；以及在該活性鰭片層上形成一第三S/D層。
熟此技藝者通過以下詳細描述就可輕鬆了解本案的額外態樣和技術效果，其中本案的具體實施例僅藉由實現本案的最佳模式之方式進行描述。如所瞭解，本案可包含其他及不同的具體實施例，並且在不背離本案的情況下，許多細節都可在許多其他方面修改。因此，圖式與說明僅供說明而不做限制。
101‧‧‧n型活性區域
103‧‧‧p型活性區域
109‧‧‧下拉電晶體
111‧‧‧上拉電晶體
113‧‧‧通道閘電晶體
115‧‧‧鰭片
117‧‧‧S/D接觸區
119‧‧‧閘極
121‧‧‧閘極接點
123‧‧‧底部S/D接點
201‧‧‧nRX區域
203‧‧‧pRX區域
205‧‧‧PD電晶體
207‧‧‧PU電晶體
209‧‧‧PG電晶體
211‧‧‧鰭片
213‧‧‧S/D接觸區
215‧‧‧閘極
217‧‧‧閘極接點
219‧‧‧交叉耦合接點
301‧‧‧硬光罩
303‧‧‧基材
305‧‧‧鰭片
307‧‧‧鰭片
309‧‧‧鰭片
311‧‧‧鰭片
401‧‧‧雙層側壁隔板
403‧‧‧氧化物層
405‧‧‧SiN層
601‧‧‧底部S/D層
801‧‧‧氧化物襯墊層
801'‧‧‧氧化物襯墊層
803‧‧‧SiN襯墊層
803'‧‧‧SiN襯墊層
901‧‧‧層間介電質
901'‧‧‧層間介電質
1001‧‧‧溝渠
1201‧‧‧金屬佈線層
1201'‧‧‧金屬佈線層
1501'‧‧‧順應SiN襯墊
1501‧‧‧順應SiN襯墊
1503‧‧‧氧化物層
1503'‧‧‧氧化物層
1701‧‧‧介電層
1801‧‧‧GAA
1803‧‧‧介電層
1805‧‧‧層間介電質
1807‧‧‧底部接點溝渠
2001‧‧‧溝渠矽化物
2003‧‧‧上方S/D層
2005‧‧‧S/D接點
2007‧‧‧層間介電質
2101‧‧‧圓圈
2103‧‧‧閘口
2105‧‧‧閘口
2301‧‧‧摻雜的底部S/D層
2303‧‧‧基材
2305‧‧‧活性鰭片層
2307‧‧‧硬光罩
2309‧‧‧鰭片
2311‧‧‧鰭片
2313‧‧‧鰭片
2315‧‧‧鰭片
2401‧‧‧氧化物襯墊層
2403‧‧‧SiN襯墊層
2405‧‧‧層間介電質
2501‧‧‧金屬佈線層
2503‧‧‧SiN層
2505‧‧‧氧化物層
2601‧‧‧專屬開口
2801‧‧‧金屬層
2801'‧‧‧專屬xc層
2901‧‧‧介電層
2903‧‧‧上方S/D層
2905‧‧‧S/D接點
2907‧‧‧層間介電質
3001‧‧‧n+/p+摻雜底部S/D層
3003‧‧‧基材
3101‧‧‧金屬佈線層
3103‧‧‧FEOL ILD RMG堆疊
3105‧‧‧SiBCN層
3107‧‧‧氧化物層
3109‧‧‧SiBCN層
3111‧‧‧氧化物層
3201‧‧‧置換鰭片溝渠
3203‧‧‧置換鰭片溝渠
3301‧‧‧置換鰭片堆疊
3303‧‧‧置換鰭片堆疊
3305‧‧‧底部S/D層
3307‧‧‧活性鰭片層
3309‧‧‧頂端S/D層
3401‧‧‧SiN蓋
3601‧‧‧GAA
本案藉由範例進行說明並且不受其限制，在附圖中的數據以及其中相同的參考編號指示相同的元件，其中：圖1圖解例示用於垂直裝置的一已知SRAM設計；圖2圖解例示用於包括一底部n/p S/D交叉耦合設計的垂直 裝置之一已知SRAM設計；圖3至圖9、圖10A至圖15A、圖16、圖17和圖18A至圖22A圖解例示根據示範具體實施例，基於一減法(substractive)鰭片晚期底部S/D處理，用於形成一VFET SRAM或邏輯胞元裝置的一子鰭片金屬佈線層之處理流程剖面圖；圖10B至圖15B和圖18B至圖22B分別圖解例示圖10A至圖15A和圖18A至圖22A的俯視圖；圖23至圖25圖解例示根據示範具體實施例，基於一減法鰭片早期S/D處理，用於形成一VFET SRAM或邏輯胞元裝置的一子鰭片金屬佈線層之部分處理流程剖面圖；圖26A至圖29A圖解例示根據示範具體實施例，基於一減法鰭片晚期底部S/D處理，用於形成一VFET SRAM或邏輯胞元裝置可增加CPP縮放的一子鰭片金屬佈線層之處理流程；圖26B至圖29B分別圖解例示圖26A至圖29A的俯視圖；以及圖30至圖36圖解例示根據示範具體實施例，基於一通道最後置換鰭片早期底部S/D處理，用於形成一VFET SRAM或邏輯胞元裝置的一子鰭片金屬佈線層之處理流程剖面圖。
在下列說明中，用於解釋說明，將公佈許多設定細節以提供對示範具體實施例通盤的了解。不過很明顯，不用這些特定細節或等量配置也可實施示範具體實施例。在其他實例中，已知的結構與裝置都以方塊圖來顯示，以避免模糊示範具體實施例。此外，除非另有所指，本說明書及申請專利範圍中用以表示成分、反應條件等等之數量、比例以及數值特性的所有數字，皆應理解為在所有情況下以「約(about)」一詞修飾之。
本發明涉及並解決當前滿足SRAM縮放所需接地規則要求的空間限制問題和障礙。
根據本發明具體實施例的方法與所得到的裝置，包括鰭片的第一和第二配對，其形成於一基材上，其中每一鰭片都具有一活性頂端部分以及一非活性底端部分，每對鰭片在一第一方向內橫向分隔，並且該等配對在與該第一方向垂直的一第二方向內彼此橫向分隔。一底部S/D層在該基材上圍繞該等鰭片之處形成圖案，並且在該基材上方依序形成順應(conformal)第一和第二襯墊層。一第一ILD形成於該順應第二襯墊層之上方，並且一金屬佈線層形成於該第一配對之間，該順應第二襯墊層上與至少該第二配對之間該底部S/D層上該等鰭片配對之間的該第二方向內，一上方表面形成於該活性頂端部分下方。一第一介電隔板，其形成於該第一ILD上方。一GAA形成於該第一介電隔板上圍繞該第一配對的每一鰭片之處，並且一第二介電隔板形成於該GAA和該第一介電隔板上方。一底部S/D接點xc或一專屬xc分別形成於與該GAA相鄰或穿透該GAA的該金屬佈線層上，並且一第二ILD形成於該基材上方。
精通技術人士從以下詳細說明當中，將可輕易了解到更多其他態樣、特徵與技術效果，其中簡單通過所考慮最佳模式的圖示來顯示並說明較佳具體實施例。本發明可包含其他及不同的具體實施例，並且許多細節都可在許多其他方面修改。因此，圖式與說明僅供說明而不做限制。
圖3至圖9、圖10A至圖15A、圖10B至圖15B、圖16、圖17、圖18A至圖22A以及圖18B至圖22B圖解例示根據示範具體實施例，基於一減法鰭片晚期底部S/D處理，用於形成一VFET SRAM或邏輯胞元裝置的一子鰭片金屬佈線層之處理流程。圖10B至圖15B和圖18B至圖22B為俯視圖，以及圖10A至圖15A和圖18A至圖22A分別為沿著A-A'線的剖面圖。為了說明，圖10B至圖15B和圖18B至圖22B僅為粗略描繪，並非完整俯視圖。請注意圖3，在一基材303上方形成例如SiN的一硬光罩 301。然後蝕刻硬光罩301和基材303，露出一對鰭片305和307的該活性頂端部分。除了該第二對鰭片形成與鰭片305和307橫向相隔以外，第二對鰭片309和311(為了方便例示，並未顯示)也同時並用後續步驟內說明的相同方式形成如圖10B內所示。一雙層側壁隔板401由例如一氧化物層403和一SiN層405形成於硬光罩301的該等側壁上，以及鰭片305和307的活性頂端部分上，如圖4內所示。然後將基材303凹陷例如40nm至100nm，露出鰭片305和307的該非活性底端部分，然後鰭片305和307的該非活性底端部分橫向凹陷，例如讓寬度留下1nm至20nm，如圖5內所示。
請注意圖6，利用磊晶成長或透過其他摻雜技術，在基材303之上並沿著鰭片305和307的該非活性底端部分之該等側壁，形成例如厚度10nm至70nm的一底部S/D層601。底部S/D層601的厚度低於圖5中說明的該凹陷深度。若基材303由矽(Si)或矽鍺(SiGe)形成，則底部S/D層601可由例如磷(P)摻雜Si(Si：P)、碳(C)和P摻雜Si(Si：CP)、硼(B)摻雜Si(Si：B)、B摻雜SiGe(SiGe：B)、砷(As)摻雜Si(Si：As)形成，或基材303和底部S/D層601可由任何其他半導體材料形成。接下來，執行退火處理來將摻雜物熱擴散，以提供某些重疊(overlap)控制，並且剝離雙層側壁隔板401，如圖7內所示。有一種可能性為在此階段上包括一早期矽化物；然而，該矽化物必須能夠承受前段(FEOL，front end of line)熱積存。請注意圖8，一氧化物襯墊層801和一SiN襯墊層803分別在基材303上方順應形成為例如0.5nm至4nm以及2nm至10nm的厚度。請注意，襯墊層801和803應可替代順應形成於具有與氧化物和SiN類似特性的不同材料之基材303上方。
然後一層間介電質ILD 901沈積在基材303上方，並用例如化學機械拋光(CMP，chemical mechanical polishing)往下平坦化至SiN襯墊層803，如圖9內所示。另外，若需要，利用多步驟氧化物沈積/凹陷/SiN沉積處理，也可加入額外蝕刻停止層(為了方便說明，並未顯示)。請注意圖 10A和圖10B，一溝渠1001由例如非等向反應離子蝕刻(RIE，reactive ion etching)往下形成於ILD 901與鰭片305和307以及鰭片309和311之間至SiN襯墊層803。溝渠1001的寬度僅通過鰭片分離設置而沒有任何其它限制。請注意圖11A和圖11B，鰭片309與311之間的氧化物襯墊層801和SiN襯墊層803之一部分用例如RIE移除，將溝渠1001往下延伸至底部S/D層601，藉此形成一底部S/D接觸區。該底部S/D接觸區可另外進一步延伸超過鰭片309與311之間。
請注意圖12A(鰭片305與307之間的剖面圖)和圖13A(鰭片309與311之間的剖面圖)，沿著溝渠1001形成一金屬佈線層1201。若需要，在鰭片309與311之間，例如由鈦(Ti)或鎳(Ni)形成的一接點層(為了方便說明，並未顯示)可選擇性用來形成一矽化物，結合選擇性退火與剝離步驟接著一多層堆疊，像是氮化鈦(TiN)和鎢(W)或TiN和鋁(Al)。在例如鰭片305與307之間的非接觸區，矽化物遭到氧化物襯墊層801阻擋。然後凹陷金屬佈線層1201直到該上方表面低於鰭片305至311的該活性部分，形成金屬佈線層1201’，如圖14A內所示。隨著鰭片305至311的尺寸，金屬佈線層1201’的剩餘厚度可為例如10nm至100nm。
然後在溝渠1001的該等側壁上以及凹陷的金屬佈線層1201'上，形成例如厚度2nm至10nm的一順應SiN襯墊1501，如圖15A所示。接下來，用氧化物層1503填入溝渠1001，然後用例如CMP將氧化物層1503往下平坦化至SiN層803。請注意圖16，將氧化物層1503、ILD901和SiN襯墊1501往下凹陷至鰭片305至311的該非活性底端部分之上方表面，形成氧化物層1503’、ILD 901’和SiN襯墊1501’。然後SiN襯墊層803和氧化物襯墊層801從鰭片305至311的該活性頂端部分剝離，形成SiN襯墊層803’和氧化物襯墊層801’。接下來，一介電層1701由例如SiN、氧化物或像是SiBCN/SiOCN/SiOC這類低k膜所形成，厚度為2nm至15nm，如圖17所示。
請注意圖18A(沿著圖18B中x軸線的剖面圖)和圖19A(沿著圖19B中y軸線的剖面圖)，一GAA 1801形成於介電層1701上圍繞每一鰭片305和307之處。依照需要，一部分GAA 1801之部分可與金屬佈線層1201’重疊。然後在介電層1701和GAA 1801上方形成類似於介電層1701的一介電層1803。接下來，一ILD 1805形成於該基材上方，然後用例如CMP往下平坦化至硬光罩301。此後，通過ILD 1805、介電層1803、介電層1701、氧化物層1503’和SiN襯墊1501’往下至金屬佈線層1201’，形成與GAA 1801相鄰的一底部接點溝渠1807。底部接點溝渠1807橫向偏移，如此與GAA 1801和金屬佈線層1201’兩者重疊來確定接觸。
接下來，一溝渠矽化物2001形成於連接金屬佈線層1201’和GAA 1801的溝渠1807，如圖20A(通過圖20B中溝渠矽化物2001的剖面圖)、圖21A(沿著圖21B中鰭片309和311的剖面圖)和圖22A(沿著圖22B中y軸線的剖面圖)內所示。此後，製程遵循傳統中段(MOL，middle of the line)成形步驟，例如移除硬光罩301以及形成一上方S/D層2003、S/D接點2005和一ILD 2007。因此，圖21B內圓圈2101之內的區域可相對於圖1和圖2中該已知VFET SRAM設計而收折，因為底部S/D層601可分別連接至金屬配線層1201’而不干擾鰭片309和311的閘口2103和2105。
圖23至圖25(剖面圖)圖解例示根據示範具體實施例，基於一減法鰭片早期S/D處理，用於形成一VFET SRAM或邏輯胞元之一者之一子鰭片金屬佈線層的部分處理流程。請注意圖23，以和圖6中底部S/D層601相同的方式，在基材203上方形成一摻雜的底部S/D層2301。然後在底部S/D層2301上方形成例如Si的一活性鰭片層2305，並且一硬光罩2307形成於活性鰭片層2305之上。然後將硬光罩2307形成圖案並且往下蝕刻活性鰭片層2305至已製圖硬光罩2307的每一側上之底部S/D層2301，露出鰭片2309和2311的活性頂端部分。此後，底部S/D層2301圍繞鰭片2309和2311的活性頂端部分而凹陷，露出鰭片2309和2311的非 活性底端部分。如圖3所例示，第二對鰭片2313和2315(為了方便例示，並未顯示)也同時並用相同方式形成，除了該第二對鰭片2313和2315形成與鰭片2309和2311橫向相隔以外，如圖10B內所示。
請注意圖24，一氧化物襯墊層2401和一SiN襯墊層2403分別在基材303上方順應形成為例如0.5nm至4nm以及2nm至10nm的厚度。然後一ILD 2405沈積在該基材上方，然後用例如CMP往下平坦化至SiN襯墊層2403。如圖12內所示，一金屬佈線層2501形成於鰭片2309與2311之間的SiN襯墊層2403上，以及至少鰭片2313與2315之間的底部S/D層2301上，如圖25內所示。一SiN襯墊2503沿著IDL 2405的該等側壁，並於金屬佈線層2501上形成。此後，一氧化物層2505形成於SiN層2503之上，然後用例如CMP往下平坦化至SiN襯墊層2403。然後，如圖16、圖17、圖18A至圖22A以及圖18B至圖22B內詳細說明來繼續該製程。同樣地，襯墊層2401和2403應可替代順應形成於具有與氧化物和SiN類似特性的不同材料之基材2303上方。
圖26A至圖29A以及圖26B至圖29B圖解例示根據示範具體實施例，基於一減法鰭片晚期底部S/D處理，用於形成一VFET SRAM或邏輯胞元裝置可增加CPP縮放的一子鰭片金屬佈線層之處理流程。圖26B至圖29B為俯視圖，並且圖26A至圖29A分別為沿著A-A'線的剖面圖。圖26B至圖29B僅為說明目的之粗略描繪，並非完整俯視圖。請注意圖26A(沿著圖26B中x軸線的剖面圖)和圖27A(沿著圖27B中y軸線的剖面圖)，圖26A和圖26B以及圖27A和圖27B中的製程大體上與圖3至圖9、圖10A至圖15A、圖10B至圖15B、圖16和圖17內描述的製程相同。然而，可使用獨特的形成圖案步驟形成一專屬開口2601，而非形成相鄰於GAA 1801之一底部S/D接點溝渠1807；該開口2601通過ILD 1805、介電層1803、GAA 1801、介電層1701、氧化物層1503’和SiN襯墊1501’往下至金屬佈線層1201’，後續使用例如一個別微影蝕刻曝光來形成一專屬xc層。
請注意圖28A和圖28B，開口2601填入一金屬層2801，例如W、Al等。然後金屬層2801往下凹陷至GAA 1801的該上方表面，形成專屬xc層2801’，圖29A內所示。專屬xc層2801’將鰭片309與311之間的底部S/D層601連接至鰭片305與307之間的GAA 1801。此後，一介電層2901形成於專屬xc層2801’上方，並且該製程遵循傳統MOL成形步驟，例如移除硬光罩301以及形成一上方S/D層2903、S/D接點2905和一ILD2907。沿著鰭片309與311之間該x軸線的剖面圖與沿著圖21A內該x軸線的剖面圖相同。因此，不同於現有的溝渠矽化物xc層2001，專屬xc層2801’可啟用最大CPP縮放。
圖30至圖36(剖面圖)圖解例示根據另一示範具體實施例，基於一通道最後置換鰭片早期底部S/D處理，用於形成一VFET SRAM或邏輯胞元裝置的一子鰭片金屬佈線層之處理流程。請注意圖30，在基材3003上方形成一n+/p+摻雜底部S/D層3001至例如5nm至50nm的厚度。然後一覆蓋介電層(為了方便說明，並未顯示)形成於底部S/D層3001上方。以相同方式，將氧化物襯墊層801和SiN襯墊層803往下移除至底部S/D層601，進而形成圖11A和圖11B內的一底部S/D接觸區，然後在設計的接觸區內蝕刻該介電層。此後，一金屬層(為了方便說明，並未顯示)形成於該非接觸區內的該介電層上方以及該接觸區內的底部S/D層3001上方，然後製作圖案形成金屬佈線層3101，如圖31內所示。金屬佈線層3101可由與金屬佈線層1201’相同的材料形成，並且可根據所要的電路設計，製作圖案至例如3nm至50nm的寬度。
接下來，一FEOL ILD RMG堆疊3103形成於金屬佈線層3101以及該介電層上方。RMG堆疊3103包括一SiBCN層3105、一氧化物層3107、一SiBCN層3109以及一氧化物層3111。另外，SiBCN層3105可由例如SiOC、SiOCN、SiC等等所形成。請注意圖32，形成置換鰭片溝渠3201和3203往下通過RMG堆疊3103至底部S/D層3001。然後，置換 鰭片堆疊3301和3303由在置換鰭片溝渠3201和3203內底部S/D層3001上形成一選擇性底部S/D層3305、在底部S/D層3305上形成一活性鰭片層3307以及在活性鰭片層3307上形成一頂端S/D層3309來形成，如圖33內所示。置換鰭片堆疊3301和3303可已摻雜或未摻雜。然後，寬度比置換鰭片堆疊3301和3303還要寬的SiN蓋3401形成於置換鰭片堆疊3301和3303上方，如圖34所示。
請注意圖35，通過蝕刻RMG堆疊3103將一部分RMG堆疊3103往下移除至SiN蓋3401每一側上的SiBCN層3105，而有一部分SiBCN層3019仍舊在SiN蓋3401底下。然後，一GAA 3601形成於SiBCN層3105上圍繞置換鰭片堆疊3301和3303中的每一者，如圖36所示。接下來，形成一溝渠矽化物(為了方便說明，並未顯示)相鄰於金屬佈線層3101上的GAA 3601，藉此連接金屬佈線層3101和GAA 3601，如圖20A和圖20B內所示，或形成一專屬xc層(為了方便說明，並未顯示)通過GAA 3601往下至金屬佈線層3101，藉此連接金屬佈線層3101和GAA 3601，如圖29A和圖29B內所示。
另外，可依照以下形成一FEOL ILD RMG堆疊：在頂端S/D層3301和金屬佈線層3401上方形成一SiN層(為了方便說明，並未顯示)；將該SiN層往下平坦化到金屬佈線層3401；在該第一SiN層上方形成一第二SiN層(為了方便說明，並未顯示)；在該第二SiN層上方形成一氧化物層(為了方便說明，並未顯示)；以及在該氧化物層上方形成一第三SiN層(為了方便說明，並未顯示)。此後，往下蝕刻該RMG堆疊至該SiN蓋每一側上的該第二SiN層，來移除該替代形成的RMG堆疊之一部分，而該第三SiN層的一部分仍舊在該SiN蓋之下。
本發明的具體實施例能夠實現許多技術效果，包括通過使用一底部S/D接點互連，減少xc接點上的空間限制，並且通過使用一專屬xc層，可增加CPP縮放。本發明的具體實施例運用在許多工業應用的設施當 中，諸如微處理器、智慧型電話、行動電話、蜂巢式手機、衛星電話、機上盒、DVD記錄器與播放器、汽車導航、印表機與週邊設備、網路與電信設備、遊戲系統以及數位相機。因此，本發明在具備VFET或邏輯胞元的任何IC裝置內具有工業適用性。
在上面的說明中，本發明以參考特定示範具體實施例來做說明。不過有證據顯示，在不背離申請專利範圍內公佈之本發明廣泛精神以及領域下，可進行許多修改與變更。因此說明書與圖式僅供參考而不做限制。應當理解，本發明能夠使用各種其他組合和具體實施例，並且能夠在本文所表達的本發明構思範圍內進行任何改變或修改。

Claims (20)

  1. 一種邏輯裝置，包括：鰭片的第一和第二配對，其形成於一基材上，其中每一鰭片都具有一活性頂端部分以及一非活性底端部分，每對鰭片在一第一方向內橫向分隔，並且該等第一和第二配對在與該第一方向垂直的一第二方向內彼此橫向分隔；一底部源極/汲極(S/D)層，其圍繞該基材上的該等鰭片而形成圖案；一順應第一襯墊層和一順應第二襯墊層，其依序形成於該基材上方；一第一層間介電質(ILD)，其形成於該順應第二襯墊層上方；一金屬佈線層，其形成於該第一配對之間該順應第二襯墊層上以及至少該第二配對之間該底部S/D層上之該等第一和第二配對之間的該第二方向內，其中一上方表面形成於該活性頂端部分下方；一第一介電隔板，其形成於該第一ILD上方；一全包覆閘(GAA)，其形成於該第一介電隔板上圍繞該第一配對的每一鰭片上；一第二介電隔板，其形成於該GAA和該第一介電隔板上方；一底部S/D接點交叉耦合(cross-couple，xc)或一專屬xc，其分別形成於與該GAA相鄰或穿透該GAA的該金屬佈線層上；以及一第二ILD，其形成於該基材上方。
  2. 如申請專利範圍第1項之邏輯裝置，其中該第一配對的鰭片分別形成一下拉(PD)和一第一上拉(PU)電晶體的一部分，以及該第二配對的鰭片分別形成一通道閘(PG)和一第二PU電晶體的一部分。
  3. 如申請專利範圍第1項之邏輯裝置，進一步包括在該金屬佈線層與該 第一介電層之間的一襯墊與氧化物層。
  4. 如申請專利範圍第1項之邏輯裝置，其中該GAA有一部分與該金屬佈線層的一部分重疊。
  5. 如申請專利範圍第1項之邏輯裝置，進一步包括在每一鰭片上的頂端S/D接點。
  6. 一種形成邏輯裝置的方法，包括：在一基材上形成鰭片的第一和第二配對，其中每一鰭片都具有一活性通道部分以及包括一凹陷區部分的一非活性底端部分，每對鰭片在一第一方向內橫向分隔，並且該等第一和第二配對在與該第一方向垂直的一第二方向內橫向分隔；將一底部源極/汲極(S/D)層形成圖案，圍繞該基材上的該等鰭片；依序在該基材之上形成一順應第一襯墊層和一順應第二襯墊層；在該基材上方形成一第一層間介電質(ILD)，其與該順應第二襯墊層共平面；在每一配對之間以及該第二方向內該等第一和第二配對之間的該ILD內形成一溝渠；沿著該溝渠形成一金屬佈線層，一上方表面形成於該頂端活性部分下方；在該金屬佈線層上方形成一氧化物層，一上方表面位於該活性頂端部分的一下方表面下方；在該基材上方形成一第一介電隔板；在該第一介電隔板上形成一全包覆閘(GAA)圍繞該第一配對的每一鰭片上； 在該GAA和該第一介電隔板上方形成一第二介電隔板；以及在該基材上方形成一第二ILD層。
  7. 如申請專利範圍第6項之方法，包括依照以下步驟形成鰭片的該第一配對和第二配對：在該基材上方形成一硬光罩；蝕刻該硬光罩與基材，露出該活性頂端部分；在該硬光罩與活性頂端部分的側壁上形成一雙層側壁隔板；將該基材凹陷40奈米(nm)至100nm，露出該非活性底端部分；橫向凹陷該非活性底端部分的一部分；以及在該鰭片的該非活性部分內形成該底部S/D層之後，將該雙層側壁隔板剝離。
  8. 如申請專利範圍第6項之方法，包括沿著該非活性底端部分的側壁形成該底部S/D層。
  9. 如申請專利範圍第6項之方法，包括依照以下步驟形成鰭片的該第一配對和第二配對以及該底部S/D層：在該基材上方形成該底部S/D層；在該底部S/D層上方形成一活性鰭片層；在該活性鰭片層上方形成一硬光罩；將該硬光罩形成圖案；在該已形成圖案的硬光罩之每一側上往下蝕刻該活性鰭片層至該底部S/D層，露出該活性頂端部分；以及凹陷該活性鰭片層四周的該底部S/D層，露出該非活性底端部分。
  10. 如申請專利範圍第6項之方法，包括依照以下步驟形成該溝渠：往下蝕刻該第一ILD至該等鰭片第一配對的鰭片間之該順應第二襯墊層；以及往下蝕刻該第一ILD和該順應第一和第二襯墊層到至少該第二配對的鰭片間之該底部S/D層。
  11. 如申請專利範圍第6項之方法，進一步包括在形成該氧化物層之前進行以下步驟：凹陷該金屬佈線層，直到該上方表面低於該頂端活性部分；在該溝渠的側壁上與該金屬佈線層上形成一順應第三襯墊層；用一氧化物填入該溝渠；往下凹陷該氧化物、ILD和順應第三襯墊層至該非活性底端部分的該上方表面；以及自該活性頂端部分將該順應第一與第二襯墊層剝離。
  12. 如申請專利範圍第6項之方法，進一步包含：形成一溝渠，其與該GAA相鄰並往下通過該第二ILD、該第二介電隔板、該第一介電隔板、該氧化物層以及該順應第三襯墊層至該金屬佈線層；以及在該溝渠內形成一溝渠矽化物，該溝渠矽化物連接該金屬佈線層與該GAA。
  13. 如申請專利範圍第6項之方法，包括形成該GAA使其有一部分與該金屬佈線層重疊。
  14. 如申請專利範圍第13項之方法，包括： 在該溝渠的側壁上與該金屬佈線層上形成一順應第三襯墊層；用一氧化物填入該溝渠；往下凹陷該氧化物、該ILD和該順應第三襯墊層至該非活性底端部分的該上方表面；以及在形成該氧化物層之前，自該活性頂端部分將該順應氧化物與SiN層剝離；以及形成往下通過該第二ILD、該第二介電層、該GAA、該第一介電隔板、該氧化物層以及該順應第三襯墊層到該金屬佈線層的一開口；用一金屬層填入該開口；往下凹陷該金屬層至該GAA的一上方表面；在該第二介電層的該開口內該GAA上形成一第三介電隔板層；以及在該開口內形成與該第二ILD共平面的一第二氧化物層。
  15. 一種形成邏輯裝置的方法，包括：在一基材上方形成一源極/汲極(S/D)層；在該S/D層上方形成一覆蓋介電層；在該覆蓋介電層上方形成一金屬佈線層；將該金屬佈線層形成圖案；在該S/D與金屬佈線層上方形成一置換金屬閘(RMG，replacement metal gate)堆疊；往下通過該RMG堆疊至該S/D層形成一置換鰭片溝渠；在該置換鰭片溝渠內形成一置換鰭片堆疊；在該置換鰭片上方形成比該置換鰭片還要寬的一氮化矽(SiN)蓋；移除在該SiN蓋每一側上的該RMG堆疊部分；以及在該RMG堆疊的剩餘部分上並圍繞該置換鰭片之處形成一全包覆 閘(GAA)。
  16. 如申請專利範圍第15項之方法，包括依照以下步驟形成該RMG堆疊：在該S/D和該金屬佈線層上方形成一第一矽氮化硼(SiBCN)、一第一碳氧化矽(SiOC)、一第一矽碳氮化物(SiOCN)或一第一碳化矽(SiC)層；在該第一SiBCN、該第一SiOC、該第一SiOCN或該第一SiC層上方形成一第一氧化物層；在該第一氧化物層上方形成一第二SiBCN、一第二SiOC、一第二SiOCN或一第二SiC層；以及在該第二SiBCN層、該第二SiOC、該第二SiOCN或該第二SiC上方形成一第二氧化物層。
  17. 如申請專利範圍第16項之方法，包括依照以下步驟移除該RMG堆疊的該部分：往下蝕刻該RMG堆疊至該SiN蓋每一側上的該第一SiBCN、該第一SiOC、該第一SiOCN或該第一SiC層，並且該第二SiBCN、該第二SiOC、該第二SiOCN或該第二SiC層的一部分仍舊在該SiN蓋之下。
  18. 如申請專利範圍第15項之方法，包括依照以下步驟形成該RMG堆疊：在該S/D與金屬佈線層上方形成一第一SiN層；將該第一SiN層往下平坦化到該金屬佈線層；在該第一SiN層上方形成一第二SiN層；在該第二SiN層上方形成一氧化物層；以及在該氧化物層之上形成一第三SiN層。
  19. 如申請專利範圍第18項之方法，包括依照以下步驟移除該RMG堆疊的該部分：往下蝕刻該RMG堆疊至該SiN蓋每一側上的該第二SiN層，而該第三SiN層的一部分仍舊在該SiN蓋之下。
  20. 如申請專利範圍第15項之方法，包括依照以下步驟形成該置換鰭片堆疊：在該置換鰭片溝渠內的該S/D層上形成一第二S/D層；在該第二S/D層之上形成一活性鰭片層；以及在該活性鰭片層上形成一第三S/D層。
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