CN106549043A - 半导体器件制造方法 - Google Patents
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- 239000010703 silicon Substances 0.000 claims abstract description 75
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 29
- 238000003475 lamination Methods 0.000 claims abstract description 23
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 21
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- 238000005516 engineering process Methods 0.000 abstract description 7
- 238000001039 wet etching Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
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- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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Abstract
本发明提供了一种FinFET制造方法,采用SOI衬底,能够获得很好的器件隔离,通过形成硅/锗硅叠层并去除其中一种材料以形成纳米线,由于硅/锗硅叠层包含于鳍片之中,纳米线并不需要采用额外的pad进行支撑,降低了工艺的难度,并且,由于硅和锗硅的材料性质差异,可以采用高选择比的低温湿法刻蚀工艺去除其中一种材料,而无需采用干法刻蚀工艺,进一步简化了工艺;而且并发明的方法与常规FinFET工艺兼容,可以简便有效地获得FinFET纳米线器件。
Description
技术领域
本发明涉及半导体器件制造方法领域,具体而言,涉及一种FinFET半导体器件的制造方法。
背景技术
近30年来,半导体器件一直按照摩尔定律等比例缩小,半导体集成电路的特征尺寸不断缩小,集成度不断提高。随着技术节点进入深亚微米领域,例如100nm以内,甚至45nm以内,传统场效应晶体管(FET),也即平面FET,开始遭遇各种基本物理定律的限制,使其等比例缩小的前景受到挑战。众多新型结构的FET被开发出来,以应对现实的需求,其中,FinFET就是一种很具等比例缩小潜力的新结构器件。
FinFET,鳍状场效应晶体管,是一种多栅半导体器件。由于结构上的独有特点,FinFET成为深亚微米集成电路领域很具发展前景的器件。顾名思义,FinFET包括一个垂直于体硅的衬底的Fin,Fin被称为鳍片或鳍状半导体柱,不同的FinFET被STI结构分割开来。不同于常规的平面FET,FinFET的沟道区位于Fin之内。栅极绝缘层和栅极在侧面和顶面包围Fin,从而形成至少两面的栅极,即位于Fin的两个侧面上的栅极;同时,通过控制Fin的厚度,使得FinFET具有极佳的特性:更好的短沟道效应抑制能力,更好的亚阈值斜率,较低的关态电流,消除了浮体效应,更低的工作电压,更有利于按比例缩小。
虽然FinFET具有上述种种优点,但是仍然存在电流小、栅控弱的情况。为了解决上述问题,纳米线被认为是一种比较好的解决方案。但是常规的方法形成纳米线的刻蚀方法比较复杂,与常规FinFET工艺并不很兼容;同时纳米线需要pad进行支撑。这导致工艺比较复杂,提高了制作成本。另外,在传统工艺,采用体硅衬底,通常进行的掺杂隔离注入可能破坏晶体结构,导致器件性能的恶化,并且,随着器件尺寸的减小,其隔离效果也越来越差
因此,需要提供一种新的FinFET制造方法,以更加简便和有效的的方法形成纳米线。
发明内容
本发明提出了一种FinFET制造方法,采用了硅/锗硅叠层以及高选择比刻蚀工艺,以简便有效地制造具有纳米线结构的FinFET器件。
本发明提供了一种半导体器件制造方法,用于制造FinFET器件,包括如下步骤:
提供SOI衬底,所述SOI衬底具有埋置氧化层和顶置半导体层;
在所述顶置半导体层上形成硅层和锗硅层交替层叠的硅/锗硅叠层;
通过图案化处理,形成鳍片;
在所述鳍片之上形成虚设栅氧化层,虚设栅极堆栈,栅极侧墙;
形成源漏延伸区以及源漏区;
全面性沉积介质层,覆盖所述虚设栅极堆栈;
平坦化处理暴露出所述虚设栅极堆栈上表面,并去除所述虚设栅极堆栈和所述虚设栅氧化层;
去除所述硅/锗硅叠层中的硅或者锗硅材料;
形成栅极绝缘层和栅极。
根据本发明的一个方面,在去除所述硅/锗硅叠层中的硅或者锗硅材料时,采用高刻蚀选择比的工艺去除硅或者锗硅材料;采用湿法工艺去除硅材料,湿法工艺选择具有羟基的有机溶剂,优选为TMAH。
根据本发明的一个方面,所述鳍片包括所述硅/锗硅叠层和所述顶置半导体层。
本发明的优点在于:采用SOI衬底,能够获得很好的器件隔离,通过形成硅/锗硅叠层并去除其中一种材料以形成纳米线,由于硅/锗硅叠层包含于鳍片之中,纳米线并不需要采用额外的pad进行支撑,降低了工艺的难度,并且,由于硅和锗硅的材料性质差异,可以采用高选择比的低温湿法刻蚀工艺去除其中一种材料,而无需采用干法刻蚀工艺,进一步简化了工艺;而且并发明的方法与常规FinFET工艺兼容,可以简便有效地获得FinFET纳米线器件。
附图说明
图1-9本发明提供的半导体制造方法的流程示意图。
具体实施方式
以下,通过附图中示出的具体实施例来描述本发明。但是应该理解,这些描述只是示例性的,而并非要限制本发明的范围。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本发明的概念。
本发明提供一种半导体器件制造方法,具体而言,涉及一种FinFET器件制造方法。下面,参见说明书附图,将详细描述本发明提供的半导体器件制造方法。
首先,参见附图1,提供SOI衬底1,所述SOI衬底1具有埋置氧化层2和顶置半导体层3。与体硅衬底相比,SOI衬底具有埋置氧化层,能够更好实现器件隔离,避免了传统体硅衬底掺杂隔离时的弊端以及隔离效果衰退。埋置氧化层2例如为二氧化硅,顶置半导体层3例如为硅。
接着,参见图2,在顶置半导体层3上,形成硅层和锗硅层交替层叠的硅/锗硅叠层4。硅/锗硅叠层4优选采用外延工艺形成,其最底层为硅或者锗,在本发明图示的实施例中,采用了锗硅层为最底层;可选的实施例中,可以采用硅层为最底层。硅/锗硅叠层4用于在随后的工艺中形成纳米线,每层硅层和锗硅层的厚度为2-50nm,优选为5-15nm,层叠的数目通常在3层以上,优选为5层,即自下向上的锗硅/硅/锗硅/硅/锗硅。
参见图3,其为侧视图,通过图案化处理,形成鳍片。优选地,鳍片包括硅/锗硅叠层4和顶置半导体层3。在本发明优选的实施例中,图案化处理的刻蚀步骤停止在埋置氧化层2上,由埋置氧化层2形成各个不同器件的电学隔离。在可选的实施例中,可以在图案化步骤中,将刻蚀进行至SOI衬底1之中,也即刻蚀穿过埋置氧化层2,在此情况下,鳍片包括硅/锗硅叠层4、顶置半导体层3、埋置氧化层2以及部分SOI衬底1;同时,在此情况下,可选地形成STI结构(未图示)。
接着,参见图4,在鳍片结构之上,形成虚设栅氧化层5,虚设栅极堆栈6,栅极侧墙7。虚设栅氧化层5、虚设栅极堆栈6、栅极侧墙7线条跨于鳍片之上,通常是与鳍片线条垂直相交。虚设栅氧化层5例如为SiO2,虚设栅极堆栈6的材料为多晶硅或者非晶硅等,在本发明的一个实施例中,采用了非晶硅。栅极侧墙7的具体形成方法包括:全面沉积栅极侧墙材料,并进行回刻蚀,其中,栅极侧墙材料包括但不限于Si3N4。
接着,参见图5,形成源漏延伸区和源漏区8。具体工艺包括去除部分硅/锗硅叠层4材料和部分顶置半导体层3材料,形成源漏极凹槽,然后进行源漏延伸区和源漏区8的填充,例如采用外延等工艺。源漏延伸区和源漏区8还可以采用硅化物,或者应力材料。
参见图6,全面性沉积介质层9,覆盖虚设栅极堆栈6、栅极侧墙7等。介质层9材料为SiO2等。
接着,参见图7,采用平坦化工艺处理以暴露出虚设栅极堆栈6的上表面,然后,去除虚设栅极堆栈6和虚设栅氧化层5,以形成栅极凹槽10。栅极凹槽10也暴露出包括硅/锗硅叠层4的鳍片的顶面和侧面。
参见图8,经由暴露出的栅极凹槽10,去除硅/锗硅叠层4中的硅或者锗硅材料之一。优选地,采用高选择比刻蚀工艺,例如湿法刻蚀,去除硅或锗硅。湿法工艺去除硅时,选择具有羟基的有机溶剂,优选为TMAH。由于湿法刻蚀相对于干法刻蚀属于低温工艺,因此,对器件的影响较干法工艺更小。本发明优选的实施例中去除了硅材料,保留锗硅作为纳米线,也即器件的沟道区,锗硅沟道区会具有更好的器件性能;在可选的实施例中,可以选择去除锗硅而保留硅材料。图8中为去除了硅材料后的示意图,当顶置半导体层3采用硅材料时,其在本步骤中也被去除,图8中斜线阴影表示去除了硅材料后形成的空间。
接着,参见图9,形成栅极绝缘层和栅极11。栅极绝缘层和栅极11为HKMG,其中,栅极绝缘层采用高K栅极绝缘层材料,选自以下材料之一或其组合构成的一层或多层:Al2O3,HfO2,包括HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx以及HfLaSiOx至少之一在内的铪基高K介质材料,包括ZrO2、La2O3、LaAlO3、TiO2、或Y2O3至少之一在内的稀土基高K介质材料。而栅极的材料为金属、合金或金属化合物,例如TiN,TaN,W等。栅极绝缘层和栅极11包围硅/锗硅叠层4中剩余的锗硅或者硅纳米线,从而形成器件。图9中为包围锗硅纳米线的示意图,其中方格阴影表示栅极绝缘层和栅极11。
以上,本发明的半导体器件制造方法已得到说明。在本发明的方法中,采用SOI衬底,能够获得很好的器件隔离,通过形成硅/锗硅叠层并去除其中一种材料以形成纳米线,由于硅/锗硅叠层包含于鳍片之中,纳米线并不需要采用额外的pad进行支撑,降低了工艺的难度,并且,由于硅和锗硅的材料性质差异,可以采用高选择比的低温湿法刻蚀工艺去除其中一种材料,而无需采用干法刻蚀工艺,进一步简化了工艺;而且并发明的方法与常规FinFET工艺兼容,可以简便有效地获得FinFET纳米线器件。
尽管已参照一个或多个示例性实施例说明本发明,本领域技术人员可以知晓无需脱离本发明范围而对器件结构和/或工艺流程做出各种合适的改变和等价方式。此外,由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此,本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例,而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。
Claims (4)
1.一种半导体器件制造方法,用于制造FinFET器件,其特征在于包括如下步骤:
提供SOI衬底,所述SOI衬底具有埋置氧化层和顶置半导体层;
在所述顶置半导体层上形成硅层和锗硅层交替层叠的硅/锗硅叠层;
通过图案化处理,形成鳍片;
在所述鳍片之上形成虚设栅氧化层,虚设栅极堆栈,栅极侧墙;
形成源漏延伸区以及源漏区;
全面性沉积介质层,覆盖所述虚设栅极堆栈;
平坦化处理暴露出所述虚设栅极堆栈上表面,并去除所述虚设栅极堆栈和所述虚设栅氧化层;
去除所述硅/锗硅叠层中的硅或者锗硅材料;
形成栅极绝缘层和栅极。
2.根据权利要求1所述的方法,其特征在于,在去除所述硅/锗硅叠层中的硅或者锗硅材料时,采用高刻蚀选择比的工艺去除硅或者锗硅材料之一。
3.根据权利要求2所述的方法,其特征在于,采用湿法工艺去除所述硅/锗硅叠层中的硅材料,湿法工艺选择具有羟基的有机溶剂,优选为TMAH。
4.根据权利要求1所述的方法,其特征在于,所述鳍片包括所述硅/锗硅叠层和所述顶置半导体层。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050224889A1 (en) * | 2004-04-09 | 2005-10-13 | Chang-Woo Oh | Surrounded-channel transistors with directionally etched gate or insulator formation regions and methods of fabrication therefor |
CN103238208A (zh) * | 2010-12-01 | 2013-08-07 | 英特尔公司 | 硅和硅锗纳米线结构 |
US20140264253A1 (en) * | 2013-03-14 | 2014-09-18 | Seiyon Kim | Leakage reduction structures for nanowire transistors |
-
2015
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050224889A1 (en) * | 2004-04-09 | 2005-10-13 | Chang-Woo Oh | Surrounded-channel transistors with directionally etched gate or insulator formation regions and methods of fabrication therefor |
CN103238208A (zh) * | 2010-12-01 | 2013-08-07 | 英特尔公司 | 硅和硅锗纳米线结构 |
US20140264253A1 (en) * | 2013-03-14 | 2014-09-18 | Seiyon Kim | Leakage reduction structures for nanowire transistors |
Cited By (2)
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---|---|---|---|---|
CN109427901A (zh) * | 2017-08-31 | 2019-03-05 | 台湾积体电路制造股份有限公司 | 半导体器件和方法 |
CN109427901B (zh) * | 2017-08-31 | 2022-03-22 | 台湾积体电路制造股份有限公司 | 半导体器件和方法 |
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