US20160141360A1 - Iii-v semiconductor devices with selective oxidation - Google Patents
Iii-v semiconductor devices with selective oxidation Download PDFInfo
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- US20160141360A1 US20160141360A1 US14/547,181 US201414547181A US2016141360A1 US 20160141360 A1 US20160141360 A1 US 20160141360A1 US 201414547181 A US201414547181 A US 201414547181A US 2016141360 A1 US2016141360 A1 US 2016141360A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 230000003647 oxidation Effects 0.000 title claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 35
- 125000006850 spacer group Chemical group 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000011810 insulating material Substances 0.000 claims abstract description 6
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- 239000012212 insulator Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N oxygen(2-);yttrium(3+) Chemical class [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052761 rare earth metal Inorganic materials 0.000 description 2
- 150000002910 rare earth metals Chemical class 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 229910052693 Europium Inorganic materials 0.000 description 1
- 229910052688 Gadolinium Inorganic materials 0.000 description 1
- 229910052772 Samarium Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- DRVWBEJJZZTIGJ-UHFFFAOYSA-N cerium(3+);oxygen(2-) Chemical class [O-2].[O-2].[O-2].[Ce+3].[Ce+3] DRVWBEJJZZTIGJ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- OGPBJKLSAFTDLK-UHFFFAOYSA-N europium atom Chemical compound [Eu] OGPBJKLSAFTDLK-UHFFFAOYSA-N 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- UIWYJDYFSGRHKR-UHFFFAOYSA-N gadolinium atom Chemical compound [Gd] UIWYJDYFSGRHKR-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- JVWJBBYNBCYSNA-UHFFFAOYSA-N lanthanum(3+) oxygen(2-) yttrium(3+) Chemical class [O--].[O--].[O--].[Y+3].[La+3] JVWJBBYNBCYSNA-UHFFFAOYSA-N 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- KZUNJOHGWZRPMI-UHFFFAOYSA-N samarium atom Chemical compound [Sm] KZUNJOHGWZRPMI-UHFFFAOYSA-N 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- XRFHCHCLSRSSPQ-UHFFFAOYSA-N strontium;oxygen(2-);titanium(4+) Chemical class [O-2].[O-2].[O-2].[Ti+4].[Sr+2] XRFHCHCLSRSSPQ-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
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- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
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- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66742—Thin film unipolar transistors
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- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Definitions
- the present invention relates generally to semiconductor devices, and more particularly to the formation of III-V semiconductor devices with starting layers which can be selectively oxidized.
- semiconductor devices involves forming electronic components in and on semiconductor substrates, such as silicon wafers. These electronic components may include one or more conductive layers, one or more insulation layers, and doped regions formed by implanting various dopants into portions of a semiconductor substrate to achieve specific electrical properties.
- Semiconductor devices include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the semiconductor devices to form integrated circuits.
- trench isolation structures To electrically isolate semiconductor devices from each other, various isolation techniques, such as trench isolation structures, have been used. Viewing the vertical direction as into the depth, or thickness, of a given substrate and the horizontal direction as being parallel to a top surface of the substrate, a trench isolation structure is vertically oriented to provide insulating separation between semiconductor devices at different horizontal locations. Traditionally, a semiconductor surface is etched to form separate device regions, and resulting trenches in between the separate device regions are filled with dielectric material to form the trench isolation structures.
- a semiconductor substrate may also employ semiconductor-on-insulator substrate arrangements, such as silicon-on-insulator (SOI) substrates.
- SOI silicon-on-insulator
- a semiconductor layer can be formed above an insulation layer which has been formed on the semiconductor substrate.
- Devices can be formed in the top semiconductor layer.
- the insulating layer provides isolation from the substrate, thereby decreasing capacitance effects for both devices and electrical connections.
- the top semiconductor layer can be etched, as described above, to provide trench isolation between device regions.
- Oxides such as strontium titanium oxides (e.g., SrTiO 3 ) and yttrium oxides (e.g., Y 2 O 3 ) have been grown on silicon substrates. More recently, epitaxial structures with closer lattice-matching have been grown, allowing for silicon substrate/epitaxial oxide/epitaxial silicon multi-layer structures.
- Grown epitaxial oxides with closer lattice-matching properties include oxides of rare earth metals and rare earth metal alloys, such as cerium, yttrium, lanthanum, samarium, gadolinium, europium, and combinations thereof (e.g., cerium oxides (CeO 2 ) and lanthanum yttrium oxides (La x Y 1-x ) 2 O 3 ).
- rare earth metals and rare earth metal alloys such as cerium, yttrium, lanthanum, samarium, gadolinium, europium, and combinations thereof (e.g., cerium oxides (CeO 2 ) and lanthanum yttrium oxides (La x Y 1-x ) 2 O 3 ).
- a method for fabricating a semiconductor device with selective oxidation comprising: providing a semiconductor substrate comprising a stack of two crystalline semiconductor layers, wherein the stack of two crystalline semiconductor layers are disposed on a top surface of the semiconductor substrate; depositing an insulating material on the semiconductor substrate; etching one or more recesses into the insulating material to form a set of fins; selectively oxidizing one of the two crystalline semiconductor layers; forming a dummy gate structure and a set of spacers along sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized crystalline semiconductor layer.
- a semiconductor structure comprising: a stack of two crystalline semiconductor layers grown on a starting semiconductor substrate, wherein the stack of two crystalline semiconductor layers comprises a first layer and a second layer; a plurality of fins patterned in the starting semiconductor substrate; a gate structure and a set of spacers, wherein a portion of the gate structure and the set of spacers are disposed around the plurality of fins; a source drain region formed adjacent to the gate structure; and a high-K dielectric material disposed around the gate structure.
- FIGS. 1A and 1B depict a plan view and a cross-sectional view of a starting semiconductor substrate on which a III-V device with selective oxidation may be formed, in accordance with an embodiment of the present invention
- FIGS. 2A-C depict a plan view and cross-sectional views of an embodiment where device regions are created on the starting substrate of FIGS. 1A and 1B through shallow trench isolation, in accordance with an embodiment of the present invention
- FIGS. 3A-C depict a plan view and cross-sectional views of the selective oxidation of one of the starting semiconductor substrate layers, in accordance with an embodiment of the present invention
- FIGS. 4A-C depict a plan view and cross-sectional views of the formation of dummy gates in the device regions created in FIGS. 2A-C , in accordance with an embodiment of the present invention
- FIGS. 5A-D depict a plan view and cross-sectional views of the formation of source and drain regions on either side of the dummy gates of FIGS. 4A-C , in accordance with an embodiment of the present invention
- FIGS. 6A-D depict a plan view and cross-sectional views of the deposition of an insulator layer over the device regions of FIGS. 2A-C , covering the source and drain regions of FIGS. 5A-D , and the subsequent planarization of the insulator layer to expose the tops of the dummy gates created in FIGS. 4A-C , in accordance with an embodiment of the present invention;
- FIGS. 7A-D depict a plan view and cross-sectional views of the removal of the dummy gates created in FIGS. 4A-C , in accordance with an embodiment of the present invention
- FIGS. 8A-D depict a plan view and cross-sectional views of the release of the selectively oxidized layer created in FIGS. 3A-C , in accordance with an embodiment of the present invention.
- FIGS. 9A-D depict a plan view and cross-sectional views of depositing a high-K dielectric and forming replacement gates between sets of sidewall spacers, in accordance with an embodiment of the present invention.
- Embodiments of the present invention provide a fabrication process for a III-V semiconductor device with crystalline starting layers which are subsequently selectively oxidized to become an insulator. Growing the starting layer as a semiconductor layer is less defective than growing a single crystal insulator starting layer.
- references in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures.
- the terms “on”, “over”, “overlying”, “atop”, “positioned on”, or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, may be present between the first element and the second element.
- FIG. 1A is a plan view of a starting substrate on which III-V devices with selective oxidation may be formed
- FIG. 1B is a cross-sectional view of FIG. 1A , taken along the line 1 B- 1 B.
- the starting substrate includes base layer(s) 102 , and may be composed of any crystalline material(s) known in the art.
- base layer(s) 102 includes a layer of Ge, which is approximately from 100 nm to 1 micrometer in thickness, on top of an insulator.
- a stack of two crystalline semiconductor layers, layer 104 and layer 106 are grown on the top surface of base layer(s) 102 .
- layer 104 is a single crystal semiconductor material composed of AlAs, and is approximately 10 nm in thickness. In other embodiments, layer 104 may be composed of any semiconductor material capable of being oxidized to a mechanically stable insulator.
- Layer 106 is a single crystal semiconductor layer, and may be composed of InGaAs, GaAs, III-V materials, or any other semiconducting material. In this exemplary embodiment, layer 106 is composed of InGaAs and is approximately 10 nm in thickness. As depicted in FIG. 1B , there are two stacks (i.e., grouping of one layer 104 and one layer 106 ) formed on the top surface of base layer(s) 102 . In other embodiments, more than two stacks or a single stack may be formed on the top surface of base layer(s) 102 .
- FIG. 2A is a plan view of the processing step of fin regions patterned on the starting substrate of FIGS. 1A and 1B
- FIG. 2B is a cross-sectional view of FIG. 2A , taken along the line 2 B- 2 B
- FIG. 2C is a cross-sectional view of FIG. 2A , taken along the line 2 C- 2 C.
- the fins are formed using a standard etch process.
- device regions are created through shallow trench isolation (STI) within the starting substrate.
- the shallow trenches are filled with one or more insulating materials 108 , such as SiO 2 , to isolate the fins from each other. This prevents electrical current leakage between adjacent semiconductor device components, preventing one device region from affecting another or shorting out through contact with another.
- FIG. 3A is a plan view of the processing step of selective oxidation of layer 104 of the starting substrate
- FIG. 3B is a cross-sectional view of FIG. 3A , taken along the line 3 B- 3 B
- FIG. 3C is a cross-sectional view of FIG. 3A , taken along the line 3 C- 3 C.
- the starting substrate is exposed at a temperature between 350° C. to 550° C. in water vapor, to selectively oxidize layer 104 (AlAs in this embodiment) to become oxidized layer 110 .
- the composition of layer 104 is initially chosen to be more readily oxidized than layer 106 , and also as a close lattice match to layer 106 .
- Oxidized layer 110 acts as an insulating layer within the stacked crystalline structure.
- oxidized layer 110 is composed of Al 2 O 3 .
- FIG. 4A is a plan view of the processing step of dummy gates 112 and sidewall spacers 113 in the fin regions on the starting substrate
- FIG. 4B is a cross-sectional view of FIG. 4A , taken along the line 4 B- 4 B
- FIG. 4C is a cross-sectional view of FIG. 4A , taken along the line 4 C- 4 C.
- Dummy gates 112 i.e., sacrificial gate structures
- source and drain regions 116 depictted in FIGS. 5A-D , may be selectively etched and replaced.
- One exemplary process for forming dummy gates 112 comprises depositing a dielectric layer over the starting substrate and a polysilicon layer over the dielectric layer.
- a lithography/gate etch process removes unnecessary portions of the stacked layers to leave dummy gates 112 , comprised of a gate oxide (not pictured) and polysilicon layer 114 .
- dummy gates 112 may be comprised of any material that can be etched selectively to the underlying upper semiconductor layer.
- a set of sidewall spacers 113 are formed adjacent to dummy gates 112 , i.e., in direct contact with the sidewall of dummy gate 112 .
- a sidewall spacer typically has a width ranging from 2 nm to 15 nm, as measured from the sidewall of a gate structure.
- Sidewall spacers 113 may be composed of a dielectric, such as a nitride, oxide, oxynitride, or a combination thereof.
- sidewall spacers 113 are composed of silicon nitride (Si 3 N x ). Those skilled in the art will recognize that a “set” of sidewall spacers 113 may actually comprise a single spacer formed around the entire gate.
- FIG. 5A is a plan view of the processing step of source and drain regions 116 formation
- FIG. 5B is a cross-sectional view of FIG. 5A , taken along the line 5 B- 5 B
- FIG. 5C is a cross-sectional view of FIG. 5A , taken along the line 5 C- 5 C
- FIG. 5D is a cross-sectional view of FIG. 5A , taken along the line 5 D- 5 D.
- Source and drain regions 116 formation includes a number of high-temperature steps (e.g., implants and anneals).
- source and drain regions 116 are formed using epitaxy.
- source and drain regions 116 are formed using an ion implantation process.
- FIG. 6A is a plan view of the processing step of depositing insulator 118
- FIG. 6B is a cross-sectional view of FIG. 6A , taken along the line 6 B- 6 B
- FIG. 6C is a cross-sectional view of FIG. 6A , taken along the line 6 C- 6 C
- FIG. 6D is a cross-sectional view of FIG. 6A , taken along the line 6 D- 6 D.
- Insulator 118 is planarized using a standard planarization method in the art, and may be deposited using, for example, chemical vapor deposition (CVD).
- CVD chemical vapor deposition
- CVD processes may also be used, including, but not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), and plasma enhanced CVD (PECVD). Other deposition techniques may also be used.
- Planarization is a material removal process that employs at least mechanical forces, such as frictional media, to produce a planar surface.
- the planarization process includes chemical mechanical polishing (CMP) or grinding.
- CMP is a material removal process which uses both chemical reactions and mechanical forces to remove material and planarize a surface.
- the preferred method for exposing polysilicon layer 114 is known as poly open planarization (POP) chemical mechanical planarization (CMP), or poly open CMP.
- FIG. 7A is a plan view of the processing step of the removal of dummy gates 112
- FIG. 7B is a cross-sectional view of FIG. 7A , taken along the line 7 B- 7 B
- FIG. 7C is a cross-sectional view of FIG. 7A , taken along the line 7 C- 7 C
- FIG. 7D is a cross-sectional view of FIG. 7A , taken along the line 7 D- 7 D.
- a first etch removes polysilicon layer 114 and is selective to sidewall spacers 113 .
- the etchant may be an isotropic etch or an anisotropic etch.
- One example of an isotropic etch is a wet chemical etch.
- the anisotropic etch may include reactive-ion etching (RIE).
- RIE reactive-ion etching
- Other examples of anisotropic etching that can be used during this process include ion beam etching, plasma etching, or laser ablation.
- FIG. 8A is a plan view of the processing step of the release of layer 110 (Al 2 O 3 )
- FIG. 8B is a cross-sectional view of FIG. 8A , taken along the line 8 B- 8 B
- FIG. 8C is a cross-sectional view of FIG. 8A , taken along the line 8 C- 8 C
- FIG. 8D is a cross-sectional view of FIG. 8A , taken along the line 8 D- 8 D.
- an etching process known in the art use of dilute HF, is used to etch layer 110 , in order to release layer 110 selective to sidewall spacers 113 , channel layer 106 , and dielectric insulator 118 .
- FIG. 9A is a plan view of the processing step of the deposition of high-K material 126 and formation of replacement gates 124
- FIG. 9B is a cross-sectional view of FIG. 9A , taken along the line 9 B- 9 B
- FIG. 9C is a cross-sectional view of FIG. 9A , taken along the line 9 C- 9 C
- FIG. 9D is a cross-sectional view of FIG. 9A , taken along the line 9 D- 9 D.
- High-K material 126 may be composed of, for example, HfO, ZrO, or TiO.
- Replacement gates 124 are formed between the existing sidewall spacers 113 , and may be composed of any metal, for example, W or Cu.
- High-K material 126 is deposited around the formed replacement gates 124 .
- Standard middle of the line and back end of the line (BEOL) processes known in the art may be performed to complete the semiconductor chip (not depicted).
- the fabrication steps depicted above may be included on a semiconductor substrate consisting of many devices and one or more wiring levels to form an integrated circuit chip.
- the resulting integrated circuit chip(s) can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- a single chip package such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier
- a multichip package such as a ceramic carrier that has either or both surface interconnections or buried interconnections.
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications, to advanced computer products having a display, a keyboard or other input device, and a central processor.
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Abstract
Description
- The present invention relates generally to semiconductor devices, and more particularly to the formation of III-V semiconductor devices with starting layers which can be selectively oxidized.
- The fabrication of semiconductor devices involves forming electronic components in and on semiconductor substrates, such as silicon wafers. These electronic components may include one or more conductive layers, one or more insulation layers, and doped regions formed by implanting various dopants into portions of a semiconductor substrate to achieve specific electrical properties. Semiconductor devices include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the semiconductor devices to form integrated circuits.
- To electrically isolate semiconductor devices from each other, various isolation techniques, such as trench isolation structures, have been used. Viewing the vertical direction as into the depth, or thickness, of a given substrate and the horizontal direction as being parallel to a top surface of the substrate, a trench isolation structure is vertically oriented to provide insulating separation between semiconductor devices at different horizontal locations. Traditionally, a semiconductor surface is etched to form separate device regions, and resulting trenches in between the separate device regions are filled with dielectric material to form the trench isolation structures.
- A semiconductor substrate may also employ semiconductor-on-insulator substrate arrangements, such as silicon-on-insulator (SOI) substrates. In a semiconductor on insulator arrangement, a semiconductor layer can be formed above an insulation layer which has been formed on the semiconductor substrate. Devices can be formed in the top semiconductor layer. The insulating layer provides isolation from the substrate, thereby decreasing capacitance effects for both devices and electrical connections. The top semiconductor layer can be etched, as described above, to provide trench isolation between device regions.
- Growing an epitaxial insulating layer on a semiconductor substrate is known. Oxides such as strontium titanium oxides (e.g., SrTiO3) and yttrium oxides (e.g., Y2O3) have been grown on silicon substrates. More recently, epitaxial structures with closer lattice-matching have been grown, allowing for silicon substrate/epitaxial oxide/epitaxial silicon multi-layer structures. Grown epitaxial oxides with closer lattice-matching properties include oxides of rare earth metals and rare earth metal alloys, such as cerium, yttrium, lanthanum, samarium, gadolinium, europium, and combinations thereof (e.g., cerium oxides (CeO2) and lanthanum yttrium oxides (LaxY1-x)2O3).
- According to one embodiment of the present invention, a method for fabricating a semiconductor device with selective oxidation is provided, the method comprising: providing a semiconductor substrate comprising a stack of two crystalline semiconductor layers, wherein the stack of two crystalline semiconductor layers are disposed on a top surface of the semiconductor substrate; depositing an insulating material on the semiconductor substrate; etching one or more recesses into the insulating material to form a set of fins; selectively oxidizing one of the two crystalline semiconductor layers; forming a dummy gate structure and a set of spacers along sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized crystalline semiconductor layer.
- According to another embodiment of the present invention, a semiconductor structure is provided, the semiconductor structure comprising: a stack of two crystalline semiconductor layers grown on a starting semiconductor substrate, wherein the stack of two crystalline semiconductor layers comprises a first layer and a second layer; a plurality of fins patterned in the starting semiconductor substrate; a gate structure and a set of spacers, wherein a portion of the gate structure and the set of spacers are disposed around the plurality of fins; a source drain region formed adjacent to the gate structure; and a high-K dielectric material disposed around the gate structure.
-
FIGS. 1A and 1B depict a plan view and a cross-sectional view of a starting semiconductor substrate on which a III-V device with selective oxidation may be formed, in accordance with an embodiment of the present invention; -
FIGS. 2A-C depict a plan view and cross-sectional views of an embodiment where device regions are created on the starting substrate ofFIGS. 1A and 1B through shallow trench isolation, in accordance with an embodiment of the present invention; -
FIGS. 3A-C depict a plan view and cross-sectional views of the selective oxidation of one of the starting semiconductor substrate layers, in accordance with an embodiment of the present invention; -
FIGS. 4A-C depict a plan view and cross-sectional views of the formation of dummy gates in the device regions created inFIGS. 2A-C , in accordance with an embodiment of the present invention; -
FIGS. 5A-D depict a plan view and cross-sectional views of the formation of source and drain regions on either side of the dummy gates ofFIGS. 4A-C , in accordance with an embodiment of the present invention; -
FIGS. 6A-D depict a plan view and cross-sectional views of the deposition of an insulator layer over the device regions ofFIGS. 2A-C , covering the source and drain regions ofFIGS. 5A-D , and the subsequent planarization of the insulator layer to expose the tops of the dummy gates created inFIGS. 4A-C , in accordance with an embodiment of the present invention; -
FIGS. 7A-D depict a plan view and cross-sectional views of the removal of the dummy gates created inFIGS. 4A-C , in accordance with an embodiment of the present invention; -
FIGS. 8A-D depict a plan view and cross-sectional views of the release of the selectively oxidized layer created inFIGS. 3A-C , in accordance with an embodiment of the present invention; and -
FIGS. 9A-D depict a plan view and cross-sectional views of depositing a high-K dielectric and forming replacement gates between sets of sidewall spacers, in accordance with an embodiment of the present invention. - The formation of nanowires on a Si substrate may be difficult when crystalline semiconductors are stacked on an insulator. Embodiments of the present invention provide a fabrication process for a III-V semiconductor device with crystalline starting layers which are subsequently selectively oxidized to become an insulator. Growing the starting layer as a semiconductor layer is less defective than growing a single crystal insulator starting layer. Detailed description of embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure.
- References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “on”, “over”, “overlying”, “atop”, “positioned on”, or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, may be present between the first element and the second element. The terms “direct contact”, “directly on”, or “directly over” mean that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating, or semiconductor layers at the interface of the two elements. The terms “connected” or “coupled” mean that one element is directly connected or coupled to another element, or intervening elements may be present. The terms “directly connected” or “directly coupled” mean that one element is connected or coupled to another element without any intermediary elements present.
- Referring now to the figures,
FIG. 1A is a plan view of a starting substrate on which III-V devices with selective oxidation may be formed, andFIG. 1B is a cross-sectional view ofFIG. 1A , taken along theline 1B-1B. The starting substrate includes base layer(s) 102, and may be composed of any crystalline material(s) known in the art. In this exemplary embodiment, base layer(s) 102 includes a layer of Ge, which is approximately from 100 nm to 1 micrometer in thickness, on top of an insulator. A stack of two crystalline semiconductor layers,layer 104 andlayer 106 are grown on the top surface of base layer(s) 102. In this exemplary embodiment,layer 104 is a single crystal semiconductor material composed of AlAs, and is approximately 10 nm in thickness. In other embodiments,layer 104 may be composed of any semiconductor material capable of being oxidized to a mechanically stable insulator.Layer 106 is a single crystal semiconductor layer, and may be composed of InGaAs, GaAs, III-V materials, or any other semiconducting material. In this exemplary embodiment,layer 106 is composed of InGaAs and is approximately 10 nm in thickness. As depicted inFIG. 1B , there are two stacks (i.e., grouping of onelayer 104 and one layer 106) formed on the top surface of base layer(s) 102. In other embodiments, more than two stacks or a single stack may be formed on the top surface of base layer(s) 102. - Referring now to
FIGS. 2A-C ,FIG. 2A is a plan view of the processing step of fin regions patterned on the starting substrate ofFIGS. 1A and 1B ,FIG. 2B is a cross-sectional view ofFIG. 2A , taken along theline 2B-2B, andFIG. 2C is a cross-sectional view ofFIG. 2A , taken along theline 2C-2C. The fins are formed using a standard etch process. Subsequent to the formation of the fins, device regions are created through shallow trench isolation (STI) within the starting substrate. In a preferred embodiment, the shallow trenches are filled with one or moreinsulating materials 108, such as SiO2, to isolate the fins from each other. This prevents electrical current leakage between adjacent semiconductor device components, preventing one device region from affecting another or shorting out through contact with another. - Referring now to
FIGS. 3A-3C ,FIG. 3A is a plan view of the processing step of selective oxidation oflayer 104 of the starting substrate,FIG. 3B is a cross-sectional view ofFIG. 3A , taken along theline 3B-3B, andFIG. 3C is a cross-sectional view ofFIG. 3A , taken along theline 3C-3C. The starting substrate is exposed at a temperature between 350° C. to 550° C. in water vapor, to selectively oxidize layer 104 (AlAs in this embodiment) to becomeoxidized layer 110. The composition oflayer 104 is initially chosen to be more readily oxidized thanlayer 106, and also as a close lattice match to layer 106.Oxidized layer 110 acts as an insulating layer within the stacked crystalline structure. In this exemplary embodiment, oxidizedlayer 110 is composed of Al2O3. - Referring now to
FIGS. 4A-4C ,FIG. 4A is a plan view of the processing step ofdummy gates 112 andsidewall spacers 113 in the fin regions on the starting substrate,FIG. 4B is a cross-sectional view ofFIG. 4A , taken along theline 4B-4B, andFIG. 4C is a cross-sectional view ofFIG. 4A , taken along theline 4C-4C. Dummy gates 112 (i.e., sacrificial gate structures) are formed and, after formation of source and drain regions 116 (depicted inFIGS. 5A-D ), may be selectively etched and replaced. One exemplary process for formingdummy gates 112 comprises depositing a dielectric layer over the starting substrate and a polysilicon layer over the dielectric layer. A lithography/gate etch process removes unnecessary portions of the stacked layers to leavedummy gates 112, comprised of a gate oxide (not pictured) andpolysilicon layer 114. Ultimately,dummy gates 112 may be comprised of any material that can be etched selectively to the underlying upper semiconductor layer. A set ofsidewall spacers 113 are formed adjacent todummy gates 112, i.e., in direct contact with the sidewall ofdummy gate 112. A sidewall spacer typically has a width ranging from 2 nm to 15 nm, as measured from the sidewall of a gate structure.Sidewall spacers 113 may be composed of a dielectric, such as a nitride, oxide, oxynitride, or a combination thereof. In one embodiment,sidewall spacers 113 are composed of silicon nitride (Si3Nx). Those skilled in the art will recognize that a “set” ofsidewall spacers 113 may actually comprise a single spacer formed around the entire gate. - Referring now to
FIGS. 5A-D ,FIG. 5A is a plan view of the processing step of source and drainregions 116 formation,FIG. 5B is a cross-sectional view ofFIG. 5A , taken along theline 5B-5B,FIG. 5C is a cross-sectional view ofFIG. 5A , taken along theline 5C-5C, andFIG. 5D is a cross-sectional view ofFIG. 5A , taken along theline 5D-5D. Source anddrain regions 116 formation includes a number of high-temperature steps (e.g., implants and anneals). In this exemplary embodiment, source and drainregions 116 are formed using epitaxy. In another embodiment, source and drainregions 116 are formed using an ion implantation process. - Referring now to
FIGS. 6A-6D ,FIG. 6A is a plan view of the processing step of depositinginsulator 118,FIG. 6B is a cross-sectional view ofFIG. 6A , taken along theline 6B-6B,FIG. 6C is a cross-sectional view ofFIG. 6A , taken along theline 6C-6C, andFIG. 6D is a cross-sectional view ofFIG. 6A , taken along theline 6D-6D.Insulator 118 is planarized using a standard planarization method in the art, and may be deposited using, for example, chemical vapor deposition (CVD). Variations of CVD processes may also be used, including, but not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), and plasma enhanced CVD (PECVD). Other deposition techniques may also be used. Following deposition ofinsulator 118,insulator 118 is planarized until the upper surfaces ofdummy gates 112 are exposed. Planarization is a material removal process that employs at least mechanical forces, such as frictional media, to produce a planar surface. In one embodiment, the planarization process includes chemical mechanical polishing (CMP) or grinding. CMP is a material removal process which uses both chemical reactions and mechanical forces to remove material and planarize a surface. The preferred method for exposingpolysilicon layer 114 is known as poly open planarization (POP) chemical mechanical planarization (CMP), or poly open CMP. - Referring now to
FIGS. 7A-7D ,FIG. 7A is a plan view of the processing step of the removal ofdummy gates 112,FIG. 7B is a cross-sectional view ofFIG. 7A , taken along theline 7B-7B,FIG. 7C is a cross-sectional view ofFIG. 7A , taken along theline 7C-7C, andFIG. 7D is a cross-sectional view ofFIG. 7A , taken along theline 7D-7D. Once the gate stack is exposed,dummy gates 112 are removed through a selective etch process, selective to the substrate/channel material andsidewall spacers 113. In this exemplary embodiment, a first etch removespolysilicon layer 114 and is selective tosidewall spacers 113. The etchant may be an isotropic etch or an anisotropic etch. One example of an isotropic etch is a wet chemical etch. The anisotropic etch may include reactive-ion etching (RIE). Other examples of anisotropic etching that can be used during this process include ion beam etching, plasma etching, or laser ablation. - Referring now to
FIGS. 8A-8D ,FIG. 8A is a plan view of the processing step of the release of layer 110 (Al2O3),FIG. 8B is a cross-sectional view ofFIG. 8A , taken along theline 8B-8B,FIG. 8C is a cross-sectional view ofFIG. 8A , taken along theline 8C-8C, andFIG. 8D is a cross-sectional view ofFIG. 8A , taken along theline 8D-8D. In this exemplary embodiment, an etching process known in the art, use of dilute HF, is used to etchlayer 110, in order to releaselayer 110 selective tosidewall spacers 113,channel layer 106, anddielectric insulator 118. - Referring now to
FIGS. 9A-D ,FIG. 9A is a plan view of the processing step of the deposition of high-K material 126 and formation ofreplacement gates 124,FIG. 9B is a cross-sectional view ofFIG. 9A , taken along theline 9B-9B,FIG. 9C is a cross-sectional view ofFIG. 9A , taken along theline 9C-9C, andFIG. 9D is a cross-sectional view ofFIG. 9A , taken along theline 9D-9D. High-K material 126 may be composed of, for example, HfO, ZrO, or TiO.Replacement gates 124 are formed between the existingsidewall spacers 113, and may be composed of any metal, for example, W or Cu. High-K material 126 is deposited around the formedreplacement gates 124. Standard middle of the line and back end of the line (BEOL) processes known in the art may be performed to complete the semiconductor chip (not depicted). - Having described the preferred embodiments of a method for selectively oxidizing layers within a III-V semiconductor device (which are intended to be illustrative and not limiting), it is noted that modifications and variations may be made by persons skilled in the art in light of the above teachings. It is, therefore, to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention, as outlined by the appended claims.
- In certain embodiments, the fabrication steps depicted above may be included on a semiconductor substrate consisting of many devices and one or more wiring levels to form an integrated circuit chip. The resulting integrated circuit chip(s) can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications, to advanced computer products having a display, a keyboard or other input device, and a central processor.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Claims (19)
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US14/547,181 US20160141360A1 (en) | 2014-11-19 | 2014-11-19 | Iii-v semiconductor devices with selective oxidation |
US15/136,048 US10367060B2 (en) | 2014-11-19 | 2016-04-22 | III-V semiconductor devices with selective oxidation |
US16/402,267 US10546926B2 (en) | 2014-11-19 | 2019-05-03 | III-V semiconductor devices with selective oxidation |
US16/752,574 US20200235207A1 (en) | 2014-11-19 | 2020-01-24 | Iii-v semiconductor devices with selective oxidation |
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US14/547,181 US20160141360A1 (en) | 2014-11-19 | 2014-11-19 | Iii-v semiconductor devices with selective oxidation |
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US15/136,048 Active 2035-04-01 US10367060B2 (en) | 2014-11-19 | 2016-04-22 | III-V semiconductor devices with selective oxidation |
US16/402,267 Active US10546926B2 (en) | 2014-11-19 | 2019-05-03 | III-V semiconductor devices with selective oxidation |
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US16/402,267 Active US10546926B2 (en) | 2014-11-19 | 2019-05-03 | III-V semiconductor devices with selective oxidation |
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US20190259834A1 (en) | 2019-08-22 |
US20160240613A1 (en) | 2016-08-18 |
US10546926B2 (en) | 2020-01-28 |
US20200235207A1 (en) | 2020-07-23 |
US10367060B2 (en) | 2019-07-30 |
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