CN104009070B - 用于鳍状场效应晶体管的金属栅极和栅极接触件结构 - Google Patents

用于鳍状场效应晶体管的金属栅极和栅极接触件结构 Download PDF

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CN104009070B
CN104009070B CN201310201889.5A CN201310201889A CN104009070B CN 104009070 B CN104009070 B CN 104009070B CN 201310201889 A CN201310201889 A CN 201310201889A CN 104009070 B CN104009070 B CN 104009070B
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CN104009070A (zh
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刘继文
王昭雄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了用于鳍状场效应晶体管的金属栅极和栅极接触件结构，其中本公开的实施例包括：衬底，衬底的一部分向上延伸形成鳍状物；覆盖鳍状物的顶面和侧壁的栅极介电层；覆盖栅极介电层的衬垫；以及位于覆盖栅极介电层的衬垫的一部分之上的连续金属部件，其中衬垫从连续金属部件的顶面开始延伸并覆盖金属部件的侧壁，栅极介电层、衬垫和连续金属部件共同形成栅极、栅极接触势垒和栅极接触件。本发明还公开了用于鳍状场效应晶体管的金属栅极和栅极接触件结构。

Description

用于鳍状场效应晶体管的金属栅极和栅极接触件结构
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及用于鳍状场效应晶体管的金属栅极和栅极接触件结构。
背景技术
由于集成电路（IC）尺寸减小的增长趋势以及对IC速度的日益苛刻的要求，晶体管需要在尺寸日益减小的情况下具有更高的驱动电流。因此，开发出了鳍状场效应晶体管（FinFET）。在典型的FinFET中，部分衬底被蚀刻掉以生成垂直的鳍状结构。这种垂直的鳍状结构被用于在横向上形成源极/漏极区，这会在鳍状物中形成沟道区。栅极沿垂直方向形成于鳍状物的沟道区域上以形成FinFET。随后，层间电介质（ILD）和多个互联层可以在FinFET上方形成。ILD包括栅极接触件，其通过多个互联层将栅极电连接至IC中的其他有源部件。
现有FinFET中的问题在于高接触阻抗。例如，典型的栅极可包括栅极介电层和覆盖栅极介电层的栅电极。FinFET中的栅电极包括功函金属层，当施加适当的偏置电压时，该功函金属层可使得FinFET在沟道区（即，鳍状物）中充电。遗憾的是，功函金属的接触阻抗相对较高。例如，栅极接触件还可包括覆盖接触件底面和侧壁的高阻抗扩散势垒层。功函金属和扩散势垒层的包含物是适当的FinFET功能性中的要素。然而，这些层的相对较高的接触阻抗组合并可在器件中产生不需要的高接触阻抗。
发明内容
根据本发明的一方面，提供一种集成电路（IC）结构，包括：衬底；位于所述衬底之上并连接于所述衬底的半导体带，其中，所述半导体带的顶部形成鳍状物；位于所述衬底之上的第一层间电介质（ILD），其中，所述鳍状物延伸进入所述第一ILD；位于所述第一ILD之上的第二ILD，其中，所述鳍状物不延伸进入所述第二ILD；衬垫，从所述第二ILD的顶面延伸进入所述第一ILD并位于所述鳍状物的顶面和侧壁之上；所述第一ILD中位于所述鳍状物之上的信号金属，其中，所述衬垫的一部分位于所述信号金属和所述鳍状物之间；以及所述第二ILD中位于所述信号金属之上并连接于所述信号金属的栅极接触件，其中，所述衬垫覆盖所述栅极接触件的侧壁，所述栅极接触件和所述信号金属形成连续金属区。
优选地，所述IC结构不包括单独的栅极接触势垒或者单独的功函金属。
优选地，所述的IC结构还包括位于所述衬垫之下并位于所述鳍状物的顶面和侧壁之上的栅极介电层。
优选地，所述的IC结构还包括位于所述栅极介电层和所述鳍状物之间的界面层。
优选地，所述的IC结构还包括在所述第一ILD和所述衬底之间设置在所述半导体带的相反侧上的第一介电区和第二介电区，其中，所述半导体带中形成所述鳍状物的部分延伸超出所述第一介电区和所述第二介电区。
优选地，所述衬垫由氮化钛、氮化钽、钛铝或它们的组合形成。
优选地，所述连续金属区由钨、铝、铜或它们的组合形成。
根据本发明的第二方面，本发明提供一种集成电路（IC）结构，包括：衬底，所述衬底的一部分向上延伸形成鳍状物；栅极介电层，位于所述鳍状物的顶面和侧壁之上；覆盖所述栅极介电层的衬垫；以及连续金属部件，位于覆盖所述栅极介电层的所述衬垫的一部分之上，所述衬垫从所述连续金属部件的顶面开始延伸并覆盖所述金属部件的侧壁，所述栅极介电层、所述衬垫和所述连续金属部件共同形成栅极、栅极接触势垒和栅极接触件。
优选地，所述栅极不包括单独的功函金属，并且所述栅极接触件不包括单独的栅极接触势垒。
优选地，所述的IC结构还包括位于所述鳍状物和所述栅极介电层之间的界面层。
优选地，所述衬垫由氮化钛、氮化钽或它们的组合形成。
优选地，所述连续金属部件由钨、铝、铜或它们的组合形成。
优选地，所述栅极介电层由氧化硅、氮化硅、具有高k值的介电材料或它们的组合形成。
根据本发明的第三方面，提供一种用于形成集成电路（IC）结构的方法，包括：蚀刻衬底以形成鳍状物；形成位于所述鳍状物的顶面和至少部分侧壁之上的栅极介电层；在所述栅极介电层上方形成伪栅极；在所述伪栅极上方形成层间电介质（ILD）；图案化所述ILD以在所述ILD中生成开口，以暴露部分所述伪栅极；移除所述伪栅极；形成覆盖所述开口的底面和侧壁的衬垫；以及由金属材料填充所述开口，其中所述栅极介电层、所述衬垫和所述金属材料共同形成栅极、栅极接触势垒和栅极接触件。
优选地，所述栅极介电层形成在介电层上方，并且所述方法还包括：在蚀刻所述衬底以形成鳍状物之后，在所述衬底之上于所述鳍状物的两侧形成所述介电层；以及使所述介电层凹进以暴露所述鳍状物。
优选地，所述的用于形成集成电路（IC）结构的方法，还包括：在移除所述伪栅极之后，移除所述栅极介电层并在所述开口中形成位于所述鳍状物的顶面和至少部分侧壁之上的新栅极介电层。
优选地，所述的用于形成集成电路（IC）结构的方法，还包括由氮化钛、氮化钽、钛铝或它们的组合来形成所述衬垫。
优选地，形成所述衬垫的步骤包括采用化学汽相沉积方法。
优选地，形成所述衬垫的步骤包括采用原子层沉积方法。
优选地，所述的用于形成集成电路（IC）结构的方法不包括在所述IC结构中形成单独的栅极势垒或者功函金属。
附图说明
为了更好地理解本发明实施例及其优点，现在结合附图参考以下说明，其中：
图1至图10是根据多个实施例的集成电路（IC）结构的中间制造阶段的截面图。
具体实施方式
下面，详细讨论本发明实施例的制造和使用。然而，应该理解，本公开提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出制造和使用本发明的具体方式，而不用于限制不同实施例的范围。
集成电路（IC）结构的实施例会关于具体环境进行描述，即鳍状场效应晶体管（FinFET）。其他晶体管结构（诸如，隧道场效应晶体管或纳米线场效应晶体管）和类似结构均在本公开的考虑范围内。FinFET可包括在微处理器、存储单元和/或其他集成电路（IC）中。
图1至图10示出了根据多个实施例的集成电路（IC）结构100的各个制造阶段的截面图。其中，截面图为穿过鳍状物而非源极/漏极区而截取的。正如在本公开的所使用的，术语集成电路（IC）结构100指代鳍状场效应晶体管（FinFET）100。FinFET100指代任意基于鳍状的多栅极晶体管。首先，形成具有覆盖栅极电介质的伪栅极的FinFET100。层间电介质（ILD）在FinFET100上方形成并被图案化以使得伪栅极暴露。然后移除伪栅极。随后形成势垒层以覆盖栅极电介质和ILD的侧壁。填充ILD的图案化开口，同时可完成栅极结构并形成栅极接触件。势垒层既充当接触势垒层又充当功函金属。因此，可删除栅极结构中的其中一个高阻抗层，这样会降低器件中的整体接触阻抗。
图1示出了FinFET100的截面图，其包括衬底102。衬底102可以是块状衬底或者绝缘体上半导体（SOI）衬底。衬底102可以由硅或者锗化硅形成，然而还可以使用包括III族、IV族和V族元素的其他半导体材料。
缓冲层104和掩模106可以在衬底102上形成。缓冲层104可例如采用热氧化处理由氧化硅形成。缓冲层104可充当粘合层并降低衬底102和掩模106之间的应变。缓冲层104可进一步充当用于蚀刻掩模106的蚀刻终止层。掩模106可例如采用低压化学汽相沉积（LPCVD）、硅的热氮化、等离子体增强化学汽相沉积（PECVD）或者等离子体阳极氮化由氧化硅形成。掩模106在后续的光刻处理期间用作硬掩模。光刻胶层108在掩模106上方形成并被图案化，这样会暴露部分下层掩模106。
现参照图2，通过光刻胶层108中的开口来蚀刻掩模106和缓冲层104。然后蚀刻衬底102，这样会形成鳍状物110。尽管在图2中仅示出了一个鳍状物110，但是替代的实施例包括在同一处理步骤中形成多个鳍状物（例如，形成多鳍finFET或同时形成多个finFET）。随后移除光刻胶层108。可选地，鳍状物还可以通过在衬底102上方沉积氧化层（例如，氧化硅）、图案化氧化层并使鳍状物外延生长来形成。
在图3中，介电层112沉积在衬底102上方。介电层112可以由氧化硅形成，然而还可以使用诸如SiN、SiC等的其他介电材料。介电层112可以是沉积在衬底102上方的覆盖层。在包括多个鳍状物的多种实施例中，介电层112可充当隔离层以隔离各个鳍状物。在介电层112上进行化学机械抛光（CMP），使得介电层112的顶面与鳍状物110的顶面齐平。
图4示出了介电层112的凹进，该凹进可例如通过蚀刻来完成。作为凹进的结果，鳍状物110的一部分暴露出来以延伸超出介电层112的顶面。当FinFET100完全形成时，鳍状物110的超出介电层112的顶面的部分充当沟道区。
图5示出栅极介电层114和伪栅极116在鳍状物110上方形成。栅极介电层114可以由二氧化硅、氮化硅或者高k介电材料（其k值例如大于7.0）形成。高k介电材料可包括金属氧化物。用于高k介电材料的金属氧化物的实例可包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物及其混合物。在一些实施例中，栅极介电层114的厚度在大约5至30范围内。栅极介电层114可通过热氧化方法在鳍状物110的顶面和侧壁上形成，或者其可以是沉积在鳍状物110上方的覆盖层。在可选的实施例中，界面层（未示出）可以在鳍状物110和栅极介电层114之间形成。界面层可包括氧化硅并充当栅极介电层114和衬底102之间的粘合/缓冲层。伪栅极116在栅极介电层114上方形成。伪栅极116可以由多晶硅、非晶硅等形成。注意，功函金属层并不由栅极介电层114和伪栅极116形成。
图6示出了栅极间隔件118和第一层间电介质（ILD）120的形成。栅极间隔件118可以由氧化硅、氮化硅等形成。第一ILD120可以由氧化硅、磷硅玻璃（PSG）、硼磷硅玻璃（BPSG）等形成。第一ILD120可以为沉积在介电层112和栅极间隔件118上方的覆盖层。随后，FinFET100的剩余部分（包括源极/漏极区和源极/漏极硅化物（未示出））在横向上形成。这些部件的形成过程为本领域技术人员所知，所以不包括在本文中。
在图7中，第二ILD122在第一ILD120、栅极间隔件118和伪栅极116上方形成。第二ILD122可以由与第一ILD120基本相同的材料以基本相同的技术形成。可选地，第二ILD122可以由与第一ILD120不同的材料形成。例如，第一ILD120可以由PSG形成，第二ILD122可以由氧化硅形成。第二ILD122被图案化以形成开口124，其可使下层伪栅极116暴露。开口124可以例如采用光刻技术与蚀刻技术的结合来形成。
图8示出了伪栅极116的移除。伪栅极116可例如采用湿蚀刻工艺和/或干蚀刻工艺移除。在至少一个实施例中，用于移除伪栅极116的湿蚀刻工艺包括暴露于包含氢氧化铵的氢氧化物溶液、稀释的氢氟酸、去离子水和/或其它适当的蚀刻剂溶液中。在其它实施例中，用于移除伪栅极116的干蚀刻工艺可以在电源功率约为650至800W、偏置功率约为100至120W、以及压力约为60至200mTorr并使用Cl2、HBr和He作为蚀刻气体的条件下执行。在可选的实施例中，栅极介电层114还可以伴随着伪栅极116的移除而移除。然后，新的栅极介电层可以由与栅极介电层114基本相同的材料并使用与先前形成栅极介电层114基本相同的技术在鳍状物110上重新形成。开口124因此扩张以包括由ILD120中的伪栅极116先前所占据的空间。
图9示出了衬垫126在开口124中的形成。衬垫126可由氮化钛、氮化钽、钛铝等形成。衬垫126可以例如由化学汽相沉积（CVD）、电镀、原子层沉积（ALD）或其他适当的技术形成。在某些实施例中，衬垫126的厚度在大约3至大约20范围内。衬垫126覆盖开口124的横向表面和侧壁。衬垫126还可覆盖ILD122的顶面。衬垫126为单层，其既充当接触势垒层又充当功函金属。即，当FinFET100导通时，衬垫126使得鳍状物110充电。同时，衬垫126防止栅极接触件（在随后的工艺步骤中形成）的金属元素扩散至周围介电层中。在现有的FinFET中可以发现，接触势垒层和功函金属可以由相同材料（例如，氮化钛、氮化钽或钛铝）形成。因此，功函金属和接触势垒层可以结合成单个衬垫。
接触势垒层与功函金属在衬垫126中的结合消除了FinFET100中的高阻抗层。因此，降低了FinFET100的整体接触阻抗。
图10示出了接触件128在开口124中的形成。开口124被填充以生成接触件128。接触件128可以由钨、铝或铜形成，然而还可以使用其他金属材料。接触件128和衬垫126可经历CMP以移除衬垫126超出第二ILD122的部分。CMP还会使得接触件128的顶面与ILD122的顶面齐平。衬垫126充当势垒层并有助于防止接触件128的金属元素扩散至第二ILD122中。同时，衬垫126充当功函金属。
与衬垫126相比，接触件128具有相对低的阻抗。此外，接触件128的位于第一ILD120中的部分在传统FinFET结构中充当栅电极的部分。即，接触件128的位于ILD120中的部分充当FinFET100的信号金属（signal metal）。因此，接触件128在FinFET100中既作为栅极接触件又作为栅电极的一部分。栅极介电层114、衬垫126和接触件128共同形成FinFET100中的栅极、栅极接触件和栅极接触势垒。尽管所示FinFET100为单鳍FinFET（即，栅极在单鳍上方形成），但是多种实施例也可以应用至多鳍FinFET。
根据一个实施例，集成电路（IC）结构包括衬底以及位于衬底之上并连接于衬底的半导体带（semiconductor strip）。半导体带的顶部形成鳍状物。IC结构还包括衬底之上的第一层间电介质（ILD）和第一ILD之上的第二ILD。鳍状物延伸进入第一ILD，但是鳍状物并不延伸进入第二ILD。衬垫从第二ILD的顶面延伸进入第一ILD并位于鳍状物的顶面和侧壁之上。第一ILD中的信号金属和第二ILD中的位于信号金属之上并连接于信号金属的栅极接触件也包括在IC结构中。衬垫在信号金属和鳍状物之间延伸，并且衬垫覆盖栅极接触件的侧壁。栅极接触件和信号金属形成连续金属区。
根据另一个实施例，集成电路（IC）结构包括衬底。衬底的一部分向上延伸形成鳍状物。栅极介电层设置为覆盖鳍状物的顶面和侧壁。衬垫覆盖栅极介电层。连续金属部件位于覆盖栅极介电层的衬垫的一部分之上。衬垫从连续金属部件的顶面开始延伸并覆盖金属部件的侧壁。另外，栅极介电层、衬垫和连续金属部件共同形成栅极、栅极接触势垒和栅极接触件。
根据又一个实施例，一种用于形成集成电路（IC）结构的方法包括：蚀刻衬底以形成鳍状物；在鳍状物的顶面和至少部分侧壁上形成栅极介电层；在栅极介电层上方形成伪栅极；在伪栅极上方形成层间电介质（ILD）；图案化ILD以在ILD中生成开口；暴露部分伪栅极；移除伪栅极；扩张开口以暴露栅极介电层；形成覆盖开口底面和侧壁的衬垫；以及由金属材料填充开口。栅极介电层、衬垫和金属材料共同形成栅极、栅极接触势垒和栅极接触件。
尽管已经详细地描述了本实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本公开主旨和范围的情况下，做各种不同的改变、替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、器件、方法和步骤的特定实施例。本领域普通技术人员通过本发明应理解，现有的或今后开发的用于执行与本文所采用的相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、器件、方法或步骤根据本发明可以被使用。因此，所附权利要求的范围应该包括这样的工艺、机器、制造、材料组分、器件、方法或步骤。

Claims (20)

1.一种集成电路结构，包括：
衬底；
位于所述衬底之上并连接于所述衬底的半导体带，其中，所述半导体带的顶部形成鳍状物；
位于所述衬底之上的第一层间电介质，其中，所述鳍状物延伸进入所述第一层间电介质；
位于所述第一层间电介质之上的第二层间电介质，其中，所述鳍状物不延伸进入所述第二层间电介质；
衬垫，从所述第二层间电介质的顶面延伸进入所述第一层间电介质并位于所述鳍状物的顶面和侧壁之上；
所述第一层间电介质中位于所述鳍状物之上的信号金属，其中，所述衬垫的一部分位于所述信号金属和所述鳍状物之间；以及
所述第二层间电介质中位于所述信号金属之上并连接于所述信号金属的栅极接触件，其中，所述衬垫覆盖所述栅极接触件的侧壁，所述栅极接触件和所述信号金属形成连续金属区。
2.根据权利要求1所述的集成电路结构，其中，所述集成电路结构不包括单独的栅极接触势垒或者单独的功函金属。
3.根据权利要求1所述的集成电路结构，还包括位于所述衬垫之下并位于所述鳍状物的顶面和侧壁之上的栅极介电层。
4.根据权利要求3所述的集成电路结构，还包括位于所述栅极介电层和所述鳍状物之间的界面层。
5.根据权利要求1所述的集成电路结构，还包括在所述第一层间电介质和所述衬底之间设置在所述半导体带的相反侧上的第一介电区和第二介电区，其中，所述半导体带中形成所述鳍状物的部分延伸超出所述第一介电区和所述第二介电区。
6.根据权利要求1所述的集成电路结构，其中，所述衬垫由氮化钛、氮化钽、钛铝或它们的组合形成。
7.根据权利要求1所述的集成电路结构，其中，所述连续金属区由钨、铝、铜或它们的组合形成。
8.一种集成电路结构，包括：
衬底，所述衬底的一部分向上延伸形成鳍状物；
位于所述衬底之上的第一层间电介质；
位于所述第一层间电介质之上的第二层间电介质；
衬垫，从所述第二层间电介质的顶面延伸进入所述第一层间电介质并位于所述鳍状物的顶面和侧壁之上；
栅极介电层，位于所述鳍状物的顶面和侧壁之上；
覆盖所述栅极介电层的衬垫；以及
连续金属部件，位于覆盖所述栅极介电层的所述衬垫的一部分之上，所述衬垫从所述连续金属部件的顶面开始延伸并覆盖所述金属部件的侧壁，所述栅极介电层、所述衬垫和所述连续金属部件共同形成栅极、栅极接触势垒和栅极接触件。
9.根据权利要求8所述的集成电路结构，其中，所述栅极不包括单独的功函金属，并且所述栅极接触件不包括单独的栅极接触势垒。
10.根据权利要求8所述的集成电路结构，还包括位于所述鳍状物和所述栅极介电层之间的界面层。
11.根据权利要求8所述的集成电路结构，其中，所述衬垫由氮化钛、氮化钽或它们的组合形成。
12.根据权利要求8所述的集成电路结构，其中，所述连续金属部件由钨、铝、铜或它们的组合形成。
13.根据权利要求8所述的集成电路结构，其中，所述栅极介电层由氧化硅、氮化硅、具有高k值的介电材料或它们的组合形成。
14.一种用于形成集成电路结构的方法，包括：
蚀刻衬底以形成鳍状物；
形成位于所述鳍状物的顶面和至少部分侧壁之上的栅极介电层；
在所述栅极介电层上方形成伪栅极；
在所述伪栅极上方形成第一层间电介质；
在所述第一层间电介质和所述伪栅极上方形成第二层间电介质；
图案化所述第二层间电介质以在所述第二层间电介质中生成开口，以暴露部分所述伪栅极；
移除所述伪栅极；
形成覆盖所述开口的底面和侧壁的衬垫，所述衬垫从所述第二层间电介质的顶面延伸进入所述第一层间电介质并位于所述鳍状物的顶面和侧壁之上；以及
由金属材料填充所述开口，其中所述栅极介电层、所述衬垫和所述金属材料共同形成栅极、栅极接触势垒和栅极接触件。
15.根据权利要求14所述的方法，其中，所述栅极介电层形成在介电层上方，并且所述方法还包括：在蚀刻所述衬底以形成鳍状物之后，
在所述衬底之上于所述鳍状物的两侧形成所述介电层；以及
使所述介电层凹进以暴露所述鳍状物。
16.根据权利要求14所述的方法，还包括：在移除所述伪栅极之后，移除所述栅极介电层并在所述开口中形成位于所述鳍状物的顶面和至少部分侧壁之上的新栅极介电层。
17.根据权利要求14所述的方法，还包括由氮化钛、氮化钽、钛铝或它们的组合来形成所述衬垫。
18.根据权利要求14所述的方法，其中，形成所述衬垫的步骤包括采用化学汽相沉积方法。
19.根据权利要求14所述的方法，其中，形成所述衬垫的步骤包括采用原子层沉积方法。
20.根据权利要求14所述的方法，其中，所述方法不包括在所述集成电路结构中形成单独的栅极势垒或者功函金属。
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