CN111613676B - 一种具有层叠结构的多栅指数晶体管及其制备方法 - Google Patents

一种具有层叠结构的多栅指数晶体管及其制备方法 Download PDF

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CN111613676B
CN111613676B CN202010281186.8A CN202010281186A CN111613676B CN 111613676 B CN111613676 B CN 111613676B CN 202010281186 A CN202010281186 A CN 202010281186A CN 111613676 B CN111613676 B CN 111613676B
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马顺利
吴天祥
任俊彦
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Abstract

本发明属于晶体管技术领域,具体为一种具有层叠结构的多栅指数晶体管。本发明多栅指数晶体管,依次由漏极、沟道、源极、沟道循环层叠构成,所有的沟道宽度均大于源漏宽度,在沟道右侧未被源漏覆盖的最右侧区域,分别形成栅氧化层和栅极,并且所有的栅极通过栅极金属相连接,以此形成统一的栅极;沟道以二维材料制备,多沟道受到统一栅极的调控;该晶体管沟道长度较小,电流流动方向沟道面积较大,因此沟道电流较大。并且所有的沟道受到统一的栅极调控,栅控能力强,集成度高,可应用于新型电子器件和医疗领域。

Description

一种具有层叠结构的多栅指数晶体管及其制备方法
技术领域
本发明属于晶体管技术领域,具体涉及具有层叠结构的多栅指数晶体管及其制备方法。
背景技术
从最基本的电子电路到最复杂的集成电路,晶体管始终是现代电子学中最重要的组成部分,并且已经有超过 80 年的发展历史。金属氧化物半导体场效应晶体管(MOSFET)自 1960 年在贝尔实验室问世以来,作为一种科学家致力研究的器件结构,已经推动了整个半导体集成电路产业按照摩尔定律迅猛发展。实际上,随着芯片的集成度越来越高,芯片上的晶体管数量接近极限,并且遇到了一些关键性的困难。近年来,科学家们发现二维材料的厚度非常薄,因此会拥有非常大的比表面积,这就有潜力制备高性能的器件。并且二维半导体材料与传统的硅不同,其优势在于薄,可以提高集成度;其次,随着石墨烯和二硫化钼等材料的发现,研究人员以此制备出了许许多多高性能的晶体管,有望在不久的将来得到重要的应用。
随着研究的进展,二维材料因其薄的特性,可以做成很多层材料,因此以二维材料为沟道的薄膜晶体管可以做成层叠结构,这样一方面有利于提高集成度,另一方面可以满足特殊场合下大电流的需求。同时与传统的硅基晶体管相比,以二维材料做制备的晶体管可以实现柔性化,随着社会信息化的加速,人与信息的有机融合是未来的发展趋势,而作为信息载体的各种微电子器件一旦实现柔性化,将从本质上促进人与信息的高效交流。近些年来,随着二维材料的研究进展,人们有望将基于二维材料所制备的晶体管应用在大规模集成电路领域。
发明内容
本发明的目的在于提出一种实现大电流、高集成度的具有层叠结构的多栅指数晶体管。
本发明提供的具有层叠结构的多栅指数晶体管,其结构为:依次以漏极、沟道、源极、沟道循环层叠,所有的沟道宽度均大于源漏宽度,在沟道右侧未被源漏覆盖的最右侧区域,分别形成栅氧化层和栅极,并且所有的栅极通过栅极金属相连接,以此形成统一的栅极。
本发明中,所述沟道以二维材料制备,多沟道受到统一栅极的调控,各层晶体管的栅极通过统一的栅极金属相连,相比较传统的二维材料器件沟道,具有更小的沟道长度(几十纳米),以及相对更大的沟道面积(相较于原有工艺增加至少上百倍以上)。
上述具有层叠结构的多栅指数晶体管,其制备方法包括:
(1)制备单栅指数晶体管,其沟道受到右侧栅极的调控;即在源漏之间有一个以二维材料所制备的沟道,其沟道长度较小,沟道宽度大于源和漏的宽度,在沟道右侧上方形成栅氧化层和栅极。源极、漏极和栅极材料可以为金属,如金;
(2)制备单栅指数环栅结构晶体管,即在上述单栅指数晶体管的基础上,为了进一步加强栅控能力,制备环栅结构;即在沟道右侧的三个方向:上方、下方以及右方形成栅氧化层和栅极,提高栅控能力;
(3)制备单栅指数双沟道晶体管,该晶体管具有两层结构,采用一个栅极对两个沟道进行控制;具体来说,采用堆叠结构,从上至下依次是漏极、沟道、源极、沟道和漏极,该结构共有两个沟道。其沟道长度较小,沟道宽度大于源漏宽度,在两个沟道右侧中间区域从上至下依次形成栅氧化层、栅极和栅氧化层,其两个沟道受到同一个栅极的控制;
(4)根据二维材料可堆叠的特性,制备具有层叠结构的多栅指数晶体管,即形成多指结构,所述多指即为多个沟道,并且多沟道受到统一栅极的控制,如图4所示。这样可优化晶体管结构,实现大电流、高集成度的特性。
本发明还涉及具有层叠结构的单栅指数晶体管,具有层叠结构的单栅指数环栅结构晶体管,具有层叠结构的单栅指数双沟道晶体管,依次如图1、图2、图3所示。
本发明的具有层叠结构的多栅指数晶体管,具有如下特点:
(1)各层晶体管的沟道由二维材料制备,其优势在于对于柔性器件的潜在应用;
(2)各层晶体管的栅极由统一的栅极金属相连,既节约了面积,提高了集成度,也相对较好的实现栅极对沟道的调控能力;
(3)较大面积的沟道和较小的沟道长度,实现较大的沟道电流;
(4)二维材料的可堆叠性使得本发明具有更高的集成度和拓展性。
附图说明
图1为具有层叠结构的单栅指数晶体管结构1示意图。
图2为具有层叠结构的单栅指数晶体管结构2示意图。
图3为具有层叠结构的单栅指数晶体管结构3示意图。
图4为具有层叠结构的多栅指数晶体管结构示意图。
具体实施方式
下面结合附图对本发明一种具有层叠结构的晶体管进行详细说明。在各个附图中,相同的结构采用类似的附图标记来表示。为了清楚起见,附图中的各个部分没有按比例绘制。此外,在图中可能未示出某些公知的部分。
在下文中描述了本发明的许多特定的细节,例如器件的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本发明。
图1示出本发明具有层叠结构的单栅指数晶体管结构1示意图。
如图1所示,晶体管100结构图中,其左图为剖面图,右图为立体结构图。晶体管100的源和漏中间是沟道,沟道长度要大于源和漏的长度,在沟道外侧分别生长有栅氧化层和栅极,沟道由二维材料构成(如MoS2),源极、漏极和栅极均由金属构成(如Au),而栅氧化层则由high k介质HfO2构成。图中L为沟道长度大小,X和Y为有效沟道截面的宽度和长度。由于L较小,电流只需流过很短的一段距离,因此该结构的沟道电流较大。
图2示出本发明具有层叠结构的单栅指数晶体管结构2示意图。
本发明的器件2结构如附图2所示,在晶体管200结构图中,其左图为剖面图,右图为立体结构图。与晶体管100的主要区别在于晶体管200采用一种环栅的结构,其栅氧化层和栅极包围着部分沟道,使得栅控能力更强,即栅极对沟道电流大小的控制能力更好。与晶体管100一样,沟道由二维材料构成(如MoS2),源极、漏极和栅极均由金属构成(如Au),而栅氧化层则由high k介质HfO2构成。图中L为沟道长度大小,X和Y为有效沟道截面的宽度和长度。
图3示出本发明具有层叠结构的单栅指数晶体管结构3示意图。
如图3所示,在晶体管300结构图中,同样其左图为剖面图,右图为立体结构图。在晶体管200的基础上,利用二维材料可堆叠的特性,制备了两个沟道,类似于两个晶体管的堆叠,好处在于由同一个栅极同时调控两个沟道,可以简化工艺和实现高集成度。与晶体管100一样,沟道由二维材料构成(如MoS2),源极、漏极和栅极均由金属构成(如Au),而栅氧化层则由high k介质HfO2构成。图中L为沟道长度大小,X和Y为有效沟道截面的宽度和长度。
图4示出本发明具有层叠结构的多栅指数晶体管结构示意图。
具有层叠结构的多栅指数晶体管结构示意图如图4所示,从晶体管400器件结构剖面图可以看出,该结构采用的是一种多指的结构,各栅极在右侧通过栅极金属统一连接起来,从而方便在栅极施加电压,各沟道均会受到统一栅极的控制。右图为立体结构图,图中仅显示了三层的器件结构,其结构依次以漏极、沟道、源极、沟道循环,以此类推,根据该结构还可以形成更多层的结构。与晶体管100一样,沟道由二维材料构成(如MoS2),源极、漏极和栅极均由金属构成(如Au),而栅氧化层则由high k介质HfO2构成。图中L为沟道长度大小,X和Y为有效沟道截面的宽度和长度。
本发明为一种具有层叠结构的晶体管,该结构最大的好处是沟道短,相较于传统工艺,沟道的横截面积更大,因此沟道电流更大。并且该结构由统一的栅极对多沟道进行调制,从而易于集成,可应用于可穿戴设备。
本发明的内容及优点虽然已详细揭示如上,然而必须说明的是,本发明的范围并不受限于说明书中所描述的方法及步骤等特定实施例,在不脱离本发明的精神和范围内,任何本领域普通技术人员皆可根据本发明所揭示的内容做出许多变形和修改,这些也应视为本发明的保护范围。

Claims (1)

1.一种具有层叠结构的多栅指数晶体管的制备方法,其特征在于,该多栅指数晶体管依次以漏极、沟道、源极、沟道循环层叠构成,所有的沟道宽度均大于源漏宽度,在沟道右侧未被源漏覆盖的最右侧区域,分别形成栅氧化层和栅极,并且所有的栅极通过栅极金属相连接,以此形成统一的栅极;所述沟道以二维材料制备,多沟道受到统一栅极的调控,各层晶体管的栅极通过统一的栅极金属相连,具有较小的沟道长度,以及相对较大的沟道面积;
具体步骤为:
(1)制备单栅指数晶体管,其沟道受到右侧栅极的调控;即在源漏之间有一个以二维材料所制备的沟道,其沟道长度较小,沟道宽度大于源和漏的宽度,在沟道右侧上方形成栅氧化层和栅极;源极、漏极和栅极材料为金属;
(2)制备单栅指数环栅结构晶体管,即在上述单栅指数晶体管的基础上,制备环栅结构;即在沟道右侧的三个方向:上方、下方以及右方形成栅氧化层和栅极,以提高栅控能力;
(3)制备单栅指数双沟道晶体管,采用两层堆叠结构,从上至下依次是漏极、沟道、源极、沟道和漏极,该结构共有两个沟道;其沟道长度较小,沟道宽度大于源漏宽度,在两个沟道右侧中间区域从上至下依次形成栅氧化层、栅极和栅氧化层,其两个沟道受到同一个栅极的控制;
(4)制备具有层叠结构的多栅指数晶体管,即形成多指结构,所述多指即为多个沟道,并且多沟道受到统一栅极的控制。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115602690A (zh) * 2022-10-12 2023-01-13 武汉华星光电技术有限公司(Cn) 显示面板

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1487599A (zh) * 2002-10-01 2004-04-07 ���ǵ�����ʽ���� 具有多个叠置沟道的场效应晶体管
CN102201442A (zh) * 2011-04-02 2011-09-28 中国科学院苏州纳米技术与纳米仿生研究所 基于沟道阵列结构的异质结场效应晶体管
CN104201170A (zh) * 2014-08-07 2014-12-10 复旦大学 一种立体包裹式金属-氧化层-金属电容
CN105070763A (zh) * 2015-07-22 2015-11-18 中国科学院半导体研究所 Soi叉指结构衬底ⅲ-ⅴ族材料沟道薄膜晶体管及制备方法
US9589956B1 (en) * 2016-04-29 2017-03-07 International Business Machines Corporation Semiconductor device with different fin pitches
CN106684132A (zh) * 2016-12-29 2017-05-17 西安电子科技大学 基于有源区沟槽结构的碳化硅双极型晶体管及其制作方法
CN109037202A (zh) * 2017-06-09 2018-12-18 三星电子株式会社 具有多栅极晶体管结构的半导体装置
CN109360859A (zh) * 2018-10-26 2019-02-19 信利半导体有限公司 薄膜晶体管设计方法、薄膜晶体管及液晶显示屏
CN110047752A (zh) * 2013-03-15 2019-07-23 英特尔公司 利用硬掩模层的纳米线晶体管制造
CN110310873A (zh) * 2019-06-25 2019-10-08 东南大学 一种扩展栅极结构的垂直型纳米间隙真空晶体管及其制备方法
CN110808280A (zh) * 2019-11-12 2020-02-18 华中科技大学 一种浮栅极型场效应晶体管存储器及其制造方法
CN110931563A (zh) * 2019-11-18 2020-03-27 天津大学 一种柔性二硫化钼晶体管及制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104078501A (zh) * 2014-06-13 2014-10-01 上海交通大学 一种基于二维半导体材料的低压场效应晶体管
CN207250526U (zh) * 2017-07-27 2018-04-17 厦门市三安集成电路有限公司 一种三维栅介质结构的增强型功率晶体管
US11022486B2 (en) * 2018-02-12 2021-06-01 National University Of Singapore MoS2 based photosensor for detecting both light wavelength and intensity
US10741660B2 (en) * 2018-06-12 2020-08-11 International Business Machines Corporation Nanosheet single gate (SG) and extra gate (EG) field effect transistor (FET) co-integration
US10615256B2 (en) * 2018-06-27 2020-04-07 International Business Machines Corporation Nanosheet transistor gate structure having reduced parasitic capacitance
CN110190111A (zh) * 2019-05-06 2019-08-30 清华大学 一种多栅三维纳米线晶体管及其制备方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1487599A (zh) * 2002-10-01 2004-04-07 ���ǵ�����ʽ���� 具有多个叠置沟道的场效应晶体管
CN102201442A (zh) * 2011-04-02 2011-09-28 中国科学院苏州纳米技术与纳米仿生研究所 基于沟道阵列结构的异质结场效应晶体管
CN110047752A (zh) * 2013-03-15 2019-07-23 英特尔公司 利用硬掩模层的纳米线晶体管制造
CN104201170A (zh) * 2014-08-07 2014-12-10 复旦大学 一种立体包裹式金属-氧化层-金属电容
CN105070763A (zh) * 2015-07-22 2015-11-18 中国科学院半导体研究所 Soi叉指结构衬底ⅲ-ⅴ族材料沟道薄膜晶体管及制备方法
US9589956B1 (en) * 2016-04-29 2017-03-07 International Business Machines Corporation Semiconductor device with different fin pitches
CN106684132A (zh) * 2016-12-29 2017-05-17 西安电子科技大学 基于有源区沟槽结构的碳化硅双极型晶体管及其制作方法
CN109037202A (zh) * 2017-06-09 2018-12-18 三星电子株式会社 具有多栅极晶体管结构的半导体装置
CN109360859A (zh) * 2018-10-26 2019-02-19 信利半导体有限公司 薄膜晶体管设计方法、薄膜晶体管及液晶显示屏
CN110310873A (zh) * 2019-06-25 2019-10-08 东南大学 一种扩展栅极结构的垂直型纳米间隙真空晶体管及其制备方法
CN110808280A (zh) * 2019-11-12 2020-02-18 华中科技大学 一种浮栅极型场效应晶体管存储器及其制造方法
CN110931563A (zh) * 2019-11-18 2020-03-27 天津大学 一种柔性二硫化钼晶体管及制作方法

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS;Jincheng Zhang, Lihe Nie, Dong Wei, et al.;《2019 IEEE 13th International Conference on ASIC (ASICON)》;20200206;1-3 *
CMOS毫米波锁相环及高精度正交信号发生器的研究设计;蒋健兵;《中国优秀硕士学位论文全文数据库 信息科技辑》;20160315;21-77 *
Realization and Performance Analysis of Facile-Processed μ-IDE-Based Multilayer HfS2/HfO2 Transistors;Shivani Sharma, Subhashis Das, Robin Khosla, et al.;《IEEE Transactions on Electron Devices》;20190605;3236 - 3241 *
SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors;Yuting Yao, Manxin Li, Tianxiang Wu, et al.;《2019 IEEE 13th International Conference on ASIC (ASICON)》;20200206;197287-197299 *
杂质吸附对背栅MoS2场效应晶体管电学性能的影响;蔡剑辉;陈治西;刘晨鹤;张栋梁;刘强;《电子器件》;20181220;1368-1371 *

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