CN113169151B - 互连结构 - Google Patents

互连结构 Download PDF

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Publication number
CN113169151B
CN113169151B CN201980077502.5A CN201980077502A CN113169151B CN 113169151 B CN113169151 B CN 113169151B CN 201980077502 A CN201980077502 A CN 201980077502A CN 113169151 B CN113169151 B CN 113169151B
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conductive interconnect
substrate
interconnect structure
conductive
bonding surface
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CN113169151A (zh
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C·E·尤佐
G·G·小方丹
J·A·泰尔
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Insulation Semiconductor Bonding Technology Co
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Evanss Adhesive Technologies
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Abstract

包括工艺步骤的代表性技术和设备可以被采用，以减轻导电互连结构中的不期望的凹陷和电介质键合表面的腐蚀。例如，嵌入层可以被添加到凹陷或腐蚀的表面上，以消除不需要的凹陷或空隙并且形成平坦的键合表面。包括工艺步骤的附加技术和设备可以被采用，以在导电互连结构中形成期望的开口，其中开口相对于互连结构的导电材料的体积可以具有预先确定的或期望的体积。这些技术、设备和工艺中的每个可以在经键合的裸片和晶片的键合表面处提供对更大直径、更大体积或混合尺寸的导电互连结构的使用。

Description

互连结构
优先权要求和相关申请的交叉引用
本申请要求于2019年10月18日提交的美国非临时申请号16/657,696,的权益，并且还根据35U.S.C.§119(e)(1)要求于2018年10月22日提交的美国临时申请号62/748,653,和于2019年09月18日提交的美国临时申请号62/902,207,的优先权，两者都通过引用以其整体并入本文。
技术领域
以下描述涉及集成电路(“IC”)。更具体地说，以下描述涉及制造IC裸片和晶片。
背景技术
微电子元件通常包括半导体材料(诸如硅或砷化镓)的薄板，该薄板通常被称为半导体晶片。晶片可以被形成为包括在晶片表面上和/或部分被嵌入在晶片内的多个集成芯片或裸片。与晶片分离的裸片通常作为单独的预封装单元被提供。在一些封装设计中，裸片被安装到衬底或芯片载体，该衬底或芯片载体进而被安装在诸如印刷电路板(PCB)的电路面板上。例如，许多裸片在适用于表面安装的封装中提供。
经封装的半导体裸片也可以以“堆叠”布置被提供，其中一个封装例如在电路板或其他载体上提供，并且另一个封装被安装在第一封装之上。这些布置可以允许多个不同裸片和设备被安装在电路板上的单个占有面积内，并且可以通过在封装之间提供短互连来进一步促进高速度操作。通常，该互连距离可能仅略大于裸片自身的厚度。为了在裸片封装的堆叠内实现互连，可以在每个裸片封装(最顶部封装除外)的两侧(例如，面)上提供用于机械连接和电连接的互连结构。
此外，裸片或晶片可以以三维布置被堆叠，作为各种微电子封装方案的一部分。这可以包括在较大的基底裸片、器件、晶片、衬底等上堆叠一个或多个裸片、器件和/或晶片的层，以竖直或水平布置堆叠多个裸片或晶片，以及两者的各种组合。
可以使用各种键合技术以堆叠布置键合裸片或晶片，键合技术包括直接电介质键合、非粘合技术(诸如，
Figure GDA0003470215510000021
)或混合键合技术(诸如，
Figure GDA0003470215510000022
)，两者均可从Xperi公司的Invensas Bonding Technologies,Inc.(以前的Ziptronix,Inc.)获得。键合包括在两个制备好的表面放在一起时在环境条件下发生的自发过程(例如，参见美国专利号6864585和7485968，以其整体并入本文)。
当使用直接键合技术来键合堆叠的裸片时，通常期望待键合的裸片的表面极其平坦和光滑。例如，通常，这些表面在表面形貌上应当具有非常低的变化(即，纳米级变化)，以便可以将这些表面紧密配合以形成持久的键。通常使用化学机械抛光(CMP)等将裸片或晶片的一个或多个键合表面平坦化，以实现键合所需的极其平坦和光滑的表面。
待键合的裸片或晶片(其可以包括硅或另一适当的材料)的相应配合表面在键合表面处通常包括被嵌入在无机电介质层(例如，诸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、碳氮化物、金刚石、类金刚石材料、玻璃、陶瓷、玻璃-陶瓷等)内的导电互连结构(其可以是金属)。
导电互连结构可以通过(例如)镶嵌技术形成，并且可以包括具有变化的宽度和尺寸的结构。导电互连结构可以在键合表面处布置和对齐，使得来自相应的裸片表面的导电互连结构在键合期间被结合。结合的互连结构在堆叠的裸片或晶片之间形成连续的导电互连(用于信号、功率、热传递、机械稳定性等)。
嵌入导电互连结构的暴露表面也可以被单独平坦化，或与裸片或晶片的键合表面一起被平坦化。导电互连结构的暴露表面的轮廓和/或形貌对于在裸片或晶片之间形成可靠的连续导电互连是重要的，并且对于在裸片或晶片之间形成可靠的电介质-电介质键也是重要的。
附图说明
参考附图阐述详细描述。在图中，附图标记的最左边的数字标识附图标记首次出现的图。在不同图中使用相同的附图标记指示相似或相同的项目。
对于该讨论，图中所示的设备和系统被示出为具有多个部件。如本文所述，设备和/或系统的各种实施方式可以包括更少的部件并且仍然在本公开的范围内。备选地，设备和/或系统的其他实施方式可以包括附加部件或所描述部件的各种组合，并且仍然在本公开的范围内。
图1A至图1D示出了具有嵌入导电互连结构的示例衬底的横截面。
图2示出了针对导电互连结构的凹陷的现有技术解决方案。
图3A至图3G示出了根据实施例的具有嵌入导电互连结构的示例衬底的横截面，包括用于减轻导电互连结构的不期望凹陷的示例技术。
图4A至图4C示出了根据实施例的具有嵌入导电互连结构的示例衬底的横截面，包括用于减轻导电互连结构的不期望凹陷和衬底的腐蚀的示例技术。
图5A至图5D示出了根据实施例的具有嵌入导电互连结构的示例衬底的横截面，包括用于减轻导电互连结构的不期望凹陷和衬底的腐蚀的另一示例技术。
图6示出了根据实施例的示例顶层工艺技术，用于在具有嵌入导电互连结构的衬底上形成键合层。
图7A至图7D示出了根据实施例的具有嵌入导电互连结构的示例衬底的横截面，包括用于在导电互连结构中形成开口的示例技术。
图8A至图8D示出了根据实施例的具有嵌入导电互连结构的示例衬底的横截面，包括用于在导电互连结构中形成开口的另一示例技术。
图9A至图9C示出了根据各种实施例的具有带有开口的嵌入导电互连结构的示例衬底的横截面，包括使用衬底的键合解决方案。
图10A至图10D示出了根据各种实施例的具有带有开口的嵌入导电互连结构的示例衬底的横截面，包括使用衬底的附加键合解决方案。
图11A至图11D示出了根据各种实施例的具有带有开口的嵌入导电互连结构的示例衬底的横截面，包括用于形成开口的另一示例技术以及使用衬底的键合解决方案。
图12示出了根据实施例的具有带有开口的嵌入导电互连结构的衬底的横截面，其被用作光学设备。
图13是图示了根据实施例的形成具有带有开口的嵌入导电互连结构的衬底的示例过程的文本流程图。
图14是图示了根据另一实施例的形成具有嵌入导电互连结构的衬底的另一示例过程的流程图。
具体实施方式
概述
包括工艺步骤的代表性技术和设备可以被采用，以减轻导电互连结构中的不期望的凹陷和电介质键合表面的腐蚀。例如，嵌入层可以被添加到凹陷或腐蚀的表面上，以消除不需要的凹陷或空隙并且形成平坦的键合表面。包括工艺步骤的附加技术和设备可以被采用，以在导电互连结构中形成期望的开口，其中开口相对于互连结构的导电材料的体积可以具有预先确定的或期望的体积。这些技术、设备和工艺中的每个可以在经键合的裸片和晶片的键合表面处提供对更大直径、更大体积或混合尺寸的导电互连结构的使用。
在一些实施例中，一个或多个保护层也可以被沉积在导电互连结构的无意或有意凹进的部分内，以防止或消除凹进部分内的原子迁移(例如，抑制表面移动)。在各种实施例中，保护层可以包括导电或非导电材料。
参考电气和电子部件以及各种载体讨论了各种实施方式和布置。尽管提到了特定的部件(即，裸片、晶片、集成电路(IC)芯片裸片、衬底等)，但这并不旨在是限制性的，并且是为了便于讨论和说明方便。参考晶片、裸片、衬底等讨论的技术和设备可应用于任何类型或数目的电子部件、电路(例如，集成电路(IC)、混合电路、ASIC、存储器设备、处理器，等)、部件的组、经封装的部件、结构(例如晶片、面板、板、PCB等)等，其可以被耦合以与彼此，与外部电路、系统、载体等对接。这些不同的部件、电路、组、封装、结构等中的每一个可以被统称为“微电子部件”。为了简单起见，除非另有说明，否则被键合到另一部件的部件在本文中被称为“裸片”。
参考图1A和图1B，在一些示例中，可以使用镶嵌技术等来在裸片或晶片的绝缘层102中形成嵌入的导电结构。屏障层106可以被沉积在绝缘层102内的一个或多个腔104之上，随后是种子层108。根据需要和/或通过设计，腔104可以具有不同的尺寸(即，体积和宽度)，具有不同的面积，以及以各种间隔相对于彼此定位。
如在图1B处所示，腔104可以使用电镀浴或其他技术，例如利用导电材料110(诸如铜)来填充。导电材料110可以包括与种子层108相同的材料，或者在一些情况下可以包括不同的材料。如图1C中所示，从键合表面112移除多余的导电材料110镀层。保留在镶嵌腔104内的导电材料110形成导电互连结构114。
参考图1C，制备裸片或晶片的用于直接键合的键合表面112可以包括：平坦化嵌入导电互连结构114的暴露表面以及裸片或晶片的绝缘(例如，电介质等)层102。这可以提供导电互连结构114和顶部绝缘层102的暴露表面的期望轮廓和形貌。由于互连结构114的导电材料110(例如，金属，例如铜)和裸片或晶片表面的绝缘体材料102(例如，二氧化硅等)的性质(机械性质、抛光速率等的差异)的不连续性，以及它们与抛光垫、抛光浆液以及其他工艺参数的相互作用，平坦化可能在高金属图案密度区域中产生电介质腐蚀(例如，参见图4A处的腐蚀404)，并且在互连结构114的暴露表面中产生凹陷116。
通常，金属图案密度越高，腐蚀越大。类似地，导电互连114的暴露表面的面积越大，凹陷缺陷116越深。两者都导致裸片或晶片的整体表面形貌的显著变化。变化可能足以削弱直接键合或降低键合在表面变化的位置处的可靠性(包括降低金属-金属键的可靠性)。
尽管可能需要一些凹进，如下面进一步讨论的，但是在导电互连结构114的暴露表面上的不期望凹陷的结果可能包括需要比期望温度更高的温度来键合制备的器件118。这可能会限制可以被键合的器件的类型或限制所使用的互连114的尺寸。此外，具有大表面积的一些互连结构114可能经历凹陷116，该凹陷可能太深而不能形成可靠的扩散键。例如，结构114的金属在退火温度下可能不能充分膨胀以形成键。如果形成键，则它可能是有缺陷和不可靠的。
例如，在如图1D处所示的一些情况下，具有较大表面积的结构114的过度凹陷116可能导致键合结构114内的空隙120，包括在退火或键合后的高温热处理步骤之后。空隙120可能引起可靠性问题，因为它们可以允许从空隙120发出的空隙或空位错位缺陷的迁移(由于金属原子(例如，诸如铜)中的表面移动而引起)，这引起器件故障，并且限制了互连结构114的电流运载能力。
减轻过度凹陷116的效果的尝试的示例由在图2处的过程200示出。例如，在框A处示出了具有导电互连结构114的器件118，导电互连结构114具有过度凹陷116。在框B处，过程包括在不平坦的键合表面112上添加绝缘层202，例如诸如电介质层，然后在框C处重新表面处理所添加的键合层202(经由CMP平坦化等)。
如在框D处所示，可以在所添加的层202中(使用单镶嵌或双镶嵌工艺)形成互连结构204，互连结构204具有比互连结构114的较大宽度(L1)和较大表面积小的宽度(L2)和小的暴露表面积。新互连结构204延伸穿过所添加的键合层202，并且与下面的凹陷的导电结构114进行电接触。目的是减少新的键合层202上的暴露金属面积，以减小表面变化，以用于与堆叠的衬底206更可靠地直接键合(参见框E)。然而，添加附加键合层202的过程可能增加10个以上的制造步骤，这极大地增加了所生产的器件118的成本。此外，新互连结构204(例如具有宽度L2)在面积上趋于比下面的原始结构114(例如具有宽度L1)小得多，这通常负面地影响电连接性质并且限制了布线设计的自由度。
示例实施方式
在各种实施方式中，使用创新的技术和设备来减轻各种尺寸(包括大面积结构，例如具有10微米以上的宽度或直径)的互连结构114的表面中的凹陷和凹进116的影响，以形成可靠的低温金属键。技术和设备有效地在具有嵌入导电互连结构114的裸片和晶片上制备直接键合表面112，导电互连结构114具有变化的宽度(例如，直径)、尺寸和大小，包括在单个裸片表面112上的混合尺寸，例如具有1微米至1000微米以上的宽度或直径的结构。此外，这些技术和设备允许使用标准制造技术，来在这种变化的裸片和晶片上进行表面112制备。在该实施方式中，嵌入层304(参见图3D)被添加到互连结构114的凹陷表面以减少或消除凹进和/或空隙。在实施例中，嵌入层304可以包括电介质材料，诸如SiC、SiC/SiCh、SiN/SiO2等。例如，嵌入层304可以包括与裸片或晶片表面102相同或不同的电介质。在其他实施例中，嵌入层304可以包括导电材料，诸如钨、钨的合金、镍合金等。备选地，嵌入层304可以包括低CTE材料、含硅材料(诸如掺杂或未掺杂的多晶硅(其可以形成硅化物))，或者其他适当的材料。更进一步地，可以使用绝缘和/或导电材料的多个涂层或层。
参考图3A和图3B(示出了横截面轮廓视图)，图案化的金属和氧化物层经常作为混合键合或
Figure GDA0003470215510000071
表面层被提供在裸片、晶片或其他微电子衬底(在下文中，“裸片302”)上。可以使用各种技术来将代表性的器件裸片302形成为包括基底衬底(参见图6)和一个或多个绝缘或电介质层102。基底衬底可以包括硅、锗、玻璃、石英、电介质表面、直接或间接带隙半导体材料或层或其他适当的材料。绝缘层102被沉积或形成在基底上，并且可以包括无机电介质材料层，诸如氧化物、氮化物、氧氮化物、碳氧化物、碳化物、碳氮化物、金刚石、类金刚石材料、玻璃、陶瓷、玻璃-陶瓷等。
如上所述，在一些示例中，可以使用镶嵌技术等来在裸片或晶片的绝缘层102中形成嵌入导电结构114。在沉积导电互连结构114的材料之前，可以在绝缘层102内的一个或多个腔104之上沉积屏障层106，然后是种子层108，以使得屏障层106被布置在导电互连结构114与绝缘层102之间。根据需要和/或通过设计，腔104可以具有不同的尺寸(即，体积和宽度)、具有不同的面积以及以各种间隔相对于彼此定位。屏障层106可以包括例如包含钽或钛或钴的材料或其他导电材料，以防止或减少导电互连结构114的材料扩散到绝缘层102中。
如在图3B处所示，腔104可以使用电镀浴或其他技术，例如利用导电材料110(诸如铜或铜合金)来填充。导电材料110可以包括与种子层108相同的材料，或者在一些情况下可以包括不同的材料。如图3C中所示，从键合表面112移除多余的导电材料110镀层。保留在镶嵌腔104内的导电材料110形成导电互连结构114。
形成键合表面112包括加工绝缘层102的表面112，以满足电介质粗糙度规格，并且加工任何金属层(例如，铜迹线、结构、焊盘等)以满足凹进规格，以制备用于直接键合的表面112。换言之，键合表面112被形成为尽可能平坦和光滑，具有非常小的表面形貌变化。
参考图3C，制备裸片302或晶片的用于直接键合的键合表面112可以包括：平坦化嵌入导电互连结构114的暴露表面以及裸片302或晶片的绝缘(例如，电介质等)层102。这可以提供导电互连结构114和顶部绝缘层102的暴露表面的期望轮廓和形貌。可以使用诸如化学机械抛光(CMP)的各种常规过程来实现低表面粗糙度。该过程提供了可以导致可靠键合的平坦、光滑的表面112。
然而，如上所述，由于互连结构114的导电材料110(例如，金属，例如铜、铝等)和裸片或晶片表面的绝缘体材料102(例如，二氧化硅等)的性质(机械性质、抛光速率等的差异)的不连续性，以及它们与抛光垫、抛光浆液以及其他工艺参数的相互作用，平坦化在与互连结构114相邻的电介质部分中产生电介质腐蚀402(参见图4A)并且在较大的互连结构114的暴露表面中产生凹陷116。
在各种实施方式中，如在图3D处所示，在裸片302的先前制备的表面112之上形成(例如，沉积、涂覆等)嵌入层304，裸片302包括具有凹进116的嵌入结构114的表面。嵌入层304利用硬CMP垫来被平坦化。如在图3E处所示，嵌入层304可以被平坦化至露出嵌入互连结构114的最高表面的点，嵌入互连结构114现在包括在结构114的暴露部分的周界内的嵌入层304，嵌入层304部分地或完全填充不期望的凹进116，并且覆盖凹进116的表面。包括导电互连结构114和嵌入层304以及平坦化绝缘层102的所制备的键合表面306现在具有最小的表面形貌变化，并且可以使用直接键合技术，被可靠地键合到的另一个裸片302、晶片等的键合表面。
例如，如在图3F和图3G处所示，可能具有类似制备的键合表面的相似裸片302(或晶片等)可以被键合到键合表面306以形成键合设备312。在一个实施例中，结合的导电互连结构114可以在较低温度下被扩散键合，从而形成统一的导电结构310，并且可以在统一的导电结构310内包括嵌入层304。这使得可以使用具有较大宽度或表面积的导电互连结构114A、混合尺寸的导电互连结构114，并且使得键合表面306上的导电互连结构114B和114C的较密间距成为可能。
在一些情况下，如在图3C处所示，其中嵌入层304包括绝缘材料，嵌入层304填充了另外会存在的空隙120，从而有效抑制了金属层的原子在嵌入层304与导电互连结构114之间的结合区域或界面处的表面移动。嵌入层304位于该周界内，因此允许键合的导电结构114的外周扩散键并且起电作用。在一些情况下，外周被维持为具有用于期望的导电性的预先确定厚度(或宽度)。此外，可以选择嵌入层304的材料以获得高键合能力(例如，SiC、SiC/SiCk、SiN/SiCk等)。
在其他情况下，在嵌入层304包括导电材料的情况下，嵌入层304具有先前讨论的质量(例如，抑制凹进内的表面移动，形成所需的具有低表面形貌变化的键合表面等)，并且还有助于在统一的导电结构310处传导信号、功率等。嵌入层304的导电材料(例如，钨、钨的合金、镍合金等)可以被选择为具有预先确定的低表面移动趋势，从而减少或避免原子迁移。在一些情况下，可以优选的是，嵌入层304的熔点高于导电互连结构114的材料110的熔点。在一些情况下，嵌入层304可以包括多种金属或类似的材料。
如Liu等人的US专利8809123中所述，本文公开的嵌入层304不同于密封层，密封层具有以下性质，使得当密封层(诸如锗、锡等)与导电垫的材料(例如，铜)被组合并且被加热到预先确定温度时，形成共晶相的金属。相反，本公开的嵌入层304镶衬或涂覆在导电互连结构114的暴露表面的一部分(例如，凹进116)上，从而减小凹进116的间隙以形成更平坦的键合表面，并且覆盖互连结构114的暴露金属以抑制在凹进116处的原子迁移。
参考图3G，在备选实施例中，其中互连114表面的面积特别大，例如具有例如100微米以上的宽度或直径，嵌入层304在平坦化期间也可能经历一些凹陷。在该实施例中，凹陷可以在统一的导电结构310内的嵌入层304中产生空隙308(或气隙)。然而，嵌入层304中的空隙308可能是无关紧要的，因为嵌入层304仍覆盖互连结构114的金属，降低了导电互连结构114的材料110的表面移动。在一个实施例中，嵌入层304内的被封闭的空隙308或腔的宽度小于互连结构114的宽度的50％。
在各种实施方式中，嵌入层304的厚度大于在镶嵌工艺期间沉积的屏障层106的厚度。例如，嵌入层304在凹进116的表面之上可以具有约15纳米至30纳米的厚度。在其他实施方式中，对于一些凹进116，嵌入层304可以比30纳米厚。例如，在一些示例中，凹进116的深度可以为大约1微米至5微米。在一些实施方式中，嵌入层304的厚度小于凹进116的宽度(或直径)。
在各种实施例中，嵌入层304的表面积的宽度(或直径)小于导电互连结构114的以其他方式暴露的表面的宽度(或直径)。例如，在各种示例中，嵌入层304的宽度或直径可以小于导电互连结构114的表面的宽度或直径的50％、20％、10％、5％或2％。
在一些实施例中，可以减小互连结构114的间隔，以获得更大的布线设计自由度。例如，由于互连114凹陷和电介质102腐蚀以更近的比率增加，先前的焊盘间距与焊盘宽度(或直径)的比率被保持较大，对于一些较大的焊盘，大约为2：1和3：1。在该实施例中，互连114焊盘的间距可以被减小到小于2。在该实施例中，当使用所公开的技术和设备时，两个相邻的互连焊盘114之间的距离小于互连114焊盘的宽度。对于一个示例，当应用所公开的技术和设备时，相邻的20微米的互连114焊盘的集合现在可以具有大约25微米的间距。
参考图4A至图4C，在另一实施方式中，嵌入层304也可以在导电结构114的凹进116的外部被使用，包括在导电结构114的屏障层106的内部或外部被使用。在一个示例中，如在图4A处所示，导电结构114可以在结构114的周界处具有一个或多个缺少金属的腔402。例如，处理步骤可能导致导电结构114中的一些导电结构腐蚀掉等，从而留下腔402。
在一个实施例中，如在图4B处所示，沉积的嵌入层304可以填充缺少结构114的金属的空腔402。如在图4C处所示，当嵌入层304被平坦化时，填充腔402的嵌入层304可以使键合层306的表面光滑。在一些实施例中，抛光嵌入层304将嵌入层304的材料捕获在屏障层106和导电结构114之间的腔402中。
在另一个示例中(也如在图4A至图4C处所示)，在平坦化步骤期间，在与导电结构114相邻的表面处的电介质材料102可能在导电结构114的外边缘处或在屏障层106处被腐蚀(或“被圆化”，参见404)。例如，在具有高金属密度的区域，腐蚀404可能更明显。如在图4A处所示，电介质腐蚀404可以在导电结构114的边缘或屏障层106之外的电介质102中包括一个或多个腔或凹进。如在图4B处所示，所沉积的嵌入层304也可以填充缺少电介质102的腔404。如在图4C处所示，当嵌入层304被平坦化时，填充腔404的嵌入层304可以使键合层102的表面306光滑。在一些实施例中，抛光嵌入层304将嵌入层304的材料捕获在腔404或凹进中。尽管腔402和404可能作为过程的一部分而无意中被形成，但是这种腔或凹进可以在键合表面上的这些位置或其他位置被有意提供，并且可以根据需要或要求具有任何合适的形状、轮廓或配置。
在另外的实施例中，参考图5A，可以在补救结构114的凹陷116时，采用另一种技术来减轻缺失导电互连结构114等的金属部分的影响。在该实施例中，电介质层102的选择部分502可以被移除，以使导电互连结构114的侧壁504的部分突出到电介质层102的表面上方(图5B)。
如在图5C处所示，可以在包括互连结构114的绝缘层102的表面之上沉积嵌入层304。嵌入层304可以建立绝缘层102的表面，从而提供准备用于键合的新层506。嵌入层304现在可以接触互连结构114和/或屏障层106的金属侧壁504的至少一部分。如在图5D处所示，嵌入层304可以被平坦化至露出互连结构114的最高点的点，同时保持具有最小表面形貌变化的平坦表面。互连结构114现在可以包括在结构114的暴露部分的周界内的嵌入层304(填充凹进116)。互连结构114和/或绝缘层102中的任何其他腔(例如402、404)也被嵌入层304覆盖。
参考图6，在各种实施方式中，还可以执行所公开的技术(被示为过程600)以在绝缘层102之上提供钝化层606，作为功能层、保护层或优选的键合层。框A示出了在基底层604之上的绝缘层102中的腔602，其使用镶嵌技术等(如上所述)利用导电材料110(例如，铜等)来被填充。如在框B处所示，通过平坦化、蚀刻等移除来自镶嵌工艺的过量填充的导电材料，从而在腔602中形成导电互连结构114。在一些情况下，使绝缘层102的表面尽可能平坦和光滑(例如，如果用于直接键合)可以是有利的。
在框C处，例如，可以使用选择性湿法蚀刻，来根据需要选择性地移除电介质102的部分502(例如，大约30nm至100nm)，使导电结构114从绝缘层102突出。在框D处，在包括互连结构114的绝缘层102的表面之上沉积嵌入层304。嵌入层304可以接触互连结构114和/或屏障层106的金属侧壁504的至少一部分。嵌入层304可以被平坦化(例如，CMP)至露出互连结构114的最高点的点，同时保持具有最小的表面形貌变化的平坦表面，如上面所讨论并且在框E处所示的。可以构成用于裸片302的优选键合层、保护层和/或功能层的钝化层606包括保留在绝缘层102上的平坦化的嵌入层304。
附加实施例
通常，当直接键合具有键合表面(包含电介质层102和一个或多个金属特征(诸如嵌入导电互连结构114)的组合)的裸片或晶片时，电介质表面102首先键合，并且特征114的金属110随后膨胀(在金属110在退火期间被加热时)。金属110的膨胀可以使得来自两个裸片302的金属110结合成统一的导电结构310(金属-金属键合)。虽然绝缘层102和金属110在退火期间都被加热，但是金属110的热膨胀系数(CTE)相对于绝缘层102的CTE通常指示：在特定温度下(例如，～300C)，金属110比绝缘层102膨胀得多的多。例如，铜的CTE为16.7，而熔融二氧化硅的CTE为0.55，硅(例如，基底604)的CTE为2.56。在一些情况下，金属110相对于绝缘层102的更大膨胀对于直接键合堆叠的裸片302可能是有问题的。
一些嵌入导电互连结构114可以部分地延伸到所制备的键合表面112下方的绝缘层102中。例如，一些图案化的金属特征可以为大约0.5微米至3微米厚。其他导电互连结构114可以包括更厚(例如，更深)的结构，包括金属硅通孔(TSV)等，其可以穿过绝缘层102的一部分或全部延伸并且包括更大体积的金属110。例如，根据衬底的厚度，TSV可以延伸大约100微米或更多。在一些应用中，可能期望形成大直径的金属结构114，例如具有10微米至100微米以上的宽度或直径，其还将包括更大体积的金属110。如上所述，这些结构114的金属在被加热时膨胀。在一些情况下，金属110的膨胀可能引起不期望的局部应力，包括在结构114的位置处的键合表面的潜在分层。在最坏的情况下，膨胀的金属110的应力可能使堆叠裸片302的键合的电介质表面112分离。
同样，利用金属或其他导电材料110形成完全填充的大的腔104可能相对昂贵。例如，通过电镀方法填充具有5微米直径、100微米深度的TSV阵列可能需要10分钟至20分钟的金属镀覆时间。然而，填充具有20微米直径和相似深度的TSV阵列可能需要在120分钟至400分钟之间，甚至更长的镀覆时间。较长的镀覆时间降低了用于填充较大的腔104的镀覆工具的产量。类似地，平坦化较大的金属填充腔104以移除键合表面上不需要的金属可能花费更多。实际上，金属填充的腔104越大，由于涂覆金属110与绝缘层102之间的热膨胀系数(CTE)的差异而导致的失配应力越大。在较大的金属TSV的情况下，过孔的直径越大，衬底的器件部分中用于器件的禁入区域越大。
参考图7A至图7D，在各种实施例中，可以采用设备、技术和工艺来减轻不期望的高应力的影响(包括由于金属110膨胀而引起的分层的可能性)，提高产量以及降低在大的腔104中形成平坦金属的拥有成本。这可以允许使用更大直径的结构114、更大体积的结构114或混合尺寸的结构114。作为示例，114A的直径大于114B的直径，114B的直径又大于114C的直径。
例如，在各种实施例中，可以在导电互连结构114中有意形成开口702。开口702可以在导电互连114的表面下方延伸预先确定深度。对于给定的金属涂覆时间，702A的开口的体积可以大于702B的开口的体积，并且开口702B的体积可以大于702C的体积。可以基于导电互连114的材料110，其材料110的厚度或体积以及其在退火期间的预期膨胀，来选择开口702的体积。在各种实施例中，开口702可以包括导电互连结构114中的任何凹进部分、间隙、腔、中空等，其为互连结构114的材料110提供扩展的空间。适当尺寸的开口702可以减小或消除膨胀材料110在堆叠的裸片302或晶片的键合接点306上的应力，因为金属110可以膨胀到开口702中。开口702的宽度例如可以在小于100nm至大于20微米之间的范围内。利用预先确定尺寸的开口702，它仍可以允许相应的互连结构114的材料110可靠地结合并且在堆叠的裸片302或晶片之间形成连续的导电互连310。
在各种实施例中，可以有意地将开口702形成为具有期望的预选体积(例如，以适应由于腔104中的涂覆金属110和周围的绝缘体102材料的热膨胀不匹配而导致的过度应力)。在其他实施例中，可以允许开口702作为处理裸片302或晶片的键合表面306的一部分而形成。在这种情况下，开口702的体积可以基于所涉及的过程和材料而可预测。
例如，在一些实施例中，可以在形成导电互连结构114时，有意形成开口702。例如，如在图7A至图7C处所示，导电互连结构114可以使用镶嵌技术而被形成，并且可以包括腔104和具有混合宽度(104A、104B和104C)和深度的结构114。如在图7A处所示，一个或多个镶嵌腔104可以形成在感兴趣的裸片302或晶片或衬底的电介质层102的表面中，以部分或全部地延伸穿过电介质层102。在一个示例中，腔104可以具有至少10微米的宽度或直径，至少5微米或甚至10微米的深度。备选地，腔104可以被形成为延伸到裸片302或晶片的基底衬底(未示出，例如参见图6处的基底604)中。屏障层106和种子层108被沉积在腔104的暴露表面之上。
如在图7B处所示，使用超填充电镀浴或使用适形电镀或非电解镀浴等，利用导电材料110(例如，铜、铜合金等)部分地填充腔104。在一些实施例中，可以通过物理气相沉积法(PVD)或通过原子层沉积法、化学气相沉积法或将导电层110旋涂到腔104中，来将导电层110涂覆到腔104中。腔104中的导电层110的部分填充在镶嵌腔104(例如，分别为104A、104B和104C)内产生具有有意开口702(例如，702A、702B和702C)的导电互连结构114。
感兴趣的裸片302或晶片或衬底的键合表面306被平坦化(使用化学机械抛光(CMP)等)，以制备用于键合的电介质表面102和导电互连结构114。这包括从电介质键合表面306将来自镶嵌工艺的不需要的镀层110和其他导电屏障层106移除，如图7C中所示。剩下的开口702’(例如，702A’、702B’和702C’)被限制在互连结构114中，并且可以具有预先确定的体积。在一个实施例中，剩下的开口702’在裸片302或晶片的键合表面306处的宽度(“w”)大于在导电层110和电介质层102之间的屏障层106的厚度。因此，剩下的开口702A’的宽度大于剩下的开口702B’的宽度，剩下的开口702B’的宽度大于剩下的开口702C’的宽度。在其他应用中，剩下的开口702’在键合表面306处的宽度(“w”)大于相应的腔104内的导电层110的厚度。在一些应用中，剩下的开口702’的深度(“d”)可以小于50nm，并且优选地小于100微米。
裸片302或晶片的键合表面306可以准备好与另一个类似的裸片302或晶片，或与其他制备的衬底704键合，以形成键合设备312。在各种实施例中，衬底704可以包括与裸片302相同或不相似或不同的材料。例如，衬底704可以包括电介质、玻璃、半导体或其他材料。在键合操作之后(其中键合表面306上的导电互连结构114(114A、114B和114C)的一个或多个平坦部分被直接键合到相对衬底704的制备的表面)，剩下的开口702’被封闭在导电互连结构114内，如图7D中所示。
在备选过程中，如在图8A至图8D处所示，在利用导电材料110部分填充镶嵌腔104之后，可以在导电材料110的表面之上，包括在导电互连结构114的表面的开口702内形成(例如，沉积、涂覆等)保护层802(参见图8C和图8D)。
在各种实施例中，保护层802可以包括电介质材料，诸如SiO2、SiC、SiN、SiC/SiO2、SiN/SiO2、SiN/多晶硅、无机电介质/有机电介质等。例如，保护层802可以包括与裸片302或晶片表面的绝缘层102相同或不同的电介质。在其他实施例中，保护层802可以包括导电材料，诸如钨、钨的合金、镍合金、钽或钛以及各种合金，例如TaN/Ta或Ta/TaN、Ti/TiN、钴、CoP、NiP、CoWP、CoP/NiP等。更进一步，保护层802可以包括低CTE材料、含硅材料(诸如掺杂或未掺杂的多晶硅(其可以形成硅化物))或其他合适的材料。更进一步，可以使用绝缘和/或导电材料的多个涂层或层。
可以通过PVD方法或通过电解或非电解镀浴或其他技术来沉积保护层。备选地，保护层802可以包括绝缘和/或导电材料的多个涂层或层。在一些应用中，保护层802可以包括一种或多种材料的适形涂层。保护层802的益处之一是抑制金属原子在与开口702内的保护层802相邻的导电层110的表面上的表面移动，从而改进键合互连114的可靠性。因此，保护层802可以用作导电互连114的一部分的键合表面。
在一个实施例中，保护层802的厚度小于导电层110在以保护层802和屏障层106为边界的相应的腔104内的厚度。在其他实施例中，保护层802可以比导电层110厚。在平坦化键合表面306(包括从键合表面306移除不需要的材料)之后，互连结构114的表面中的剩下的开口702’(702A’、702B’和702C’)保留在剩下的开口702’(其可以具有预先确定的体积)的内表面上的保护层802。
可以制备裸片302或晶片以用于键合到另一个类似的裸片302或晶片(如在图3F、图3G、图9B和图9C处所示的)，和/或键合到一些其他制备的衬底704(如在图7D、图9A和图9C处所示的)，以形成键合设备312。在一个实施例中，可以通过已知方法将图8D的平坦化的晶片单体化，经单体化的晶片被清洁并且准备用于键合操作。例如，来自单体化的晶片的裸片302或晶片可以被键合到平坦衬底704或其他载体以形成键合设备312。在一个实施例中，平坦载体704或裸片302可以包括单层级或多层级BEOL互连结构114或包括一个或多个RDL层的电介质。在键合操作期间，裸片302的导电互连结构114与相似的裸片302或晶片和/或制备的衬底704的表面上的接收导电互连结构114对齐和紧密配合，以形成统一的导电结构310。
在各种情况下，如在图9A至图9C处所示，裸片302或晶片可以正面-正面(图9B)或背面-正面(图9C)键合，和/或被键合到平坦衬底704(图9A和9C)以形成键合设备312。在键合之后，导电互连结构114具有封闭的腔702’，其中保护层802镶衬腔702’的内表面。从裸片302的横截面看，一个或多个被封闭的腔702’的轮廓可以是在几何上规则或不规则的形状。在各种实施例中，接收衬底704可以包括导电层，该导电层封闭一个或多个腔702’，如在图9A和图9C处所示。
换言之，在示例实施例中，如在图7D处所示，键合设备312可以包括导电层的直接键合到衬底704的一部分(例如，在裸片302的键合表面处的导电互连114的一部分)，并且可以包括该导电层的未键合到相同衬底704的另一部分(例如，导电互连114内的封闭腔702’的内部部分)。并且在另一实施方式中，如在图9A处所示，键合设备312可以包括导电层的直接键合到衬底704的一部分(例如，导电互连114在裸片302的键合表面处的一部分)，并且可以包括导电层的直接涂覆有保护层802、未键合到相同衬底704的另一部分(例如，导电互连114内的封闭腔702’的内部部分)。
在一些应用中，在晶片或裸片302包括TSV或贯穿电极的情况下，在如图9B中所示的键合操作之后，裸片302的键合晶片的背面可以被减薄并且被形成为暴露导电结构(TSV或贯穿电极)的背面。附加的制备的裸片302或晶片可以被电耦合到键合裸片302或晶片背面上的暴露的TSV。所述裸片302或晶片的电耦合尤其可以包括使用DBI方法或倒装芯片方法。
另外的实施例
在图10A至图12处示出了另外的实施例。在一个实施例中，如在图10A至图10D处所示，上面讨论的导电材料110的部分填充被施加得较薄，并且相当于镶嵌腔104内的适形或非适形金属涂层1002。根据导电层1002的厚度，该较薄的涂层1002可以导致相对于导电互连结构114具有非常大体积的开口702’。
另外，如在图10B处所示，涂层1002在一些情况下可以更厚，或者针对不同的设备312或在单个设备312内具有变化的厚度。例如，在一些实施例中，开口702’的横截面宽度(“w”)比导电层1002(例如，在腔104的侧壁上)的厚度(“t”)大3倍以上。此外，在一些实施例中，开口702’的深度(“d”)可以大于开口702’的横截面宽度(“w”)。
在一种实施方式中，如在图10C处所示，开口702’的内表面(即，导电层1002的暴露表面)可以如上所述的那样被保护涂层802涂覆。在另一实施例中，如在图10D处所示，可以在导电互连结构114(具有或不具有保护层802)的开口702’内沉积顺应性材料1004(例如，诸如填充材料或密封材料)。顺应性材料1004可以部分或全部填充开口702。
参考图11A至图12，在一些实施例中，所描述的技术和过程可以用于形成用于设备312的硅通孔1102(TSV)等。在TSV 1102的情况下，多个层可以镶衬TSV 1102内的开口702的内侧壁。在一些实施例中，TSV 1102可以由中间过孔或最后过孔方法形成。在中间过孔工艺的情况下，无论如何形成TSV 1102或贯穿衬底的过孔或贯穿玻璃的过孔(TGV)或贯穿衬底的电极(TSE)或贯穿板的过孔，都可以应用背面露出工艺，以从背面暴露部分导电互连结构114。
例如，如在图11A和图11B处所示，在部分填充腔104之后，可以在具有或不具有保护层802的情况下(取决于实施例)，在导电层110之上施加一个或多个附加层1104。在各种示例中，一个或多个附加层1104可以包括一个或多个电介质层等。
如在图11B处所示，对键合表面306进行平坦化形成具有一个或多个附加层1104的导电互连114。参考图11C，可以通过研磨、抛光、反应性离子蚀刻方法和其他已知方法，来减薄裸片302的背面并且露出导电互连114的背面，以暴露导电互连结构114的内部，导电互连结构114的内部形成TSV 1102。TSV 1102提供了贯穿裸片302的中空或贯穿的导电开口702，如在图11C和图11D处所示的。在一些实施例中，如图所示，贯穿开口702的内部导电表面镶衬有电介质层1104。然后，可以将制备的背面直接键合到另一个裸片302、晶片或制备的衬底704。
如在图11D处所示，可以将一个或多个部件1106(诸如光学设备或其他微电子部件)键合到裸片302的正面键合表面306。在一些情况下，TSV 1102提供从一个或多个部件1106到其他裸片302、晶片或制备的基板704(键合到裸片302的背面)的电信号或光学信号传输。例如，如在图12处所示，光学设备312被示出。在该示例中，衬底704可以包括玻璃1202的一个或多个层，并且包括反射器1204和根据应用需要而可选地包括腔1206。在这种情况下，TSV 1102可以传送光学信号，并且在一些情况下也可以传送电信号。
在各种其他实施例中，可以使用其他技术来改变导电互连结构114的表面，以减轻金属膨胀的影响。例如，在一些示例中，可以选择性地蚀刻(经由酸蚀刻、等离子体氧化等)导电互连结构114的表面，以提供期望的开口702深度。在另外的实施例中，导电互连结构114可以被选择、形成或处理以具有不平坦的顶表面。例如，导电互连结构的顶表面可以是圆形、圆顶形、凸形、凹形、不规则形或其他非平坦形。
示例过程
图13和图14包括上述过程和技术的基于文本的过程流。所描述的过程流程的应用提供了在直接键合的裸片、晶片、衬底等的键合表面处使用较大宽度或直径(例如，例如10微米至1000微米)的导电互连结构。
描述过程的顺序不旨在被解释为限制性的，并且过程中的任何数目的所描述的过程框可以以任何顺序被组合，以实现过程或备选过程。此外，在不脱离本文描述的主题的精神和范围的情况下，可以从过程中删除各个框。此外，可以在不脱离本文描述的主题的范围的情况下，以任何合适的硬件、软件、固件或其组合来实现过程。在备选的实施方式中，其他技术可以以各种组合被包括在过程中，并且仍然在本公开的范围内。
图13图示了根据各种实施例的，在感兴趣的裸片(例如，诸如裸片302)、晶片或其他衬底的键合表面处，减轻导电互连结构(例如，诸如导电互连结构114)的表面中的不期望的凹进(例如，诸如凹进116)的代表性过程1300。例如，嵌入层(例如，诸如嵌入层304)可以形成在凹进中，填充凹进以提供适于直接键合的平坦和光滑的键合表面。过程1300参考图1A至图6。
在一种实施方式中，在框1302处，过程1300包括：在第一衬底(例如，诸如裸片302)中形成一个或多个第一嵌入导电互连结构(例如，诸如导电互连结构114)。
在框1304处，过程包括平坦化第一衬底的第一表面以形成平坦的形貌，该平坦的形貌包括第一表面和一个或多个第一嵌入导电互连结构的表面。在框1306处，过程包括在第一衬底的第一表面和一个或多个第一嵌入导电互连结构之上沉积第一嵌入层(例如，诸如嵌入层304)。
在框1308处，过程包括：平坦化第一嵌入层，直到露出一个或多个第一嵌入导电互连结构的表面，以及形成第一嵌入层的键合表面，一个或多个第一嵌入导电互连结构的第一凹进部分至少部分地填充有第一嵌入层的一部分，第一嵌入层的该部分覆盖一个或多个第一嵌入导电互连结构的第一凹进部分的表面。
在一种实施方式中，过程包括：通过利用第一嵌入层覆盖第一凹进部分的表面，来抑制第一凹进部分的材料的原子的表面移动。
在一种实施方式中，过程包括：在第二衬底中形成一个或多个第二嵌入导电互连结构；平坦化第二衬底的第一表面以形成平坦的形貌，该平坦的形貌包括第二衬底的第一表面和一个或多个第二嵌入导电互连结构的表面；在没有粘合剂的情况下，经由直接键合将第二衬底的第一表面键合到第一衬底的键合表面；以及将一个或多个第二嵌入导电互连结构直接键合到一个或多个第一嵌入导电互连结构。
在另一实施方式中，过程包括：在第二衬底的第一表面和一个或多个第二嵌入导电互连结构之上沉积第二嵌入层；以及平坦化第二嵌入层，直到露出一个或多个第二嵌入导电互连结构的表面并且形成第二键合层的第二键合表面，一个或多个第二嵌入导电互连结构的第一凹进部分至少部分地填充有第二嵌入层的一部分，第二嵌入层的该部分覆盖一个或多个第二嵌入导电互连结构的第一凹进部分的表面。
在一种实施方式中，过程还包括：在没有粘合剂的情况下，经由直接键合将第二嵌入层的一部分键合到第一嵌入层的一部分。
作为备选实施方式，过程包括：在第一衬底中形成一个或多个第一嵌入导电互连结构；平坦化第一衬底的第一表面以形成平坦的形貌，平坦化的形貌包括第一表面和一个或多个第一嵌入导电互连结构的表面；选择性地移除第一表面的一部分，以使一个或多个第一嵌入导电互连结构突出到第一衬底的第一表面上方；在第一衬底的第一表面和一个或多个第一嵌入导电互连结构之上沉积第一嵌入层，第一嵌入层接触一个或多个第一嵌入导电互连结构的侧壁的一部分；以及平坦化第一嵌入层，直到露出一个或多个第一嵌入导电互连结构的表面，以及形成第一嵌入层的键合表面和一个或多个第一嵌入导电互连结构的表面。
图14图示了根据各种实施例的，在感兴趣的裸片(例如，诸如裸片302)、晶片或其他衬底的键合表面处，在导电互连结构(例如，诸如导电互连结构114)的表面中形成开口(例如，诸如开口702)的代表性的过程1400。例如，开口可以形成在导电互连结构中。过程1400参考图7A至图12。
在一种实施方式中，在框1402处，过程1400包括在第一衬底的第一表面中形成一个或多个第一腔。
在框1404处，过程包括在一个或多个第一腔内形成一个或多个第一嵌入导电互连结构，包括将第一嵌入导电互连结构中的一个或多个第一嵌入导电互连结构形成为在一个或多个第一嵌入导电互连结构的暴露表面中具有第一凹进部分。
在一种实施方式中，过程包括：通过使用镶嵌工艺部分填充一个或多个第一腔，来形成一个或多个第一嵌入导电互连结构和第一凹进部分。在一个实施例中，一个或多个第一嵌入导电互连结构包括在一个或多个第一腔的一个或多个内表面之上的适形金属涂层。
在一种实施方式中，过程包括在一个或多个第一嵌入导电互连结构的第一凹进部分之上沉积保护层。在另外的实施方式中，过程包括在保护层之上沉积一个或多个附加层，一个或多个附加层中的至少一个包括电介质材料。
在框1406处，过程包括：平坦化第一衬底的第一表面，以形成第一平坦键合表面，第一平坦键合表面包括第一表面和一个或多个第一嵌入导电互连结构的暴露表面。
在一种实施方式中，过程包括在第二衬底中形成一个或多个第二嵌入导电互连结构，包括将第二嵌入导电互连结构中的一个或多个第二嵌入导电互连结构形成为在一个或多个第二嵌入导电互连结构的暴露表面中具有第二凹进部分；平坦化第二衬底的第一表面以形成第二平坦的键合表面，该键合表面包括第二衬底的第一表面和一个或多个第二嵌入导电互连结构的暴露表面；在没有粘合剂的情况下，经由直接键合将第二衬底的第二平坦键合表面键合到第一衬底的第一平坦键合表面；以及将一个或多个第二嵌入导电互连结构直接键合到一个或多个第一嵌入导电互连结构。
在另外的实施方式中，过程包括在一个或多个第二嵌入导电互连结构的第二凹进部分之上沉积保护层。在示例中，过程包括：通过利用保护层覆盖第二凹进部分的表面，来抑制第二凹进部分的材料的原子的表面移动。在另一示例中，过程包括：通过利用保护层覆盖第二凹进部分的表面，来控制一个或多个第二嵌入导电互连结构的材料的膨胀的方向。
作为备选实施方式，过程包括：在第一衬底的第一表面中形成一个或多个第一腔；形成一个或多个第一嵌入导电互连结构，该第一嵌入导电互连结构具有在一个或多个第一腔内的一个或多个开口；以及形成平坦表面，该平坦表面包括具有一个或多个开口的第一嵌入导电互连结构中的一个或多个。
作为另一备选实施方式，过程包括：在第一衬底的第一表面中形成一个或多个第一腔；形成一个或多个第一嵌入导电互连结构，该第一嵌入导电互连结构具有在一个或多个第一腔内的一个或多个开口；形成平坦表面，该平坦表面包括具有一个或多个开口的第一嵌入导电互连结构中的一个或多个第一嵌入导电互连结构；以及将具有开口的互连结构的平坦表面直接键合到第二衬底的制备的表面。
在各种实施例中，与本文描述的过程步骤相比，一些过程步骤可以被修改或消除。
本文所描述的技术、部件和设备不限于图1A至图14的图示，并且可以在不脱离本公开的范围的情况下被应用于其他设计、类型、布置和构造，包括与其他电气部件一起被应用。在一些情况下，可以使用附加或备选的部件、技术、序列或过程来实现本文所述的技术。此外，可以以各种组合来布置和/或组合部件和/或技术，同时产生相似或近似相同的结果。
结论
尽管已经以结构特征和/或方法论行为专用的语言描述了本公开的实施方式，但是应当理解的是，这些实施方式不必限于所描述的特定特征或行为。相反，公开了特定特征和行为作为实现示例设备和技术的代表性形式。

Claims (26)

1.一种微电子组件，包括：
第一衬底，具有键合表面，所述第一衬底的所述键合表面具有平坦的形貌；
第一导电互连结构和第二导电互连结构，被嵌入在所述第一衬底中并且在所述第一衬底的所述键合表面处暴露，所述第二导电互连结构在所述键合表面处具有比所述第一导电互连结构更大的表面积；
第一凹进部分，被布置在所述第一导电互连结构的表面中；以及
第二凹进部分，被布置在所述第二导电互连结构的表面中，所述第二凹进部分具有比所述第一凹进部分大的体积，所述第一凹进部分至少部分地填充有第一嵌入层的第一部分，并且所述第二凹进部分至少部分地填充有第一嵌入层的第二部分，所述第一导电互连结构比所述第一嵌入层的所述第一部分更宽，并且所述第二导电互连结构比所述第一嵌入层的所述第二部分更宽。
2.根据权利要求1所述的微电子组件，还包括：第二衬底，具有键合表面，所述第二衬底的所述键合表面具有平坦的形貌，并且在没有粘合剂的情况下被直接键合到所述第一衬底的所述键合表面；以及
第一导电互连结构和第二导电互连结构，被嵌入在所述第二衬底中并且在所述第二衬底的所述键合表面处暴露，所述第二衬底的所述第二导电互连结构在所述键合表面处具有比所述第二衬底的所述第一导电互连结构更大的表面积，所述第二衬底的所述第一导电互连结构被直接键合到所述第一衬底的所述第一导电互连结构，并且所述第二衬底的所述第二导电互连结构被直接键合到所述第一衬底的所述第二导电互连结构。
3.根据权利要求2所述的微电子组件，还包括：第一凹进部分，被布置在所述第二衬底的所述第一导电互连结构的表面中；以及第二凹进部分，被布置在所述第二衬底的所述第二导电互连结构的表面中，所述第二衬底的所述第一凹进部分和所述第二凹进部分至少部分地填充有第二嵌入层，所述第二嵌入层在没有粘合剂的情况下被直接键合到所述第一嵌入层。
4.根据权利要求3所述的微电子组件，其中所述第一衬底和所述第二衬底的所述第一导电互连结构形成第一导电互连，并且所述第一衬底和所述第二衬底的所述第二导电互连结构形成第二导电互连，并且其中所述第一衬底和所述第二衬底的所述第一凹进部分在所述第一导电互连内形成第一腔，并且所述第一衬底和所述第二衬底的所述第二凹进部分在所述第二导电互连内形成第二腔，所述第一腔和所述第二腔完全衬有所述第二嵌入层和所述第一嵌入层。
5.根据权利要求4所述的微电子组件，其中所述第二腔的体积大于所述第一腔的体积。
6.根据权利要求2所述的微电子组件，其中所述第一衬底和所述第二衬底的所述第二导电互连结构具有大于5微米的表面宽度尺寸。
7.根据权利要求1所述的微电子组件，还包括在所述第一衬底的所述第一和/或第二导电互连结构的周界内、在所述第一衬底的所述第一和/或第二导电互连结构的所述表面中的一个或多个腔，所述一个或多个腔填充有所述第一嵌入层。
8.根据权利要求1所述的微电子组件，其中所述第一嵌入层包括含硅材料。
9.根据权利要求8所述的微电子组件，其中所述含硅材料包括SiC、SiC/SiO2、SiN/SiO2或硅化物。
10.根据权利要求1所述的微电子组件，其中所述第一嵌入层包括导电材料，所述第一嵌入层的导电材料不同于所述第一导电互连结构和所述第二导电互连结构的材料。
11.根据权利要求1所述的微电子组件，其中所述第一嵌入层的材料的熔点或热膨胀系数大于所述第一导电互连结构的材料的熔点或热膨胀系数。
12.一种微电子组件，包括：
第一衬底，具有键合表面，所述第一衬底的所述键合表面具有平坦的形貌，第一导电互连结构被嵌入在所述第一衬底中，在所述第一导电互连结构的所述表面的一部分上具有第一嵌入层；
第二衬底，具有键合表面，所述第二衬底的所述键合表面具有平坦的形貌，第二导电互连结构被嵌入在所述第二衬底中，在所述第二导电互连结构的所述键合表面的一部分上具有第二嵌入层；
键合界面，在键合界面处所述第一衬底的所述键合表面被键合到所述第二衬底的所述键合表面，所述第一衬底和所述第二衬底的所述第一嵌入层和所述第二嵌入层接触并且形成封闭的腔，所述第一导电互连结构的一部分接触所述第二导电互连结构的一部分。
13.根据权利要求12所述的微电子组件，其中所述第一嵌入层和所述第二嵌入层分别与所述第一导电互连结构和所述第二导电互连结构适形。
14.根据权利要求12所述的微电子组件，其中所述腔在所述键合界面下方延伸超过100nm。
15.一种微电子组件，包括：
第一衬底，具有键合表面，所述第一衬底的所述键合表面具有平坦的形貌；
一个或多个第一导电互连结构，被嵌入在所述第一衬底中并且在所述第一衬底的所述键合表面处暴露；
第一凹进部分，被布置在所述一个或多个第一导电互连结构中的至少一个第一导电互连结构的表面中，其中所述第一凹进部分的深度大于20nm；以及
保护层的一部分，被布置在所述第一凹进部分中，所述保护层的所述部分和所述一个或多个第一导电互连结构中的所述至少一个第一导电互连结构的一部分被暴露在所述键合表面。
16.根据权利要求15所述的微电子组件，还包括：第二衬底，具有键合表面，所述第二衬底的所述键合表面具有平坦的形貌，并且在没有粘合剂的情况下被直接键合到所述第一衬底的所述键合表面；以及
一个或多个第二导电互连结构，被嵌入在所述第二衬底中并且在所述第二衬底的所述键合表面处暴露，所述一个或多个第二导电互连结构被直接键合到所述一个或多个第一导电互连结构。
17.根据权利要求16所述的微电子组件，还包括被布置在所述一个或多个第二导电互连结构中的至少一个第二导电互连结构的表面中的第二凹进部分，所述第二凹进部分的体积对应于所述一个或多个第二导电互连结构的导电材料在被加热到预先确定温度时的膨胀。
18.根据权利要求17所述的微电子组件，其中所述一个或多个第二导电互连结构和所述一个或多个第一导电互连结构形成一个或多个导电互连，并且其中所述第一凹进部分和所述第二凹进部分在所述一个或多个导电互连中的至少一个导电互连内形成腔。
19.根据权利要求18所述的微电子组件，其中所述腔部分地或全部衬有所述保护层。
20.根据权利要求19所述的微电子组件，其中所述保护层包含硅。
21.根据权利要求20所述的微电子组件，其中所述保护层包括SiC、SiC/SiO2或SiN/SiO2。
22.根据权利要求21所述的微电子组件，其中所述一个或多个第一导电互连结构具有大于10微米的表面宽度尺寸。
23.根据权利要求19所述的微电子组件，其中所述保护层包括钨、钨的合金、镍、镍的合金、钴、钴的合金、钽、钽的合金、钛或钛的合金。
24.根据权利要求19所述的微电子组件，还包括被布置在所述保护层之上的电介质层。
25.根据权利要求15所述的微电子组件，其中所述第一凹进部分被布置在所述一个或多个第一导电互连结构的周界内。
26.根据权利要求15所述的微电子组件，其中所述一个或多个第一导电互连结构包括多个导电互连结构，所述多个导电互连结构在所述键合表面处具有不同宽度和/或表面积。
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