CN108140405B - 用于双极存储器写入验证的方法和装置 - Google Patents

用于双极存储器写入验证的方法和装置 Download PDF

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CN108140405B
CN108140405B CN201680053000.5A CN201680053000A CN108140405B CN 108140405 B CN108140405 B CN 108140405B CN 201680053000 A CN201680053000 A CN 201680053000A CN 108140405 B CN108140405 B CN 108140405B
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N·伯杰
B·S·路易
M·艾尔-巴拉吉
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Abstract

公开了一种用于双极存储器器件的有利的写入验证操作。验证操作在与写入操作相同的偏置条件下执行。因此，该验证操作减少了在以与写入操作相反的偏置执行验证操作时引起的干扰状况。有利的写入验证操作可以利用源线和位线上的控制逻辑来执行。在另一实施例中，利用耦合到控制逻辑的多路复用器执行有利的写入操作。多路复用器根据程序锁存器中的数据确定是应该执行验证(0)还是验证(1)操作。此外，多路复用器可以基于寄存器位选择用于读取操作的偏置条件。微调电路可选地提供保护带并修改参考电压，用于以与正常读取操作相反的极性执行的验证操作。

Description

用于双极存储器写入验证的方法和装置
技术领域
本专利文件总地涉及随机存取存储器(RAM)。更具体地，本专利文件涉及包括双极存储器元件的RAM中的写入验证操作。这里描述的方法和器件在自旋传递扭矩磁性存储器(spin-transfer torque magnetic memory，STT-MRAM)器件中是特别有用的。
背景技术
磁阻随机存取存储器(Magnetoresistive random-access memory，“MRAM”)是通过磁存储元件存储数据的非易失性存储器技术。这些元件是两个铁磁板或电极，它们可以保持磁场并且被诸如非磁性金属或绝缘体之类的非磁性材料分开。这种结构被称为磁性隧道结(magnetic tunnel junction，“MTJ”)。通常，其中一个板具有其钉扎的磁化(即“参考层”)，这意味着该层具有比其他层更高的矫顽力，并且需要更大的磁场或自旋极化电流来改变其磁化取向。通常将第二个板称为自由层，并且可以通过相对于参考层的较小磁场或自旋极化电流来改变其磁化方向。
MRAM器件通过改变自由层的磁化取向来存储信息。具体地，基于自由层相对于参考层是平行还是反平行对准，可以在每个MRAM单元中存储“1”或“0”。由于自旋极化电子隧穿效应，单元的电阻由于两层磁场的取向而改变。单元的电阻对于平行和反平行状态将是不同的，因此单元的电阻可以用来区分“1”和“0”。MRAM器件的一个重要特征是它们是非易失性存储器器件，因为即使在断电的情况下它们也能保持信息。这两个板的横向尺寸可以是亚微米的，并且磁化方向相对于热波动仍然是稳定的。
MRAM器件被认为是用于广泛存储器应用的下一代结构。基于自旋扭矩传递切换的MRAM产品已经进入大型数据存储器件。自旋传递扭矩磁性随机存取存储器(“STT-MRAM”)或自旋传递切换，使用自旋对准(“极化”)电子来改变磁性隧道结中自由层的磁化取向。一般来说，电子拥有自旋、电子固有的量子化数目的角动量。电流通常是非极化的，即它由50％上旋和50％下旋的电子组成。通过磁性层流过的电流以与磁性层(即偏振器)的磁化取向相对应的自旋取向使电子极化，从而产生自旋极化电流。如果自旋极化电流流过磁性隧道结器件中的自由层的磁性区域，则电子将其自旋角动量的一部分传递到磁化层，以在自由层的磁化上产生扭矩。因此，该自旋传递扭矩可以切换自由层的磁化，实际上，根据自由层相对于参考层是处于平行状态还是反平行状态，该自由层来写入“1”或“0”。
STT-MRAM器件属于依赖于双极存储器元件的一类器件。双极存储器元件使用电流将数据“写入”存储器元件。根据电流的流动方向，逻辑高(1)或逻辑低(0)位可以被写入存储器元件。这种双极存储器器件可以包括MRAM、电阻随机存取存储器(RRAM)、相变存储器(PCM)等等。例如，RRAM器件可以利用忆阻器作为存储器元件。沿一个方向流动的电流可以用于将逻辑(1)写入忆阻器。在相反方向上流动的电流可以用于将逻辑(0)写入忆阻器。
在图1中示出了具有偏振器层和MTJ的典型MRAM器件。图1示出了用于常规STT-MRAM器件的垂直磁性隧道结(“MTJ”)叠层100。如图所示，叠层100包括提供在叠层100的底部的一个或更多个籽晶层110，以在上面的沉积层中引发所期望的晶体生长。此外，MTJ 130被沉积在SAF层120的顶部。MTJ 130包括参考层132(其是磁性层)，非磁性隧穿势垒层(即，绝缘体)134和自由层136(其也是磁性层)。应该理解的是，参考层132实际上是SAF层120的一部分，但是当在参考层132上形成非磁性隧穿势垒层134和自由层136时，形成MTJ 130的一个铁磁板。如图1所示，磁性参考层132具有垂直于其平面的磁化方向。还如图1所示，自由层136也具有垂直于其平面的磁化方向，但其方向可以变化180度。
SAF层120中的第一磁性层114设置在籽晶层110之上。SAF层120还具有设置在第一磁性层114之上的反铁磁性耦合层116。此外，非磁性间隔层140设置在MTJ 130的顶部，以及可选的偏振器150设置在非磁性间隔层140的顶部。偏振器150是磁性层，其在一个实施例中在其平面内具有磁性方向，但是垂直于参考层132和自由层136的磁性方向。偏振器150被提供以使施加到MTJ结构100的电子(“自旋对齐的电子”)的电流极化。注意，在其他实施例中，如果存在偏振器150，则其也可以具有垂直于其平面的磁性方向，正如参考层132和自由层136。此外，可以在偏振器150的顶部提供一个或更多个覆盖层160，以保护MTJ叠层100上的下面的层。最后，使用反应离子蚀刻(RIE)工艺，在覆盖层160上沉积硬掩模170，且提供硬掩模170以图案化MTJ结构100的下层。
磁性存储器器件的电阻对自由磁性层的磁化矢量与参考层的磁化矢量的相对取向是敏感的。当自由磁性层和参考层的磁化矢量分别反平行对准时，磁性存储器器件的电阻最高。当自由磁性层和参考层的磁化矢量分别平行对准时，磁性器件的电阻最低。因此，电阻测量或其等同可以确定自由磁性层的磁化矢量的取向。
在MRAM存储器写入操作中，验证操作可以用于检查写入操作是否已经成功完成并且已经写入了正确的数据。通常，验证操作以与读取操作类似的方式执行。例如，可以在偏压条件下实现读取，其中位线(bit line)被驱动到高电势，而源线(source line)被驱动到低电势以穿过MTJ产生电流，从而可以进行电阻测量。验证操作也可以在包括RRAM和PCM等的其他双极存储器元件中实现。
在这些器件中，数据在写入操作和验证操作期间存储在程序锁存器中。存储在锁存器(写入缓冲器)中的数据决定写入操作期间位线上的电压状况。在写入操作中，位线和源线偏置取决于所存储的数据。例如，如果要写入的数据是逻辑零(0)，则位线可以被驱动为高，而源线被驱动为低。如果要写入的数据是逻辑1(1)，将需要存在相反的偏置条件，以便使穿过MTJ的电流的极性反向，在这种情况下，为了写入逻辑1(1)，源线将被驱动为高，而位线将被驱动为低。
在读取操作或验证操作期间，位线通常处于高电压(但是比写入操作期间处于较低的电压)，而源线处于低电压，通常接近零伏特。通常，写入验证操作可以以与读取操作类似的方式来实现。然而，上述操作可能导致所谓的干扰状况，这是在写入逻辑1(1)操作之后执行验证操作时发生的。在这种情况下，随着源线被驱动至高电压而位线被驱动到低电压，存储器位被写入。因此，在验证操作期间，数据将被读取，其位线和源线的极性与在读取操作期间通常的极性相反。用于写入、读取和验证操作的先前电路在图2A和2B中示出。
图2A示出了在写入(0)、验证和读取操作期间示例性双极存储器器件200(在这种情况下为MRAM器件)的操作。双极存储器器件200包括耦合到源线208和位线210的存储器单元202。存储器单元202包括MTJ 204和选择晶体管206。选择晶体管进一步耦合到字线212。MTJ 204耦合到位线210，并且选择晶体管206耦合到源线208。本领域的普通技术人员将理解的是，相反的配置也是可能的。也就是说，MTJ 204可以耦合到源线208，而选择晶体管206可以耦合到位线210。
在写入(0)、验证和读取操作期间，源线上的电压节点214被驱动为低，而位线上的电压节点216被驱动为高。相反的偏置条件也可以适用于写入(0)、验证和读取操作，并且简单地依赖于写入(0)的命名规则(naming convention)。读者也将会理解的是，验证和读取操作在相同的偏置条件下发生。电压节点214可被驱动到接地或以其他方式保持接近0V。电压节点216可被驱动到正电压。例如，电压节点216被驱动到1.0V用于验证操作；1.2V用于读取操作；以及更高电压用于写入操作。电压被施加到字线212以激活选择晶体管206，以允许电流i在位线和源线之间流动。
在写入(0)操作期间，存储器单元202两端的电压差导致电流i流动。电流i导致MTJ204的自由层的磁化，以与MTJ 204的参考层对准或变得与其平行。在验证和读取操作期间，电流i不足以改变自由层的状态，并且存储在MTJ 204中的位可以被确定。
图2B示出了在写入(1)操作期间的示例性双极存储器器件250(在该示例中是MRAM器件)的操作。双极存储器器件250包括耦合到源线258和位线260的存储器单元252。存储器单元252包括MTJ 254和选择晶体管256。选择晶体管进一步耦合到字线262。MTJ 254耦合到位线260，并且选择晶体管256耦合到源线258。本领域的普通技术人员将理解的是，相反的配置也是可能的。也就是说，MTJ 254可以耦合到源线258，而选择晶体管256可以耦合到位线260。
除了源线和位线上的电压的极性被翻转之外，图2B的双极存储器器件250与图2A的双极存储器器件200相同。因此，源线258上的电压节点264被驱动为高而位线260上的电压节点266被驱动为低。电压节点264对于写入(1)操作也可以处于比写入(0)操作期间位线上的对应电压略高的电压。这是因为在该配置中，选择晶体管256两端的电压降较高。而且，字线262上的电压被选择以使电流流动。这种相反的偏置条件使得电流i沿着与图2A的双极存储器器件200相反的方向流动。这导致了写入(1)操作。
然而，执行如图2B所示的写入(1)操作以及然后执行如图2A所示的验证操作，导致干扰状况。这是因为相反的偏置电压被施加到源线和位线，用于写入(1)操作和验证操作。
因此，在验证双极存储器器件中的数据位时，有利的写入-验证操作对于减少干扰状况是必要的。
发明内容
本公开的示例性实施例涉及双极存储器器件中有利的写入验证操作。此外，本公开公开了有益的读取操作。
公开了一种用于双极存储器器件的有利的写入验证操作。验证操作在与写入操作相同的偏置条件下执行。因此，验证操作减少了在以与写入操作相反的偏置执行验证操作时引起的干扰状况。
在一个实施例中，该方法包括将数据位写入存储器单元。存储器单元包括双极存储器元件和选择晶体管。存储器单元耦合在位线与源线之间。通过在源线和位线两端施加第一电压来提供第一电流以将数据位写入存储器单元，来执行写入操作。如果要将逻辑高写入存储器单元，则第一电压差可以包括第一极性。如果要将逻辑低写入存储器单元，则第一电压差可以是第二极性。
该方法还可以包括通过在存储器单元两端施加第二电压来验证写入存储器单元的数据位。如果逻辑高被写入，则第二电压差可以是第一极性。类似地，如果逻辑低被写入，则第二电压差可以是第二极性。
在一个实施例中，可以使用耦合到源线的第一偏置电路和耦合到位线的第二偏置电路来施加第一电压差。在一个实施例中，同样可以使用耦合到源线的第一偏置电路和耦合到位线的第二偏置电路来施加第二电压差。在另一实施例中，验证操作可使用耦合到源线的读出放大器(sense amplifier)来检测对应于双极存储器元件中的数据位的逻辑电平。在另一实施例中，验证操作可以使用耦合到位线的读出放大器来检测对应于双极存储器元件中的数据位的逻辑电平。在另一实施例中，第二电压差可以通过施加第二电压差时微调(trimming)所施加的电压来施加。第二电压差与读取操作期间施加的电压差的极性相反。
在另一实施例中，耦合到多路复用器(mux)的偏置电路可以施加第一电压差。多路复用器可以耦合到源线和位线。多路复用器可以根据程序锁存器中的数据来选择是否将源线或位线上的电压驱动为高。在另一实施例中，耦合到多路复用器的偏置电路可以施加第二电压差。多路复用器可以耦合到源线和位线。多路复用器可以根据程序锁存器中的数据来选择是否将源线或位线上的电压驱动为高。
在另一个实施例中，公开了一种有利的读取操作。读取操作可以包括通过施加第二电压差来读取写入存储器单元的数据位。读取操作可以通过基于耦合到源线和位线的多路复用器中的寄存器位选择是否将源线或位线驱动为高来执行。在一个实施例中，选择将源线驱动为高以执行读取操作。在另一实施例中，选择将位线驱动为高以执行读取操作。
在实施例中，双极存储器元件可以包括磁性隧道结、垂直磁性隧道结、忆阻器或硫属化物玻璃。
可以利用源线和位线上的控制逻辑来执行有利的写入验证操作。在另一实施例中，利用耦合到控制逻辑的多路复用器(mux)来执行有利的写入操作。多路复用器根据程序锁存器中的数据确定是应该执行验证(0)还是验证(1)操作。此外，多路复用器可以基于寄存器位来选择用于读取操作的偏置条件。微调电路可选地提供保护带并修改参考电压，用于以与正常读取操作相反的极性执行的验证操作。
本公开在与写入操作相同的偏置条件下，执行双极存储器器件的验证操作。因此，如果写入(0)操作在位线为高且源线为低的情况下执行，则验证(0)操作也在位线为高且源线为低的情况下执行。类似地，如果写入(1)操作在位线为低且源线为高的情况下执行，则验证(1)操作也可以在位线为低且源线为高的情况下执行。这与在一个偏置条件(例如，位线为高且源线为低)下执行的过去的验证操作相比是不同的。如果是这种情况，则验证(1)操作以与写入(1)操作相反的偏置执行，其导致干扰情况。
此外，本公开利用若干示例性双极存储器器件来执行验证操作。在一个实施例中，可以通过将一个或更多个偏置电路分别耦合到源线和位线中的每一个，来实现对施加在源线和位线上的逻辑电平的控制。在替代实施例中，可以使用耦合至多路复用器的偏置电路来实现对施加在源线和位线上的逻辑电平的控制。在替代实施例中，偏置电路本身可以被集成到读出放大器。
在实施例中，例如微调电路补偿验证(1)操作在与读取操作相反的偏置条件下执行的事实。由于晶体管两端的电压降可能因读取/验证偏置而不同，因此微调电路可根据需要调整电压。
因为验证操作与读取操作类似地执行，所以在实施例中，多路复用器可以基于寄存器位来选择读取操作的方向。如果读取操作应该在验证(0)方向上执行，则寄存器位可以确定源线应该被驱动为低，而位线应该被驱动为高。如果读取操作应该在验证(1)方向上执行，则寄存器位可以确定源线应该被驱动为高，而位线应该被驱动为高。
附图说明
作为本说明书的一部分而包括的附图示出了当前优选的实施例，并且与上面给出的一般性描述以及下面给出的优选实施例的详细描述一起，用于解释和教导本文描述的原理。
图1示出了示例性垂直磁性隧道结叠层(MTJ)100。
图2A示出了在写入(0)、读取及验证操作期间的示例性双极存储器器件200的操作。
图2B示出了在写入(1)操作期间的示例性双极存储器器件250的操作。
图3A示出了在写入(0)、读取及验证(0)操作期间的示例性双极存储器器件300的操作。
图3B示出了在写入(1)及验证(1)操作期间的示例性双极存储器器件350的操作。
图4示出了具有控制逻辑的示例性双极存储器器件400。
图5示出了具有控制逻辑和多路复用器的示例性双极存储器器件500的替代实施例。
具体实施方式
呈现以下描述以使得本领域的任何技术人员能够利用有利的写入验证操作来创建和使用双极存储器器件。这里公开的每个特征和教导可以单独使用或者与其他特征结合使用，以实现所公开的装置和方法。参考附图更详细地描述了单独和组合地利用这些附加特征和教导中的许多的代表性示例。该详细描述仅旨在教导本领域技术人员用于实践本教导的优选方面的更多细节，而不旨在限制权利要求的范围。因此，在下面的详细描述中公开的特征的组合对于以最宽泛的意义来实践教导可能不是必需的，而是被教导仅仅是为了描述本教导的特别代表性的示例。
在下面的描述中，仅为了解释的目的，阐述特定的术语以提供对本教导的透彻理解。然而，对于本领域技术人员来说显而易见的是，这些特定的细节对实践本教导来说是不需要的。本公开的特征和优点通过示例性STT-MRAM器件而被教导。然而，本领域的普通技术人员将理解的是，本公开的教导适用于其他双极存储器元件，包括使用其他双极存储器元件的MRAM、RRAM、PCM和RAM。
图3A和3B示出了利用本公开的有利写入验证操作的双极存储器器件300和350。注意，图3A-3B、图4和图5示出了面内MTJ，其中自由层和参考层的磁化方向在层的平面内。这里描述的实施例同样适用于垂直MTJ(其中自由层和参考层的磁化方向在层的平面之外)。本公开使得验证操作能够在与写入操作相同的偏置条件下发生。因此，验证(0)使用与写入(0)相同的偏置条件发生。同样，验证(1)在与写入(1)相同的偏置条件下发生。偏置条件是指双极存储器元件上的电压的极性而不是电压值。如将在本公开中更详细解释的，对于写入、验证和读取操作，电压条件的绝对值可以是不同的。
由于在验证操作期间数据是已知的，因此验证操作可以以与写入操作期间相同的操作极性来实现。这样做避免了干扰问题，因为对于写入操作和验证操作两者，电流流向是沿相同的方向。与写入操作的情况一样，在验证操作期间，存储在写入锁存器/缓冲器中的数据(例如逻辑低(0)或逻辑高(1))将确定偏置条件(例如，源线和位线上的低电压或高电压)。注意，写入锁存器/缓冲器被设置在存储器阵列附近。在存储器阵列和写入/锁存器缓冲器之间可以解码或可以不解码，以减少所需的写入/锁存器缓冲器的总数。在替代实施例中，写入锁存器/缓冲器可以与读出放大器块组合。
图3A示出了在写入(0)、验证(0)和读取操作期间的示例性双极存储器器件300的操作。双极存储器器件300包括耦合到源线308和位线310的存储器单元302。存储器单元302包括MTJ 304和选择晶体管306。选择晶体管进一步耦合到字线312。MTJ 304耦合到位线310，并且选择晶体管306耦合到源线308。本领域的普通技术人员将理解的是，相反的配置也是可能的。也就是说，MTJ 304可以耦合到源线308，而选择晶体管306可以耦合到位线310。
在写入(0)、验证(0)和读取操作期间，源线308上的电压节点314被驱动为低，而位线310上的电压节点316被驱动为高。相反的偏置条件也可以适用于写入(0)、验证(0)和读取操作，并且简单地依赖于写入(0)的命名规则。电压节点314可以被驱动到接地或以其他方式保持接近0V。电压节点316可以被驱动为正电压。例如，电压节点316被驱动到1.0V用于验证操作；1.2V用于读取操作；以及更高电压用于写入操作。应注意，验证操作通常比读取操作更严格。这是为了确保将来的读取操作正确地发生。因此，验证和读取操作也可以在相同电压(例如1.2V)下完成。然而，施加用于验证操作的电压的时间(例如，18ns)可以比施加用于读取操作的时间(例如，20ns)更少。或者，读取和验证可以在相同的电压和时序下，使用针对这两个操作不同的参考电压来执行。电压被施加到字线312以激活选择晶体管306，以允许电流i在位线和源线之间流动。
与示例性双极存储器器件350的操作一致，在写入(0)操作期间，电流i导致MTJ304的自由层的磁化以与MTJ 304的参考层对准或变得平行。本领域的普通技术人员将理解的是，在其他实施例中，电流i可能导致MTJ 304的自由层变得与参考层反平行，这将导致依赖于命名规则的写入(1)或(0)操作。在读取操作期间，电流i不足以改变自由层的状态，并且存储在MTJ 304中的位可以被确定。通常，施加到电压节点316的验证电压低于用于读取操作的电压，以确保将来的读取操作是准确的。然而，这可能不一定是这种情况，验证电压可以处于与读取电压相同的电压值，但是如上所述仅仅施加较短的时间。
总之，当写入逻辑低(0)时，位线上将会施加高电压，并且源线上将会施加低电压。在该写入操作的验证操作期间，位线上也将会施加高电压，而源线上将会施加低电压。
图3B示出了在写入(1)和验证(1)操作期间的示例性双极存储器器件350的操作。双极存储器器件350包括耦合到源线358和位线360的存储器单元352。存储器单元352包括MTJ 354和选择晶体管356。选择晶体管进一步耦合到字线362。MTJ 354耦合到位线360，并且选择晶体管306耦合到源线308。本领域的普通技术人员将理解的是，相反的配置也是可能的。也就是说，MTJ 354可以耦合到源线358，而选择晶体管356可以耦合到位线360。
除了源线和位线的电压的极性被翻转之外，图3B的双极存储器器件350与图3A的双极存储器器件300相同。因此，源线358上的电压节点364被驱动为高而位线360上的电压节点366被驱动为低。电压节点364对于写入(1)操作也可以处于比写入(0)操作期间位线上的对应电压略高的电压。这是由于选择晶体管356引起的电压降。还可能由于如果位线和源线垂直(而不是如图3A和3B所示的平行)造成的寄生损失而发生电压下降。而且，选择晶体管362两端的电压被改变以使电流能够流动。这种相反的偏置条件导致电流i沿着与图3A的双极存储器器件300相反的方向流动。这导致了写入(1)操作。与示例性双极存储器器件350的操作一致的是，在写入(1)操作期间，电流i使MTJ 354的自由层的磁化变得与MTJ 304的参考层反平行。本领域的普通技术人员将理解的是，在其他实施例中，电流i可能导致MTJ354的自由层变得与参考层平行，这将导致依赖于命名规则的写入(1)或(0)操作。验证(1)操作也在相同的偏置条件下执行。
与写入逻辑低(0)的情况不同，当写入逻辑高(1)时，在位线上施加低电压，而在源线上施加高电压。在这种写入操作的验证操作期间，与过去的器件不同，在位线上也施加了低电压，而在源线上也施加了低电压。这与之前的器件完全相反，并且可以提供更快的验证操作。此外，因为写入(1)和验证(1)操作是在相同的极性下执行的，所以这样的验证操作不会导致干扰状况，因为当从写入操作转换到验证操作时，位线和源线不需要改变到相反的极性。对于写入和验证两者，位线保持在低电压。同样地，对于写入和验证两者，源线保持在高电压，尽管在写入操作期间电压水平本身应该低于源线上的电压水平。
图4示出了双极存储器器件400。在读取、写入和验证操作期间，已经结合图3A和图3B讨论了双极存储器器件400的基本操作。用于执行读取、写入和验证操作的控制逻辑的操作将在图4的背景下讨论。
双极存储器器件400还包括耦合到源线408的控制逻辑414。此外，双极存储器器件400包括耦合到位线410的控制逻辑416。控制逻辑414和416可以包括读出放大器、偏置电路和程序锁存器。如在图4可以看出，可以通过分别将一个或更多个偏置电路耦合到源线和位线中的每一个，来实现对施加在源线410和位线408上的逻辑电平的控制。
如图3A和3B所述，在写入操作期间，耦合到位线408和源线410的偏置电路驱动位线和源线上的电压。用于驱动电压的偏置电路的配置对于本领域的普通技术人员是已知的。此外，在读取和验证操作期间，耦合到源线和位线的读出放大器可用于确定写入MTJ404的逻辑电平。
在写入和验证操作期间，可以使用耦合到偏置电路的程序锁存器来确定将要施加在源线和位线上的电压。即程序锁存器确定逻辑高(1)应当在前一个写入周期期间已经被写入MTJ 404。然后，如图3B所述，偏置电路将驱动源线为高，并且位线为低，以执行写入(1)和验证(1)操作。
偏置电路可以可选地包括微调电路。微调电路执行各种功能。首先，在验证(0)操作期间，微调电路可以降低用于验证操作的电压或施加电压的时间。这是因为验证操作应该比读取操作更严格地被执行。因此，在验证操作期间，微调电路执行保护带功能。此外，验证(1)操作在与读取操作相反的极性下发生。因此，微调电路可以翻转在正常读取操作期间所施加的电压，以便执行验证(1)操作。因为如图3A所述的验证(1)操作导致选择晶体管两端的电压降，所以与在验证(0)操作期间施加到位线的电压相比，微调电路还可以增加源线上的电压。因此，微调电路根据需要微调施加到源线和位线上的电压，以执行验证操作。随后，源线408上的读出放大器414或位线410上的读出放大器416可用于确定写入MTJ 404的逻辑电平。
双极存储器器件的设计者通常还在测试期间调整微调电路，以确保双极存储器器件在场内正常工作。通常，微调电路针对工艺变化和温度效应(process variation andtemperature effects，PVT)进行调整，以确保源线和位线被驱动到适当的电压。此外，微调电路可以被调整，使得通过双极存储器器件的电流不会损坏双极存储器器件的组件，诸如选择晶体管和双极存储器元件。因此，在制造双极存储器器件之后，可以使用微调电路来增加双极存储器器件的产量。
图5示出了用于示例性双极存储器器件500的替代实施例。在读取、写入和验证操作期间，已经结合图3A和图3B讨论了双极存储器器件500的基本操作。用于执行读取、写入和验证操作的控制逻辑和多路复用器的操作将在图5的背景下讨论。
双极存储器器件500进一步包括耦合到源线508和位线510的多路复用器514。此外，双极存储器器件500包括耦合到多路复用器514的控制逻辑516。控制逻辑516可以包括读出放大器、偏置电路和程序锁存器。
如图5所示，可以用多路复用的单个读出放大器来实现对施加在源线和位线上的逻辑电平的控制。Mux 514的选择输入是在程序锁存器中的在写入操作期间被写入到MTJ504的值。因此，在写入和验证操作期间，多路复用器514选择是否应由控制逻辑516中的偏置电路将位线或源线驱动为高。因此，例如，控制逻辑516中的偏置电路使得位线在写入(0)操作期间被驱动为高，并且源线在写入(1)操作期间被驱动为高。
如在图4中示出的实施例的背景下所描述的，器件应该补偿对写入逻辑电平高(1)操作的验证将导致位线和源线具有与在读取操作期间所使用的极性相反极性的事实。在验证逻辑电平高(1)操作期间，可以通过偏移电压/电流参考实现这种补偿，例如经由具有微调电路的偏置电路。这允许在正常读取操作期间补偿位线和源线上的逻辑电平。逻辑电平高(1)的写入验证操作将需要通过晶体管，然而正常读取操作时位线被驱动为高，以及因此电压不会在穿过晶体管时损失。或者，也可以通过移位或重新调节用于验证写入逻辑电平低(0)和逻辑电平高(1)两者的电压/电流参考窗口来实现这种补偿。这可以通过在写入验证操作期间，将逻辑电平高和逻辑电平低的两个跳变点移位来实现。
多路复用器514也可以用于确定是否应该通过驱动源线为高或位线为高来执行读取操作。如前述所讨论的，类似于验证操作实现读取操作。因此，尽管如在图3A中所述用位线为高和源线为低来执行，读取操作也可以在位线为低和源线为高的情况下执行，类似于图3B的验证(1)操作。多路复用器514根据寄存器位来选择位线还是源线应该被驱动为高。例如，如果读取操作在源线为高以及位线为低时执行得更精确，则可以将寄存器位设置为使得偏置电路将源线驱动为高用于读取操作。当设置寄存器位时，也可以考虑诸如功率和可靠性等其他考虑因素。
以上描述和附图仅被认为是说明实现在此描述的特征和优点的特定实施例。可以对特定的工艺条件进行修改和替换。因此，本专利文件中的实施例不被认为受到前面的描述和附图的限制。

Claims (23)

1.一种用于将数据写入存储器器件的方法，所述方法包括：
将数据位写入存储器单元，其中所述存储器单元包括位线和源线，并且其中，所述存储器单元包括双极存储器元件，所述写入包括：
如果所述数据位是第一逻辑值，则在所述位线和所述源线两端施加具有第一极性的第一差分电压；以及
如果所述数据位是第二逻辑值，则在所述位线和所述源线两端施加具有第二极性的第二差分电压，其中所述第二极性与所述第一极性相反；以及
在所述将数据位写入存储器单元之后，验证所述存储器单元的所述位，包括：
当所述数据位是所述第一逻辑值时，在所述位线和所述源线两端施加具有所述第一极性的又一差分电压；或
当所述数据位是所述第二逻辑值时，在所述位线和所述源线两端施加具有所述第二极性的又一差分电压，
当验证操作在与读取操作相反的极性下发生时，施加到所述位线和所述源线的电压可以被微调电路微调以执行所述验证操作。
2.根据权利要求1所述的方法，其中在给定所述数据位是第一逻辑值的情况下，所述写入还包括在所述位线和所述源线两端施加第一差分电压偏置幅度；并且其中所述验证还包括在所述位线和所述源线两端施加第二差分电压偏置幅度，其中所述第一差分电压偏置幅度不同于所述第二差分电压偏置幅度。
3.根据权利要求1所述的方法，其中所述双极存储器元件包括磁性隧道结。
4.根据权利要求1所述的方法，其中所述双极存储器元件包括忆阻器。
5.根据权利要求1所述的方法，其中所述写入进一步包括将所述位写入所述双极存储器元件，其中所述双极存储器元件包括硫属化物玻璃。
6.根据权利要求1所述的方法，其中所述存储器单元还包括第一偏置电路，并且其中进一步施加具有所述第一极性的差分电压还包括使用耦合到所述源线的第一偏置电路和耦合到所述位线的第二偏置电路来施加差分电压。
7.根据权利要求1所述的方法，进一步包括检测对应于所述双极存储器元件中的所述位的所述逻辑值，其中所述检测由耦合到所述源线的读出放大器执行。
8.根据权利要求1所述的方法，进一步包括检测对应于所述双极存储器元件中的所述数据位的所述逻辑值，其中所述检测由耦合到所述位线的读出放大器执行。
9.根据权利要求1所述的方法，其中所述验证进一步包括从程序锁存器读取所述位。
10.根据权利要求9所述的方法，其中所述施加具有所述第二极性的所述第二差分电压进一步包括使用耦合到多路复用器的偏置电路来施加具有所述第二极性的所述第二差分电压，其中所述多路复用器耦合到所述源线和所述位线，并且其中进一步地，所述多路复用器基于所述程序锁存器中的数据选择是否将所述源线或所述位线上的电压驱动为高。
11.根据权利要求1所述的方法，其中所述验证进一步包括使用耦合到多路复用器的读出放大器来检测所述双极存储器元件中的所述位的逻辑值。
12.一种用于将数据写入存储器器件的装置，所述装置包括：
耦合在位线和源线之间的存储器单元，其中所述存储器单元包括双极存储器元件和选择晶体管；
其中所述双极存储器元件可操作为耦合到所述位线；以及
其中所述选择晶体管可操作为耦合到所述源线，以及
其中进一步地，所述存储器单元可操作为响应于在所述位线和所述源线两端施加第一差分电压来提供电流以将数据位写入所述存储器单元，而将写入操作的所述数据位存储到所述双极存储器元件中，其中如果所述数据位是逻辑高则所述第一差分电压包括第一极性，并且其中如果所述数据位是逻辑低则所述第一差分电压包括第二极性，以及
其中进一步地，在所述写入操作之后，所述存储器单元可操作为响应于在所述位线和所述源线两端施加第二差分电压，而在所述数据位的验证期间被读取，其中如果所述数据位是逻辑高则所述第二差分电压是所述第一极性，并且其中如果所述数据位是逻辑低则所述第二差分电压是所述第二极性，
当验证操作在与读取操作相反的极性下发生时，施加到所述位线和所述源线的电压可以被微调电路微调以执行所述验证操作。
13.根据权利要求12所述的装置，其中，在所述验证所述数据期间并且在给定所述数据位是第一逻辑值的情况下，所述存储器单元还可操作为在所述写入操作期间，在所述位线和所述源线两端施加第一差分电压偏置幅度，并且在所述验证期间，在所述位线和所述源线两端施加第二差分电压偏置幅度，其中所述第一差分电压偏置幅度不同于所述第二差分电压偏置幅度。
14.根据权利要求12所述的装置，其中所述双极存储器元件从以下所构成的组中选择：忆阻器、硫属化物玻璃和磁性隧道结。
15.根据权利要求12所述的装置，进一步包括：
第一偏置电路；以及
第二偏置电路，其中所述第一偏置电路耦合到所述源线，并且其中所述第二偏置电路耦合到所述位线，且所述第一偏置电路和所述第二偏置电路可操作为施加所述第一差分电压。
16.根据权利要求12所述的装置，进一步包括：
第一偏置电路；以及
第二偏置电路，其中所述第一偏置电路耦合到所述源线，并且其中所述第二偏置电路耦合到所述位线，且所述第一偏置电路和所述第二偏置电路可操作为施加所述第二差分电压。
17.根据权利要求12所述的装置，进一步包括：
读出放大器，其可操作为在所述验证之前检测对应于所述双极存储器元件中的所述数据位的逻辑电平。
18.根据权利要求12所述的装置，进一步包括：
微调电路，其可操作为在所述验证期间减小所述第二差分电压。
19.根据权利要求12所述的装置，进一步包括：
微调电路，其可操作为减少施加所述第二差分电压期间的时间量。
20.根据权利要求19所述的装置，其中所述第二差分电压与在读取操作期间所施加的电压差具有相反的极性。
21.根据权利要求12所述的装置，进一步包括：
程序锁存器；
多路复用器；以及
偏置电路，其中所述偏置电路耦合到所述多路复用器，其中所述多路复用器耦合到所述源线和所述位线，其中利用所述偏置电路施加所述第一差分电压，并且其中所述多路复用器可操作为基于所述程序锁存器中的数据的值而驱动所述第一差分电压的极性。
22.根据权利要求12所述的装置，进一步包括：
程序锁存器；
多路复用器；以及
偏置电路，其中所述偏置电路耦合到所述多路复用器，其中所述多路复用器耦合到所述源线和所述位线，其中利用所述偏置电路施加所述第二差分电压，并且其中所述多路复用器可操作为基于所述程序锁存器中的数据的值而驱动所述第二差分电压的极性。
23.根据权利要求22所述的装置，进一步包括：
读出放大器，其中所述读出放大器耦合到所述多路复用器，并且其中所述读出放大器可操作为检测对应于所述双极存储器元件中的所述数据位的逻辑电平。
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