JP6122170B1 - 不揮発性ram及び不揮発性ramを含むシステム - Google Patents
不揮発性ram及び不揮発性ramを含むシステム Download PDFInfo
- Publication number
- JP6122170B1 JP6122170B1 JP2016052297A JP2016052297A JP6122170B1 JP 6122170 B1 JP6122170 B1 JP 6122170B1 JP 2016052297 A JP2016052297 A JP 2016052297A JP 2016052297 A JP2016052297 A JP 2016052297A JP 6122170 B1 JP6122170 B1 JP 6122170B1
- Authority
- JP
- Japan
- Prior art keywords
- write
- read
- writing
- memory cell
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1657—Word-line or row circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1693—Timing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/02—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using magnetic elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2209—Concurrent read and write
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2245—Memory devices with an internal cache buffer
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Multimedia (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
(実施例)
図1は、システムの例を示している。
図4は、不揮発性RAMの例を示している。
本実施例は、分割ワードライン構造と相性がよい。分割ワード線構造とは、グローバルな第1のワード線と、第1のワード線に共通に接続されるローカルな複数の第2のワード線と、複数の第2のワード線を互いに独立にアクセス可能とするデコーダと、を備えたメモリセルアレイ構造のことである。
以上、実施形態によれば、高速(high speed)、かつ、高い書き換え耐性(high endurance)の不揮発性RAMを実現できる。
Claims (6)
- メモリセルアレイと、
書き込み時に前記メモリセルアレイをアクセス可能である第1のアクセス回路と、
読み出し時に前記メモリセルアレイをアクセス可能であり、前記第1のアクセス回路と並列に動作可能な第2のアクセス回路と、
前記書き込み時に複数の書き込みパルスのうちのいずれかを前記メモリセルアレイに供給する書き込み回路と、
を具備し、
前記複数の書き込みパルスは、第1の書き込み電圧及び第1のパルス幅を有する第1の書き込みパルスと、前記第1の書き込み電圧よりも低い第2の書き込み電圧及び前記第1のパルス幅よりも長く且つ読み出しパルスのパルス幅よりも長い第2のパルス幅を有する第2の書き込みパルスとを含む
不揮発性RAM。 - 前記書き込み時に、書き込みアドレス及び書き込みデータを記憶する書き込みバッファを含み、前記読み出し時に、前記読み出しアドレスが前記書き込みアドレスに一致する場合、前記書き込みバッファからの前記書き込みデータを読み出しデータとして出力するインターフェース部をさらに具備する請求項1に記載の不揮発性RAM。
- 前記メモリセルアレイは、複数のブロックを備え、
前記第1及び第2のアクセス回路は、それぞれ、前記複数のブロックに共通の第1のワード線と、前記複数のブロックに対応する複数の第2のワード線と、前記第1のワード線及び前記複数の第2のワード線間に接続される複数のデコーダと、を備える、
請求項1に記載の不揮発性RAM。 - 前記第1のアクセス回路は、書き込みアドレスに基づき前記書き込みの対象となる第1のメモリセルをアクセスし、前記第2のアクセス回路は、読み出しアドレスに基づき前記読み出しの対象となる第2のメモリセルをアクセスし、
前記第1及び第2のメモリセルが同一のロウに配置され、かつ、前記第1及び第2のメモリセルが同一のメモリセルでない場合、前記書き込み及び前記読み出しの一方を中断する、
請求項1に記載の不揮発性RAM。 - 前記不揮発性RAMは、MRAM(マグネティックランダムアクセスメモリ)である請求項1乃至4のいずれか1項に記載の不揮発性RAM。
- 請求項1乃至5のいずれか1項に記載の不揮発性RAMと、
高速化を優先する状況か否かを判断し、高速化を優先する状況と判断した場合には前記第1の書き込みパルスを用いて書き込みを行うように、高速化を優先する状況と判断しない場合には前記第2の書き込みパルスを用いて書き込みを行うように、前記不揮発性RAMに指示する制御部と、
を具備するシステム。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016052297A JP6122170B1 (ja) | 2016-03-16 | 2016-03-16 | 不揮発性ram及び不揮発性ramを含むシステム |
US15/266,327 US9858976B2 (en) | 2016-03-16 | 2016-09-15 | Nonvolatile RAM comprising a write circuit and a read circuit operating in parallel |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016052297A JP6122170B1 (ja) | 2016-03-16 | 2016-03-16 | 不揮発性ram及び不揮発性ramを含むシステム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP6122170B1 true JP6122170B1 (ja) | 2017-04-26 |
JP2017168167A JP2017168167A (ja) | 2017-09-21 |
Family
ID=58666479
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016052297A Active JP6122170B1 (ja) | 2016-03-16 | 2016-03-16 | 不揮発性ram及び不揮発性ramを含むシステム |
Country Status (2)
Country | Link |
---|---|
US (1) | US9858976B2 (ja) |
JP (1) | JP6122170B1 (ja) |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10163479B2 (en) | 2015-08-14 | 2018-12-25 | Spin Transfer Technologies, Inc. | Method and apparatus for bipolar memory write-verify |
US10254967B2 (en) | 2016-01-13 | 2019-04-09 | Sandisk Technologies Llc | Data path control for non-volatile memory |
US10460781B2 (en) | 2016-09-27 | 2019-10-29 | Spin Memory, Inc. | Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank |
US10437723B2 (en) | 2016-09-27 | 2019-10-08 | Spin Memory, Inc. | Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device |
US10818331B2 (en) | 2016-09-27 | 2020-10-27 | Spin Memory, Inc. | Multi-chip module for MRAM devices with levels of dynamic redundancy registers |
US10366774B2 (en) | 2016-09-27 | 2019-07-30 | Spin Memory, Inc. | Device with dynamic redundancy registers |
US10360964B2 (en) | 2016-09-27 | 2019-07-23 | Spin Memory, Inc. | Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device |
US10437491B2 (en) | 2016-09-27 | 2019-10-08 | Spin Memory, Inc. | Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register |
US10546625B2 (en) | 2016-09-27 | 2020-01-28 | Spin Memory, Inc. | Method of optimizing write voltage based on error buffer occupancy |
US10446210B2 (en) | 2016-09-27 | 2019-10-15 | Spin Memory, Inc. | Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers |
US10528255B2 (en) | 2016-11-11 | 2020-01-07 | Sandisk Technologies Llc | Interface for non-volatile memory |
US10528267B2 (en) | 2016-11-11 | 2020-01-07 | Sandisk Technologies Llc | Command queue for storage operations |
US10528286B2 (en) | 2016-11-11 | 2020-01-07 | Sandisk Technologies Llc | Interface for non-volatile memory |
US10114589B2 (en) * | 2016-11-16 | 2018-10-30 | Sandisk Technologies Llc | Command control for multi-core non-volatile memory |
US10481976B2 (en) | 2017-10-24 | 2019-11-19 | Spin Memory, Inc. | Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers |
US10656994B2 (en) | 2017-10-24 | 2020-05-19 | Spin Memory, Inc. | Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques |
US10489245B2 (en) | 2017-10-24 | 2019-11-26 | Spin Memory, Inc. | Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them |
US10529439B2 (en) | 2017-10-24 | 2020-01-07 | Spin Memory, Inc. | On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects |
US10740029B2 (en) * | 2017-11-28 | 2020-08-11 | Advanced Micro Devices, Inc. | Expandable buffer for memory transactions |
US10395712B2 (en) | 2017-12-28 | 2019-08-27 | Spin Memory, Inc. | Memory array with horizontal source line and sacrificial bitline per virtual source |
US10424726B2 (en) | 2017-12-28 | 2019-09-24 | Spin Memory, Inc. | Process for improving photoresist pillar adhesion during MRAM fabrication |
US10360962B1 (en) | 2017-12-28 | 2019-07-23 | Spin Memory, Inc. | Memory array with individually trimmable sense amplifiers |
US10891997B2 (en) | 2017-12-28 | 2021-01-12 | Spin Memory, Inc. | Memory array with horizontal source line and a virtual source line |
US10811594B2 (en) | 2017-12-28 | 2020-10-20 | Spin Memory, Inc. | Process for hard mask development for MRAM pillar formation using photolithography |
US10395711B2 (en) | 2017-12-28 | 2019-08-27 | Spin Memory, Inc. | Perpendicular source and bit lines for an MRAM array |
US10886330B2 (en) | 2017-12-29 | 2021-01-05 | Spin Memory, Inc. | Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch |
US10784439B2 (en) | 2017-12-29 | 2020-09-22 | Spin Memory, Inc. | Precessional spin current magnetic tunnel junction devices and methods of manufacture |
US10546624B2 (en) * | 2017-12-29 | 2020-01-28 | Spin Memory, Inc. | Multi-port random access memory |
US10840439B2 (en) | 2017-12-29 | 2020-11-17 | Spin Memory, Inc. | Magnetic tunnel junction (MTJ) fabrication methods and systems |
US10367139B2 (en) | 2017-12-29 | 2019-07-30 | Spin Memory, Inc. | Methods of manufacturing magnetic tunnel junction devices |
US10424723B2 (en) | 2017-12-29 | 2019-09-24 | Spin Memory, Inc. | Magnetic tunnel junction devices including an optimization layer |
US10840436B2 (en) | 2017-12-29 | 2020-11-17 | Spin Memory, Inc. | Perpendicular magnetic anisotropy interface tunnel junction devices and methods of manufacture |
US10438996B2 (en) | 2018-01-08 | 2019-10-08 | Spin Memory, Inc. | Methods of fabricating magnetic tunnel junctions integrated with selectors |
US10438995B2 (en) | 2018-01-08 | 2019-10-08 | Spin Memory, Inc. | Devices including magnetic tunnel junctions integrated with selectors |
US10446744B2 (en) | 2018-03-08 | 2019-10-15 | Spin Memory, Inc. | Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same |
US11107978B2 (en) | 2018-03-23 | 2021-08-31 | Spin Memory, Inc. | Methods of manufacturing three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer |
US20190296228A1 (en) | 2018-03-23 | 2019-09-26 | Spin Transfer Technologies, Inc. | Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer |
US11107974B2 (en) | 2018-03-23 | 2021-08-31 | Spin Memory, Inc. | Magnetic tunnel junction devices including a free magnetic trench layer and a planar reference magnetic layer |
US10784437B2 (en) | 2018-03-23 | 2020-09-22 | Spin Memory, Inc. | Three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer |
US10411185B1 (en) | 2018-05-30 | 2019-09-10 | Spin Memory, Inc. | Process for creating a high density magnetic tunnel junction array test platform |
US10692569B2 (en) | 2018-07-06 | 2020-06-23 | Spin Memory, Inc. | Read-out techniques for multi-bit cells |
US10593396B2 (en) | 2018-07-06 | 2020-03-17 | Spin Memory, Inc. | Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations |
US10559338B2 (en) | 2018-07-06 | 2020-02-11 | Spin Memory, Inc. | Multi-bit cell read-out techniques |
US10600478B2 (en) | 2018-07-06 | 2020-03-24 | Spin Memory, Inc. | Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations |
US10650875B2 (en) | 2018-08-21 | 2020-05-12 | Spin Memory, Inc. | System for a wide temperature range nonvolatile memory |
US10699761B2 (en) | 2018-09-18 | 2020-06-30 | Spin Memory, Inc. | Word line decoder memory architecture |
US11621293B2 (en) | 2018-10-01 | 2023-04-04 | Integrated Silicon Solution, (Cayman) Inc. | Multi terminal device stack systems and methods |
US10971680B2 (en) | 2018-10-01 | 2021-04-06 | Spin Memory, Inc. | Multi terminal device stack formation methods |
US11107979B2 (en) | 2018-12-28 | 2021-08-31 | Spin Memory, Inc. | Patterned silicide structures and methods of manufacture |
US11955169B2 (en) | 2021-03-23 | 2024-04-09 | Qualcomm Incorporated | High-speed multi-port memory supporting collision |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01178193A (ja) * | 1988-01-07 | 1989-07-14 | Toshiba Corp | 半導体記憶装置 |
JP2001135083A (ja) * | 1999-11-04 | 2001-05-18 | Matsushita Electric Ind Co Ltd | マルチポートメモリ |
WO2011161798A1 (ja) * | 2010-06-24 | 2011-12-29 | 富士通株式会社 | 半導体記憶装置及び半導体記憶装置の制御方法 |
JP2012022726A (ja) * | 2009-09-28 | 2012-02-02 | Toshiba Corp | 磁気メモリ |
JP2013127829A (ja) * | 2011-12-16 | 2013-06-27 | Toppan Printing Co Ltd | 不揮発性メモリセル、不揮発性メモリセルアレイおよび不揮発性デュアルポートメモリ |
JP2013528887A (ja) * | 2010-03-22 | 2013-07-11 | クアルコム,インコーポレイテッド | 抵抗性記憶素子を含むマルチポート不揮発性メモリ |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3226886B2 (ja) * | 1999-01-29 | 2001-11-05 | エヌイーシーマイクロシステム株式会社 | 半導体記憶装置とその制御方法 |
US7298665B2 (en) * | 2004-12-30 | 2007-11-20 | Sandisk 3D Llc | Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation |
JP5140859B2 (ja) | 2008-08-27 | 2013-02-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8315081B2 (en) | 2010-03-22 | 2012-11-20 | Qualcomm Incorporated | Memory cell that includes multiple non-volatile memories |
JP5597666B2 (ja) * | 2012-03-26 | 2014-10-01 | 株式会社東芝 | 半導体記憶装置、情報処理システムおよび制御方法 |
KR20140044121A (ko) | 2012-10-04 | 2014-04-14 | 삼성전자주식회사 | 멀티 인터페이스를 갖는 멀티포트 반도체 메모리 장치 |
JP6364365B2 (ja) | 2015-02-25 | 2018-07-25 | 株式会社東芝 | 半導体記憶装置 |
-
2016
- 2016-03-16 JP JP2016052297A patent/JP6122170B1/ja active Active
- 2016-09-15 US US15/266,327 patent/US9858976B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01178193A (ja) * | 1988-01-07 | 1989-07-14 | Toshiba Corp | 半導体記憶装置 |
JP2001135083A (ja) * | 1999-11-04 | 2001-05-18 | Matsushita Electric Ind Co Ltd | マルチポートメモリ |
JP2012022726A (ja) * | 2009-09-28 | 2012-02-02 | Toshiba Corp | 磁気メモリ |
JP2013528887A (ja) * | 2010-03-22 | 2013-07-11 | クアルコム,インコーポレイテッド | 抵抗性記憶素子を含むマルチポート不揮発性メモリ |
WO2011161798A1 (ja) * | 2010-06-24 | 2011-12-29 | 富士通株式会社 | 半導体記憶装置及び半導体記憶装置の制御方法 |
JP2013127829A (ja) * | 2011-12-16 | 2013-06-27 | Toppan Printing Co Ltd | 不揮発性メモリセル、不揮発性メモリセルアレイおよび不揮発性デュアルポートメモリ |
Also Published As
Publication number | Publication date |
---|---|
JP2017168167A (ja) | 2017-09-21 |
US9858976B2 (en) | 2018-01-02 |
US20170270988A1 (en) | 2017-09-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6122170B1 (ja) | 不揮発性ram及び不揮発性ramを含むシステム | |
JP7240452B2 (ja) | 不揮発性メモリの複数区画の同時アクセスのための装置及び方法 | |
US10672445B2 (en) | Memory device including local support for target data searching and methods of operating the same | |
US9087564B2 (en) | Semiconductor storage having different operation modes | |
US11449441B2 (en) | Multi-ported nonvolatile memory device with bank allocation and related systems and methods | |
KR102466965B1 (ko) | 반도체장치 | |
KR102420897B1 (ko) | 메모리 모듈, 이를 포함하는 메모리 시스템 및 그의 동작 방법 | |
KR20200023999A (ko) | 반도체장치 및 반도체시스템 | |
US20120155200A1 (en) | Memory device, memory system including the same, and control method thereof | |
US20180330781A1 (en) | Apparatuses and methods for accessing memory cells | |
KR20190107330A (ko) | 반도체장치 | |
US11495286B2 (en) | Semiconductor devices | |
US11037653B2 (en) | Memory devices performing repair operations and repair operation methods thereof | |
US9653133B2 (en) | Semiconductor device and semiconductor system | |
US9672890B2 (en) | Semiconductor memory apparatus | |
US12009058B2 (en) | Address latch, address control circuit and semiconductor apparatus including the address control circuit | |
US10186306B2 (en) | Apparatus and method for non-volatile memory address decoding | |
US8553477B2 (en) | Data interface circuit, nonvolatile memory device including the same and operating method thereof | |
KR20140072367A (ko) | 불휘발성 메모리 장치 및 그것의 동작 방법 | |
JP2012168998A (ja) | 半導体記憶装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170209 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170228 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170330 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 6122170 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |