JP5635666B2 - 半導体装置の製造方法 - Google Patents
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(1) 下部Cu配線25を含む層間絶縁膜23上にシリコン窒化膜86及び層間絶縁膜24を堆積する。
(2) シリコン窒化膜86及び層間絶縁膜24を貫通するビアホール109を選択的に形成する。
(3) ビアホール109を含む層間絶縁膜24上に金属膜ストラップEB9となる金属薄膜を堆積する。
(4) 層間絶縁膜24上における金属膜ストラップEB9上にMTJ素子MD9及び上部電極ET9それぞれの形成層を堆積する。
(5) 上記形成層をパターニングしてMTJ素子MD9及び上部電極ET9を得る。
(6) 上記(3)で形成した金属薄膜をパターニングして金属膜ストラップEB9を形成する。
(7) 全面に層間絶縁膜66を堆積する。
(8) 層間絶縁膜66を貫通するビアホール49及び上部Cu配線37の形成領域を選択的に形成する。
(9)上部Cu配線37を埋込み堆積した後、CMP処理する。
図1はこの発明の実施の形態1であるMRAMにおける1単位のメモリ素子構成を示す断面図である。
図4〜図19は図1〜図3で示した実施の形態1のMRAMの第1の製造方法を示す断面図である。以下、これらの図を参照して、メモリセル部を中心にMRAMの製造処理内容を説明する。
図16〜図20は実施の形態1のMARAMの第2の製造方法を示す断面図である。なお、図16〜図20において、(a) はメモリセル部の構造を示し、(b) は周辺回路部の構造を示している。以下、これらの図を参照して第2の製造方法を説明する。
図22は図8で示したレジストアッシング処理時におけるCAP層CP1の材料依存性及びプロセス依存性を示すグラフである。横軸にアッシング条件、縦軸に書込み電流Iswのバラツキ(a.u.(arbitrary unit(任意単位))を示している。なお、図22で示すグラフではCAP層CP1の膜厚は5nmの場合を示している。
結晶質のRu単体を構成材料とするCAP層CP1は5〜10nmの膜厚が望ましいと考えられる。CAP層CP1の膜厚を5nm以上にするのは図23で示したように書込み電流Iswをバラツキの低減化を効果的に図るためである。
図25は実施の形態2のMRAMのメモリ素子構成に対応する平面図である。同図に示すように、金属膜ストラップEB1はビアホール9を介して下方のリード線25rと電気的に接続される。一方、MTJ素子MD1(CAP層CP1,ハードマスクHM1含む)はデジット線25dの上方に形成され、上部Cu配線37(形成幅W37)と直接接続される。
図26〜図28は実施の形態2のMARAMの製造方法を示す断面図である。なお、図26〜図28において、(a) はメモリセル部の構造を示し、(b) は周辺回路部の構造を示している。また、(a) は図25のC−C断面に相当する。以下、これらの図を参照して製造方法を説明する。
(MTJ素子MD1の種別)
MTJ素子MD1として、外部より受ける磁場によってその抵抗値が変化する特性を有するMTJ素子(第1種のMTJ素子)が通常考えられる。しかし、STT(Spin Torque Transfer)−RAMと呼ばれるMTJ素子(第2種のMTJ素子)は自身を流れる電流によってその抵抗値が変化する性質を有する。このようなSTT−RAMと呼ばれるMTJ素子をMTJ素子MD1として用いることもできる。
Claims (7)
- (a) 半導体基板の上方に下部電極用の下部導電層を形成するステップと、
(b) 前記下部導電層上に第1の磁性膜、絶縁膜及び第2の磁性膜の順に積層されるMTJ素子用の積層構造を形成するステップとを備え、前記第2の磁性膜は構成材料としてコバルト、鉄及びニッケルから少なくとも2つの金属を含む化合物にボロンを含み、前記絶縁膜は非晶質の構成材料を含み、
(c) 前記積層構造上に第1の保護膜用の第1の導電層を形成するステップをさらに備え、前記第1の導電層は構成材料として結晶質のルテニウム単体構造を含み、
(d) 前記第1の導電層上に第2の保護膜用の第2の導電層を形成するステップをさらに備え、前記第2の導電層は構成材料としてタンタル単体構造を含み、
(e) 前記(d)ステップ後に、レジストパターンをマスクとして、前記第2の導電層をパターニングして前記第2の保護膜を得るステップと、
(f) 前記(e)ステップ後に、前記積層構造上に前記第1の導電層が存在する状態で、アンモニアガスを用いたアッシングによって、前記レジストパターンを除去するステップと、
(g) 前記(f)ステップ後に、前記第2の保護膜をマスクとして、前記第1の導電層及び前記積層構造をパターニングして前記第1の保護膜及び前記MTJ素子を得るステップとをさらに備える、
半導体装置の製造方法。 - (a) 半導体基板の上方に下部電極用の下部導電層を形成するステップと、
(b) 前記下部導電層上に第1の磁性膜、絶縁膜及び第2の磁性膜の順に積層されるMTJ素子用の積層構造を形成するステップとを備え、前記第2の磁性膜は構成材料としてコバルト、鉄及びニッケルから少なくとも2つの金属を含む化合物にボロンを含み、前記絶縁膜は非晶質の構成材料を含み、
(c) 前記積層構造上に第1の保護膜用の第1の導電層を形成するステップをさらに備え、前記第1の導電層は構成材料として結晶質のルテニウム単体構造を含み、
(d) 前記第1の導電層上に第2の保護膜用の第2の導電層を形成するステップをさらに備え、前記第2の導電層は構成材料としてタンタル単体構造を含み、
(e) 前記(d)ステップ後に、レジストパターンをマスクとして、前記第2の導電層をパターニングして前記第2の保護膜を得るステップと、
(f)前記(e)ステップ後に、前記積層構造上に前記第1の導電層が存在する状態で、前記レジストパターンを除去するステップと、
(g) 前記(f)ステップ後に、前記第2の保護膜をマスクとして、前記第1の導電層及び前記積層構造をパターニングして前記第1の保護膜及び前記MTJ素子を得るステップとをさらに備え、
前記第2の導電層の膜厚は、前記第1の導電層の膜厚よりも厚い、
半導体装置の製造方法。 - (a) 半導体基板の上方に下部電極用の下部導電層を形成するステップと、
(b) 前記下部導電層上に第1の磁性膜、絶縁膜及び第2の磁性膜の順に積層されるMTJ素子用の積層構造を形成するステップとを備え、前記第2の磁性膜は構成材料としてコバルト、鉄及びニッケルから少なくとも2つの金属を含む化合物にボロンを含み、前記絶縁膜は非晶質の構成材料を含み、
(c) 前記積層構造上に第1の保護膜用の第1の導電層を形成するステップをさらに備え、前記第1の導電層は構成材料として結晶質のルテニウム単体構造を含み、
(d) 前記第1の導電層上に第2の保護膜用の第2の導電層を形成するステップをさらに備え、前記第2の導電層は構成材料としてタンタル単体構造を含み、
(e) 前記(d)ステップ後に、レジストパターンをマスクとして、前記第2の導電層をパターニングして前記第2の保護膜を得るステップと、
(f)前記(e)ステップ後に、前記積層構造上に前記第1の導電層が存在する状態で、アンモニアガスを用いたアッシングによって、前記レジストパターンを除去するステップと、
(g) 前記(f)ステップ後に、前記第2の保護膜をマスクとして、前記第1の導電層及び前記積層構造をパターニングして前記第1の保護膜及び前記MTJ素子を得るステップとをさらに備え、
前記第2の導電層の膜厚は、前記第1の導電層の膜厚よりも厚い、
半導体装置の製造方法。 - 請求項1ないし請求項3のうち、いずれか1項に記載の半導体装置の製造方法であって、
(h) 少なくとも前記MTJ素子並びに第1及び第2の保護膜を覆って絶縁膜を形成するステップと、
(i) 前記絶縁膜の表面から選択的に除去し、少なくとも前記第2の保護膜の表面の一部を露出させるステップと、
(j) 前記第2の保護膜上に上部配線部を形成するステップとを備え、前記上部配線部は前記第2の保護膜の表面上に形成される電気的接続部を含む、
半導体装置の製造方法。 - 請求項1ないし請求項4のうち、いずれか1項に記載の半導体装置の製造方法であって、
前記ステップ(c) は、
前記第1の導電層を、前記第2の磁性膜に接するように前記第2の磁性膜上に形成するステップを含む、
半導体装置の製造方法。 - 請求項1ないし請求項5のうち、いずれか1項に記載の半導体装置の製造方法であって、
前記第2の導電層の膜厚は40nm〜80nmであり、
前記第1の導電層の膜厚は5nm〜10nmである、
半導体装置の製造方法。 - 請求項1ないし請求項6のうち、いずれか1項に記載の半導体装置の製造方法であって、
前記絶縁膜は、酸化アルミニウムまたは酸化マグネシウムである、
半導体装置の製造方法。
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