JP5676842B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5676842B2 JP5676842B2 JP2008142098A JP2008142098A JP5676842B2 JP 5676842 B2 JP5676842 B2 JP 5676842B2 JP 2008142098 A JP2008142098 A JP 2008142098A JP 2008142098 A JP2008142098 A JP 2008142098A JP 5676842 B2 JP5676842 B2 JP 5676842B2
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- resistance
- resistance value
- semiconductor device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
11−1〜11−n レファレンス用抵抗素子
12 抵抗選択回路
21−1〜21−5 抵抗素子切り替え用スイッチ
41−1〜41−n アンド回路
42−1〜42−n インバータ
43−1〜43−n ヒューズ
44 インバータ
45−1〜45−n 複合論理回路
91−1〜91−n レファレンス用抵抗素子
92−1〜92−n ヒューズ
93−1〜93−n レファレンス抵抗切り替えスイッチ
101 メモリセル
102 Yスイッチ
103 センスアンプ
104 レファレンス用抵抗素子
105 レファレンスアンプ
106 比較器
107 比較読み出し回路
1011 記憶素子
1012 選択トランジスタスイッチ
1031,1051 負荷
1032,1052 トランジスタ
1033,1053 インバータ
Claims (14)
- 複数のメモリセルを有し、各メモリセルに含まれる記憶素子の抵抗値を変化させて情報を記憶する半導体装置において、
前記複数のメモリセルについて前記抵抗値の分布測定を可能にするレファレンス系回路を備え、前記レファレンス系回路は、レファレンス抵抗の抵抗値を有し、
前記複数のメモリセルにおいて低抵抗状態の分布度数と高抵抗状態の分布度数との間に偏りがあり、さらに、前記レファレンス抵抗の前記抵抗値が前記低抵抗状態における抵抗値と前記高抵抗状態における抵抗値の中間値よりも前記分布度数の分布ピークの高い方に偏らせた値に決定されていることを特徴とする半導体装置。 - 前記レファレンス系回路は、前記記憶素子の抵抗値と比較される前記レファレンス抵抗の前記抵抗値を、前記記憶素子が持ち得る最低抵抗値よりも低い第1の抵抗値から、前記記憶素子が持ち得る最高抵抗値よりも高い第2の抵抗値まで可変にした抵抗選択回路を備えることを特徴とする請求項1に記載の半導体装置。
- 前記抵抗選択回路は、複数の抵抗素子にそれぞれスイッチを直列接続して直列接続体とし、これら直列接続体を並列接続して構成されると共に入力される制御信号に応じて前記複数の抵抗素子を選択的に組み合わせて前記レファレンス抵抗を構成することを特徴とする請求項2に記載の半導体装置。
- 前記制御信号を生成するデコーダをさらに有し、該デコーダが入力される選択信号に応じて入力されるコマンド信号に基づく第1の制御信号又はヒューズ設定に基づく第2の制御信号を選択的に前記制御信号として出力することを特徴とする請求項3に記載の半導体装置。
- 互いに異なる抵抗値を持つ複数の抵抗素子にそれぞれヒューズを介してスイッチを直列接続して直列接続体とし、これら直列接続体を並列接続し、ヒューズ切断前は、外部入力される制御信号に応じて前記複数の抵抗素子を選択的に組み合わせて前記レファレンス抵抗を構成し、ヒューズ切断後は、ヒューズの状態に応じて前記複数の抵抗素子を選択的に組み合わせて前記レファレンス抵抗を構成するようにした前記抵抗選択回路を備えることを特徴とする請求項2に記載の半導体装置。
- 前記記憶素子の抵抗値を第1の電位に変換するセンスアンプと、前記レファレンス抵抗の前記抵抗値を第2の電位に変換するレファレンスアンプと、前記第1の電位と前記第2の電位とを比較する比較器と、を備えることを特徴とする請求項2乃至5のいずれかに記載の半導体装置。
- 前記センスアンプと前記比較器とを複数有し、前記レファレンスアンプから前記第2の電位が前記比較器に共通に供給されていることを特徴とする請求項6に記載の半導体装置。
- 複数のメモリセルを有し、各メモリセルに含まれる記憶素子の抵抗値を変化させて情報を記憶する半導体装置のレファレンス抵抗の抵抗値を決定するレファレンスレベル決定方法において、
前記複数のメモリセルについて前記抵抗値の分布測定を行い、
前記複数のメモリセルにおいて低抵抗状態の分布度数と高抵抗状態の前記分布度数との間に偏りがある場合には、前記レファレンス抵抗の抵抗値を前記低抵抗状態の抵抗値と前記高抵抗状態の抵抗値の中間の値よりも前記分布度数の分布ピークの高い方に偏らせた値に決定することを特徴とするレファレンスレベル決定方法。 - 前記分布測定は、前記記憶素子の抵抗値と比較される前記レファレンス抵抗の前記抵抗値を、前記記憶素子が持ち得る最低抵抗値よりも低い第1の抵抗値から、前記記憶素子が持ち得る最高抵抗値よりも高い第2の抵抗値まで可変させる抵抗選択回路を用いて行われることを特徴とする請求項8に記載のレファレンスレベル決定方法。
- 前記抵抗選択回路は、複数の抵抗素子にそれぞれスイッチを直列接続して直列接続体とし、これら直列接続体を並列接続して構成されると共に入力される制御信号に応じて前記複数の抵抗素子を選択的に組み合わせて前記レファレンス抵抗を構成することを特徴とする請求項9に記載のレファレンスレベル決定方法。
- 前記制御信号はデコーダにより生成され、該デコーダが入力される選択信号に応じて前記デコーダに入力されるコマンド信号に基づく第1の制御信号又はヒューズ設定に基づく第2の制御信号を選択的に前記制御信号として出力することを特徴とする請求項10に記載のレファレンスレベル決定方法。
- 前記抵抗選択回路は、互いに異なる抵抗値を持つ複数の抵抗素子にそれぞれヒューズを介してスイッチを直列接続して直列接続体とし、これら直列接続体を並列接続し、ヒューズ切断前は、外部入力される制御信号に応じて前記複数の抵抗素子を選択的に組み合わせて前記レファレンス抵抗を構成し、ヒューズ切断後は、ヒューズの状態に応じて前記複数の抵抗素子を選択的に組み合わせて前記レファレンス抵抗を構成することを特徴とする請求項9に記載のレファレンスレベル決定方法。
- センスアンプを用いて前記記憶素子の抵抗値を第1の電位に変換し、レファレンスアンプを用いて前記レファレンス抵抗の前記抵抗値を第2の電位に変換し、前記第1の電位と前記第2の電位とを比較器を用いて比較することを特徴とする請求項9乃至12のいずれかに記載のレファレンスレベル決定方法。
- 前記センスアンプと前記比較器とを複数用い、前記レファレンスアンプからの前記第2の電位を前記比較器に共通に供給することを特徴とする請求項13に記載のレファレンスレベル決定方法。
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JP2008142098A JP5676842B2 (ja) | 2008-05-30 | 2008-05-30 | 半導体装置 |
US12/453,988 US8094480B2 (en) | 2008-05-30 | 2009-05-28 | Semiconductor device |
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JP5676842B2 true JP5676842B2 (ja) | 2015-02-25 |
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TWI410975B (zh) * | 2008-04-29 | 2013-10-01 | Sandisk Il Ltd | 具有狀態電壓位準的調適性設定之非揮發性記憶體及其方法 |
US7701750B2 (en) * | 2008-05-08 | 2010-04-20 | Macronix International Co., Ltd. | Phase change device having two or more substantial amorphous regions in high resistance state |
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2008
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2009
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JP2009289352A (ja) | 2009-12-10 |
US20090296452A1 (en) | 2009-12-03 |
US8094480B2 (en) | 2012-01-10 |
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