CN103354951B - 互连结构 - Google Patents

互连结构 Download PDF

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Publication number
CN103354951B
CN103354951B CN201180067223.4A CN201180067223A CN103354951B CN 103354951 B CN103354951 B CN 103354951B CN 201180067223 A CN201180067223 A CN 201180067223A CN 103354951 B CN103354951 B CN 103354951B
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substrate
conductive prominence
conductive
area
conducting element
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CN103354951A (zh
Inventor
德巴布拉塔·吉普塔
桥本夕纪夫
伊利亚斯·默罕默德
劳拉·米尔卡瑞米
拉杰什·卡特卡
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

微电子元件(10)包括第一表面(22)和第一薄导电元件(52)，第一薄导电元件(52)在第一表面(22)暴露且具有由第一区域和第二区域组成的工作面(54)。具有与工作面(54)的第一区域连接并覆盖该区域的基底(58)的第一导电突起(56)延伸至远离基底的端部(62)。第一介电材料层(40)覆盖第一薄元件(52)的第二区域，并至少与第一导电突起(56)的基底(58)接触。组件(10)进一步包括第二基板(18)，第二基板具有第二工作面(24)和从第二工作面(24)向外延伸的第二导电突起(76)。第一易熔金属块(70)使第一突起(56)与第二突起(76)连接，并沿第一突起(56)的边缘朝第一介电材料层(40)延伸。

Description

互连结构
相关申请的交叉引用
本申请要求申请号为12/965192、申请日为2010年12月10日的申请日之利益，其公开的内容以引用的方式并入本文。
背景技术
本申请涉及封装微电子组件内采用的互连结构。特别地，其涉及在如倒装芯片结合中微电子芯片及裸片与基板的连接、或如形成堆叠封装时基板之间的连接中采用的互连结构。本文描述的结构可用于减少互连结合的失效，这种失效归因于具有在先技术结构的元器件之间发生电迁移而导致空穴的形成。
电迁移是互连失效的主要诱因，尤其是在互连内电流密度及器件工作温度都高的高性能器件内。总的来说，电迁移由于互连组件内采用的各材料的扩散速率不同而导致。例如，互连组件可包括，在两个基板中每个上都形成的由铜制成的接触垫，及在接触垫之间结合的焊料块。焊料与两个接触垫机械固定，因此，其上形成有接触垫的基板也与两个垫电连接，使得电流承载的信号能通过焊料块在两个垫之间传递。在这个示例中，焊料与铜垫之间的扩散速率可能是不同的。扩散速率为，长时间工作尤其是在承受电流或器件工作导致的热量时，金属结构内分子移动的速率。
互连结构内形成的空穴可降低采用这种互连结构的微电子组件的可靠性。另外，在空穴周围区域内，空穴的存在增加了材料内的电流密度。而这进一步使扩散速率的差异增加，导致空穴加速形成，最终导致互连元件的电失效及机械失效。
目前用于降低电迁移的方式包括，在焊料内应用阻挡金属或掺杂剂。但是，这些方式存在自身可靠性的问题，而且导致成本的增加可能大于它们的效果。因此，需要另外的方法来降低电迁移。
发明内容
本发明实施例涉及微电子组件。微电子组件包括第一表面，及在第一表面暴露、且具有由第一区域和第二区域组成的工作面的第一薄导电元件。具有基底与工作面的第一区域连接并覆盖该区域的第一导电突起，延伸至远离基底的端部。第一介电材料层覆盖第一薄元件的第二区域，并至少与第一导电突起的基底接触。组件进一步包括，具有第二工作面和远离第二工作面而延伸的第二导电突起的第二基板。第一易熔金属块使第一突起与第二突起连接，使得第一工作面的第一表面面向第二表面。第一块沿第一突起的边缘朝第一介电材料层延伸。在另一实施例中，第一易熔金属块可与第一介电材料层接触。
微电子组件可构造为，使得第一表面形成在基板上，而第二表面形成在微电子元件上。附加地或替代地，第一表面可在进一步具有微电子元件附接于其上的基板上形成，而第二表面可在第二基板上形成。在另一实施例中，微电子组件包括复数个互连结构，每个都包括，第一导电元件、第一导电突起、第二导电突起和第一金属块。每个互连结构在第一工作面面的第一区域与第二工作面之间连接，且具有与上述类似的结构，其中第一介电材料层覆盖薄元件的第二区域。
第一介电材料层内的第一开口可限定内表面，使得内表面沿第一突起的一部分延伸，并基本与其接触。相应地，第一介电材料层可具有沿垂直于第一薄元件的第一工作面的方向延伸的厚度。该厚度可为第一导电突起高度的约20%至50%。
第一导电突起的基底可具有外周，使得第一工作面的第二区域在第一突起基底的外周之外暴露。这种布置可进一步在第一薄元件的第一工作面与第一导电元件侧壁之间形成拐角。拐角可沿第一导电元件基底的外周设置，且第一介电材料层可基本覆盖该拐角。
在另一实施例中，第二薄导电元件可在第二表面暴露，且可具有由第一区域和第二区域组成的第二工作面。第二突起可进一步具有与第二薄元件的第一区域连接、并覆盖该区域且限定外周的基底，及远离基底的端头部分。第二介电材料层可覆盖第二薄元件的第二区域。另外，第一块可在第二导电突起的一部分上朝第二介电材料层延伸。
本发明的另一实施例涉及微电子组件，包括第一表面及在第一表面暴露且具有由第一区域和第二区域组成的工作面的第一薄导电元件。第一导电突起与第一工作面的第一区域连接并覆盖该区域，并延伸至远离该区域的端部。导电突起具有沿其一部分形成的屏障，屏障具有远离第一薄导电元件的第一边缘。组件进一步包括第二工作面，第二导电突起远离第二工作面而延伸。第一易熔金属块使第一导电突起与第二导电突起连接，使得第一工作面的第一表面面向第二基板的第二表面。第一块沿第一导电突起的一部分延伸至朝向屏障第一边缘的位置，屏障位于第一薄元件与第一金属块之间。屏障可为形成在第一导电突起内的表面处理层。表面处理层可通过氧化而形成、或可为施加至第一导电突起表面上的涂层。
在又一实施例中，微电子组件包括具有第一表面和第一薄导电元件的第一基板，第一薄导电元件在第一表面暴露且具有第一工作面。具有基底与第一工作面连接的第一导电突起，延伸至远离第一工作面的端部，并在基底与端部之间限定侧壁。介电材料层沿第一基板的第一表面延伸，且具有第二表面及远离第二表面的第三表面。介电材料层进一步具有形成在其内并限定外周的第一开口。金属镀层具有沿第一导电突起的端部及侧壁的至少一部分延伸的第一部分。金属镀层的第二部分沿介电材料层的一部分向外延伸，并远离第一导电突起。第一焊料块至少在镀层的第一部分上形成，并朝第三表面延伸。
又一实施例涉及的微电子组件包括基板，基板具有第一表面、在第一表面暴露并限定工作面的复数个第一导电垫、及复数个第一金属柱。每个金属柱限定具有外周的基底，并与相应的一个第一导电垫连接。每个金属柱沿侧壁从基底延伸至远离第一导电垫的端部。组件进一步包括具有内表面、外表面及复数个开口的介电材料层。内表面沿基板的第一表面延伸，外表面远离基板。各第一金属柱贯穿开口而突出，使得介电材料层至少与第一金属柱的外周接触。复数个易熔金属块与至少一些第一金属柱的端部接触，并沿第一金属柱的侧壁朝介电材料层的外表面延伸。微电子元件承载在基板上，并至少与一些第一导电垫电连接。
又一实施例涉及的微电子组件包括第一基板，第一基板具有第一表面及具有第一工作面且在第一表面暴露的第一薄导电元件。第一导电突起具有与第一工作面连接的基底，并延伸至远离第一工作面的端部。侧壁在基底与端部之间限定。组件进一步包括，具有第二表面及远离第二表面的第三表面的介电材料层。第二表面沿第一基板的第一表面延伸，介电材料层内形成有具有周壁的第一开口。第一焊料块在第一导电突起上形成，并沿端部和侧壁的一部分延伸至位于基底与端部之间的位置。第一导电突起贯穿第一开口而延伸，使得开口的周壁与侧壁的一部分接触。焊料块朝介电材料层的第三表面延伸。
附图说明
图1示出了包括根据本发明实施例互连结构的封装微电子元件的堆叠组件。
图2示出了包括根据本发明另一实施例互连结构的封装微电子元件的堆叠组件。
图3示出了说明根据图1实施例互连结构在第一条件下的特性的图表。
图4示出了说明根据图1实施例互连结构在第二条件下的特性的图表。
图5示出了说明在先技术互连结构在第一条件下的特性的图表。
图6示出了说明图5中在先技术互连结构在第二条件下的特性的图表。
图7示出了根据替代实施例互连结构的元器件。
图8示出了根据另一替代实施例互连结构的元器件。
图9示出了根据替代实施例互连结构的元器件。
图10示出了根据另一变例互连结构的元器件。
图11示出了包括沉积金属层的互连结构的元器件。
具体实施方式
现在参照附图，其中相同的标号用于相同的特征，图1和图2示出了微电子子组件12、14的堆叠封装10。通过包括将进一步详述的元器件的一个或多个互连结构50，微电子子组件相互电接合及机械接合在一起。
图1中堆叠封装10包括下组件12和上组件14。需要指出的是，本文中应用的，术语上和下，及指示方向或位置的任意其他术语，如水平或竖直、左或右、及其他，是参照附图和使用时的示例性模式的。本说明书中的这些术语是为了清楚的目的而采用，并不是限制，对于本领域普通技术人员来说，其他位置和方向是可以理解的。下基板16和上基板18中每个具有各自的下表面20、24和上表面22、26。上表面22、26通常平行于它们各自的下表面20、24，且所有表面20、22、24、26通常都是平坦的。上基板14和下基板12中每个的厚度在各自的上表面22、26与下表面20、24之间限定。上基板14和下基板12的厚度可大致相等，或可不同。厚度通常小于基板12、14的长度和宽度，条件是足以使基板12、14大致为薄的、晶圆状的结构，并落入本领域普通技术人员通常理解的范围内。
每个组件12、14还包括各自的微电子元件30、32。所示的微电子元件30以倒装芯片结合的方式附接至下基板16，其中微电子元件30反转，使得其导电触点（未示出）面向上表面22。然后,微电子元件利用从其触点延伸的导电突起34固定至基板16，并利用焊料块36或另一导电结合材料与形成在基板16上的第二导电突起38结合。用于使微电子元件30与基板16连接的其他可能布置包括面朝上安装，其中微电子元件30的触点背对上表面26，采用粘接剂使微电子元件30与上表面26结合在一起，导线引线用于使微电子元件30的触点与形成于基板16上的如迹线或垫等的导电特征电连接。所示的微电子元件32以类似方式固定在基板18上，且可选择如上所述之一的附接方式。
图1所示的互连结构50包括的导电垫52，具有在基板16上表面22暴露的工作面54。本文中应用的术语“暴露”，不是指垫52以任何特定方式附接在基板16上、或二者之间的任何相对位置。而是指，导电结构可与一理论点接触，该理论点沿垂直于介电结构表面的方向，从介电结构外部向该介电结构的表面移动。因此，暴露在介电结构表面上的端子或其他导电结构，可从该表面突出；可与该表面平齐；或可相对该表面凹陷，并通过介电元件上的孔或凹坑暴露。通过直接在表面22上沉积或类似过程形成垫，垫52可而附接至基板16，或垫52可嵌入基板16内，使得工作面54与表面22平齐、或位于表面22上方或下方的一高度，只要工作面54保持在表面22上暴露即可。在替代实施例中，互连结构50可包括导电迹线或导电迹线的一部分，用于补充或替代导电垫52。
导电柱56形成在导电垫52工作面54的一部分上。从图1可以看出，柱56的基底58覆盖工作面54的一部分，并使工作面的另一部分从基底58的外周延伸，并在表面22暴露。柱56还限定从柱56的基底58延伸至端部62的边缘表面60。如本领域普通技术人员可以理解的一样，尽管图1示出的为导电柱，但可采用形成导电突起的替代结构，包括引脚、突柱或类似物。
互连结构50进一步包括，具有在基板18下表面24暴露的工作面66的导电垫64。与接触垫52一样，垫64可嵌入基板18内，使得工作面66与下表面24平齐，或位于下表面24的上方或下方，只要工作面66保持在表面24暴露即可。利用贯穿基板18而形成的导电通路68，垫64可与形成在基板18上表面26上的如迹线或导线等导电特征连接。在替代实施例中，互连结构50可包括，在下表面24暴露的取代垫64的迹线或迹线的一部分。
焊料块70用于使柱56与垫64机械结合和电结合。在封装10的形成与组装过程中，焊料块70可首先在柱56上或垫64上形成，然后当组件12、14对齐排列在一起后回流，以使焊料块70与柱56或垫64中的另一个固定。一旦置入封装10内后，焊料块70就形成了上边缘72和下边缘74。上边缘72和下边缘74中每个都可形成为单个的线或点或面。如图1所示，上边缘72为沿围绕垫64的表面24的一部分延伸的表面。上边缘72还可形成为与垫64接触的表面，或为环绕垫的圆，或者与表面24接触、或者远离，根据垫64的几何形状而定。
本文公开的结构和技术可有助于减少垫和与垫连接的焊料块之间的界面处的电迁移。电迁移可引起在相互接触的区域，两个或更多金属元件呈现出不同扩散速率的问题。在这种情况下，在结合界面内可能产生空穴。也就是说，一种金属会脱离另一种金属，形成其间的间隙或开口。
与焊料块连接两个相面对的垫的结构相比，互连结构50内的柱56或另一导电突起的应用，沿电流通过的路线，减小了柱56的端部62与垫64之间的距离。相应地，其中柱56和垫64都由铜制成时，在铜-焊料-铜的互连结构内，图1的结构可显示出有效地减少了导致空穴产生的电迁移。当在电互连结构内应用的同类金属（like metal）被第二金属分隔开时，金属间化合物（ inter-metallic compound），及同类金属，在第二金属内形成。这种金属间化合物将从一个同类金属结构朝另一同类金属结构延伸。金属间化合物的形成是减少由于电迁移而使空穴形成的因素，因为金属间化合物具有比焊料低的电迁移率。通过减小结构内同类金属与同类金属之间的距离，可形成从一个同类金属结构延伸至另一同类金属结构的金属间化合物。在图1的示例中，其中垫64和柱56由铜制成，而焊料块70包括锡，金属间化合物的比例可变化，例如从Cu3Sn变为Cu3Sn5。另外，本文所示的互连结构可降低同类金属在整个互连结构内的浓度梯度，这示为减少电迁移的主要因素。结构内的浓度梯度是指浓度变化的速度，例如结构内同类金属浓度随空间变化的速度。柱56延伸至焊料块70内，使结构内铜的表面积增加，其进一步使焊料块70内的金属间化合物增加。金属间化合物的这种增量的扩展能降低结构内铜的变化速度，进一步降低电迁移。
图3至图6所示的图表说明了上述的现象。图3和图4示出在一水平位置处，与图1类似的互连结构在其整个竖直距离内铜浓度的变化。所示的图表对应于互连结构50，其中垫52、64和柱56由铜制成，而焊料块70由包含锡的焊料化合物制成。图3示出当结构在温度（T0）且没有电流通过时出现的铜浓度，表明这种温度条件下，焊料块70内没有铜。图4示出相同结构在存在电流的平衡温度下，整个结构内的铜浓度。图4中的图表示出焊料块70内存在铜浓度，其存在是由于金属间化合物的形成。示出的金属间化合物从柱56的端部62延伸至垫52的工作面54。铜浓度既沿端部62又沿工作面54延伸，也表明沿其基本没有空穴形成。另外，图4中的图表示出，柱56的存在可降低整个互连结构50内铜浓度变化的速度。例如，在紧邻近垫64的焊料块70内的区域，代表铜浓度的曲线的方向急剧变化。相反地，在邻近柱56的焊料块70内的区域，代表铜浓度的曲线的方向变化缓和得多。需要指出的是，图表仅为示例性的，用于解释本文描述的工作情况，并不是按比例或准确表示图中所示特定结构的工作情况。
图5和图6所示的图表示出在先技术互连结构150的铜浓度，该在先技术互连结构150具有位于两个接触垫152、164之间的焊料块170，其中垫152、164之间的距离190与图3和图4中垫52、64之间的距离90基本相同。图5示出在T0温度时结构内的铜浓度，表明在这种条件下焊料块170内没有铜存在。图6示出在平衡温度下结构内的铜浓度，示出由于金属间化合物的形成，焊料块170内具有一些铜浓度，但该浓度没有贯穿焊料块170而延伸。这导致断开处形成空穴186。
相应地，在柱56具有的端部62延伸至焊料块70内、并朝焊料块另一侧的如垫64等同类金属的结构延伸时，柱的存在可减小由于电迁移形成空穴的可能性。在结构内穿过总距离90而延伸的距离，大于金属间化合物预期延伸的距离时，这尤其是正确的。在柱56和垫64由铜制成且焊料块70包括锡的实施例中，端部62与工作面66之间的距离92可为距离90的约10%至50%。需要指出的是，在图3中，距离90在基板18的下表面24与介电层40的外表面之间限定，距离90在围绕垫52、64的任意类型的结构的主表面之间限定。
在一个实施例中，下边缘74形成围绕柱56的边缘表面60的一部分的圆形线或环形表面，柱延伸至焊料块70内。另外，下边缘74与垫52分隔开，使得焊料块70与垫52的任意部分都不直接接触，包括围绕柱56的基底58而仍暴露的部分。可对柱56、尤其是对邻近基底58的边缘表面60进行处理，可防止焊料块70浸润边缘表面60并与工作面54或垫52接触。这种处理可包括氧化或类似的过程。类似地，可围绕边缘表面60施加抵抗焊料流动的材料层。
在另一实施例中，通过在工作面54上延伸并与边缘表面68邻近基底58的至少一部分接触的介电层40，焊料块70的下边缘74保持为远离垫52的工作面54。在这个实施例中，允许焊料块70流动至与介电层40接触，包括表面42，使得下边缘74可以与垫52间隔开的位置关系沿表面延伸。
通过使焊料块70远离垫52，由于电迁移形成空穴的可能性也可降低。这种类型的互连结构，通过降低焊料块70内的电流集聚而减少电迁移。如图7和图8所示，经过互连结构50的电流对角地沿线移动，从结构一端上的点移动至结构另一端与初始点基本横向相对的另一点。这表明电流从图7中的垫252沿线296所表示的路线移动，经过焊料块270返回至柱256内。然后电流离开柱256，在到达垫264之前，再次进入焊料块270内。这种路线导致在邻近柱256基底258的焊料块270的部分内电流集聚。电流集聚是继电迁移之后可导致空穴形成的另一主要因素，空穴形成导致互连失效。
如图8所示，通过在焊料块70的下边缘74与暴露垫52之间插入介电层40，在垫52外没有电流经过。而是，电流将沿只进入焊料块70内一次的线96移动，示出为在端部与焊料块70的界面处进入。这可以大约为1.25至1.75之间的系数降低电流聚集的梯度，其可再次降低空穴形成的可能性。只要焊料块70通过介电层40保持为远离垫52，类似路径可在焊料块沿介电层40的一部分向外延伸的结构内发现。
图1所示的介电层40为沿基板16上表面22的主要部分延伸的。这个部分包括没有被其他接触元件穿过的所有上表面22。替代地，介电层40可在环绕互连结构50内应用的所有柱56的部分内形成，并向外延伸至足以使焊料块70保持远离相关接触垫52的距离。在这种实施例中，介电层部分可与接触垫的大小和形状基本相同，或稍大，从而可靠地覆盖垫的任何另外暴露的部分。
在实施例中，在覆盖垫52的区域，介电层40可具有厚度43，使得焊料块70的下端74保持与垫间隔开一距离。这个距离可包括材料总厚度中所有容差的补偿，以确保没有导致垫52的工作面54非预期暴露的孔或间隙存在。厚度43可为约10微米至30微米之间。在这种实施例中，介电层40将具有一个孔44或复数个孔44，任意互连柱56穿过孔延伸。孔44形成有内表面46，与从基底58向上延伸的边缘表面60的一部分接触。
如图11所示，镀层488可在柱456上施加，包括端部462和暴露在介电层440上方的边缘表面460的一部分。镀层488可有助于保证柱456与焊料块之间的可靠互连。
图2示出包括具有互连结构50的复数个微电子子组件12、14的堆叠组件10。除了图2中封装10内的互连结构50包括从垫64的工作面66延伸的导电柱76以外，图2所示的封装10与图1所示的基本类似。柱包括附接在工作面66上的基底78，及延伸至远离工作面66的端部82的边缘表面80。第二介电层41可沿基板18的下表面24而形成，并覆盖工作面66和暴露在基底78外周之外的垫64的任何部分。与介电层40类似，介电层41保持焊料块70的上边缘72远离接触垫64，以减少邻近上表面72处的焊料块70内的电流聚集。这进一步降低互连结构50内形成空穴的可能性，如参照介电层40在上文所述。
图9和图10说明，通过保持焊料块不与相关导电垫接触，致使包含在互连结构内的焊料块内的电流聚集降低。图9示出的互连结构350包括垫352及在垫上形成的柱356。焊料块370使柱356及垫352与上部垫364及在垫上形成的柱376附接。由线396表示的电流，从触点垫352流出而进入焊料块370内，然后返回至柱356内，然后又返回焊料块370内。然后电流（线396）在返回焊料块370之前，进入柱376内，最后进入垫364内。这种电流路线396致使在焊料块370上边缘372和下边缘374的区域内，电流聚集增加。如图10所示，介电层40、41的存在防止电流（线96）穿过邻近其上边缘72和下边缘74的焊料块70区域，以约为1.25至1.75之间的系数，降低每个区域内的电流聚集梯度。这可致使由于在焊料块70每个端部的界面内形成空穴而互连失效的可能性降低。
另外，组件14内的柱76的存在，可进一步减小互连结构70内同类金属与同类金属之间的距离，如参照图1在上文所述。在图2的结构内，这个距离由端对端的距离94来表示。当距离94为距离90的大约10%至30%之间时，距离94可致使从端部62延伸至端部82的金属间化合物的形成。替代地，柱76可为任意导电突起，如突柱、引脚或类似物。通过在两个组件12、14内都包括导电突起，获得产生可靠的金属间化合物的连接、同时在相邻互连结构50之间获得比如图1所示采用柱至垫的布置中可能的间距更小的间距是可能的，同时可具有更大的总距离90。另外，与简单地使焊料块70形成在垫64上相比，通过在垫64上形成介电层41，更低的电流聚集是可能的。通过在互连结构50内包括柱76，浓度梯度对电迁移的影响也可进一步降低。在这种结构内，互连结构50中柱56的区域内铜浓度变化速度的降低，也可在柱76的区域内获得，从而在焊料块70的两个端部都没有铜浓度的急剧变化。
图1和图2所示的包括介电层40、41及其相关结构的互连结构50，可在其他连接类型中采用，不限于图1和图2所示的堆叠子组件布置。例如，它们可在倒装芯片结合（如图1和图2中所示的微电子元件30与基板16之间的结合）中采用，及在与微电子子组件（如微电子子组件12）与另一基板以面向上或者以倒装芯片的结合方式的连接中采用。另外，在基板18的上表面26上，组件（如组件14）可进一步包括具有形成于其上的柱和介电层的附加触点垫，以与柱56和介电层40相同的方式，与另一微电子组件采用如图1和图2所示的互连结构连接。这种布置可继续，以在堆叠封装内附接另外的组件。
尽管本发明参照特定实施例进行描述，可以理解的是，这些实施例只是说明本发明的原理和应用。因此，应理解为，在不偏离由附加的权利要求书所限定的本发明实质和范围的情况下，说明的实施例可做出许多修改及可设计出其他布置。

Claims (23)

1.微电子组件，包括：
第一表面；
第一薄导电元件，在所述第一表面暴露，并具有包含第一区域和第二区域的第一工作面；
第一导电突起，具有与所述第一工作面的第一区域连接并覆盖该区域的基底，且延伸至远离所述基底的第一端部，所述第一导电突起还包括从所述基底延伸至所述第一端部的连续的边缘；
第一介电材料层，覆盖所述第一薄导电元件的第二区域，并至少与所述第一导电突起的所述边缘接触；及
第一基板，具有第二表面和远离所述第二表面而延伸的第二导电突起；
第二薄导电元件，在所述第一基板的所述第二表面暴露，所述第二薄导电元件具有包含第一区域和第二区域的第二工作面，且其中所述第二导电突起具有基底、远离所述第二表面的第二端部以及从所述第二导电突起的基底延伸至所述第二端部的连续的边缘，所述基底限定外周且与所述第二薄导电元件的第一区域连接并覆盖该区域；
第二介电材料层，覆盖所述第二薄导电元件的第二区域，并至少与所述第二导电突起的所述边缘接触；及
第一易熔金属块，在所述第一介电材料层与所述第二介电材料层之间延伸，并使所述第一导电突起与所述第二导电突起连接，使得所述第一工作面面向所述第二表面，其中所述第一易熔金属块沿所述第一导电突起的所述边缘朝所述第一介电材料层延伸；
其中所述第一导电突起的第一端部与所述第二导电突起的第二端部间隔开第一距离，并在其间限定间隙，且其中所述第一易熔金属块在所述间隙内延伸。
2.根据权利要求1所述的微电子组件，其中所述第一表面形成在第二基板上，且所述第一基板具有附接于其上的微电子元件。
3.根据权利要求1所述的微电子组件，其中所述第一表面形成在第二基板上，所述第二基板进一步具有附接于其上的微电子元件。
4.根据权利要求1所述的微电子组件，其中所述第一易熔金属块与所述第一介电材料层接触。
5.根据权利要求1所述的微电子组件，其中所述第一介电材料覆盖所述第一表面的至少一部分。
6.根据权利要求1所述的微电子组件，其中所述第一距离在10微米至30微米之间。
7.根据权利要求1所述的微电子组件，进一步包括在所述第一表面暴露的复数个薄导电元件、复数个第一导电突起和复数个第二导电突起，每个薄导电元件都具有包括第一区域和第二区域的工作面，每个第一导电突起都与所述复数个薄导电元件中相应的一个的第一工作面的第一区域连接，并延伸至远离其的第一端部，每个所述第二导电突起远离所述第二工作面而延伸；
其中所述第一介电材料层覆盖所述薄导电元件的第二区域，复数个第一易熔金属块使所述第一导电突起中相应的一个与所述第二导电突起中相应的一个连接，其中每个相应的第一易熔金属块在每个相应的第一导电突起的一部分上朝所述第一介电层延伸。
8.根据权利要求1所述的微电子组件，进一步包括在所述第一介电材料层内限定内表面的第一开口，且其中所述内表面沿所述第一导电突起的一部分延伸，并与其接触。
9.根据权利要求8所述的微电子组件，其中所述第一介电材料层具有沿垂直于所述第一薄导电元件的第一工作面的方向延伸的厚度，且其中所述厚度在10微米至30微米之间。
10.根据权利要求8所述的微电子组件，其中所述第一介电材料层具有沿垂直于所述第一薄导电元件的第一工作面的方向延伸的厚度，且其中所述厚度为所述第一导电突起的高度的20%至50%。
11.根据权利要求1所述的微电子组件，其中所述第一导电突起的基底具有外周，其中所述第一工作面的第二区域在所述第一导电突起的基底的外周之外暴露。
12.根据权利要求11所述的微电子组件，其中所述第一导电突起限定侧壁，所述侧壁沿其横截面轮廓为笔直的。
13.根据权利要求12所述的微电子组件，其中在所述第一薄导电元件的第一工作面与所述第一薄导电元件的侧壁之间形成拐角，所述拐角沿所述第一薄导电元件的基底的外周设置，且其中所述第一介电材料层覆盖所述拐角。
14.根据权利要求11所述的微电子组件，其中所述第一导电突起的基底包括在所述基底与所述第一端部之间延伸的笔直部分及从所述基底的外周延伸的过渡部分，所述过渡部分沿其横截面轮廓为拱形， 且其中所述第一介电材料层覆盖所述过渡部分。
15.根据权利要求11所述的微电子组件，其中所述第一导电突起的基底与所述第一薄导电元件通过导电金属层而连接，所述导电金属层具有与所述第一导电突起的基底的外周对齐的外表面，且其中所述第一介电材料层覆盖所述导电金属层的外表面。
16.根据权利要求要求1所述的微电子组件，其中所述第一易熔金属块在所述第二导电突起的一部分上朝所述第二介电材料层延伸。
17.根据权利要求1所述的微电子组件，其中所述第一导电突起限定侧壁，且其中沉积金属层形成在所述第一导电突起的所述第一端部及其所述侧壁的至少一部分上。
18.根据权利要求17所述的微电子组件，其中所述第一介电材料层包括与所述第一表面平行的外表面，所述沉积金属层进一步形成为，其一部分沿所述外表面并远离所述第一导电突起向外延伸。
19.根据权利要求1所述的微电子组件，进一步包括形成在所述第一基板上并从所述第二薄导电元件延伸的导电迹线。
20.根据权利要求1所述的微电子组件，所述第一导电突起的边缘从其基底向其第一端部逐渐变细。
21.根据权利要求20所述的微电子组件，所述第一易熔金属块沿所述第一导电突起的所述边缘延伸。
22.根据权利要求1所述的微电子组件，所述第一导电突起呈截头圆锥形。
23.微电子组件，包括：
第一表面；
第一薄导电元件，在所述第一表面暴露，并具有包含第一区域和第二区域的第一工作面；
第一导电突起，具有与所述第一工作面的第一区域连接并覆盖该区域的基底，且延伸至远离所述基底的第一端部，所述第一导电突起还包括从所述基底延伸至所述第一端部的连续的边缘；
第一介电材料层，覆盖所述第一薄导电元件的第二区域，并至少与所述第一导电突起的所述边缘接触；及
第一基板，具有第二表面和远离所述第二表面而延伸的第二导电突起；
第二薄导电元件，在所述第一基板的所述第二表面暴露，所述第二薄导电元件具有包含第一区域和第二区域的第二工作面，且其中所述第二导电突起具有基底、远离所述第二表面的第二端部以及从所述第二导电突起的基底延伸至所述第二端部的连续的边缘，所述基底限定外周且与所述第二薄导电元件的第一区域连接并覆盖该区域；
第二介电材料层，覆盖所述第二薄导电元件的第二区域，并至少与所述第二导电突起的所述边缘接触；及
第一易熔金属块，在所述第一介电材料层与所述第二介电材料层之间延伸，并使所述第一导电突起与所述第二导电突起连接，使得所述第一工作面面向所述第二表面，其中所述第一易熔金属块沿所述第一导电突起的所述边缘朝所述第一介电材料层延伸；
其中所述第一导电突起的边缘从其基底向其第一端部逐渐变细，所述第一易熔金属块沿所述第一导电突起的所述边缘延伸。
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Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5592055B2 (ja) 2004-11-03 2014-09-17 テッセラ，インコーポレイテッド 積層パッケージングの改良
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
US8796849B2 (en) 2012-10-22 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Metal bump joint structure
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9806045B2 (en) * 2013-08-29 2017-10-31 Taiwan Semiconductor Manufacturing Company Ltd. Interconnection structure including a metal post encapsulated by solder joint having a concave outer surface
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
JP6282454B2 (ja) * 2013-12-10 2018-02-21 新光電気工業株式会社 半導体パッケージの製造方法
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
KR102270283B1 (ko) * 2014-11-11 2021-06-29 엘지이노텍 주식회사 반도체 패키지
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US11186656B2 (en) 2019-05-24 2021-11-30 Chevron Phillips Chemical Company Lp Preparation of large pore silicas and uses thereof in chromium catalysts for olefin polymerization
CN112752994B (zh) * 2019-08-30 2022-08-02 京东方科技集团股份有限公司 背板、背光源、显示装置及背板的制造方法
JP2021044278A (ja) * 2019-09-06 2021-03-18 キオクシア株式会社 半導体装置
CN111029296B (zh) * 2019-11-22 2022-11-22 中国电子科技集团公司第十三研究所 堆叠间距可控的多层基板堆叠结构的制备方法
US11502056B2 (en) * 2020-07-08 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure in semiconductor package and manufacturing method thereof
KR20220011006A (ko) * 2020-07-20 2022-01-27 삼성전자주식회사 반도체 패키지
US11404386B2 (en) * 2020-08-28 2022-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11581251B2 (en) * 2020-11-10 2023-02-14 Qualcomm Incorporated Package comprising inter-substrate gradient interconnect structure
US11521947B1 (en) * 2021-07-14 2022-12-06 Nxp Usa, Inc. Space efficient flip chip joint design

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7569935B1 (en) * 2008-11-12 2009-08-04 Powertech Technology Inc. Pillar-to-pillar flip-chip assembly
CN101874296A (zh) * 2007-09-28 2010-10-27 泰塞拉公司 利用成对凸柱进行倒装芯片互连

Family Cites Families (280)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3214827A (en) 1962-12-10 1965-11-02 Sperry Rand Corp Electrical circuitry fabrication
US3775844A (en) 1970-06-25 1973-12-04 Bunker Ramo Method of fabricating a multiwafer electrical circuit structure
US3766439A (en) 1972-01-12 1973-10-16 Gen Electric Electronic module using flexible printed circuit board with heat sink means
US3873889A (en) 1973-08-08 1975-03-25 Sperry Rand Corp Indicator module and method of manufacturing same
JPS54148484U (zh) 1978-04-08 1979-10-16
US4225900A (en) 1978-10-25 1980-09-30 Raytheon Company Integrated circuit device package interconnect means
JPS57107501U (zh) 1980-12-22 1982-07-02
US4567543A (en) 1983-02-15 1986-01-28 Motorola, Inc. Double-sided flexible electronic circuit module
US4576543A (en) 1983-11-07 1986-03-18 Kmw Products Limited Knock-down construction for front end loader
US5220488A (en) 1985-09-04 1993-06-15 Ufe Incorporated Injection molded printed circuits
JPH0831835B2 (ja) 1985-10-30 1996-03-27 株式会社日立製作所 クロツク再生回路
JPS62117346A (ja) 1985-11-18 1987-05-28 Fujitsu Ltd 半導体装置
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
US4695870A (en) 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
JPS6397941A (ja) 1986-10-14 1988-04-28 Fuji Photo Film Co Ltd 感光材料
JPS63153889U (zh) 1987-03-30 1988-10-07
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
US4781601A (en) 1987-07-06 1988-11-01 Motorola, Inc. Header for an electronic circuit
US4804132A (en) 1987-08-28 1989-02-14 Difrancesco Louis Method for cold bonding
JPS6486527A (en) 1987-09-29 1989-03-31 Hitachi Cable Ccb tape carrier
US5198888A (en) 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US5028986A (en) 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5116456A (en) 1988-04-18 1992-05-26 Solon Technologies, Inc. Apparatus and method for growth of large single crystals in plate/slab form
US4991290A (en) 1988-07-21 1991-02-12 Microelectronics And Computer Technology Flexible electrical interconnect and method of making
JPH02174255A (ja) 1988-12-27 1990-07-05 Mitsubishi Electric Corp 半導体集積回路装置
US5068714A (en) 1989-04-05 1991-11-26 Robert Bosch Gmbh Method of electrically and mechanically connecting a semiconductor to a substrate using an electrically conductive tacky adhesive and the device so made
US5077598A (en) 1989-11-08 1991-12-31 Hewlett-Packard Company Strain relief flip-chip integrated circuit assembly with test fixturing
CA2034703A1 (en) 1990-01-23 1991-07-24 Masanori Nishiguchi Substrate for packaging a semiconductor device
AU637874B2 (en) 1990-01-23 1993-06-10 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US5083697A (en) 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US4975079A (en) 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing
US5046238A (en) 1990-03-15 1991-09-10 Rogers Corporation Method of manufacturing a multilayer circuit board
US5345205A (en) 1990-04-05 1994-09-06 General Electric Company Compact high density interconnected microwave system
DE59104134D1 (de) 1990-04-09 1995-02-16 Ascom Tech Ag Bit- und rahmensynchronisiereinheit für einen zugriffsknoten einer optischen übertragungseinrichtung.
US5251806A (en) 1990-06-19 1993-10-12 International Business Machines Corporation Method of forming dual height solder interconnections
US5130779A (en) 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
JPH04151843A (ja) 1990-10-16 1992-05-25 Casio Comput Co Ltd Ｉｃチップのボンディング方法
US5117282A (en) 1990-10-29 1992-05-26 Harris Corporation Stacked configuration for integrated circuit devices
US5172303A (en) 1990-11-23 1992-12-15 Motorola, Inc. Electronic component assembly
US5116459A (en) 1991-03-06 1992-05-26 International Business Machines Corporation Processes for electrically conductive decals filled with organic insulator material
US5541525A (en) 1991-06-04 1996-07-30 Micron Technology, Inc. Carrier for testing an unpackaged semiconductor die
JPH0513967A (ja) 1991-07-03 1993-01-22 Mitsubishi Electric Corp 半導体記憶制御装置及びその高密度実装方法
WO1993004375A1 (en) 1991-08-23 1993-03-04 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US5397916A (en) 1991-12-10 1995-03-14 Normington; Peter J. C. Semiconductor device including stacked die
US5281852A (en) 1991-12-10 1994-01-25 Normington Peter J C Semiconductor device including stacked die
US5224023A (en) 1992-02-10 1993-06-29 Smith Gary W Foldable electronic assembly module
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
JP2894071B2 (ja) 1992-03-09 1999-05-24 株式会社日立製作所 半導体装置
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5247423A (en) 1992-05-26 1993-09-21 Motorola, Inc. Stacking three dimensional leadless multi-chip module and method for making the same
US5820770A (en) 1992-07-21 1998-10-13 Seagate Technology, Inc. Thin film magnetic head including vias formed in alumina layer and process for making the same
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
JP3151219B2 (ja) 1992-07-24 2001-04-03 テツセラ，インコーポレイテッド 取り外し自在のリード支持体を備えた半導体接続構成体およびその製造方法
EP0586888B1 (en) 1992-08-05 2001-07-18 Fujitsu Limited Three-dimensional multichip module
US5324892A (en) 1992-08-07 1994-06-28 International Business Machines Corporation Method of fabricating an electronic interconnection
JP3105089B2 (ja) 1992-09-11 2000-10-30 株式会社東芝 半導体装置
US5334804A (en) 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
JP2716336B2 (ja) 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
US5455740A (en) 1994-03-07 1995-10-03 Staktek Corporation Bus communication system for stacked high density integrated circuit packages
US5811982A (en) 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US5398863A (en) 1993-07-23 1995-03-21 Tessera, Inc. Shaped lead structure and method
US5390844A (en) 1993-07-23 1995-02-21 Tessera, Inc. Semiconductor inner lead bonding tool
US5397921A (en) 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5454160A (en) 1993-12-03 1995-10-03 Ncr Corporation Apparatus and method for stacking integrated circuit devices
US5457879A (en) 1994-01-04 1995-10-17 Motorola, Inc. Method of shaping inter-substrate plug and receptacles interconnects
JP3378334B2 (ja) 1994-01-26 2003-02-17 株式会社東芝 半導体装置実装構造体
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
US5448511A (en) 1994-06-01 1995-09-05 Storage Technology Corporation Memory stack with an integrated interconnect and mounting structure
US5466635A (en) 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
US5615824A (en) 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
US5798286A (en) 1995-09-22 1998-08-25 Tessera, Inc. Connecting multiple microelectronic elements with lead deformation
US5518964A (en) 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US5989936A (en) 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US5539153A (en) 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5491302A (en) 1994-09-19 1996-02-13 Tessera, Inc. Microelectronic bonding with lead motion
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
EP0703612B1 (en) 1994-09-20 1998-11-25 STMicroelectronics S.r.l. Method for electrically insulating heat sinks in electronic power devices
JP2570628B2 (ja) 1994-09-21 1997-01-08 日本電気株式会社 半導体パッケージおよびその製造方法
US5587342A (en) 1995-04-03 1996-12-24 Motorola, Inc. Method of forming an electrical interconnect
JP2606177B2 (ja) 1995-04-26 1997-04-30 日本電気株式会社 印刷配線板
US5985692A (en) 1995-06-07 1999-11-16 Microunit Systems Engineering, Inc. Process for flip-chip bonding a semiconductor die having gold bump electrodes
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
JP3297254B2 (ja) 1995-07-05 2002-07-02 株式会社東芝 半導体パッケージおよびその製造方法
US5777379A (en) 1995-08-18 1998-07-07 Tessera, Inc. Semiconductor assemblies with reinforced peripheral regions
JP3549294B2 (ja) 1995-08-23 2004-08-04 新光電気工業株式会社 半導体装置及びその実装構造
US5810609A (en) 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
US5861666A (en) 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US5674785A (en) 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
US5646446A (en) 1995-12-22 1997-07-08 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5789815A (en) 1996-04-23 1998-08-04 Motorola, Inc. Three dimensional semiconductor package having flexible appendages
JPH1013003A (ja) 1996-06-26 1998-01-16 Casio Comput Co Ltd 半導体装置
US5689091A (en) 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
JPH10125734A (ja) 1996-10-24 1998-05-15 Matsushita Electric Ind Co Ltd 半導体ユニットおよびその製造方法
US5762845A (en) 1996-11-19 1998-06-09 Packard Hughes Interconnect Company Method of making circuit with conductive and non-conductive raised features
US5929521A (en) 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
JPH1140694A (ja) 1997-07-16 1999-02-12 Oki Electric Ind Co Ltd 半導体パッケージおよび半導体装置とその製造方法
US6335571B1 (en) 1997-07-21 2002-01-01 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
WO1999009595A1 (en) 1997-08-19 1999-02-25 Hitachi, Ltd. Multichip module structure and method for manufacturing the same
CA2213590C (en) 1997-08-21 2006-11-07 Keith C. Carroll Flexible circuit connector and method of making same
JPH1187556A (ja) 1997-09-08 1999-03-30 Hitachi Ltd 半導体装置
JPH1197576A (ja) 1997-09-22 1999-04-09 Matsushita Electric Ind Co Ltd 半導体装置
JP3937265B2 (ja) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 半導体装置
JPH11111886A (ja) 1997-10-07 1999-04-23 Sony Corp 実装基板およびその製造方法
US6217972B1 (en) 1997-10-17 2001-04-17 Tessera, Inc. Enhancements in framed sheet processing
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US5973391A (en) 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
US6329594B1 (en) 1998-01-16 2001-12-11 Bae Systems Information And Electronic Systems Integration, Inc. Integrated circuit package
US5956234A (en) 1998-01-20 1999-09-21 Integrated Device Technology, Inc. Method and structure for a surface mountable rigid-flex printed circuit board
US6061245A (en) 1998-01-22 2000-05-09 International Business Machines Corporation Free standing, three dimensional, multi-chip, carrier package with air flow baffle
US6235996B1 (en) 1998-01-28 2001-05-22 International Business Machines Corporation Interconnection structure and process module assembly and rework
US6300679B1 (en) 1998-06-01 2001-10-09 Semiconductor Components Industries, Llc Flexible substrate for packaging a semiconductor component
US6414391B1 (en) 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6218302B1 (en) 1998-07-21 2001-04-17 Motorola Inc. Method for forming a semiconductor device
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000100869A (ja) 1998-09-22 2000-04-07 Hitachi Ltd 半導体装置およびその製造方法
JP3407275B2 (ja) 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US6332270B2 (en) 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
JP3137186B2 (ja) 1999-02-05 2001-02-19 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 層間接続構造体、多層配線基板およびそれらの形成方法
US6965166B2 (en) 1999-02-24 2005-11-15 Rohm Co., Ltd. Semiconductor device of chip-on-chip structure
US6980017B1 (en) 1999-03-10 2005-12-27 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
JP2000277649A (ja) 1999-03-26 2000-10-06 Matsushita Electric Works Ltd 半導体装置及びその製造方法
US6177729B1 (en) 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
JP3446825B2 (ja) 1999-04-06 2003-09-16 沖電気工業株式会社 半導体装置およびその製造方法
US6225206B1 (en) 1999-05-10 2001-05-01 International Business Machines Corporation Flip chip C4 extension structure and process
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
US6782610B1 (en) 1999-05-21 2004-08-31 North Corporation Method for fabricating a wiring substrate by electroplating a wiring film on a metal base
JP3973340B2 (ja) 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
TW512467B (en) 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
JP2001118872A (ja) 1999-10-18 2001-04-27 Daiwa Kogyo:Kk バンプの形成方法
US6869750B2 (en) 1999-10-28 2005-03-22 Fujitsu Limited Structure and method for forming a multilayered structure
US6882045B2 (en) 1999-10-28 2005-04-19 Thomas J. Massingill Multi-chip module and method for forming and method for deplating defective capacitors
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6534861B1 (en) 1999-11-15 2003-03-18 Substrate Technologies Incorporated Ball grid substrate for lead-on-chip semiconductor package
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6216941B1 (en) 2000-01-06 2001-04-17 Trw Inc. Method for forming high frequency connections to high temperature superconductor circuits and other fragile materials
JP2001196381A (ja) 2000-01-12 2001-07-19 Toyo Kohan Co Ltd 半導体装置、半導体上の回路形成に用いる金属積層板、および回路形成方法
JP3865989B2 (ja) 2000-01-13 2007-01-10 新光電気工業株式会社 多層配線基板、配線基板、多層配線基板の製造方法、配線基板の製造方法、及び半導体装置
US20030001286A1 (en) 2000-01-28 2003-01-02 Ryoichi Kajiwara Semiconductor package and flip chip bonding method therein
US6469394B1 (en) 2000-01-31 2002-10-22 Fujitsu Limited Conductive interconnect structures and methods for forming conductive interconnect structures
JP3752949B2 (ja) 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
ATE459099T1 (de) 2000-03-10 2010-03-15 Chippac Inc Flipchip-verbindungsstruktur und dessen herstellungsverfahren
JP2001284783A (ja) 2000-03-30 2001-10-12 Shinko Electric Ind Co Ltd 表面実装用基板及び表面実装構造
US6565441B1 (en) 2000-04-07 2003-05-20 Arista Enterprises Inc. Dedicated wireless digital video disc (DVD) controller for video game consoles
JP2001308095A (ja) 2000-04-19 2001-11-02 Toyo Kohan Co Ltd 半導体装置およびその製造方法
US6592019B2 (en) 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6647310B1 (en) 2000-05-30 2003-11-11 Advanced Micro Devices, Inc. Temperature control of an integrated circuit
JP2002016096A (ja) 2000-06-27 2002-01-18 Citizen Watch Co Ltd 半導体装置とその製造方法
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
JP2002289768A (ja) 2000-07-17 2002-10-04 Rohm Co Ltd 半導体装置およびその製法
JP3653452B2 (ja) 2000-07-31 2005-05-25 株式会社ノース 配線回路基板とその製造方法と半導体集積回路装置とその製造方法
US6592109B2 (en) 2000-07-31 2003-07-15 Toyo Tire & Rubber Co., Ltd. Liquid sealing type body mount
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
JP3735526B2 (ja) 2000-10-04 2006-01-18 日本電気株式会社 半導体装置及びその製造方法
JP2002124548A (ja) 2000-10-17 2002-04-26 Hitachi Cable Ltd テープキャリア及びそれを用いた半導体装置
JP2002151551A (ja) 2000-11-10 2002-05-24 Hitachi Ltd フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6734539B2 (en) 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
US6800169B2 (en) 2001-01-08 2004-10-05 Fujitsu Limited Method for joining conductive structures and an electrical conductive article
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
JP2002261204A (ja) 2001-03-02 2002-09-13 Hitachi Aic Inc インターポーザ基板及びその電子部品実装体
US6648213B1 (en) 2001-03-05 2003-11-18 Saturn Electronics & Engineering, Inc. Manufacturing method for attaching components to a substrate
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US7242099B2 (en) 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
JP4141135B2 (ja) 2001-03-28 2008-08-27 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 多層配線基板の製造方法
US20050097727A1 (en) 2001-03-28 2005-05-12 Tomoo Iijima Multi-layer wiring board, method for producing multi-layer wiring board, polishing machine for multi-layer wiring board, and metal sheet for producing wiring board
JP3851517B2 (ja) 2001-04-18 2006-11-29 カシオマイクロニクス株式会社 半導体装置およびその製造方法並びにその接合構造
JP2002313996A (ja) 2001-04-18 2002-10-25 Toshiba Chem Corp 半導体パッケージ用基板およびその製造方法
JP2003051665A (ja) 2001-05-31 2003-02-21 Fujikura Ltd 電子部品の実装方法
DE10128573A1 (de) 2001-06-13 2003-01-02 Infineon Technologies Ag Verhindern der unerwünschten externen Erfassung von Operationen in integrierten Digitalschaltungen
US6547124B2 (en) 2001-06-14 2003-04-15 Bae Systems Information And Electronic Systems Integration Inc. Method for forming a micro column grid array (CGA)
JP2003007768A (ja) 2001-06-25 2003-01-10 Sumitomo Metal Mining Co Ltd 層間接続材、その製造方法及び使用方法
JP4663165B2 (ja) 2001-06-27 2011-03-30 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP3692978B2 (ja) * 2001-07-24 2005-09-07 日立電線株式会社 配線基板の製造方法
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
US6992379B2 (en) 2001-09-05 2006-01-31 International Business Machines Corporation Electronic package having a thermal stretching layer
US6767819B2 (en) 2001-09-12 2004-07-27 Dow Corning Corporation Apparatus with compliant electrical terminals, and methods for forming same
JP2003092472A (ja) 2001-09-19 2003-03-28 Hitachi Metals Ltd 多層配線板形成用積層箔及びそれを用いた多層配線板の製造方法
JP4080827B2 (ja) 2001-09-24 2008-04-23 富士通株式会社 接合方法および導電性回路構造
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP2005506690A (ja) 2001-10-09 2005-03-03 テッセラ，インコーポレイテッド 積層パッケージ
JP3787295B2 (ja) 2001-10-23 2006-06-21 ローム株式会社 半導体装置
JP3583396B2 (ja) * 2001-10-31 2004-11-04 富士通株式会社 半導体装置の製造方法、薄膜多層基板及びその製造方法
JP3875077B2 (ja) 2001-11-16 2007-01-31 富士通株式会社 電子デバイス及びデバイス接続方法
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
TWI284973B (en) 2002-04-03 2007-08-01 Advanced Semiconductor Eng Flip-chip joint structure, and fabricating process thereof
US6744142B2 (en) 2002-06-19 2004-06-01 National Central University Flip chip interconnection structure and process of making the same
US6803303B1 (en) 2002-07-11 2004-10-12 Micron Technology, Inc. Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts
US20040007779A1 (en) 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
JP4107932B2 (ja) 2002-10-03 2008-06-25 唯知 須賀 電子部品実装装置の製造方法
JP2005026645A (ja) 2002-10-15 2005-01-27 Shinko Electric Ind Co Ltd 回路基板及びその製造方法
US7087458B2 (en) 2002-10-30 2006-08-08 Advanpack Solutions Pte. Ltd. Method for fabricating a flip chip package with pillar bump and no flow underfill
JP2004179232A (ja) 2002-11-25 2004-06-24 Seiko Epson Corp 半導体装置及びその製造方法並びに電子機器
TW200423344A (en) 2002-12-31 2004-11-01 Texas Instruments Inc Composite metal column for mounting semiconductor device
JP2004221450A (ja) 2003-01-17 2004-08-05 Toppan Printing Co Ltd プリント配線板およびその製造方法
CN100531526C (zh) 2003-01-17 2009-08-19 凸版印刷株式会社 金属光蚀刻制品及该制品的制造方法
US20040155358A1 (en) 2003-02-07 2004-08-12 Toshitsune Iijima First and second level packaging assemblies and method of assembling package
JP3823318B2 (ja) * 2003-03-11 2006-09-20 セイコーエプソン株式会社 半導体チップの回路基板への実装方法、半導体装置、電子デバイスおよび電子機器
TW200507218A (en) 2003-03-31 2005-02-16 North Corp Layout circuit substrate, manufacturing method of layout circuit substrate, and circuit module
JP2005045191A (ja) 2003-07-04 2005-02-17 North:Kk 配線回路基板の製造方法、及び多層配線基板の製造方法
JP4036786B2 (ja) 2003-04-24 2008-01-23 唯知 須賀 電子部品実装方法
TWI234252B (en) 2003-05-13 2005-06-11 Siliconware Precision Industries Co Ltd Flash-preventing window ball grid array semiconductor package and chip carrier and method for fabricating the same
JP2004342802A (ja) 2003-05-15 2004-12-02 Sharp Corp 突起電極付きプリント基板およびその製造方法
JP4389471B2 (ja) 2003-05-19 2009-12-24 パナソニック株式会社 電子回路の接続構造とその接続方法
JP4104490B2 (ja) 2003-05-21 2008-06-18 オリンパス株式会社 半導体装置の製造方法
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6888255B2 (en) 2003-05-30 2005-05-03 Texas Instruments Incorporated Built-up bump pad structure and method for same
US7005241B2 (en) 2003-06-09 2006-02-28 Shinko Electric Industries Co., Ltd. Process for making circuit board or lead frame
US20050124091A1 (en) 2003-06-09 2005-06-09 Shinko Electric Industries Co., Ltd. Process for making circuit board or lead frame
US7242097B2 (en) 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
JP4056001B2 (ja) 2003-07-11 2008-03-05 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法
JP2005077955A (ja) 2003-09-02 2005-03-24 Sanyo Electric Co Ltd エッチング方法およびそれを用いた回路装置の製造方法
JP4190989B2 (ja) 2003-09-12 2008-12-03 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法及び多層配線基板の製造方法
JP2005123547A (ja) 2003-09-24 2005-05-12 Ibiden Co Ltd インターポーザ、多層プリント配線板
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7495179B2 (en) 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
US8641913B2 (en) 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
WO2005065207A2 (en) 2003-12-30 2005-07-21 Tessera, Inc. Microelectronic packages and methods therefor
JP3997991B2 (ja) 2004-01-14 2007-10-24 セイコーエプソン株式会社 電子装置
JP2005216696A (ja) 2004-01-30 2005-08-11 Ngk Spark Plug Co Ltd 中継基板、中継基板付き基板
JP2005243761A (ja) 2004-02-25 2005-09-08 Ngk Spark Plug Co Ltd 中継基板、中継基板付き樹脂製基板
JP2005285986A (ja) 2004-03-29 2005-10-13 Daiwa Kogyo:Kk 柱状金属体の形成方法及び柱状金属体
KR100606441B1 (ko) 2004-04-30 2006-08-01 엘지.필립스 엘시디 주식회사 클리체 제조방법 및 이를 이용한 패턴 형성방법
JP4661122B2 (ja) 2004-05-18 2011-03-30 ソニー株式会社 部品実装配線基板および配線基板への部品の実装方法
WO2005122706A2 (en) 2004-05-31 2005-12-29 Joon-Mo Kang Method of aligning semiconductor device and semiconductor structure thereof
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
JP5329083B2 (ja) 2004-06-25 2013-10-30 テッセラ，インコーポレイテッド ポストおよびパッドを有する部品
US6956165B1 (en) 2004-06-28 2005-10-18 Altera Corporation Underfill for maximum flip chip package reliability
US20060091538A1 (en) 2004-11-04 2006-05-04 Kabadi Ashok N Low profile and tight pad-pitch land-grid-array (LGA) socket
JP4908750B2 (ja) 2004-11-25 2012-04-04 ローム株式会社 半導体装置
US7317249B2 (en) 2004-12-23 2008-01-08 Tessera, Inc. Microelectronic package having stacked semiconductor devices and a process for its fabrication
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP2007023338A (ja) 2005-07-15 2007-02-01 Shinko Electric Ind Co Ltd 金属板パターン及び回路基板の形成方法
TWI273667B (en) 2005-08-30 2007-02-11 Via Tech Inc Chip package and bump connecting structure thereof
JP5279180B2 (ja) * 2005-10-03 2013-09-04 ローム株式会社 半導体装置
EP1962342A4 (en) * 2005-12-14 2010-09-01 Shinko Electric Ind Co SUBSTRATE WITH INTEGRATED CHIP AND METHOD FOR MANUFACTURING THE SAME
JP4742844B2 (ja) 2005-12-15 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8067267B2 (en) * 2005-12-23 2011-11-29 Tessera, Inc. Microelectronic assemblies having very fine pitch stacking
TWI286829B (en) 2006-01-17 2007-09-11 Via Tech Inc Chip package
DE102006006825A1 (de) 2006-02-14 2007-08-23 Infineon Technologies Ag Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelements
JP4672576B2 (ja) 2006-03-09 2011-04-20 富士通株式会社 電子デバイス及びその製造方法
JP4661657B2 (ja) 2006-03-30 2011-03-30 株式会社デンソー バンプ接合体の製造方法
CN101479839A (zh) 2006-04-24 2009-07-08 株式会社村田制作所 电子元件、使用该电子元件的电子元件装置及其制造方法
US7964800B2 (en) 2006-05-25 2011-06-21 Fujikura Ltd. Printed wiring board, method for forming the printed wiring board, and board interconnection structure
TW200801513A (en) 2006-06-29 2008-01-01 Fermiscan Australia Pty Ltd Improved process
JP4901384B2 (ja) 2006-09-14 2012-03-21 パナソニック株式会社 樹脂配線基板とそれを用いた半導体装置および積層型の半導体装置
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
JP2010514217A (ja) 2006-12-19 2010-04-30 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド チップ・コンデンサ組み込み型ｐｗｂ
US7939939B1 (en) 2007-06-11 2011-05-10 Texas Instruments Incorporated Stable gold bump solder connections
US7911805B2 (en) 2007-06-29 2011-03-22 Tessera, Inc. Multilayer wiring element having pin interface
KR101458538B1 (ko) 2007-07-27 2014-11-07 테세라, 인코포레이티드 적층형 마이크로 전자 유닛, 및 이의 제조방법
CN101861646B (zh) 2007-08-03 2015-03-18 泰塞拉公司 利用再生晶圆的堆叠封装
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US20090071707A1 (en) 2007-08-15 2009-03-19 Tessera, Inc. Multilayer substrate with interconnection vias and method of manufacturing the same
US8505199B2 (en) 2007-08-15 2013-08-13 Tessera, Inc. Method of fabricating an interconnection element having conductive posts
KR101572600B1 (ko) 2007-10-10 2015-11-27 테세라, 인코포레이티드 다층 배선 요소와 마이크로전자 요소가 실장된 어셈블리
TWI389290B (zh) 2007-11-08 2013-03-11 Ind Tech Res Inst 晶片結構及其製程、晶片堆疊結構及其製程
JP2009158593A (ja) 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
KR20090080623A (ko) * 2008-01-22 2009-07-27 삼성전기주식회사 포스트 범프 및 그 형성방법
JP4483969B2 (ja) 2008-03-31 2010-06-16 セイコーエプソン株式会社 基板及びその製造方法、半導体装置の製造方法
JP2009302095A (ja) 2008-06-10 2009-12-24 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
US8115310B2 (en) 2009-06-11 2012-02-14 Texas Instruments Incorporated Copper pillar bonding for fine pitch flip chip devices
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101874296A (zh) * 2007-09-28 2010-10-27 泰塞拉公司 利用成对凸柱进行倒装芯片互连
US7569935B1 (en) * 2008-11-12 2009-08-04 Powertech Technology Inc. Pillar-to-pillar flip-chip assembly

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