TWI495069B - 互連結構 - Google Patents

互連結構 Download PDF

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Publication number
TWI495069B
TWI495069B TW100145661A TW100145661A TWI495069B TW I495069 B TWI495069 B TW I495069B TW 100145661 A TW100145661 A TW 100145661A TW 100145661 A TW100145661 A TW 100145661A TW I495069 B TWI495069 B TW I495069B
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TW
Taiwan
Prior art keywords
conductive
substrate
layer
dielectric material
microelectronic assembly
Prior art date
Application number
TW100145661A
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English (en)
Other versions
TW201232737A (en
Inventor
Debabrata Gupta
Yukio Hashimoto
Ilyas Mohammed
Laura Mirkarimi
Rajesh Katkar
Original Assignee
Tessera Inc
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Application filed by Tessera Inc filed Critical Tessera Inc
Publication of TW201232737A publication Critical patent/TW201232737A/zh
Application granted granted Critical
Publication of TWI495069B publication Critical patent/TWI495069B/zh

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    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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Description

互連結構
本發明係關於在封裝微電子總成中使用之互連結構。特定言之，其係關於諸如在覆晶結合中，或在多個基板之間，諸如在形成堆疊式封裝中將微電子晶片及晶粒連接至基板時使用之互連結構。本文所述之結構可用來減小互連結合歸因於由先前結構之組件之間之電遷移造成之空隙形成的故障。
尤其在互連中之電流密度及裝置操作溫度高之高效能裝置中，電遷移是互連故障的一主要原因。一般言之，電遷移是由互連總成中之材料之不同擴散速率所造成。舉例而言，一互連總成可包含由銅製成且形成於兩個基板之各者上之一接觸墊以及在該等接觸墊之間結合之一焊料塊。焊料機械地固定兩個接觸墊，且因此，在其上形成該等接觸墊之基板且亦電連接兩個墊使得由一電流承載之一信號可透過該焊料塊而在該兩個墊之間傳遞。在此實例中，焊料與墊之銅之間之擴散速率可有所不同。擴散速率係金屬結構內分子移動速率，尤其是在經受由裝置操作造成之一電流或經受熱期間之分子移動速率。
互連結構中形成之空隙會減少使用該等互連結構之微電子總成之可靠性。此外，空隙之存在增加圍繞該等空隙之區域中之材料內之電流密度。此可繼而進一步加劇擴散速率之差異，引起空隙形成之加速，最終引起互連元件之電氣故障及機械故障二者。
當前減少電遷移之手段包含在焊料中使用障壁金屬或摻雜物。然而，此等手段呈現其等自身之可靠性問題且所導致之成本增加超過其效能。相應地，需要用於減小電遷移之其他手段。
本發明之一實施例係關於一種微電子總成。該微電子總成包含一第一表面以及暴露在該第一表面且具有包括第一區及第二區之一面的一第一薄導電元件。具有連接至該面之該第一區並覆蓋該第一區的一基底之一第一導電凸出部延伸至遠離該基底之一末端。一第一介電材料層覆蓋該第一薄元件之該第二區且接觸該第一導電凸出部之至少該基底。該總成進一步包含一第二基板，該第二基板具有一第二面及自該第二面延伸出之一第二導電凸出部。一第一可熔金屬塊將該第一凸出部連接至該第二凸出部使得該第一面之該第一表面係定向成朝向該第二表面。該第一金屬塊沿該第一凸出部之一邊緣延伸朝向該第一介電材料層。
該微電子總成可經組態使得該第一表面係形成於一基板上且該第二表面係形成於一微電子元件上。另外或是或者，該第一表面可形成於一基板上，該基板進一步使一微電子元件貼附於其上，且該第二表面係形成於一第二基板上。在另一實施例中，該微電子總成包含複數個互連結構，該複數個互連結構各包含一第一導電元件、一第一導電凸出部、一第二導電凸出部及一第一金屬塊。各互連結構係連接於該第一面之該第一區與該第二面之間且具有類似於上述結構之一結構，其中該第一介電材料層覆蓋該等薄元件之該等第二區。
該第一介電材料層中之第一開口可界定一內表面使得該內表面沿該第一凸出部之一部分延伸成大體上與之接觸。相應地，該第一介電材料層可具有在垂直於該第一薄元件之該第一面之一方向上延伸之一厚度。該厚度可為該第一導電凸出部之一高度之約20%至50%。
該第一導電凸出部之該基底可具有一周邊，使得該第一面之該第二區係暴露在該第一凸出部之該基底之該周邊之外側。此配置可在該第一薄元件之該第一面與該第一導電元件之該側壁之間進一步形成一角。該角可定位成沿該第一導電元件之該基底之外周邊，且該第一介電材料層可大體上覆蓋該角。
在另一實施例中，一第二薄導電元件可暴露在該第二表面上且可具有由第一區及第二區組成之一第二面。該第二凸出部可進一步具有一基底，該基底連接至該第二薄元件之該第一區並覆蓋之且界定一周邊，以及遠離該基底之一末端部分。一第二介電材料層可覆蓋該第二薄元件之該第二區。此外，該第一金屬塊可在該第二導電凸出部之一部分上延伸朝向該第二介電材料層。
本發明之另一實施例係關於一種微電子總成，該微電子總成包含一第一表面，以及一第一薄導電元件，該第一薄導電元件暴露在該第一表面上且具有由第一區及第二區組成之一面。一第一導電凸出部係連接至該第一面之該第一區並覆蓋之並且延伸至遠離該第一區之一末端。該導電凸出部沿其之一部分形成具有遠離該第一薄導電元件之一第一邊緣之一障壁。該總成進一步包含具有自其延伸出之一第二導電凸出部之一第二面。一第一可熔金屬塊將該第一導電凸出部連接至該第二導電凸出部，使得該第一面之該第一表面係定向成朝向該第二基板之該第二表面。該第一金屬塊沿該第一導電凸出部之一部分延伸至朝向該障壁之該第一邊緣之一位置，該障壁係佈置於該第一薄元件與該第一金屬塊之間。該障壁可為形成於該第一導電凸出部中之一表面處理層。該表面處理層可藉由氧化而形成或者可為塗覆於該第一導電凸出部之一表面上之一塗層。
在另一實施例中，該微電子總成包含具有一第一表面之一第一基板以及暴露在該第一表面且具有一第一面之一第一薄導電元件。使一基底連接至該第一面之一第一導電凸出部延伸至遠離該第一面之一末端且在該基底與該末端之間界定一側壁。一介電材料層沿該第一基板之該第一表面延伸且具有一第二表面及遠離該第二表面之一第三表面。該介電材料層進一步具有界定形成於其中之一周邊之一第一開口。具有一第一部分之一金屬電鍍層沿該末端及該第一導電凸出部之該側壁之至少一部分延伸。該金屬電鍍層之一第二部分沿該介電材料層之一部分向外延伸且遠離該第一導電凸出部。一第一焊料塊係形成於該電鍍層之至少該第一部分上且朝向該第三表面延伸。
另一實施例係關於一種微電子總成，該微電子總成包含具有一第一表面之一基板、暴露在該第一表面上且界定一面之複數個第一導電墊，以及複數個第一金屬柱。各金屬柱界定具有一外周邊且連接至該等第一墊之一各自者之一基底。各金屬柱沿一側壁從該基底延伸至遠離該第一導電墊之末端。該總成進一步包含一第一介電材料層，該第一介電材料層具有一內表面、一外表面及複數個開口。該內表面沿該基板之該第一表面延伸，該外表面係遠離該基板。該等第一金屬柱之各自者凸出通過該等開口，使得該介電材料層接觸該等第一金屬柱之至少該等外側周邊。複數個可熔金屬塊接觸第一金屬柱之至少一些之末端且沿該等第一金屬柱之側壁延伸朝向該介電材料層之外表面。一微電子元件係承載於該基板上且係電氣連接至該等第一導電墊之至少一些。
另一實施例係關於一種微電子總成，該微電子總成包含具有一第一表面之一第一基板及暴露在該第一表面上且具有一第一面之一第一薄導電元件。具有一基底之一第一導電凸出部係連接至該第一面且延伸至遠離該第一面之一末端。一側壁係界定於該基底與該末端之間。該總成進一步包含一介電材料層，該介電材料層具有一第二表面及遠離該第二表面之一第三表面。該第二表面沿該第一基板之該第一表面延伸，且該介電材料層具有一第一開口，其具有形成於其中之一周邊。一第一焊料塊係形成於該第一導電凸出部上，該第一焊料塊沿該末端及該側壁之一部分延伸至佈置於該基底與該末端之間之一位置。該第一導電凸出部延伸通過該第一開口使得其周邊接觸該側壁之一部分。該焊料塊延伸朝向該介電材料層之該第三表面。
現參考圖式，其中相同參考符號用於類似特徵部，圖1及圖2展示微電子子總成12、14之堆疊式封裝10。該等微電子子總成藉由包含本文將進一步討論之組件之一或多個互連結構50而互相電接合且機械接合。
圖1之堆疊式封裝10包含一下部總成12及一上部總成14。應注意，如本文所使用，術語上部及下部，併同諸如水平或垂直、左或右及類似者之方向或定位之任何其他術語係參考圖式且參考一示例性使用模式。由於熟悉此項技術者將理解其他定位及定向，故本描述中出於清楚之目的而使用此等術語且該等術語並無限制性。下部基板16及上部基板18之各者具有各自下表面20、24及上表面22、26。該等上表面22、26大致上平行於其等之各自下表面20、24,且全部表面20、22、24、26大致上係平坦的。上部基板14及下部基板12之各者之一厚度係在各自上表面22、26與下表面20、24之間界定。此厚度在上部基板14與下部基板12之間可大體上相同或可變化。該厚度通常小於基板12、14之長度及寬度達足以給予該等基板12、14一充分薄、晶圓狀結構之一因數且落在熟悉此項技術者通常理解之一範圍內。
各總成12、14亦包含一各自微電子元件30、32。微電子元件30係展示成藉由覆晶結合而貼附至下部基板16，其中微電子元件30經翻轉使得其導電接觸件(未展示)面朝上表面22。接著使用導電凸出部34將該微電子元件貼附至基板16，該等導電凸出部34從其接觸件延伸且使用焊料塊36或另一導電結合材料而結合至形成於基板16上之第二導電凸出部38。可用於將微電子元件30連接至基板16之其他配置包含面向上式安裝，其中微電子元件30上之接觸件背對上表面26，使用黏著劑將微電子元件30結合至上表面26，並且使用引線將該微電子元件30之接觸件電連接至形成於基板16上之導電特徵部，諸如跡線或墊。微電子元件32係展示成以一類似方式貼附至基板18，且可替代地如上所述般附接。
圖1所展示之互連結構50包含一導電墊52，該導電墊52具有暴露在基板16之上表面22上之一面54。如本文所使用之術語「暴露在...」並非指將墊52之任何特定構件附接至基板16或在其之間之任何相對定位上。實際上，其指示導電結構可用於與一理論點接觸，該理論點在垂直於介電結構之表面之一方向上從介電結構之外側移動朝向該介電結構之表面。因此，暴露在一介電結構之一表面之一端子或其他導電結構可從此表面凸出；可與此表面齊平；或可相對於此表面內凹且透過介電質中之一孔或凹入部而暴露。可藉由在表面22上直接沈積或類似方法形成墊而將墊52貼附至基板16，或者只要面54保持暴露在表面22上，則可將其嵌入於基板16內使得面54與表面22齊平或置放在高於或低於該表面22之一高度處。在替代實施例中，互連結構50除一導電墊52之外或替代該導電墊52可包含一導電跡線或一導電跡線之一部分。
一導電支柱56係形成於導電墊52之面54之一部分上。如圖1可見，支柱56之基底58覆蓋面54之一部分且使其另一部分從基底58之周邊延伸且暴露在表面22上。支柱56亦界定遠離基底58延伸至支柱56之末端62之一邊緣表面60。儘管圖1展示一導電支柱，然而如熟悉此項技術者將理解，可使用形成一導電凸出部之替代結構，包含一接針、一柱或類似者。
互連結構50進一步包含一接觸墊64,該接觸墊64具有暴露在基板18之下表面24上之一面66。如同接觸墊52,墊64可嵌入於基板18中使得只要面66保持暴露於其上，則面66與下表面24齊平、在該下表面24上方或下方。可使用通過基板18形成之一導電通孔68而將墊64連接至形成於基板18之上表面26上之導電特徵部，諸如跡線或接線。在一替代實施例中，互連結構50可包含暴露在下表面24上代替墊64之一跡線或一跡線之一部分。
一焊料塊70係用於將支柱56機械及電氣地結合至墊64。在形成且組裝封裝10期間，焊料塊70最初可形成於支柱56或墊64上且接著在總成12、14對準在一起時回流以容許焊料塊70貼附至支柱56或墊64之另一者。一旦處於封裝10中之適當位置，焊料塊70便形成一上邊緣72及一下邊緣74。上邊緣72及下邊緣74之各者可形成為一單線或點或一表面。如圖1所展示，上邊緣72為沿圍繞墊64之表面24之一部分延伸的一表面。上邊緣72亦可取決於墊64之幾何形狀而形成接觸墊64之一表面或圍繞接觸表面24或遠離該表面24之墊之一圓形線。
本文揭示之結構及技術可幫助減小墊與連接該等墊之一焊料塊之間之一界面處之電遷移。電遷移可在互相接觸之兩個或多個金屬元件展現不同擴散速率之區域中造成多個問題。在此情形中，可在結合界面中發生空隙形成。亦即，可將一個金屬拉離另一金屬，在其等之間形成一間隙或開口。
當與包含連接兩個相對墊之一焊料塊之一結構相比較時，在互連結構50中使用支柱56或另一導電凸出部減小支柱56之末端62與墊64之間沿電流在其等之間行進之一線之距離。相應地，圖1之結構(其中支柱56及墊64二者係由銅形成)已展示出能有效減小引起一銅-焊料-銅互連結構中之空隙形成的電遷移。當在一電子互連結構中使用類似金屬(其中其等係由一第二金屬隔開)時，包含類似金屬之一金屬內(inner-metallic)化合物形成於第二金屬內。此金屬內化合物將從一類似金屬結構延伸朝向另一類似金屬結構。金屬內化合物形成係減小歸因於電遷移之空隙形成之一因素，因為金屬內化合物具有比焊料更慢之一電遷移速率。藉由減少結構內類似金屬至類似金屬之距離，金屬內化合物可形成為從一個類似金屬結構延伸至另一類似金屬結構。在圖1之實例中，其中墊64及支柱56係由銅形成且焊料塊70包含錫，該金屬內化合物可在比率上從例如Cu3 Sn變為Cu3 Sn5 。此外，本文所展示之互連結構可減小互連結構各處之類似金屬之濃度梯度，此已展示為減小電遷移之一驅動因素。一結構內之濃度梯度為在其處例如類似金屬之濃度在一結構內在空間上變化之濃度。柱56延伸至焊料塊70中增加銅在結構內之表面積，此進一步增加金屬內化合物在焊料塊70內之存在。金屬內化合物之此增加量之延伸可降低該結構內存在銅下之變化速率，得以進一步減小電遷移。
圖3至圖6所展示之圖形圖解說明上述現象。圖3及圖4展示銅在一互連結構中之一水平位置處之變化濃度，該互連結構在其垂直距離各處類似於圖1之互連結構。所展示之圖形對應於一互連結構50，其中墊52、64及支柱56係由銅形成且焊料塊70係由含錫之一焊料化合物形成。圖3展示該結構在無一電流流經其中時發生之一溫度(T0 )下時銅之濃度，其指示在該溫度條件下焊料塊70內無銅。圖4展示存在一電流時在一均衡溫度下在相同結構各處之銅之濃度。圖4之圖形展示焊料塊70內存在歸因於金屬內化合物形成而存在之一銅濃度。金屬內化合物係展示為從支柱56之末端62延伸至墊52之面54。沿末端62及面54二者之銅之濃度亦展示沿其處大體上無空隙形成。此外，圖4之圖形展示存在支柱56可降低通過互連50之銅之濃度之變化速率。表示銅濃度之線例如在恰鄰近墊64之焊料塊70內之區域中突然改變方向。相反地，表示銅濃度之線之方向變化在鄰近支柱56之焊料塊70之區域中較不顯著得多。應注意該等圖形僅係示例而圖解說明本文所討論之行為，其可能未按比例繪製或精確代表圖式中所展示之特定結構之行為。
圖5及圖6所展示之圖形展示通過在兩個接觸墊152與164之間佈置一焊料塊170之一先前互連結構之銅之濃度，其中墊152、164之間之距離190與圖3及圖4之墊52、64之間之距離90大體上相同。圖5展示在T0 下結構內之銅之濃度，指示該條件下焊料塊170內無銅。圖6展示在平衡溫度下該結構內之銅濃度且展示焊料塊170內歸因於金屬內化合物形成之一些銅濃度，但是該濃度未延伸通過焊料塊170。此導致形成導致破裂之空隙186。
相應地，存在具有延伸至焊料塊70中且朝向該焊料塊之另一側上之一類似金屬結構之一末端62的一支柱56，諸如墊64可減少歸因於電遷移之空隙形成之可能性。此在延伸通過大於通過其可預期延伸一金屬內化合物之距離的一整體距離90之結構中尤為真實。在支柱56及墊64係由銅形成且焊料塊70包含錫之一實施例中，末端62與面66之間之距離92可在約10%與50%之距離90之間。應注意雖然圖3中距離90係界定在基板18之下表面24與介電層40之外表面之間，但是距離90係界定在圍繞墊52、64之任何種類之結構之主表面之間。
在一實施例中，下邊緣74在支柱56之邊緣表面60之一部分周圍形成延伸至焊料塊70中之一圓形線或環形表面。此外，下邊緣74係與墊52隔開使得焊料塊70不會直接接觸墊52之任何部分，包含在支柱56之基底58周圍保持暴露之部分。可對支柱56，尤其對靠近基底58之邊緣表面60應用可防止焊料塊70沿邊緣表面60芯吸成與面54或墊52接觸的一處理。此類處理可包含氧化或類似處理。類似地，可在邊緣表面60周圍塗覆抗焊料流動之一層材料。
在另一實施例中，焊料塊70之下邊緣74係藉由在墊52之面54上延伸且延伸成與鄰近基底58之邊緣表面68之至少一部分接觸之一介電層40而固定成遠離面54。在此實施例中，容許焊料塊70流動而與包含表面42之介電層40接觸，使得下邊緣74可沿其延伸成與墊52成一隔開關係。
藉由保持焊料塊70遠離墊52，亦可減小歸因於電遷移之空隙形成之可能性。此類型之一互連結構藉由降低焊料塊70內之電流之濃度而減小電遷移。如圖7及圖8所展示，行進通過互連結構50之一電流對角地沿多個線從該結構之一末端上之一點移動至該結構之另一末端上與原始點大體上橫向相對之一點。此意指從圖7之墊252行進之電流將沿由線296表示且流過焊料塊270之一路徑移動且返回至支柱256中。接著該電流在到達墊264之前離開支柱256且重新進入焊料塊270。此路徑導致靠近支柱256之基底258之焊料塊270之部分中之電流濃度。電流濃度係可造成導致互連故障之空隙形成之電遷移之另一驅動力。
如圖8所展示，藉由在焊料塊70之下邊緣74與暴露墊52之間插入介電層40，將不會有電流從墊52中行進離開。事實上，電流將沿僅進入焊料塊70一次且展示於末端62與焊料塊70之間之界面中之一線96行進。此可減小電流濃度梯度達約1.25與1.75之間之一因數，此可繼而減小空隙形成之可能性。一類似路徑將在其中只要焊料塊70係藉由介電層40而固定成遠離墊52，則焊料塊70沿介電層40之一部分向外延伸之一結構中觀察到。
圖1中介電層40係展示成沿基板16之上表面22之一主要部分延伸。此部分包含未被其他接觸元件穿透之上表面22之全部。或者，介電層40可形成於圍繞互連結構50中使用之任何支柱56之部分中，該部分延伸成從其處遠離通過足以保持焊料塊70遠離相關聯接觸墊52之一距離。在此一實施例中，介電層部分可與接觸墊大體上相同大小及形狀或稍大，以便可靠地覆蓋墊之任何其他暴露部分。
在一實施例中，介電層40在覆蓋墊52之區域中具有一厚度42，使得焊料塊70之下末端74離其保持隔開一距離。此距離可包含整體材料厚度中之任何容差之補償以確保不存在引起墊52之面54之非希望之暴露之孔和間隙。厚度42可在約10 μm與30 μm之間。在此一實施例中，介電層40將具有任何互連支柱56通過其而延伸之一孔44或複數個孔44。孔44形成可接觸從基底58向上延伸之邊緣表面60之一部分之一內表面46。
如圖11所展示，可在包含末端462及在介電層440上暴露之邊緣表面460之一部分之支柱456上塗覆一電鍍層488。電鍍層488可幫助確保支柱456與焊料塊470之間之一可靠互連。
圖2展示包含具有互連結構50之複數個微電子子總成12、14之一堆疊總成10。除圖2之封裝10中之互連結構50包含從墊64之面66延伸之一導電柱76之外，圖2所展示之封裝10大體上類似於圖1所展示之封裝。柱包含貼附至面66上之基底78，以及延伸至遠離面66之一末端82之一邊緣表面80。可沿基板18之下表面24形成覆蓋面66之任何部分及暴露在基底78之周邊之外側之墊64的一第二介電層41。如同介電層40，介電層41使焊料塊70之上邊緣72保持接觸墊64，此減小靠近上邊緣72之焊料塊70之電流濃度。如上文相對於介電層40所述，此進一步減小互連結構50內之空隙形成之可能性。
圖9及圖10圖解說明一互連結構中包含之一焊料塊內由於使該焊料塊保持不與一相關聯導電墊接觸所致之電流濃度之減小。圖9展示包含其上形成一支柱356之一墊352的一互連結構350。一焊料塊370將支柱356及墊552附接至一上部墊364及形成於其上之一柱376。接著由線396表示之電流從接觸墊352流出且流入焊料塊370中，接著往回流入支柱356中且接著回至焊料塊370中。接著電流(線396)在往回流入焊料塊370中之前流入柱376中且最後流入墊364中。此電流路徑396導致焊料塊370內在焊料塊570之上邊緣372及下邊緣374之區域中有增加之電流濃度。如圖10所展示，介電層40、41之納入防止電流(線96)流過靠近其上邊緣72或下邊緣74之焊料塊70，此減小各區域中之電流濃度梯度達約1.25與1.75之間之一因數。此可導致因焊料塊70之各末端上之界面中因空隙形成而使互連失效之可能性降低。
另外，如上文參考圖1所述，在總成14中包含柱76可進一步減少互連結構70內之類似金屬與類似金屬之距離。在圖2之結構中，此距離係由末端至末端距離94表示。在距離94為距離90之約10%與30%之間時，距離94可引起從末端62延伸至末端82之一金屬內化合物之形成。或者，柱76可為任何導電凸出部，諸如一支柱、一接針或類似者。藉由在總成12、14二者上包含導電凸出部，可在覆蓋一較大整體距離90時達成一連接，該連接在於鄰近互連結構50之間達成比如圖1所展示使用一支柱至墊配置時可產生之間距更細微之一間距時產生一可靠金屬內化合物。此外，藉由在墊64上形成一介電層41，與簡單具有在其處形成焊料快70之一墊64相比較，一較低電流濃度是可能的。藉由在互連結構50中包含柱76，亦可進一步減小濃度梯度促成電遷移。在此一結構中，亦可在柱76之區域中達成支柱56之區域中之銅濃度互連50之變化速率之減小，藉此移除焊料塊70之兩末端處之銅濃度之任何突然變化。
圖1及圖2所展示包含介電層40、41及其等之相關結構之互連結構50可用於除圖1及圖2所展示之堆疊型子總成配置之外之其他連接類型。舉例而言，其等可在覆晶結合(諸如圖1及圖2中微電子元件30與基板16之間所展示)中，以及在面向上式或覆晶式結合中將諸如微電子子總成12之一微電子子總成連接至另一基板時使用。此外，諸如總成14之一總成可在基板18之上表面26上進一步包含一額外接觸墊，該基板18在其上以使用諸如圖1或圖2所展示之一互連結構而使支柱56及介電層40連接至一額外微電子總成的方式形成一支柱及介電層。此配置可在一堆疊型封裝內繼續附接其他總成。
儘管本文已參考特定實施例描述本發明，然而應理解此等實施例僅示例本發明之原理及應用。因此，應理解可對示例性實施例作出眾多修改且可在不脫離如隨附申請專利範圍所界定之本發明之精神及範疇下設計其他配置。
10．．．微電子總成堆疊式封裝
12．．．微電子子總成
14．．．微電子子總成
16．．．下部基板
18．．．上部基板
20．．．下表面
22．．．上表面
24．．．下表面
26．．．上表面
30．．．微電子元件
32．．．微電子元件
34．．．導電凸出部
36．．．焊料塊
38．．．第二導電凸出部
40．．．介電層
41．．．介電層
42．．．表面
44．．．孔
46．．．內表面
50．．．互連結構
52．．．導電墊
54．．．基板之面
56．．．導電支柱
58．．．基底
60．．．邊緣表面
62．．．支柱末端
64．．．接觸墊
66．．．基板之面
68．．．通孔
70．．．焊料塊
72．．．焊料塊上邊緣
74．．．焊料塊下邊緣
76．．．導電柱
78．．．基底
80．．．邊緣表面
82．．．末端
90．．．墊距離
92．．．末端與面之距離
94．．．末端至末端之距離
96．．．電流路徑
152．．．墊
164．．．墊
170．．．焊料塊
186．．．空隙
190．．．墊間距離
252．．．墊
256．．．支柱
258．．．基底
270．．．焊料塊
296．．．電流路徑
350．．．互連結構
352．．．墊
356．．．支柱
364．．．上部墊
370．．．焊料塊
372．．．上邊緣
374．．．下邊緣
376．．．柱
396．．．電流路徑
440．．．介電層
456．．．支柱
460．．．邊緣表面
462．．．末端
470．．．焊料塊
488．．．電鍍層
552．．．墊
570．．．焊料塊
圖1展示包含根據本發明之一實施例之一互連結構之封裝式微電子元件的一堆疊總成；
圖2展示包含根據本發明之另一實施例之一互連結構之封裝式微電子元件的一堆疊總成；
圖3展示圖解說明在一第一條件下根據圖1之實施例之一互連結構之特性的一圖；
圖4展示圖解說明在一第二條件下根據圖1之實施例之一互連結構之特性的一圖；
圖5展示圖解說明在一第一條件下一先前技術互連結構之特性的一圖；
圖6展示圖解說明在一第二條件下圖5之該先前技術互連結構之特性的一圖；
圖7展示根據一替代實施例之一互連結構的一組件；
圖8展示根據另一替代實施例之一互連結構的一組件；
圖9展示根據一替代實施例之一互連結構的一組件；
圖10展示根據另一替代例之一互連結構的一組件；及
圖11展示包含一經沈積之金屬層之一互連結構的一組件。
12．．．微電子子總成
14．．．微電子子總成
18．．．上部基板
20．．．下表面
22．．．上表面
24．．．下表面
26．．．上表面
30．．．微電子元件
32．．．微電子元件
34．．．導電凸出部
36．．．焊料塊
38．．．第二導電凸出部
40．．．介電層
41．．．介電層
50．．．互連結構
52．．．導電墊
54．．．基板之面
56．．．導電支柱
58．．．基底
60．．．邊緣表面
62．．．支柱末端
64．．．接觸墊
66．．．基板之面
68．．．通孔
70．．．焊料塊
72．．．焊料塊上邊緣
74．．．焊料塊下邊緣

Claims (28)

  1. 一種微電子總成，其包括：一第一表面；一第一薄導電元件，其暴露在該第一表面且具有包括第一區及第二區之一第一面；一第一導電凸出部，其具有連接至該第一面之該第一區並覆蓋該第一區的一基底並且延伸至遠離該基底之一第一末端；一第一介電材料層，其覆蓋該第一薄導電元件之該第二區且接觸該第一導電凸出部之至少該基底；及一第一基板，其具有一第二表面及自該第二表面延伸出之一第二導電凸出部；及一第一可熔金屬塊，其將該第一導電凸出部連接至該第二導電凸出部使得該第一面係定向成朝向該第二表面，其中該第一可熔金屬塊沿該第一導電凸出部之一邊緣延伸朝向該第一介電材料層，其中該第一導電凸出部之該基底具有一周邊，其中該第一面之該第二區係暴露在該第一導電凸出部之該基底之該周邊之外側，其中該第一導電凸出部之該基底包含自該第一末端延伸之一筆直部分，以及自該基底之一外周邊延伸之一過渡部分，該過渡部分沿其之一橫截面剖面呈弓形，且其中該第一介電材料層覆蓋該過渡部分。
  2. 如請求項1之微電子總成，其中該第一表面係形成於一基板上且其中該第二表面係形成於一微電子元件上。
  3. 如請求項1之微電子總成，其中該第一表面係形成於一第二基板上且該第一基板進一步具有貼附於其上的一微電子元件。
  4. 如請求項1之微電子總成，其中該第一可熔金屬塊接觸該第一介電材料層。
  5. 如請求項1之微電子總成，其中該第一介電材料層覆蓋該第一表面之至少一部分。
  6. 如請求項1之微電子總成，其中該第二導電凸出部包含遠離該第二表面之一末端，且其中該第一導電凸出部之該末端與該第二導電凸出部之該末端係以在其等間界定一間隙之一第一距離而隔開，且其中該第一可熔金屬塊在該間隙內延伸。
  7. 如請求項6之微電子總成，其中該第一距離在10μm與30μm之間。
  8. 如請求項1之微電子總成，其進一步包含暴露在該第一表面上之複數個薄導電元件，該複數個薄導電元件各具有具有第一區及第二區之一面；以及複數個第一導電凸出部，其各連接至該複數個薄導電元件之一各自者之該第一面之該第一區且延伸至遠離該第一區之一第一末端；以及複數個第二導電凸出部，其各自該第二表面延伸出；其中該第一介電材料層覆蓋該等薄導電元件之該等第二區，且複數個第一可熔金屬塊將該等第一導電凸出部之各自者連接至該等第二導電凸出部之各自者，其中該 各自第一可熔金屬塊在該各自第一導電凸出部之一部分上延伸朝向該第一介電材料層。
  9. 如請求項1之微電子總成，其中該第一介電材料層中之第一開口界定一內表面，且其中該內表面沿該第一導電凸出部之一部分延伸且接觸該第一導電凸出部的至少該部分。
  10. 如請求項9之微電子總成，其中該第一介電材料層具有在垂直於該第一薄導電元件之該第一面之一方向上延伸之一厚度，且其中該厚度在約10μm與30μm之間。
  11. 如請求項9之微電子總成，其中該第一介電材料層具有在垂直於該第一薄導電元件之該第一面之一方向上延伸之一厚度，且其中該厚度為該第一導電凸出部之一高度之約20%至50%。
  12. 如請求項1之微電子總成，其中該第一導電凸出部界定一側壁，該側壁沿其之一橫截面剖面呈筆直。
  13. 如請求項12之微電子總成，其中一角係形成於該第一薄導電元件之該第一面與該第一導電凸出部之該側壁之間，該角係定位成沿該第一導電凸出部之該基底之外周邊，且其中該第一介電材料層覆蓋該角。
  14. 如請求項1之微電子總成，其中該第一導電凸出部之該基底係藉由一層導電金屬而連接至該第一薄導電元件，該層導電金屬具有與該第一導電凸出部之該基底之一外周邊對準之一外表面，且其中該第一介電材料層覆蓋該層導電金屬之該外表面。
  15. 如請求項1之微電子總成，其進一步包含：一第二薄導電元件，其暴露在該第二表面上且具有由第一區及第二區組成之一第二面，且其中該第二導電凸出部具有界定一周邊且連接至該第二薄導電元件之該第一區並覆蓋該第一區的一第二基底，以及遠離該第二基底之一末端部分；覆蓋該第二薄導電元件之該第二區之一第二介電材料層。
  16. 如請求項15之微電子總成，其中該第一可熔金屬塊在該第二導電凸出部之一部分上延伸朝向該第二介電材料層。
  17. 如請求項1之微電子總成，其中該第一導電凸出部界定一側壁，且其中一經沈積之金屬層係形成於該第一導電凸出部之該末端及其之該側壁之至少一部分上。
  18. 如請求項17之微電子總成，其中該第一介電材料層包含平行於該第一表面之一外表面，且進一步形成電鍍層，其中該電鍍層之一部分沿該外表面向外延伸且遠離該第一導電凸出部。
  19. 如請求項1之微電子總成，其中該第一薄導電元件係一圓形墊。
  20. 如請求項19之微電子總成，進一步包含形成於該第一基板上且從該圓形墊延伸之導電跡線。
  21. 一種微電子總成，其包括：一第一表面； 一第一薄導電元件，其暴露在該第一表面上且具有由第一區及第二區組成之一第一面；一第一導電凸出部，其連接至該第一面之該第一區並覆蓋該第一區並且延伸至遠離該第一區之一第一末端，且沿其之一部分形成具有遠離該第一薄導電元件之一第一邊緣之一障壁；一第二表面，其具有自該第二表延伸出之一第二導電凸出部；及一第一可熔金屬塊，其將該第一導電凸出部連接至該第二導電凸出部使得該第一表面係定向成朝向一第一基板之第二表面，其中該第一可熔金屬塊沿該第一導電凸出部之一部分延伸至朝向該障壁之該第一邊緣之一位置，該障壁係佈置於該第一薄導電元件與該第一可熔金屬塊之間，其中該第一導電凸出部之該基底具有一周邊，其中該第一面之該第二區係暴露在該第一導電凸出部之該基底之該周邊之外側，其中該第一導電凸出部之該基底包含自該第一末端延伸之一筆直部分，以及自該基底之一外周邊延伸之一過渡部分，該過渡部分沿其之一橫截面剖面呈弓形，且其中該第一介電材料層覆蓋該過渡部分。
  22. 如請求項21之微電子總成，其中該障壁係形成於該第一導電凸出部中之一表面處理層。
  23. 如請求項22之微電子總成，其中該表面處理層係藉由氧化而形成。
  24. 如請求項22之微電子總成，其中該表面處理層係塗覆於該第一導電凸出部之一表面上之一塗層。
  25. 如請求項21之微電子總成，其中該障壁係一層介電材料。
  26. 如請求項25之微電子總成，其中該層介電材料覆蓋該第一薄導電元件之該第二區。
  27. 一種微電子總成，其包括：一第一子總成，其包含：具有一第一表面之一第一基板；複數個第一導電墊，其各具有暴露於該第一表面上之一第一面；複數個第一凸出部，其各界定具有一周邊且連接至該等第一導電墊之一各自者之一基底，該等第一凸出部從該等各自第一導電墊延伸出，其中該第一導電墊之該等第一面之暴露部分係界定於該等第一凸出部之該等基底之該等周邊之外側；及一第一介電材料層，其覆蓋該等第一導電墊之該等第一面之該等暴露部分，且界定該等第一凸出部之各自者經過其之複數個開口，該第一介電材料層接觸該等第一凸出部之至少該等周邊且界定一第一外表面；一第二子總成，其包含具有一第二表面之一第二基板、暴露在該第二表面上之複數個第二導電墊及複數個第二凸出部，該等第二凸出部各具有連接至該等第二導電墊之一各自者之一基底且從該基底延伸出；及 複數個可熔金屬塊，其等將該複數個第一凸出部各自接合至該複數個第二凸出部之各自者，使得該第二基板之該第二表面係定向成朝向該第一基板之該第一面，其中該等可熔金屬塊覆蓋延伸至該第一介電材料層之該第一外表面之該等第一凸出部之至少部分，其中該等第一凸出部之該等基底包含自該第一末端延伸之一筆直部分，以及自該基底之一外周邊延伸之一過渡部分，該過渡部分沿其之一橫截面剖面呈弓形，且其中該第一介電材料層覆蓋該過渡部分。
  28. 一種微電子總成，其包括：具有一第一表面之一第一基板；暴露在該第一表面且具有一第一面之一第一薄導電元件；具有一基底之一第一導電凸出部，該基底連接至該第一面且延伸至遠離該第一面之一第一末端，一側壁係界定於該基底與該末端之間；一介電材料層，其具有一第二表面及遠離該第二表面之一第三表面，該第二表面沿該第一基板之該第一表面延伸，該介電材料層具有界定形成於其中之一周邊之一第一開口；一金屬電鍍層，其具有沿該第一末端及該第一導電凸出部之該側壁之至少一部分延伸之一第一部分，以及沿該介電材料層之一部分向外延伸且遠離該第一導電凸出部之一第二部分；及 一第一焊料塊，其形成於該金屬電鍍層之至少該第一部分上且延伸朝向該第三表面，其中該第一導電凸出部之該基底具有一周邊，其中該第一面之該第二區係暴露在該第一導電凸出部之該基底之該周邊之外側，其中該第一導電凸出部之該基底包含自該第一末端延伸之一筆直部分，以及自該基底之一外周邊延伸之一過渡部分，該過渡部分沿其之一橫截面剖面呈弓形，且其中該第一介電材料層覆蓋該過渡部分。
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