TWI590404B - 電子裝置 - Google Patents

電子裝置 Download PDF

Info

Publication number
TWI590404B
TWI590404B TW103128768A TW103128768A TWI590404B TW I590404 B TWI590404 B TW I590404B TW 103128768 A TW103128768 A TW 103128768A TW 103128768 A TW103128768 A TW 103128768A TW I590404 B TWI590404 B TW I590404B
Authority
TW
Taiwan
Prior art keywords
pad
bump
solder
bumps
component
Prior art date
Application number
TW103128768A
Other languages
English (en)
Other versions
TW201508888A (zh
Inventor
石井克実
山浦正志
Original Assignee
村田製作所股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 村田製作所股份有限公司 filed Critical 村田製作所股份有限公司
Publication of TW201508888A publication Critical patent/TW201508888A/zh
Application granted granted Critical
Publication of TWI590404B publication Critical patent/TWI590404B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/14155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17519—Bump connectors having different functions including bump connectors providing primarily thermal dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding

Description

電子裝置
本發明係關於一種電子裝置。
作為於構裝基板上構裝晶片之手法，已知有覆晶構裝。於覆晶構裝中，係於晶片表面設置作為突起狀之端子之凸塊，且將該凸塊焊接於構裝基板上之焊墊。藉由此種構裝方法，相比於在晶片外周設置端子之情形，可減小包含晶片之電子裝置之面積，或者可減少因配線電感所致之損耗。
於此種覆晶構裝中，提出除了使用截面大致圓狀之一般的凸塊(以下亦稱為「支柱凸塊」)外，還使用截面積大於支柱凸塊且截面大致橢圓狀之凸塊(以下亦稱為「條狀凸塊」)，以提高經由凸塊之散熱性(例如，專利文獻1)。
[先前技術文獻]
[專利文獻]
[專利文獻1]國際公開第2005/034237號
圖13係表示支柱凸塊與條狀凸塊混合存在之晶片之一例之 圖。於晶片1300設有支柱凸塊1301(1301a、1301b)及條狀凸塊1302。圖14係晶片1300之X-X'線之剖面圖。條狀凸塊1302之截面積大於支柱凸塊1301，故而如圖14所示，焊料1401熔融時因表面張力作用而鼓起之焊料1401之中央附近之高度有時變得高於支柱凸塊1301之焊料1400(1400a、1400b)。此外，條狀凸塊1302有由於散熱之目的而被設於電晶體單元(transistor cell)之情形。於該情形時，因電晶體單元之厚度不同，自晶片1300之表面起之條狀凸塊1302之高度有時會變得高於支柱凸塊1301之高度。若條狀凸塊1302之高度變高，則向凸塊轉印焊料時，轉印至條狀凸塊1302之焊料之高度有時會變得高於轉印至支柱凸塊1301之焊料之高度。
圖15係表示已將晶片1300構裝於構裝基板1500之狀態之一例的圖。於構裝基板1500設有與支柱凸塊1301a、1301b對應之焊墊1501a、1501b、及與條狀凸塊1302對應之焊墊1502。於圖15所示之例中，條狀凸塊1302雖利用焊料1401而與焊墊1502良好地連接，但支柱凸塊1301a、1301b與焊墊1501a、1501b之連接變得不良。此種連接不良係由於焊料1400a、1400b之高度、與焊料1401之高度之差異而引起。
本發明係鑒於此種狀況研究而成者，其目的在於在使用第1凸塊、與截面積大於第1凸塊之第2凸塊進行覆晶構裝之電子裝置中，提昇凸塊與焊墊之連接性。
本發明之一態樣之電子裝置具備構裝零件、及構裝有構裝零件之被構裝零件，構裝零件於與被構裝零件對向之面具備第1凸塊、及該對向之面方向之截面積大於第1凸塊的第2凸塊，被構裝零件於與構裝零件對向之面具備與第1凸塊焊接之第1焊墊、及與第2凸塊焊接之第2焊墊，且第2焊墊之面積相對於第2凸塊之截面積之比大於第1焊墊之面積相對於第1凸塊之截面積之比。
根據本發明，於使用第1凸塊、及截面積大於第1凸塊之第2凸塊進行覆晶構裝之電子裝置中，可提昇凸塊與焊墊之連接性。
100‧‧‧電子裝置
101、1300‧‧‧晶片
102、1500‧‧‧構裝基板
103‧‧‧密封樹脂
200、400‧‧‧表面
210、1301‧‧‧凸塊(支柱凸塊)
211、1302‧‧‧凸塊(條狀凸塊)
300、301、1400、1401‧‧‧焊料
410、411、1501、1502‧‧‧焊墊
1200、1200a~1200n‧‧‧定位機構(阻焊劑)
1210、1210a~1210h‧‧‧定位機構(開口部)
圖1係表示本發明之一實施形態之電子裝置之外觀之一例的圖。
圖2係表示晶片上之凸塊之配置之一例的圖。
圖3係圖2之A-A'線之剖面圖。
圖4係表示構裝基板上之焊墊之配置之一例的圖。
圖5係說明於構裝基板構裝有晶片之狀態之一例的圖。
圖6係圖5之A-A'線之剖面圖。
圖7係表示構裝狀態與構裝前狀態之焊料之外觀之一例的圖。
圖8係表示推斷之構裝前狀態之焊料之形狀之一例的圖。
圖9係表示構裝狀態之焊料之形狀之一例的圖。
圖10係表示將構裝狀態之焊料分割成3個構造之一例的圖。
圖11係表示與焊料之高度相應之焊墊面積之一例的圖。
圖12A係表示設於焊墊之定位機構之一例的圖。
圖12B係表示設於焊墊之定位機構之另一例的圖。
圖12C係表示設於焊墊之定位機構之另一例的圖。
圖12D係表示設於焊墊之定位機構之另一例的圖。
圖12E係表示設於焊墊之定位機構之另一例的圖。
圖12F係表示考慮了焊墊位置後配置之定位機構之一例的圖。
圖13係表示支柱凸塊與條狀凸塊混合存在之晶片之一例的圖。
圖14係晶片之X-X'線之剖面圖。
圖15係表示已將晶片構裝於構裝基板之狀態之一例的圖。
以下，參照圖式對本發明之一實施形態進行說明。圖1係表示本發明之一實施形態之電子裝置之外觀之一例的圖。電子裝置100係將構裝零件構裝於被構裝零件上而構成。於圖1所示之例中，電子裝置100具備晶片101作為構裝零件，且具備構裝基板102作為被構裝零件，晶片101與構裝基板102之間係藉由密封樹脂103而被密封。
圖2係表示晶片101上之凸塊之配置之一例的圖。此外，圖3係圖2之A-A'線之剖面圖。表面200係與構裝基板102對向之面。於該表面200以自表面200突出之方式形成有複數之凸塊。具體而言，於晶片101除了設有截面大致圓狀之凸塊(以下亦稱為「支柱凸塊」)210(210a、210b)外，還設有截面大致橢圓狀之凸塊(以下亦稱為「條狀凸塊」)211。支柱凸塊210(第1凸塊)與條狀凸塊211(第2凸塊)之寬度(圖2之上下方向)大致相同，相對於此，長度(圖2之左右方向)係以條狀凸塊211較為長。即，於表面200之截面積亦為條狀凸塊211大於支柱凸塊210。又，只要條狀凸塊211之截面積大於支柱凸塊210之截面積，則凸塊之形狀並不限於圖2所示者。
支柱凸塊210及條狀凸塊211係用於將晶片101內之電路與外部電性連接、或將晶片101產生之熱散熱者，例如使用銅(Cu)或金(Au)等形成。於支柱凸塊210(210a、210b)之前端形成有用於連接於構裝基板102上之焊墊之焊料300(300a、300b)。同樣地，於條狀凸塊211之前端亦形成有焊料301。
條狀凸塊211係用於例如降低線路具有之阻抗、或提昇散熱性。具體而言，於異質接合雙極性電晶體等電晶體單元之上，有時會設置 條狀凸塊211用於散熱。該情形時，如圖3所示，因電晶體單元之厚度不同，晶片101之表面200至條狀凸塊211之高度有時會較支柱凸塊210之高度高出例如4~6μm左右。因此，為使晶片200之表面至焊料之前端之高度變得相同，亦可向支柱凸塊210及條狀凸塊211轉印焊料。
圖4係表示構裝基板102上之焊墊之配置之一例的圖。構裝基板102為例如作為絕緣性基板之陶瓷基板或印刷基板(PCB：Printed Circuit Board)。表面400係與晶片101對向之面。於該表面400設有與晶片101之凸塊焊接之複數之焊墊。具體而言，如圖4所示，設有與晶片101之支柱凸塊210a、210b焊接之焊墊410a、410b(第1焊墊)。同樣地，設有與晶片101之條狀凸塊211焊接之焊墊411(第2焊墊)。焊墊410、411為例如經實施鍍鎳(Ni)、鍍鈀(Pa)、及鍍金(Au)者。又，與條狀凸塊211焊接之焊墊411係連接於例如接地電位(GROUND)。
圖5係對已將晶片101構裝於構裝基板102之狀態之一例進行說明的圖。於圖5中，以虛線圖示設於晶片101之凸塊。如圖5所示，焊墊410、411分別為大於凸塊210、211之截面積之大小。作為一例，可將支柱凸塊210之半徑設為75μm，將焊墊410之半徑設為85μm。該情形時，焊墊410之面積相對於支柱凸塊210之截面積之比為約1.3倍。相對於此，可將焊墊411之面積相對於條狀凸塊211之截面積之比設為例如2倍之程度。即，焊墊411之面積相對於條狀凸塊211之截面積之比，大於焊墊410之面積相對於支柱凸塊210之截面積之比。
圖6係圖5之A-A'線之剖面圖。如上述般，焊墊411之面積相對於條狀凸塊211之截面積之比變得相對較大，故而形成於條狀凸塊211之焊料301之塗佈擴散變得較形成於支柱凸塊210之焊料300大。藉此，與凸塊和焊墊之面積之比對於支柱凸塊210及條狀凸塊211而言程度相同之情形相比，條狀凸塊211之隱沒量變大，支柱凸塊210與焊墊410之連接性提 昇。
參照圖7~圖11，說明用於決定焊接有條狀凸塊211之焊墊411之大小之模擬之一例。圖7係表示已將晶片101構裝於構裝基板102之狀態(構裝狀態)、及構裝前之狀態(構裝前狀態)下之焊料300之外觀之一例的圖。此處，作為一例，將支柱凸塊210之截面之半徑(支柱半徑：r1)設為37.5μm，將焊墊410之半徑(焊墊半徑r2)設為42.5μm，將構裝狀態下之焊料300之高度(焊料厚：h1)設為14μm。於構裝狀態下，若焊料300塗佈擴散至焊墊410之整個表面，焊料300之形狀便成為圖7之左側所示者。該情形時之焊墊410之面積相對於支柱凸塊之截面積之比為約1.3。若於該條件下，計算構裝狀態之焊料300(圓錐台)之體積則為70463μm3。然後，若基於該體積，求出焊料300之構裝前狀態下之高度(鍍敷厚：t)，則為15.9μm。
圖8係表示自構裝前狀態之焊料300之形狀推斷出的構裝前狀態之焊料301之形狀之一例的圖。又，為簡化模擬，凸塊之每單位面積形成之焊料之量設為焊料300、301相同。此外，焊料300、301之短邊方向之長度(寬度)相同(r1×2)。此外，作為一例，將自條狀凸塊211之長邊方向除去兩端(r1×2)後之長度(中央長度=d)設為99.5μm。若將焊料301之構裝前狀態之高度(鍍敷厚：t)設為與焊料300相同，則構裝前狀態之焊料301與條狀凸塊211接觸之面之面積(條狀面積)變成11880μm2，體積變成189487μm3。
圖9係表示構裝狀態之焊料301之形狀之一例的圖。若於構裝狀態下，焊料301塗佈擴散至焊墊411之整個表面，則焊料301之形狀變成圖9所示者。於該形狀下，將焊料301之體積設為189487μm3，求出焊墊411之面積。圖10係表示將構裝狀態之焊料301分割成3個構造之一例之圖。左右之構造分別為將上表面之半徑r1、下表面之半徑(焊墊半徑)r3 之圓錐台一分為二者。此外，中央之構造變成上表面係橫向長度d、縱向長度r1×2、下表面係橫向長度d、縱向長度(焊墊寬度)r3×2之角錐台。
圖11係表示基於以上之條件算出之與焊料301之高度(焊料厚：h2)相應之焊墊411之面積(焊墊面積)。於焊料301之高度(焊料厚：h2)與焊料300之高度(焊料厚：h1)為相同之14μm的情形時，焊墊411之面積(焊墊面積)為15246μm2。該情形時，焊墊411之面積(焊墊面積)相對於條狀凸塊211之截面積(條狀面積)之比(面積比)為約1.3。
實際上，如上述般，晶片101之表面200至條狀凸塊211之高度有時亦高於支柱凸塊210之高度。例如，若將該高度之差設為4μm，則焊料301之高度(焊料厚：h2)以該差之大小變低。即，本模擬中焊料301之高度(焊料厚：h2)成為10μm。於該情形時，焊墊411之面積(焊墊面積)為26873μm2，面積比為約2.3。即，焊墊411之面積相對於條狀凸塊211之截面積之比，變得大於焊墊410之面積相對於支柱凸塊210之截面積之比。
如此，以焊墊411之面積相對於條狀凸塊211之截面積之比大於焊墊410之面積相對於支柱凸塊210之截面積之比的方式形成焊墊411，藉此條狀凸塊211之隱沒量變大，可提昇支柱凸塊210與焊墊410之連接性。
其次，參照圖12A~圖12F，針對定位機構進行說明，該定位機構係用於將條狀凸塊211之移動限制於焊墊411之特定範圍。
圖12A係表示設於焊墊411之定位機構之一例之圖。如圖12A所示，於焊墊411，在與長邊方向之側面平行之位置(特定範圍之周圍)設有定位機構1200(1200a、1200b)。定位機構1200係藉由例如阻焊劑(抗蝕劑)而形成於焊墊411之表面上。如圖12A之下方所示，藉由定位機構 1200而於圖12A之左右方向限制焊料301之流動，藉此可將條狀凸塊211之移動限制於定位機構1200a、1200b之間(特定範圍)。又，定位機構1200a、1200b形成用於使焊料301塗佈擴散之流路(例如圖12A之上下方向)。藉此，與圖6所示之例同樣地，條狀凸塊211之隱沒量變大，可提昇支柱凸塊210與焊墊410之連接性。
圖12B係表示設於焊墊411之定位機構之另一例之圖。於圖12B所示之構成中，代替圖12A所示之定位機構1200b，而設有定位機構1200c、1200d。而且，於定位機構1200c、1200d之間形成有間隙1201(流路)。藉此，與圖12A之情形同樣地，條狀凸塊211之移動被限制於定位機構1200a、1200c、1200d之間(特定範圍)。進而，如圖12B之下方所示，焊料301亦自定位機構1200c、1200d之間之間隙1201塗佈擴散，故而可增大焊料301之塗佈擴散面積。
圖12C係表示設於焊墊411之定位機構之另一例之圖。於圖12C所示之構成中，代替圖12B所示之定位機構1200a，而設有定位機構1200e、1200f。而且，於定位機構1200e、1200f之間形成有間隙1202(流路)。藉此，與圖12A之情形同樣地，條狀凸塊211之移動被限制於定位機構1200c~1200f之間(特定範圍)。進而，如圖12C之下方所示，焊料301除了自定位機構1200c、1200d之間之間隙1201塗佈擴散，亦自定位機構1200e、1200f之間之間隙1202塗佈擴散，藉此可增大焊料301之塗佈擴散面積。
圖12D係表示設於焊墊411之定位機構之另一例之圖。於圖12D所示之構成中，在沿著焊墊411之外周之位置(特定範圍之周圍)設有複數之定位機構1200g~1200n。複數之定位機構1200g~1200n之中，定位機構1200g~1200j可與圖12C所示之定位機構1200c~1200f同樣地，於圖12D之左右方向限制條狀凸塊211之移動。進而，於圖12D所示之構成中，可藉由定位機構1200k~1200n，亦於圖12D之上下方向限制條狀凸塊211 之移動。
圖12E係表示設於焊墊411之定位機構之另一例之圖。如圖12E所示，於焊墊411之外周(特定範圍之周圍)設有定位機構1210a~1210h。定位機構1210係形成於焊墊411之外周之開口部(狹縫)。定位機構1210a~1210f可與圖12D所示之定位機構1200g~1200j同樣地，於圖12E之左右方向限制條狀凸塊211之移動。進而，定位機構1210g、1210h可與圖12D所示之定位機構1200k~1200n同樣地，亦於圖12E之上下方向限制條狀凸塊211之移動。
圖12F係表示考慮焊墊410之位置而配置之定位機構之一例之圖。如圖12F所示，於焊墊410與焊墊411接近而配置之情形時，可於焊墊411中之與焊墊410接近之側設置定位機構1200。如此，藉由於焊墊411中之與焊墊410接近之側設置定位機構1200，可防止焊料301越過焊墊411而塗佈擴散至焊墊410之狀況。於設置圖12E所示之定位機構1210之情形時亦相同。
以上，對本實施形態進行了說明。根據本實施形態，焊墊411之面積相對於條狀凸塊211之截面積之比，變得大於焊墊410之面積相對於支柱凸塊210之截面積的比。藉此，形成於條狀凸塊211之焊料301之塗佈擴散變得大於形成於支柱凸塊210之焊料300。因此，與凸塊和焊墊之面積之比對於支柱凸塊210及條狀凸塊211而言程度相同之情形相比，條狀凸塊211之隱沒量變大，可提昇支柱凸塊210與焊墊410之連接性。又，焊墊411之面積可藉由例如圖7~圖11所示之模擬而算出。
此外，如圖12A~圖12F所例示般，藉由於焊墊411上設置定位機構，可將凸塊211之移動限制於焊墊411之特定範圍。因此，可提昇凸塊211與焊墊411之連接性。
此外，如圖12A~圖12E所例示般，藉由沿著對向之2條邊 設置定位機構，可將焊墊411之移動限制於被2條邊圍住的範圍(特定範圍)。
進而，如圖12B~圖12E所例示般，藉由於對向之2條邊之至少一側形成焊料301之流路，而可增大焊料301之塗佈擴散面積。
此外，如圖12F所例示般，藉由於焊墊411中之與焊墊410接近之側設置定位機構，可防止焊料301越過焊墊411而塗佈擴散至焊墊410之狀況。
又，本實施形態係為了使本發明之理解容易者，並非限定性地解釋本發明者。本發明可不脫離其主旨地進行變更/改良，且本發明亦包含其等價物。
例如，於本實施形態中，係將構裝零件設為晶片101、將被構裝零件設為構裝基板102而進行說明，但構裝零件及被構裝零件之組合並不限定於此，只要為能夠覆晶連接者便可使用任意零件。例如，亦可適用於作為覆晶連接之一形態之晶片上晶片連接。即，構裝零件及被構裝零件可均為晶片。
此外，例如於本實施形態中，係將截面積較小之凸塊設為支柱凸塊、將截面積較大之凸塊設為條狀凸塊，但凸塊之形狀並不限定於此，可設為任意形狀。
100‧‧‧電子裝置
101‧‧‧晶片
102‧‧‧構裝基板
103‧‧‧密封樹脂
210a、210b‧‧‧凸塊(支柱凸塊)
211‧‧‧凸塊(條狀凸塊)
410a、410b、411‧‧‧焊墊

Claims (8)

  1. 一種電子裝置，其具備構裝零件、及構裝有上述構裝零件之被構裝零件，上述構裝零件於與上述被構裝零件對向之面具備截面為大致圓狀的第1凸塊、及在上述對向之面方向之截面為大致橢圓狀且截面積大於上述第1凸塊的第2凸塊，上述被構裝零件於與上述構裝零件對向之面具備與上述第1凸塊焊接之第1焊墊、及與上述第2凸塊焊接之第2焊墊，且上述第2焊墊之面積相對於上述第2凸塊之截面積之比，大於上述第1焊墊之面積相對於上述第1凸塊之截面積之比。
  2. 如申請專利範圍第1項之電子裝置，其中上述被構裝零件為構裝基板，上述第2凸塊係為了使上述構裝零件產生之熱散熱至上述構裝基板而設。
  3. 如申請專利範圍第1或2項之電子裝置，其中上述第2焊墊具有定位機構，該定位機構將上述第2凸塊之移動限制於上述第2焊墊之特定範圍，且形成焊料向上述特定範圍外之流路。
  4. 如申請專利範圍第3項之電子裝置，其中上述定位機構係設於上述第2焊墊之上述特定範圍之周圍之抗蝕劑。
  5. 如申請專利範圍第3項之電子裝置，其中上述定位機構係設於上述第2焊墊之上述特定範圍之周圍之開口部。
  6. 如申請專利範圍第3項之電子裝置，其中上述定位機構至少沿著上述特定範圍之對向之2條邊而設。
  7. 如申請專利範圍第6項之電子裝置，其中上述定位機構於上述2條邊之至少一側形成上述流路。
  8. 如申請專利範圍第3項之電子裝置，其中上述定位機構至少設於上述第2焊墊中之與上述第1焊墊接近之側。
TW103128768A 2013-08-23 2014-08-21 電子裝置 TWI590404B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013174002A JP6066324B2 (ja) 2013-08-23 2013-08-23 電子装置

Publications (2)

Publication Number Publication Date
TW201508888A TW201508888A (zh) 2015-03-01
TWI590404B true TWI590404B (zh) 2017-07-01

Family

ID=52479645

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103128768A TWI590404B (zh) 2013-08-23 2014-08-21 電子裝置

Country Status (4)

Country Link
US (1) US9524946B2 (zh)
JP (1) JP6066324B2 (zh)
CN (1) CN104427782B (zh)
TW (1) TWI590404B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI681524B (zh) * 2017-01-27 2020-01-01 日商村田製作所股份有限公司 半導體晶片
JP6963448B2 (ja) 2017-09-13 2021-11-10 太陽誘電株式会社 電子部品
CN108347822B (zh) * 2018-01-31 2020-03-10 维沃移动通信有限公司 一种电路板、终端设备及电路板的制造方法
WO2020017582A1 (ja) 2018-07-20 2020-01-23 株式会社村田製作所 モジュール
WO2020022352A1 (ja) 2018-07-27 2020-01-30 株式会社村田製作所 セラミック積層基板、モジュールおよびセラミック積層基板の製造方法
JP2020061406A (ja) 2018-10-05 2020-04-16 株式会社村田製作所 半導体装置
JP2021170582A (ja) 2020-04-15 2021-10-28 株式会社村田製作所 増幅モジュール
JP2022011066A (ja) * 2020-06-29 2022-01-17 日本電気株式会社 量子デバイス

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11111771A (ja) * 1997-10-07 1999-04-23 Matsushita Electric Ind Co Ltd 配線基板の接続方法、キャリア基板および配線基板
US7576436B2 (en) * 2002-12-13 2009-08-18 Advanced Semiconductor Engineering, Inc. Structure of wafer level package with area bump
JP4010244B2 (ja) * 2002-12-20 2007-11-21 ヤマハ株式会社 表面実装型パッケージ
JP2005101031A (ja) * 2003-09-22 2005-04-14 Rohm Co Ltd 半導体集積回路装置、及び電子機器
US7462942B2 (en) * 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
US8067837B2 (en) * 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
TWI282159B (en) 2005-12-20 2007-06-01 Internat Semiconductor Technol Thermally enhanced thin flip-chip package
US9941240B2 (en) * 2013-07-03 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor chip scale package and manufacturing method thereof

Also Published As

Publication number Publication date
CN104427782A (zh) 2015-03-18
JP2015041760A (ja) 2015-03-02
US20150054178A1 (en) 2015-02-26
US9524946B2 (en) 2016-12-20
TW201508888A (zh) 2015-03-01
CN104427782B (zh) 2017-08-11
JP6066324B2 (ja) 2017-01-25

Similar Documents

Publication Publication Date Title
TWI590404B (zh) 電子裝置
TWI495069B (zh) 互連結構
US7791211B2 (en) Flip chip package structure and carrier thereof
JP3631120B2 (ja) 半導体装置
TWI378543B (en) Semiconductor package having dimpled plate interconnections
TW201503304A (zh) 半導體裝置及其製法
JP5290215B2 (ja) 半導体装置、半導体パッケージ、インタポーザ、及びインタポーザの製造方法
JP2013236039A (ja) 半導体装置
US20130334684A1 (en) Substrate structure and package structure
TWI503935B (zh) 半導體封裝件及其製法
KR101740878B1 (ko) 반도체 장치
JP2007005452A (ja) 半導体装置
JP2010118522A (ja) 半導体装置および半導体装置の製造方法
TWI634823B (zh) 電子裝置
TWI378546B (en) Substrate and package for micro bga
TWI505422B (zh) 分散晶片角隅應力之窗口型球格陣列封裝構造
JP2016162813A (ja) プリント基板及びハンダ付け方法
TW201428902A (zh) 半導體裝置及其製法
US20240030107A1 (en) Semiconductor device and mounting structure thereof
US9293399B2 (en) Semiconductor device and electronic unit provided with the same
KR100818095B1 (ko) 플립 칩 패키지 및 그의 형성방법
JP2013026481A (ja) 半導体装置及び半導体装置の実装構造
JP2005197496A (ja) 回路基板及び回路基板の製造方法、並びに半導体パッケージ及び半導体パッケージの製造方法。
JP2006303035A (ja) 半導体装置
WO2011064937A1 (ja) 半導体装置及びその製造方法