JP2006303035A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2006303035A JP2006303035A JP2005120142A JP2005120142A JP2006303035A JP 2006303035 A JP2006303035 A JP 2006303035A JP 2005120142 A JP2005120142 A JP 2005120142A JP 2005120142 A JP2005120142 A JP 2005120142A JP 2006303035 A JP2006303035 A JP 2006303035A
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- semiconductor device
- solder
- substrate
- solder joint
- wiring board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Wire Bonding (AREA)
Abstract
【解決手段】 半導体装置10は、BGA型の半導体装置であり、配線基板20と、配線基板20にワイヤボンディング実装された半導体チップ30と、半導体チップ30と電気的に接続され、半導体チップ30の表面とは反対側の配線基板20の裏面上に突出した複数の外部電極と、配線基板20の側面および配線基板20の裏面に対して凹部となるように形成されたハンダ接合部60とを備える。
【選択図】 図2
Description
図1は、実施形態1にかかる半導体装置の裏面に設けられた外部電極およびハンダ接合部の配列を示す図である。図2は、図1のA−A’線上における半導体装置の断面図である。
図6は、実施形態1の半導体装置におけるハンダ接合部の形成方法を示す図である。図6は、複数の半導体チップ30が配線基板20アレイ状に実装された状態を示す。図6では、ハンダ接合部の形成方法の説明のため、半導体チップ30の結線に必要なボンディングワイヤ32等が省略されている。切断線X1〜X3および切断線Y1〜Y3は、各半導体装置10を切り出すべき線を示す。
図8は、実施形態2にかかる半導体装置の裏面に設けられた外部電極およびハンダ接合部の配列を示す図である。実施形態2の半導体装置210の説明において、実施形態1と同様な構成については同じ符号を用いて適宜説明を省略する。図9は、実施形態2にかかる半導体装置に設けられたハンダ接合部の斜視図である。
図10は、実施形態2の半導体装置におけるハンダ接合部の形成方法を示す図である。実施形態2のハンダ接合部の形成方法は、実施形態1と基本的には同様である。ただし、本実施形態では、切断線が交差する箇所において隅部が隣接する4つの半導体装置10に対応して4つの端面スルーホール250が一度に形成される。このように、端面スルーホール250を切断線が交差する領域に形成し、切断線に沿って配線基板20を切り離すことにより、端面スルーホール250をさらに効率的に形成することができる。
Claims (5)
- 基板と
前記基板に実装された半導体チップと、
前記半導体チップと電気的に接続され、前記半導体チップの表面とは反対側の前記基板の裏面上に突出した複数の外部電極と、
前記基板の端面および前記基板の裏面に対して凹部となるように形成されたハンダ接合部と、
を備えることを特徴とする半導体装置。 - 前記基板の表面の形状が四角形であり、
前記ハンダ接合部が、前記基板の少なくとも2カ所に設けられていることを特徴とする請求項1に記載の半導体装置。 - 一対の前記ハンダ接合部が、前記基板の対角の隅部に設けられていることを特徴とする請求項2に記載の半導体装置。
- 前記ハンダ接合部が、前記基板の少なくとも3辺の各辺に1カ所以上設けられていることを特徴とする請求項2に記載の半導体装置。
- 前記ハンダ接合部が前記半導体チップと電気的に接続されていないことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005120142A JP4712426B2 (ja) | 2005-04-18 | 2005-04-18 | 半導体装置 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2005120142A JP4712426B2 (ja) | 2005-04-18 | 2005-04-18 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006303035A true JP2006303035A (ja) | 2006-11-02 |
JP4712426B2 JP4712426B2 (ja) | 2011-06-29 |
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JP2005120142A Active JP4712426B2 (ja) | 2005-04-18 | 2005-04-18 | 半導体装置 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008018604A1 (fr) * | 2006-08-11 | 2008-02-14 | Seiko Epson Corporation | PROCÉDÉ DE FABRICATION D'UN CORPS de réception de liquide, et corps de réception de liquide |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002359320A (ja) * | 2001-06-01 | 2002-12-13 | Toyo Commun Equip Co Ltd | 電子部品の外部電極パターン |
JP2003168758A (ja) * | 2001-11-30 | 2003-06-13 | Toshiba Corp | 半導体装置 |
JP2003197813A (ja) * | 2001-12-28 | 2003-07-11 | Mitsubishi Electric Corp | 電子装置 |
JP2004200416A (ja) * | 2002-12-18 | 2004-07-15 | Kyocera Corp | 配線基板 |
-
2005
- 2005-04-18 JP JP2005120142A patent/JP4712426B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002359320A (ja) * | 2001-06-01 | 2002-12-13 | Toyo Commun Equip Co Ltd | 電子部品の外部電極パターン |
JP2003168758A (ja) * | 2001-11-30 | 2003-06-13 | Toshiba Corp | 半導体装置 |
JP2003197813A (ja) * | 2001-12-28 | 2003-07-11 | Mitsubishi Electric Corp | 電子装置 |
JP2004200416A (ja) * | 2002-12-18 | 2004-07-15 | Kyocera Corp | 配線基板 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008018604A1 (fr) * | 2006-08-11 | 2008-02-14 | Seiko Epson Corporation | PROCÉDÉ DE FABRICATION D'UN CORPS de réception de liquide, et corps de réception de liquide |
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JP4712426B2 (ja) | 2011-06-29 |
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