JP2021005687A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2021005687A JP2021005687A JP2019120264A JP2019120264A JP2021005687A JP 2021005687 A JP2021005687 A JP 2021005687A JP 2019120264 A JP2019120264 A JP 2019120264A JP 2019120264 A JP2019120264 A JP 2019120264A JP 2021005687 A JP2021005687 A JP 2021005687A
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- Prior art keywords
- layer
- semiconductor device
- plating layer
- wiring
- substrate
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- 238000007747 plating Methods 0.000 claims abstract description 254
- 239000000758 substrate Substances 0.000 claims abstract description 210
- 229910000679 solder Inorganic materials 0.000 claims abstract description 87
- 239000000463 material Substances 0.000 claims description 99
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- 239000010949 copper Substances 0.000 description 32
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- 238000010030 laminating Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020935 Sn-Sb Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 229910008757 Sn—Sb Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
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Classifications
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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Abstract
Description
以下、第1実施形態の半導体装置A10を説明する。
図1及び図2に示すように、半導体装置A10は、基板10、配線部20、接合部40、半導体素子50、封止樹脂60、外部導電膜70を備えている。配線部20は、主面配線21と貫通配線22とを含む。
各貫通配線22は、各貫通孔105に配設されている。各貫通配線22は、上面221、下面222、複数の側面223を有している。上面221及び下面222は、厚さ方向zにおいて互いに反対側を向く。各側面223は、上面221と下面222とに挟まれている。第1実施形態において、貫通配線22の上面221は、基板10の基板主面101と面一である。また、第1実施形態において、貫通配線22の下面222は、基板10の基板裏面102と面一である。この下面222は、基板10の基板裏面102から露出する露出面である。なお、貫通配線22の上面221及び下面222の少なくとも一方が基板10の基板主面101及び基板裏面102と面一ではないようにしてもよい。また、貫通配線22の側面223は、貫通孔105の内壁面106と接している。貫通配線22は、電気導電性を有する材料からなる。貫通配線22の材料としては、例えばCu、Cu合金、等を用いることができる。
金属層56は、電極パッド52の露出する部分と、電極パッド52を露出する保護膜54の開口の端部を覆うように形成されている。金属層56は、例えばTi/Cuからなり、導電層32を形成するシード層として形成される。
バリア層58は、導電層57の下面を覆うように形成されている。バリア層58は、Ni、Niを含む合金、Niを含む複数の金属層からなる。バリア層58としては、例えばNi,Pd,Au、これらの2つ以上の金属を含む合金、等を用いることができる。バリア層58の下面は、実装用電極55の下面であり、半導体素子50の接続面である。この接続面は、接合部40のはんだ層44の上面441と対向し、その上面に接している。半導体素子50の実装用電極55は、接合部40に接続され、これにより、半導体素子50が基板10に実装される。
次に、第1実施形態の半導体装置A10の製造方法の一例を説明する。
図4から図11は、第1実施形態の半導体装置A10の製造工程を説明するための断面図である。なお、図4から図11は、1つの半導体装置A10にかかる部分を示している。図4から図11において、2本の破線は、1つの半導体装置A10となる範囲を示す。これらの図において示される各方向の定義は、図1及び図2にて示される方向の定義と同一である。
図4に示すように、支持基板800を用意する。支持基板800は、例えばSiの単結晶材料からなる。なお、支持基板800として、エポキシ樹脂等の合成樹脂材料からなる基板を用いてもよい。支持基板800の上面801に、端子ピラー822を形成する。端子ピラー822は、例えばCu,Cu合金からなる。
図3に示すように、主面配線21は、金属層31と導電層32と第1めっき層33とを含む。主面配線21は、金属層31を形成する工程と、金属層31に対してフォトリソグラフィによりマスクを形成する工程と、金属層31に接する導電層32を形成する工程と、金属層31に接する導電層32を形成する工程と、導電層32の上面321の第1めっき層33を形成する工程を含む。
次に、主面配線21の上に接合部40を形成する工程の一例を、図12から図15に従って説明する。
図12に示すように、主面配線21は、基板10となる基材810の上面811に積層された金属層31、導電層32、第1めっき層33からなる。基材810の上面811に、金属層31、第1導電層32、第1めっき層33、第2導電層34をこの順番で積層する。先ず、金属層31を、例えばスパッタリング法により形成する。金属層31が互いに積層されたTi層及びCu層からなる場合、先ず基材810の上面811に接するTi層を形成した後、このTi層に接するCu層を形成する。次いで、導電層32を、例えば電解めっき法により形成する。電解めっき法において、金属層31を導電経路とし、金属層31をシード層として金属層31の上面311にめっき金属としてCuを析出させて導電層32を形成する。シード層とする金属層31の上面311に、図示しないレジストマスクを形成することにより、主面配線21となる部分のみに、導電層32及び次の第1めっき層33を形成することができる。次に、第1めっき層33を、例えば電解めっき法により形成する。電解めっき法において、金属層31及び導電層32を導電経路とし、導電層32をシード層として導電層32の上面321にめっき金属としてNiを析出させて第1めっき層33を形成する。上述のレジストマスクを除去した後、露出する金属層31を例えばエッチングにより除去することによって、金属層31と導電層32と第1めっき層33とからなる主面配線21が得られる。
次に、第1実施形態の半導体装置A10の作用を説明する。
半導体装置A10は、基板主面101を有する基板10と、基板主面101に形成された配線部20とを有する。配線部20は、基板10の基板主面101に形成された導電層32と、導電層32の上面321に設けられ、酸化膜が形成される第1めっき層33とを有する。配線部20の上には、半導体素子50を実装するための接合部40が形成されている。接合部40は、導電層32に積層された第2めっき層41と、第2めっき層41に積層されたはんだ層44とを有する。半導体素子50は、接合部40のはんだ層44及び第2めっき層41を介して、配線部20に接続される。
なお、配線部20の上面がCu、Cu合金からなる導電層32の場合、露出する表面に対して自然酸化により形成される酸化膜は、フラックスによって除去される。なお、酸化膜は、フラックスによって完全に除去されなくても薄くなる。これらのように、Cuの表面が露出する配線部では、リフロー処理の加熱によって液相状態となったはんだ層44が第2めっき層41の上から流れ出し易い。
(1−1)半導体装置A10は、基板主面101を有する基板10と、基板主面101に形成された配線部20とを有する。配線部20は、基板10の基板主面101に形成された導電層32と、導電層32の上面321に設けられ、酸化膜が形成される第1めっき層33とを有する。配線部20の上には、半導体素子50を実装するための接合部40が形成されている。接合部40は、導電層32に積層された第2めっき層41と、第2めっき層41に積層されたはんだ層44とを有する。半導体素子50は、接合部40のはんだ層44及び第2めっき層41を介して、配線部20に接続される。
(1−3)複数の接合部40において、各接合部40のはんだ層44が第2めっき層41の上に留まるので、各接合部40の高さにばらつきが生じるのを抑制できる。このため、半導体素子50の傾きを抑制できる。
(1−5)第2めっき層41は、第1めっき層33の開口333に充填された充填部42を有している。この充填部42は、第1めっき層33の開口333内において、配線部20の導電層32に接続されている。このため、配線部20と接合部40との間の密着性を向上でき、接合部40の脱落を抑制できる。
図16に示す半導体装置A11は、基板10、配線部20、接合部40、半導体素子50、封止樹脂60、外部導電膜70を有している。配線部20は、基板10の基板主面101に形成された主面配線21と、基板10を貫通する貫通配線22とを含む。
基板11は、薄い板状であり、貫通孔は形成されていない。基板11は、基板主面111、基板裏面112、複数の基板側面113を有している。基板主面111及び基板裏面112は、厚さ方向zにおいて、互いに反対側を向く。基板主面111及び基板裏面112は、平坦である。この基板11の材料としては、例えば、エポキシ樹脂等を主剤とした合成樹脂、セラミックス、ガラス、Si等の半導体材料、等を用いることができる。なお、Si等の半導体材料からなる基板11の場合、基板主面111を覆う絶縁層が設けられる。絶縁層は、例えばSiO2等の酸化膜、ポリイミド等の樹脂膜が用いられる。
主面配線21は、基板11の基板主面111に形成されている。主面配線21の上面211は、基板11の基板主面111と同じ方向を向く。主面配線21の下面212は、基板11の基板裏面112と同じ方向を向き、基板11の基板主面111と対向している。主面配線21の側面213は、基板11の基板側面113と同じ方向を向く。
以下、第2実施形態の半導体装置A20を説明する。
なお、第2実施形態において、第1実施形態の半導体装置A10と同一または類似の構成部材については同一の符号を付し、その部材の説明の一部又は全てを省略する。
第2実施形態の第2めっき層45は、上面451、下面452、複数の側面453を有している。上面451と下面452は、厚さ方向zにおいて互いに反対側を向く。上面451は、第2導電層34の上面341と同じ方向を向く。下面452は、第2導電層34の上面341と対向し、上面341に接している。各側面453は、上面451と下面452とに挟まれている。各側面453は、平坦である。各側面453は、上面451と下面452とに交差する。第2めっき層45と第2導電層34は、厚さ方向zから視て互いに重なり合っている。
次に、第2実施形態の接合部40の製造方法の一例を説明する。
なお、第2実施形態において、半導体装置A20を製造する工程のは、第1実施形態の半導体装置A10を製造する工程と概略同じであるため、図面及び説明を省略する。
図22に示すように、基板10となる基材810の上面811に、金属層31、第1導電層32、第1めっき層33、第2導電層34をこの順番で積層する。
先ず、マスクM10の開口M11から露出する第2導電層34の上面341に、第2めっき層45を、例えば電解めっき法により形成する。第2導電層34を導電経路とし、第2導電層34の上面341にめっき金属としてNiを析出させ、第2めっき層45を形成する。
第2実施形態の半導体装置A20において、配線部20は、金属層31、第1導電層32、第1めっき層33、第2導電層34を有する。第1導電層32及び第2導電層34はCuよりなり、第1めっき層33はNiよりなる。このような配線部20は、第1導電層32と第1めっき層33と第2導電層34とが一工程にて形成される。このため、Niよりなる第1めっき層33と、Cuよりなる第2導電層34との間に、酸化膜は形成されない。このため、第1めっき層33に対して第2導電層34が密着する。
(2−1)半導体装置A20の配線部20は、金属層31、第1導電層32、第1めっき層33、第2導電層34を有する。第1導電層32及び第2導電層34はCuよりなり、第1めっき層33はNiよりなる。接合部40は、第2めっき層45とはんだ層44とを有する。第2めっき層45はNiよりなる。したがって、第2めっき層45と第1めっき層33とにより、リフロー処理において液相状態のはんだ層44の流れ出しが抑制される。
(2−3)第2導電層34に対する第2めっき層45の生成が容易であるため、第2めっき層45における未成長部分の発生を抑制できる。このため、第2めっき層45における高抵抗化、つまり配線部20における高抵抗化を抑制できる。
以下、第3実施形態を説明する。
図26及び図27に示すように、半導体装置A30は、基板12、配線部20、外部導電膜70、半導体素子50、封止樹脂60を備えている。配線部20は、主面配線24と貫通配線としての柱状体25とを含む。
基材13は、主面131、裏面132、複数の側面133を有している。主面131と裏面132は、厚さ方向zにおいて、互いに反対側を向く。主面131及び裏面132は平坦である。基材13は、例えば電気絶縁性を有する材料からなる。この材料としては、例えば、シリコン(Si)等の単結晶の真性半導体材料、エポキシ樹脂等を主剤とした合成樹脂、を用いることができる。基材13の主面131としては、例えば結晶方位が(100)である(100)面を採用することができる。
主面配線24は、基板12の基板主面121の側に形成された配線部20の一部である。主面配線24は、上面241、下面242、側面243を有している。第3実施形態の主面配線24は、金属層と導電層と第1めっき層とを含む。
第2めっき層41は、第1実施形態の半導体装置A10と同様に、主面配線24を構成する第1めっき層の開口から露出する導電層に接続されている(図3参照)。なお、第3実施形態において、配線部20(主面配線24)を金属層と第1導電層と第1めっき層と第2導電層とを含む構成とし、第2導電層の上に第2めっき層41を形成してもよい。
次に、第3実施形態の半導体装置A30の製造方法の一例を説明する。
図28から図35は、第3実施形態の半導体装置A30の製造工程を説明するための断面図である。なお、図28から図35は、1つの半導体装置A30にかかる部分を示している。図28から図35において、2本の破線は、1つの半導体装置A30となる範囲を示す。これらの図において示される各方向の定義は、図26及び図27にて示される方向の定義と同一である。
(3−1)単結晶の半導体材料からなる基材13を用いた半導体装置A30において、半導体素子50を実装する際のリフロー処理におけるはんだ層44の流れ出しを抑制できる。
・基材13の裏面132に絶縁層が形成されていても良い。絶縁層は、電気絶縁性を有する被膜である。裏面132に形成される絶縁層として、例えばSiO2、樹脂、SiO2及び樹脂とを含むもの、とすることができる。
本実施形態は、以下のように変更して実施することができる。
・図36に示すように、接合部40のはんだ層44の側面443を、はんだ層44の外側に向かって湾曲した面としてもよい。
10,11,12…基板
20…配線部
21,23,24…主面配線
22…貫通配線
31…金属層
32…導電層(第1導電層)
33…第1めっき層
34…第2導電層
40…接合部
41,45…第2めっき層
42…充填部
43…突出部
44…はんだ層
50…半導体素子
60…封止樹脂
70…外部導電膜
105,125,135,605…貫通孔
141…第1絶縁層
142…第2絶縁層
Claims (22)
- 主面を有する基板と、
前記主面に形成された第1導電層と、前記第1導電層の上に設けられ、酸化膜が形成される第1めっき層と、を有する配線部と、
素子実装面と、前記素子実装面に形成された素子電極とを有する半導体素子と、
前記第1めっき層と同じ材料からなり前記第1導電層に積層された第2めっき層と、前記第2めっき層に積層され前記素子電極が接合されたはんだ層とを有する接合部と、
前記半導体素子を覆う封止樹脂と、
を備えた半導体装置。 - 前記第1めっき層は、前記第1導電層の上面を露出する開口を有し、
前記第2めっき層は、少なくとも前記開口内に充填されて前記第1めっき層と接続される、
請求項1に記載の半導体装置。 - 前記開口の内壁面は、前記第1めっき層の内部に向かう凹状に形成されている、
請求項2に記載の半導体装置。 - 前記開口の内壁面は、前記第1めっき層の上面側よりも前記第1めっき層の下面側が小さい、
請求項2又は請求項3に記載の半導体装置。 - 前記第2めっき層は、前記開口内に設けられるとともに、前記第1めっき層の上面から突出している、
請求項2から請求項4のいずれか一項に記載の半導体装置。 - 前記第2めっき層は、前記開口に充填された充填部と、前記第1めっき層の上面よりも突出する突出部とを有する、
請求項2から請求項4のいずれか一項に記載の半導体装置。 - 前記主面と垂直な厚さ方向から視て、前記充填部は前記突出部よりも大きい、
請求項6に記載の半導体装置。 - 前記主面と垂直な厚さ方向から視て、前記第1めっき層の開口は、前記第2めっき層の前記突出部よりも大きい、
請求項6に記載の半導体装置。 - 前記充填部の上面は、前記第1めっき層の上面と面一である、
請求項6から請求項8の何れか一項に記載の半導体装置。 - 主面を有する基板と、
前記主面に形成された第1導電層と、前記第1導電層の上面に設けられ、酸化膜が形成される第1めっき層と、前記第1めっき層の上面に設けられた第2導電層と、を有する配線部と、
素子実装面と、前記素子実装面に形成された素子電極とを有する半導体素子と、
前記第2導電層に積層された第2めっき層と、前記第2めっき層に積層され前記素子電極が接合されたはんだ層とを有する接合部と、
前記半導体素子を覆う封止樹脂と、
を備えた半導体装置。 - 前記第2導電層の側面は、前記第2導電層の内部に向かう凹状に形成されている、
請求項10に記載の半導体装置。 - 前記基板は、前記主面と反対側を向く裏面と前記主面との間まで前記基板を貫通した貫通孔を有し、
前記配線部は、前記第1導電層及び前記第1めっき層を含む主面配線と、前記貫通孔に設けられ、前記主面配線に接続された貫通配線と、を有する、
請求項1から請求項11のいずれか一項に記載の半導体装置。 - 前記貫通配線は、前記基板から露出する露出面を有し、
前記半導体装置は、前記貫通配線の前記露出面を覆う外部導電膜をさらに有する、
請求項12に記載の半導体装置。 - 前記封止樹脂は、前記配線部の上面から前記封止樹脂の上面まで貫通する貫通孔を有し、
前記配線部は、前記第1導電層及び前記第1めっき層を含む主面配線と、前記貫通孔に設けられ、前記主面配線に接続された貫通配線と、を有する、
請求項1から請求項11のいずれか一項に記載の半導体装置。 - 前記貫通配線は、前記封止樹脂から露出する露出面を有し、
前記半導体装置は、前記貫通配線の前記露出面を覆う外部導電膜をさらに有する、
請求項14に記載の半導体装置。 - 前記基板は、樹脂から構成される、
請求項12から請求項15のいずれか一項に記載の半導体装置。 - 前記基板は、半導体材料からなり、
前記主面と前記第1導電層との間に介在する第1絶縁層と、
前記貫通孔の内壁と前記貫通配線との間に介在する第2絶縁層と
を備えた、
請求項12または請求項13に記載の半導体装置。 - 前記貫通配線は、前記第1導電層を向く上面を有し、前記上面は、前記貫通配線の内側に向かう凹状である、
請求項17に記載の半導体装置。 - 前記第1導電層は、Cuよりなり、
前記第1めっき層及び前記第2めっき層は、Niよりなる、
請求項1から請求項18のいずれか一項に記載の半導体装置。 - 前記第2導電層は、Cuよりなる、
請求項10又は請求項11に記載の半導体装置。 - 前記第1導電層の下面に形成された金属層を備えた、
請求項1から請求項20のいずれか一項に記載の半導体装置。 - 前記金属層はTiを含む、
請求項21に記載の半導体装置。
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