CN103238215A - 非易失性存储器单元阵列 - Google Patents

非易失性存储器单元阵列 Download PDF

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CN103238215A
CN103238215A CN2011800578660A CN201180057866A CN103238215A CN 103238215 A CN103238215 A CN 103238215A CN 2011800578660 A CN2011800578660 A CN 2011800578660A CN 201180057866 A CN201180057866 A CN 201180057866A CN 103238215 A CN103238215 A CN 103238215A
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刘峻
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Micron Technology Inc
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Abstract

本发明揭示一种每单位单元包含五个存储器单元的非易失性存储器单元阵列。本发明还揭示一种包含五个存储器单元的经垂直堆叠的非易失性存储器单元层阵列,所述五个存储器单元占据所述层中的个别层内的4F的连续水平面积。本发明还揭示一种包括多个单位单元的非易失性存储器单元阵列,所述多个单位单元个别地包括可编程材料的三个竖直区,所述三个竖直区包括所述单位单元的至少三个不同存储器单元的所述可编程材料。本发明还揭示一种包含连续体积的经垂直堆叠的非易失性存储器单元层阵列,所述连续体积具有多个经垂直定向的存储器单元与多个经水平定向的存储器单元的组合。本发明揭示其它实施例及方面。

Description

非易失性存储器单元阵列
技术领域
本文中所揭示的实施例涉及非易失性存储器单元阵列。
背景技术
存储器是一种类型的集成电路,且在计算机系统中用于存储数据。其通常制作成一个或一个以上个别存储器单元阵列。所述存储器单元可为易失性、半易失性或非易失性。在许多实例中(包含当计算机关断时),非易失性存储器单元可存储数据达延长的时间周期。易失性存储器耗散且因此在许多实例中需要以每秒多次的方式刷新/重新写入。不管如何,每一阵列中的最小单位称为存储器单元且经配置而使存储器以至少两个不同可选择状态保留或存储。在二进制系统中,将所述状态视为“0”或“1”。在其它系统中,至少一些个别存储器单元可经配置以存储两个以上信息电平或状态。
集成电路制作继续努力产生更小且更密集的集成电路。因此,个别电路装置具有愈少组件,成品装置的构造可愈小。最小且最简单的存储器单元将可能由具有接纳于其间的可编程材料的两个电流导电电极构成。所述可编程材料经选择或设计以配置成至少两个不同电阻状态中的选定一者以使得能够通过个别存储器单元来存储信息。对所述单元的读取包括确定所述可编程材料处于所述状态中的哪一状态,且将信息写入到所述单元包括将所述可编程材料置于预定电阻状态中。一些可编程材料在缺少刷新的情况下保持一电阻状态,且因此可并入到非易失性存储器单元中。
一些可编程材料可含有大于电子及空穴的移动电荷载流子,举例来说,在一些实例性应用中为离子。不管如何,可通过使移动电荷载流子在可编程材料中移动而将所述可编程材料从一个存储器状态转换到另一存储器状态以更改所述可编程材料内的电荷密度的分布。利用离子作为移动电荷载流子的一些实例性存储器装置为电阻性RAM(RRAM)单元,其可包含含有多价氧化物的若干个类别的存储器单元,且在一些特定应用中其可包含忆阻器。利用离子作为电荷载流子的其它实例性存储器装置为可编程金属化单元(PMC);或者,其可称为导电桥接RAM(CBRAM)、纳米桥接存储器或电解质存储器。
RRAM单元可含有夹在一对电极之间的可编程材料。对所述RRAM单元的编程可包括使所述可编程材料在其中电荷密度在整个材料中相对均匀地散布的第一存储器状态与其中所述电荷密度集中于所述材料的特定区中(例如,到一个电极比到另一电极更近的区)的第二存储器状态之间转变。
PMC可类似地具有夹在一对电流导电电极之间的可编程材料。所述PMC可编程材料包括离子导电材料,举例来说,适合硫属化物或各种适合氧化物中的任一者。跨越电极施加的适合电压产生电流导电超离子簇或丝。此起因于穿过离子导电材料的离子输送,其使所述簇/丝从所述电极中的一者(阴极)、穿过所述离子导电材料且朝向另一电极(阳极)生长。所述簇或丝形成所述电极之间的导电路径。跨越所述电极施加的相对电压基本上使所述过程反转且因此移除电流导电路径。因此,PMC包括高电阻状态(对应于缺少电极之间的导电丝或簇的状态)及低电阻状态(对应于具有电极之间的导电丝或簇的状态),其中此些状态彼此可反转地互换。
发明内容
附图说明
图1是根据本发明的实施例的非易失性存储器单元阵列的图解性等距视图。
图2是图1的阵列的一部分的片断视图。
图3是图2的片断视图。
图4是图2的俯视图。
图5是穿过图4中的线5-5截取的截面图。
图6是用以表征本发明的一些实施例的空单位单元的图解性等距视图。
图7是根据本发明的一些实施例的图1阵列的单位单元的图解性等距视图。
图8是根据本发明的实施例的非易失性存储器单元阵列的图解性等距视图。
图9是图8的阵列的一部分的片断视图。
图10是图8的一部分的图解性俯视图。
图11是根据本发明的一些实施例的图8阵列的单位单元的图解性视图。
图12是穿过图10中的线12-12截取的截面图。
图13是根据本发明的实施例的非易失性存储器单元阵列的图解性等距视图。
具体实施方式
本发明的实施例包含非易失性存储器单元阵列。最初参考图1到5描述此些存储器单元的经垂直堆叠层的阵列10的一些实例性实施例。图1展示其内已制作多个非易失性存储器单元的阵列区域的一部分。通常将在所述阵列区域外部制作逻辑电路(未展示)。用于操作存储器阵列的控制电路及/或其它外围电路(未展示)可或可不完全或部分地接纳于所述阵列区域内,其中实例性阵列区域至少囊括给定阵列/子阵列的所有存储器单元。此外,还可独立地、联合地或以其它方式相对于彼此制作及操作多个子阵列。如本文档中所使用,还可将“子阵列”视为阵列。
图1描绘三个经垂直堆叠的存储器单元层12、14、16。可使用更多或更少层。因此,可从层12竖直向外及/或从层16竖直向内接纳一个或一个以上层。不管如何,将相对于适合基底衬底(未展示)来制作阵列10,所述基底衬底可为同质的或不同质的(举例来说,包括多种不同组成材料及/或层)。作为实例,其可包括块体单晶硅及/或绝缘体上半导体衬底。作为额外实例,其可包括其中形成有导电触点或通孔的电介质材料,所述导电触点或通孔垂直地或以其它方式延伸成与从所述电介质材料竖直向内接纳的电子装置组件、区或材料电流导电电连接。在本文档中,垂直为大体正交于主表面的方向,在制作期间相对于所述主表面处理衬底且可将所述主表面视为界定大体水平方向。此外,如本文中所使用的“垂直”及“水平”为在三维空间中独立于衬底的定向而相对于彼此大体垂直的方向。此外,在本文档中,“竖直”及“竖直地”是参考从其上制作电路的基底衬底的垂直方向来说的。所述基底衬底可或可不为半导体衬底。在本文档的上下文中,术语“半导体衬底”或“半导电衬底”经定义而意指包括半导电材料的任一构造,所述半导电材料包含但不限于块体半导电材料(例如,半导电晶片)(单独地或以其上包括其它材料的组合件方式)及半导电材料层(单独地或以包括其它材料的组合件方式)。术语“衬底”是指任何支撑结构,包含但不限于上文所描述的半导电衬底。图1的阵列结构将可能囊括于电介质材料内/由电介质材料囊封,为使阵列内的操作性存储器单元组件清晰起见,在所述图中的任一者中未展示所述电介质材料。
垂直层12、14、16可具有相同或不同相应构造。在一个实施例中,所有此些层具有相同构造(举例来说)以实现最终最高密度及/或易于制作。不管如何,个别垂直层中的至少一些层可由某些属性表征,所述属性的实例实施例最初参考图1到5来描述。图2到5是可相对于本发明的一些实施例视为关注区的图1相同部分的视图。在图2到5中展示层12的仅一部分,且为清晰起见未展示直接下部邻近层14的组件。在一个实施例中,可将图2到5视为包括图1的阵列10的连续体积,且在一个实施例中可将其视为描绘或囊括下文所描述的阵列12的“单位单元”的等距视图。不管如何,图5是从左侧且笔直地向图2观看的竖直端视图,而图4是图2的俯视图。图3是图2的部分及片断部分视图。
个别垂直层包括相应多个经水平定向的第一电极线的竖直外层18(图2、3及5)及竖直内层20。具体来说,外层18具有第一电极线22且内层20具有第一电极线24。外层18的第一电极线22相对于内层20的第一电极线24交叉,且在一个实施例中以约90°交叉。
多个经垂直定向的第二电极线26延伸穿过内层20及外层18。经垂直定向的第二电极线26中的个别电极线在内层中及外层中的紧邻相应对的第一电极线之间延伸。举例来说,在图2到5中,所图解说明的第二电极线26在外层18的所描绘紧邻对的第一电极线22之间延伸且在内层20的所描绘紧邻对的第一电极线24之间延伸。经垂直定向的第二电极线26还竖直向内及向外延伸穿过经垂直堆叠的非易失性存储器单元层中的其它层。可将经垂直定向的第二电极线26视为具有第一对相对横向侧30及第二对相对横向侧32。在一个实施例中且如所展示,第一对相对横向侧30与第二对相对横向侧32相对于彼此以约90°定向。在一个实施例中,第一电极线为数据/读出线,且第二电极线为存取线。
第一及第二电极线包括电流导电材料,可为同质的或不同质的且可具有相同组成或具有不同组成。在本文档的上下文中,“电流导电材料”为组合物,其中电流流动将在产生亚原子正电荷及/或负电荷时主要通过亚原子正电荷和/或负电荷的移动(相对于主要通过离子的移动)固有地发生于其中。实例性电流导电材料为元素金属、元素金属的合金、电流导电金属化合物及经导电掺杂的半导电材料,包含其任何组合。
可编程材料35接纳于第二电极线26的所述对相对横向侧中的一者中的每一者与所述内层及外层中的一者的第一电极线中的一者之间。可编程材料还接纳于第二电极线26的另一对相对横向侧中的每一者与所述内层及外层中的另一者的第一电极线之间。在图1到5中,实例性可编程材料35接纳于横向侧30中的每一者与外层18中的不同邻近第一电极线22之间,且还接纳于横向侧32中的每一者与内层20中的不同邻近第一电极线24之间。可编程材料35可沿圆周完全地包围内层及外层中的一者或两者内的个别经垂直定向的第二电极线26,其中在图1到5的实例性实施例中相对于此些层18及20两者展示完全包围。在一个实施例中且如所展示,可编程材料35还接纳于外层18的个别第一电极线22与内层20的个别第一电极线24之间此两者交叉处。
不管如何,可编程材料35可为固体、凝胶、非晶、结晶或任何其它适合相,且可为同质的或不同质的。可使用任何现存或尚待开发的可编程材料,其中下文仅提供一些实例。
一种实例性可编程材料为离子导电材料。此些实例性适合材料包括:硫属化物类型(例如,包括锗、硒、锑、碲、硫、铜等中的一者或一者以上的材料,其中实例性硫属化物类型材料为Ge2Sb2Te5、GeS2、GeSe2、CuS2及CuTe);及/或能够固有地(或借助添加剂)支持电解质行为的氧化物,例如氧化锆、氧化铪、氧化钨、氧化铜、氧化铌、氧化铁、氧化硅(具体来说,二氧化硅)、氧化钆等。此些材料可具有分散于其中用于离子导电的银、铜、钴及/或镍离子及/或其它适合离子,类似于第7,405,967号美国专利及第2010/0193758号美国专利公开案中所揭示的结构。
额外实例性可编程材料包含多电阻状态包括金属氧化物的材料。举例来说,此材料可包括通常视为或理解为有源或无源区的至少两个不同层或区(但并非必需地)。或者,此材料可仅包括有源材料。包括金属氧化物且可配置成多电阻状态的实例性有源单元区组合物包含SrxRuyOz、RuxOy及InxSnyOz中的一者或组合。其它实例包含MgO、Ta2O5、SrTiO3、SrZrO3、BaTiO3、Ba(1-x)SrxTiO3、ZrOx(可能掺杂有La)及CaMnO3(掺杂有Pr、La、Sr或Sm中的一者或一者以上)。实例性无源单元区组合物包含Al2O3、TiO2及HfO2中的一者或组合。不管如何,可编程材料复合物可包括额外金属氧化物或不包括金属氧化物的其它材料。在第6,753,561号、第7,149,108号、第7,067,862号及第7,187,201号美国专利中以及在第2006/0171200号及第2007/0173019号美国专利申请公开案中描述及揭示包括一个或一个以上层(包含可编程的包括金属氧化物的材料)的多电阻状态区的实例性材料及构造。此外,如常规的,多电阻状态包括金属氧化物的材料囊括丝型金属氧化物、铁电金属氧化物及其它金属氧化物,且无论是现存的还是尚待开发的,只要可选择性地改变包括金属氧化物的材料的电阻即可。
所述可编程材料可包括忆阻材料。作为实例,此材料可为静态可编程半导电材料,其包括接纳于电介质内的移动掺杂剂使得所述材料可在至少两个不同电阻状态之间静态编程。所述状态中的至少一者包含移动掺杂剂的局部化或聚集,使得电介质区形成且借此提供较高电阻状态。此外,可使用两个以上可编程电阻状态。在本文档的上下文中,“移动掺杂剂”是半导电材料的可在通过将电压差施加到电极对而在至少两个不同静态状态之间重复地编程装置的正常装置操作期间移动到电介质内的不同位置的组分(除自由电子以外)。实例包含以其它方式化学计量的材料中的原子空位及原子间隙。特定实例性移动掺杂剂包含在非晶氧化物或结晶氧化物或者其它含氧材料中的氧原子空位、在非晶氮化物或结晶氮化物或者其它含氮材料中的氮原子空位、在非晶氟化物或结晶氟化物或者其它含氟材料中的氟原子空位及非晶氧化物或结晶氧化物中的间隙金属原子。可使用一种以上类型的移动掺杂剂。其中接纳移动掺杂剂的实例性电介质包含能够基于移动掺杂剂的足够高数量及浓度而具有局部化导电性的适合氧化物、氮化物及/或氟化物。独立于移动掺杂剂的考虑,其内接纳移动掺杂剂的电介质可为或可不为同质的。特定实例性电介质包含TiO2、AlN及/或MgF2。包括氧空位作为移动掺杂剂的实例性可编程材料可包括取决于氧空位的位置及氧空位在其被接纳的位置中的数量而处于至少一个经编程电阻状态的TiO2与TiO2-x的组合。包括氮空位作为移动掺杂剂的实例性可编程材料为取决于氮空位的位置及氮空位在其被接纳的位置中的数量而处于至少一个经编程状态的AlN与AlN1-x的组合。包括氟空位作为移动掺杂剂的实例性可编程材料可为取决于氟空位的位置及氟空位在其被接纳的位置中的数量而处于至少一个经编程电阻状态的MgF2与MgF2-x的组合。作为另一实例,移动掺杂剂可包括含氮材料中的铝原子间隙。
又一些实例性可编程材料包含聚合物材料,例如孟加拉玫瑰红(Bengala Rose)、AlQ3Ag、Cu-TCNQ、DDQ、TAPA及基于荧光素的聚合物。
本文中所揭示的可编程材料以及其它材料可通过任何现存或尚待开发的技术来沉积。实例包含气相沉积(即,化学气相沉积、原子层沉积及/或物理气相沉积)及/或液相沉积,其中的任一者可对一种或一种以上下伏材料具选择性或非选择性。在实例性液相沉积中,可发生表面介导输送(毛细管作用)及/或电动流动。可使用或可不使用润湿剂、表面活性剂或其它表面改质剂。此外且不管沉积方法如何,可随后处理(例如,退火或辐照)任何经沉积材料。
图1到5的实施例将可编程材料35描绘为直接抵靠所述可编程材料被接纳于其间的导电线中的每一者而接纳。在此文档中,当材料或结构相对于彼此存在至少某一物理触碰接触时,所陈述材料或结构“直接抵靠”另一者。相比之下,“在…上方”囊括“直接抵靠”以及介入材料或结构导致所陈述材料或结构相对于彼此无物理触碰接触的构造。或者,一种或一种以上额外材料(例如,一个或一个以上选择装置)可接纳于可编程材料与此些交叉线中的一者或两者之间。可使用任一现存或尚待开发的选择装置,其中晶体管及二极管仅为两个实例。
紧邻电极线可彼此间隔开以(举例来说)通过可编程材料35及/或通过电介质材料来防止两个此种邻近线相对于彼此永久短路。在一个实施例中,外层的第一电极线在阵列内每一处均与内层的第一电极线竖直地间隔开。在一个实施例中,至少部分地通过可编程材料35竖直地位于外层18的个别第一电极线22与内层20的个别第一电极线24之间此两者交叉处而发生此分离。
本发明的实施例包括经垂直堆叠的非易失性存储器单元层阵列,其包括占据所述层中的个别层内4F2的连续水平面积的五个存储器单元。图1到5的实施例仅为此实施例的一个实例。在本文档中,“F”为使用掩模图案的特征边缘形成的最小特征的最小横向特征尺寸,所述掩模图案从形成此些最小特征的材料向外接纳。举例来说,图4图解性地描绘由在每一侧上为2F的粗体线正方形(借此具有4F2的面积)构成的连续水平面积“A”。图4实例中的最小特征宽度“F”由第一电极线22的所描绘个别线宽度及紧邻的此些线之间的空间的宽度表征。在此特定实例中,所描绘最小线宽度与最小空间宽度彼此相等,且为F。个别存储器单元包括其间具有可编程材料35的直接重叠邻近电极线,其中图2到4中的面积A内的五个此些存储器单元标示为个别存储器单元1、2、3、4及5(如小虚线圆圈)。在各图式中为清晰起见,圆圈1、2、3、4及5较小,其中所述存储器单元当然至少囊括其间具有可编程材料35的面对的相应电极的所有表面积。
本发明的实施例包含包括某一连续体积的经垂直堆叠的非易失性存储器单元层阵列,所述连续体积具有多个经垂直定向的存储器单元与多个经水平定向的存储器单元的组合。在本文档的上下文中,经垂直定向的存储器单元由沿水平方向流过可编程材料的主要电流表征。此外,在本文档的上下文中,经水平定向的存储器单元由沿垂直方向流过可编程材料的主要电流表征。历史上,水平交叉点存储器单元如此命名是因为其相对电极通常为水平定向而彼此垂直相对。垂直交叉点存储器单元在历史上如此命名是因为其相对电极相对于彼此横向定向,其中所述电极中的一者为伸长的且沿垂直方向延续。然而,在本文档的上下文中,所提及的存储器单元的垂直或水平定向仅相对于流过可编程材料的主要电流而不管电极的定向如何。不管如何,在一个实施例中,连续体积具有经完全垂直定向的存储器单元与经完全水平定向的存储器单元的组合。在本文档的上下文中,如果流动到电极、从电极流动及在电极之间流动的所有电流均沿水平方向,那么存储器单元为完全垂直定向的。此外,在本文档的上下文中,如果流动到电极、从电极流动及在电极之间流动的所有电流均沿垂直方向,那么存储器单元为完全水平定向的。
图1到5的实施例仅为具有经垂直定向的存储器单元与经水平定向的存储器单元的组合的一个实例性实施例。举例来说,阵列内的存储器单元1为经水平定向的存储器单元,而存储器单元2、3、4及5为经垂直定向的存储器单元。此外,存储器单元1为完全水平定向的,且存储器单元2、3、4及5为完全垂直定向的。不管如何,在一个实施例中,所述阵列包括比经水平定向的存储器单元多的经垂直定向的存储器单元。在一个实施例中,每四个经垂直定向的存储器单元有一个经水平定向的存储器单元。在一个实施例中,所有阵列均包括经垂直定向的存储器单元与经水平定向的存储器单元的组合(相对于其仅仅某一连续体积)。图1到5的所描绘及所描述的实施例仅为具有这些刚刚所述属性中的每一者的一个实例性阵列。
在一个实施例中,非易失性存储器单元阵列包括每单位单元五个存储器单元。在本文档的上下文中,“单位单元”是体现阵列的晶格的所有结构特性且通过三维重复构成所述晶格的最简单多面体。举例来说,考虑图4、6及7。图4描绘由2F×2F侧界定的水平面积。将此面积在存储器单元层12内向内平移到下部层20中的第一电极线24的基底产生图1的阵列10的图6及7中的单位单元40。为清晰起见,单位单元40在图6中展示为空的且在图7中展示为含有存储器单元组件22、24、26及35。
图1到7描绘其中单位单元40为六面体的实施例,所述六面体可为或可不为立方体,且在所描绘的实施例中并非完美立方体。图1到7还描绘其中每单位单元40有五个且仅有五个存储器单元的实施例。尽管如此且不管如何,可将在一个实施例中呈六面体的形式的单位单元40视为具有两个相对面42、44及在相对面42与44之间延伸的四个拐角体积45、46、47及48。(图6)。在一个实施例中,用于所述存储器单元中的四个存储器单元的可编程材料从此些相对面中的一者或另一者延伸到六面体内部所述四个拐角体积中的单个拐角体积内。举例来说,关于图7,拐角体积46构成此单个拐角体积,对于此单个拐角体积且在此单个拐角体积内接纳存储器单元2、3、4及5的可编程材料35。在一个实施例中,除所述四个存储器单元以外的另一存储器单元的可编程材料接纳于所述六面体的与所述单个拐角体积对角相对的拐角体积内。举例来说,在图7中,存储器单元1构成与拐角体积46对角相对的拐角体积48内的此实例性另一存储器单元。
本发明的实施例囊括包括多个单位单元的非易失性存储器单元阵列,所述多个单位单元个别地包括可编程材料的三个竖直区。此些区包括单位单元的至少三个不同存储器单元的可编程材料。在一个实施例中,所述三个区包括所述单位单元的至少四个不同存储器单元的可编程材料,且在一个实施例中包括五个不同存储器单元的可编程材料。图1到7的上述实施例仅为具有这些刚刚所述属性中的每一者的一个实例性实施例。举例来说,将图5视为相对于如图6及7所表示的单个单位单元40展示三个竖直区18、50、20。此些区中的每一者包括单位单元的至少三个不同存储器单元的可编程材料35。换句话说,在所述三个区中的每一者中包含至少一个不同存储器单元。举例来说,竖直区18包括存储器单元3及4的可编程材料,竖直区20包括存储器单元2及5的可编程材料且竖直区50包括存储器单元1的可编程材料。
在一个实施例中,所述竖直区在所述单位单元中的个别单位单元内彼此横向平行延伸,其中图1到7描绘一个此种实例。此实例还描绘其中所述竖直区在所述单位单元中的每一者内具有恒定相应竖直厚度的实施例。在所描绘实例中,集合竖直区具有至少两个不同竖直厚度,其中(举例来说)区18的竖直厚度与区20的竖直厚度相同。此还构成其中三个区18中的竖直最外区及三个区20中的竖直最内区在所述单位单元中的个别单位单元内具有相同厚度且其中此两者中的每一者均比夹在其间的中间区50厚的实例性实施例。
图1描绘其中紧邻对12/14及14/16的经垂直堆叠的存储器单元层彼此间隔开使得无可编程材料接纳于其间的实例性实施例。因此,此些邻近层12与14以及14与16之间的空间可用/由电介质材料填充从而有助于最小化经垂直堆叠的存储器单元层对中的邻近者之间的寄生电相互作用。图8描绘替代实施例阵列10a。已在适当之处使用了来自首先描述的实施例的相似编号,其中用后缀“a”或用不同编号指示一些构造差异。在阵列10a中,可编程材料35a竖直接纳于经垂直堆叠的存储器单元层中的紧邻对中的一者的竖直内层20的第一电极线24与经垂直堆叠的存储器单元层的紧邻对中的另一者的竖直外层18的第一电极线22之间。可编程材料35a可具有与可编程材料35的组成相同的组成或具有与其不同的组成。
图8的实施例可被视为使单位单元沿向下或向上方向中的任一者延伸以囊括可编程材料35a的区中的接纳于经垂直堆叠的存储器单元层12、14、16的紧邻对之间的一者。因此,在此实例中,可每单位单元添加另一存储器单元,其中每一单位单元含有六个存储器单元,其中(在一个实施例中且如所展示)此六个存储器单元占据4F2的水平面积。参见(举例来说)描绘存储器单元1、2、3、4、5、6的图9及10以及描绘单位单元40a的图11。图9及10分别与图3及4相同,但图解性地添加在面积A内占据的所添加存储器单元6的标示。存储器单元6囊括一个层(即,层12)的第一电极线24、紧挨下部层14的第一电极线22及夹在其间的可编程材料35a。图11与图7相同,但另外展示向下延伸以囊括可编程材料35a的单位单元40a。此还构成其中每四个经垂直定向的存储器单元(2、3、4及5)有两个经水平定向的存储器单元(1及6)的实例性实施例。此还仅描绘单位单元内有六个存储器单元的一个实例性实施例,其中除首先所陈述的四个存储器单元以外的两个存储器单元接纳于六面体的与其内接纳首先所陈述的四个存储器单元的单个拐角体积对角相对的拐角体积中。此还构成包括所述单位单元的另一存储器单元(存储器单元6)的可编程材料35a的又一竖直区60(图12)。
图8描绘其中可编程材料35/35a大部分仅接纳于紧邻导电电极线之间的实例性实施例。图13描绘另一实例性阵列10b。已在适当之处使用了来自上述实施例的相似编号,其中用后缀“b”指示一些构造差异。在阵列10b中,可编程材料35b已作为毯覆保形层沉积于每一处。
可将存储器阵列10的个别单位单元40视为包括五个电极线,其中的四者相对于“x”或“y”轴水平延续。对于标示为“n”的个别层12、14、16,在图4中另外将相对于“x”轴延续的那些线24个别地标示为VRi及VRi+1。在图4中另外将相对于“y”轴延续的那些线22个别地标示为VCj及VCj+1。第五线由在图4中另外标示为VV的单个垂直延伸的第二电极线26囊括。下文的表I展示可用于读取、写入或擦除个别层“n”内的图1到7的单元1、2、3、4、5中的任一个别单元的相对电压V的实例性相对绝对值。实例性表I偏压方案可依赖于可为本征或通过选择装置(上文指(举例来说)二极管)的个别单元的电流-电压特性的非线性。
表I
Figure BDA00003280480700101
下文的表II为针对图9中的层n(12)及层n+1(14)的图8到13实施例的存储器单元1、2、3、4、5及6的类似对应表。
表II
Figure BDA00003280480700102
Figure BDA00003280480700111

Claims (44)

1.一种每单位单元包括五个存储器单元的非易失性存储器单元阵列。
2.根据权利要求1所述的阵列,其中每单位单元仅有五个存储器单元。
3.根据权利要求2所述的阵列,其中所述五个存储器单元占据4F2的水平面积。
4.根据权利要求1所述的阵列,其中每单位单元仅有六个存储器单元。
5.根据权利要求4所述的阵列,其中所述六个存储器单元占据4F2的水平面积。
6.根据权利要求1所述的阵列,其包括多个经垂直定向的存储器单元及多个经水平定向的存储器单元。
7.根据权利要求6所述的阵列,其包括比经水平定向的存储器单元多的经垂直定向的存储器单元。
8.根据权利要求6所述的阵列,其中每单位单元仅有五个存储器单元,且每四个经垂直定向的存储器单元有一个经水平定向的存储器单元。
9.根据权利要求6所述的阵列,其中每单位单元仅有六个存储器单元,且每四个经垂直定向的存储器单元有两个经水平定向的存储器单元。
10.根据权利要求1所述的阵列,其中所述单位单元为六面体,所述六面体具有在所述六面体的两个相对面之间延伸的四个拐角体积,且所述五个存储器单元包括可编程材料,所述存储器单元中的四个存储器单元的所述可编程材料从所述相对面中的一者或另一者延伸到所述六面体内部所述四个拐角体积中的单个拐角体积内。
11.根据权利要求10所述的阵列,其中除所述四个存储器单元以外的另一存储器单元的所述可编程材料接纳于所述六面体的与所述单个拐角体积对角相对的所述拐角体积中。
12.根据权利要求11所述的阵列,其中所述四个存储器单元各自为垂直定向的且所述另一存储器单元为水平定向的。
13.根据权利要求10所述的阵列,其中所述单位单元包括六个存储器单元,所述六个存储器单元包括可编程材料,除所述四个存储器单元以外的两个存储器单元的所述可编程材料被接纳于所述六面体的与所述单个拐角体积对角相对的所述拐角体积中。
14.根据权利要求13所述的阵列,其中所述四个存储器单元各自为垂直定向的且所述两个存储器单元为水平定向的。
15.一种包括五个存储器单元的经垂直堆叠的非易失性存储器单元层阵列,所述五个存储器单元占据所述层中的个别层内的4F2的连续水平面积。
16.根据权利要求15所述的阵列,其包括占据所述层中的个别层内的所述4F2的连续水平面积的六个存储器单元。
17.一种包括多个单位单元的非易失性存储器单元阵列,所述多个单位单元个别地包括可编程材料的三个竖直区,所述三个竖直区包括所述单位单元的至少三个不同存储器单元的所述可编程材料。
18.根据权利要求17所述的阵列,其中所述三个竖直区包括所述单位单元的至少四个不同存储器单元的所述可编程材料。
19.根据权利要求18所述的阵列,其中所述三个竖直区包括五个不同存储器单元的所述可编程材料。
20.根据权利要求18所述的阵列,其包括可编程材料的另一竖直区且其包括所述单位单元的另一存储器单元,所述单位单元包括六个不同存储器单元。
21.根据权利要求17所述的阵列,其中所述单位单元为六面体。
22.根据权利要求17所述的阵列,其中所述竖直区在所述单位单元中的个别单位单元内彼此横向平行延伸。
23.根据权利要求17所述的阵列,其中所述竖直区在所述单位单元中的个别单位单元内具有恒定相应竖直厚度。
24.根据权利要求23所述的阵列,其中所述竖直区在所述单位单元中的个别单位单元内具有至少两个不同竖直厚度。
25.根据权利要求24所述的阵列,其中所述竖直区在所述单位单元中的个别单位单元内具有仅两个不同竖直厚度。
26.根据权利要求25所述的阵列,其中所述三个竖直区中的竖直最外区及竖直最内区在所述单位单元中的个别单位单元内具有相同厚度。
27.根据权利要求26所述的阵列,其中所述三个竖直区中的所述竖直最外区及所述竖直最内区在所述单位单元中的个别单位单元内比所述三个竖直区中的夹在其间的中间区厚。
28.一种包括连续体积的经垂直堆叠的非易失性存储器单元层阵列,所述连续体积具有多个经垂直定向的存储器单元与多个经水平定向的存储器单元的组合。
29.根据权利要求28所述的阵列,其包括比经水平定向的存储器单元多的经垂直定向的存储器单元。
30.根据权利要求29所述的阵列,其中每四个经垂直定向的存储器单元有一个经水平定向的存储器单元。
31.根据权利要求29所述的阵列,其中每四个经垂直定向的存储器单元有两个经水平定向的存储器单元。
32.根据权利要求28所述的阵列,其中所有所述阵列包括多个经垂直定向的存储器单元与多个经水平定向的存储器单元的组合。
33.根据权利要求28所述的阵列,其中所述连续体积包括经完全垂直定向的存储器单元与经完全水平定向的存储器单元的组合。
34.一种经垂直堆叠的非易失性存储器单元层阵列,所述垂直层中的个别层包括:
相应多个经水平定向的第一电极线的竖直外层及竖直内层,所述外层的所述第一电极线相对于所述内层的所述第一电极线交叉;
多个经垂直定向的第二电极线,其延伸穿过所述内层及所述外层,所述经垂直定向的第二电极线中的个别经垂直定向的第二电极线在所述内层中及所述外层中的紧邻相应对的第一电极线之间延伸,所述个别经垂直定向的第二电极线具有第一及第二对相对横向侧;及
可编程材料,其在所述第一对的所述相对横向侧与所述内层及外层中的一者中的所述第一电极线之间且在所述第二对的所述相对横向侧与所述内层及外层中的另一者中的所述第一电极线之间。
35.根据权利要求34所述的阵列,其中所述第一电极线为数据/读出线且所述第二电极线为存取线。
36.根据权利要求34所述的阵列,其包括竖直地处在所述外层的个别第一电极线与所述内层的个别第一电极线之间此两者交叉处的可编程材料。
37.根据权利要求34所述的阵列,其中所述外层的所述第一电极线在所述阵列内每一处均与所述内层的所述第一电极线竖直地间隔开。
38.根据权利要求37所述的阵列,其中所述外层的所述第一电极线与所述内层的所述第一电极线至少部分地通过在所述外层的个别第一电极线与所述内层的个别第一电极线之间此两者交叉处的可编程材料竖直地间隔开。
39.根据权利要求34所述的阵列,其中所述外层的个别第一电极线相对于所述内层的个别第一电极线以约90°交叉。
40.根据权利要求34所述的阵列,其中所述第一对及第二对相对横向侧相对于彼此以约90°定向。
41.根据权利要求34所述的阵列,其中可编程材料沿圆周完全包围所述外层内的个别经垂直定向的第二电极线。
42.根据权利要求34所述的阵列,其中可编程材料沿圆周完全包围所述内层内的个别经垂直定向的第二电极线。
43.根据权利要求34所述的阵列,其中可编程材料沿圆周完全包围所述内层及外层内的个别经垂直定向的第二电极线。
44.根据权利要求34所述的阵列,其中所述经垂直堆叠的存储器单元层的紧邻对至少部分地通过竖直地被接纳于所述经垂直堆叠的存储器单元层的所述紧邻对中的一者的所述竖直内层的所述第一电极线与所述经垂直堆叠的存储器单元层的所述紧邻对中的另一者的所述竖直外层的所述第一电极线之间的可编程材料而彼此间隔开。
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CN103238215B (zh) 2017-02-15
US20150078056A1 (en) 2015-03-19
US20120140542A1 (en) 2012-06-07
TWI484621B (zh) 2015-05-11
WO2012074662A3 (en) 2012-07-26
EP2647048B1 (en) 2016-02-03
US9454997B2 (en) 2016-09-27
KR20130088167A (ko) 2013-08-07
KR101474673B1 (ko) 2014-12-17
JP5699225B2 (ja) 2015-04-08
EP2647048A2 (en) 2013-10-09
TW201230300A (en) 2012-07-16
JP2014502050A (ja) 2014-01-23

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