TWI233204B - Nonvolatile memory element and associated production methods and memory element arrangements - Google Patents

Nonvolatile memory element and associated production methods and memory element arrangements Download PDF

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TWI233204B
TWI233204B TW092119191A TW92119191A TWI233204B TW I233204 B TWI233204 B TW I233204B TW 092119191 A TW092119191 A TW 092119191A TW 92119191 A TW92119191 A TW 92119191A TW I233204 B TWI233204 B TW I233204B
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memory element
electrode
volatile memory
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TW200408119A (en
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Franz Schuler
Georg Tempel
Laurent Breuil
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Infineon Technologies Ag
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    • H—ELECTRICITY
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
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    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Switching materials based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Switching materials based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors
    • H10N70/8845—Carbon or carbides
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
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    • G11—INFORMATION STORAGE
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    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/33—Material including silicon
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
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    • G11C2213/79—Array wherein the access device being a transistor

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  • Semiconductor Memories (AREA)

Abstract

The invention relates to a nonvolatile memory element and to associated production methods and memory element arrangements, in which case, in order to reduce a forming voltage, a first electrode (1) has a field amplifier structure (4) for amplifying a field strength of an electric field (E) generated by means of a second electrode (3) in a changeover material (2).

Description

1233204 修正 曰 M3t 92119191 五、發明說明（1) 發明之領域 記，i::!'關於一種非揮發記憶體元件、其產製方法及 2發性記憶體元件…在生成步驟之後，可知至才：有 用預：：ί傳導性狀態，且傳導狀態間的轉換，可藉由使 的計劃電壓進行-次或多次的影響。 件上:’至第一 ’係說明-般形式的非揮發記憶體元 件=間化的區段圖與簡化的u—丨特性曲線，如美國專利 5’360，981中所述者。 根據第一圖A，此非揮發記憶體元件具有一第一電極 成於其上的一轉換材質2以及一第二電極3，該電極工 與-極3對應連接用於電壓的應用與電場E的產生。該轉換 材質2包含如飽和的氫非晶矽半導體材質（氫化非晶型 矽），其具有P-型掺質。例如，一電傳導材質，較佳為鉻 係用作為該第一電極1。該第二電極3之合適的選擇，係造 成該轉換材質2之類比轉換作用或是數位轉換作用。根據 第一圖A，例如使用釩（V)、鈷（Co)、鎳（Ni )盥（Tb)作 (w)或銀（Ag)則是會具有數位轉換作用。 此非揮發記憶體元件的特性是特別需要一生成步驟， 其係在開始進行，且可在第一位置形成該記憶體元件之實 際非揮發記憶體性質。 根據第一圖B，例如初始存在的線性U - I特性曲線，僅1233204 Amendment M3t 92119191 V. Description of the invention (1) Fields of invention, i ::! 'About a non-volatile memory element, its production method, and a secondary memory element ... After the generation step, we can only know that : Useful Pre :: ί Conductive state, and the transition between conductive states can be effected one or more times by the planned voltage. On the file: ‘to the first’ are non-volatile memory elements in the general form = interstitial segment graph and simplified u-characteristic curve, as described in U.S. Patent 5’360,981. According to the first figure A, this non-volatile memory element has a conversion material 2 and a second electrode 3 on which a first electrode is formed. The electrode is connected to the -pole 3 for voltage application and electric field E. The generation. The conversion material 2 contains, for example, a saturated hydrogen amorphous silicon semiconductor material (hydrogenated amorphous silicon), which has a P-type dopant. For example, an electrically conductive material, preferably chromium, is used as the first electrode 1. A suitable choice of the second electrode 3 is to make an analog conversion effect or a digital conversion effect of the conversion material 2. According to the first figure A, for example, the use of vanadium (V), cobalt (Co), nickel (Ni) (Tb) as (w) or silver (Ag) has a digital conversion effect. The property of this non-volatile memory element is a special need for a generation step, which is performed at the beginning and can form the actual non-volatile memory properties of the memory element in the first position. According to the first graph B, for example, the linear U-I characteristic curve that initially exists, only

第4頁 2004.10.li.Q04 1233204 五 發明說明（2) __ 藉由應用-生成電壓Fa ’係 性曲線範圍。此生成電壓Fa係相對的二圖c之二體特 係於5至3。伏特之間，根據 U :圍 特進行生成步驟。 风也座h二-20伏 因此，僅在此生成步驟已進 電壓FA於該轉換材質2之後， 疋在使用此生成 有非揮發記憶體性質，：例二一 狀態或是特性曲線分支開（Οί〇與關（qff) $ ===生_ :該㈣之特性曲線’鉻(Cr)係被用作為電極：圖 有P-型摻質之飽和的氫非晶矽係作為轉換材質2。、且/、 根據第一圖C在生成步驟之徭所γ ―、 向來回移動。 你/口則頭方 更 可藉由 該傳導 態或特 另一設 傳導性 兩傳導 或者是 根據第 性狀態 精確地，例如一轉換材質2且古 φ 柿闲机舛+ ^有該傳導狀態開（ON) 使用5又计電壓Verase約2 · 5伏特而妯£ 饤_被再次设計，因 性狀悲或特性曲線分支開（〇 N) ㈣ b 、^ )轉變至其他傳導 性曲線分支關（OFF )。同樣的方斗、士 7手—Γ生狀 万式中，例如可藉由 計電壓Vwr i t e - 3伏特，於該轆抱 Λ轉換材質2再次產生該 狀態開（0Ν)。在此方式中，哕#F αα & 。亥知KA的特性曲線中該 性狀態開（0N)與關（OFF)之間可 J」向别或向後轉變， 影響低於該設計電壓設計的個別的讀取電壓V ， -圖C可為i伏特。由於該族“特性曲線或是；導 開（OfO與關（OFF)—旦設計好了，在此轉換材質2中Page 4 2004.10.li.Q04 1233204 V. Description of the invention (2) __ The voltage curve range is generated by applying-Fa. The generated voltage Fa is relative to the two-body c-body, which is 5 to 3 in particular. Between the volts, the generation step is performed according to the U: circle. The wind is also h-20 volts. Therefore, only after this generation step has applied the voltage FA to the conversion material 2, 疋 has non-volatile memory properties when using this generation: Example 21 state or characteristic curve branch ( Οί〇 与 关 (qff) $ === 生 _: The characteristic curve of the Cr (Cr) system is used as the electrode: P-type doped saturated hydrogen amorphous silicon system is used as the conversion material 2. , And /, according to the first figure C in the step of the generation step γ, move back and forth. You / mouth, the head can even conduct two conductions through the conductive state or another conductive state, or according to the first state Precisely, for example, a conversion material 2 and the ancient φ persimmon idler 舛 + ^ have the conduction state ON (ON) using 5 and counting the voltage Verase about 2 · 5 volts and 妯 £ 饤 _ is redesigned because of the sadness or The characteristic curve branch open (〇N) ㈣ b, ^) transitions to other conductivity curve branch off (OFF). In the same square bucket and fighter 7-handed style, in the Wan style, for example, the voltage can be calculated by the voltage Vwr i t e-3 volts, and the material 2 can be used to generate the state on (0N) again. In this way, 哕 #F αα &. In the characteristic curve of Haizhi KA, the state between ON (0N) and OFF (OFF) can be changed from “J” to different or backward, which affects the individual read voltage V that is lower than the design voltage design,-Figure C can be i volts. Because the family ’s “characteristic curve or; OfO and OFF (off)-once designed, in this conversion material 2

第5頁 五、發明說明（3) ί::改變’所以係以相關的讀取電流獲得-非揮發記憶 段圖第Γ Γ說0m用的非揮發記億體元件之簡化ε 上形成P -掺雜的飽和的氫非 卜摻雜餘和的氫非晶石夕声2B :飞拉非人日日石二'，該石夕表面係與 轉換材質2更且右去妓/ 接合。向著第二電極3，該 P — n-i纟士谨。跄姑未摻雜的雜飽和的氫非晶矽，因而得到 f+ > Ί 。 a此種形式的非揮發記憶體元件之優點為 用於所需的味出牛ΐ 言，電極材質較不是關鍵， 材質，g 1日i ν 1 Α之甩壓係高於根據第一圖Α之該轉換 Γ因。 不能作為往後大部分非揮發記憶以的生產 第二圖B係說明在生成| 卜 曲線，造成—改善的設計，^因：後，、簡化的族κΑ特性 與關（_)間較高的距離。口為不问的傳導性狀態開⑽） 發明之概述 所以本發明之目的係 產製方法及記憶體元件排 '、：揮發記憶體元件、其 體電路中。特別地，本發明之目用整合於習用之半導 形成該非揮發記憶體作用。 糸優化該生成步驟，以 根據本發明，本發明 第1項中該非揮發記憶體元件之特徵、係藉由申請專利範圍 由申請專利範圍第8項之方以二二此目的之達成係藉 24項之記憶體元件排列之特徵。申請專利範圍第22至5. Description of the invention on page 5 (3) ί :: Change is obtained by the relevant read current-Non-volatile memory segment chart No. Γ Γ says that 0m of the non-volatile memory element used for simplification ε forms P- Doped saturated hydrogen non-bubble doped co-doped hydrogen amorphous stone Xisheng 2B: Feilai non-human sun and sun stone 2 ', the surface of this stone and the conversion material 2 is more right to prostitute / join. Towards the second electrode 3, the P — n-i 纟 Shi Jin. Un-doped hetero-saturated hydrogen amorphous silicon is obtained, thus f + > Ί is obtained. a The advantage of this type of non-volatile memory element is that it is used for the required taste. The electrode material is less critical. The material, g 1 day i ν 1 Α has a higher pressure than the first figure Α. This transforms the Γ factor. Can not be used as the production of most non-volatile memory in the future. The second figure B illustrates the generation of | Curves, resulting in-improved design, because: the later, the simplified family κΑ characteristics and the higher (_) distance. The mouth is open regardless of the conductive state.) Summary of the invention Therefore, the object of the present invention is the production method and the memory element row, and: the volatile memory element and its body circuit. In particular, the purpose of the present invention is to form the non-volatile memory by integrating into a conventional semiconductor.糸 Optimize the generation step so that according to the present invention, the characteristics of the non-volatile memory element in the first item of the present invention are obtained by applying the patent scope by the party applying for the eighth item of the patent scope to achieve the two or two purposes. The characteristics of the memory element arrangement of the item. Patent application range 22 to

第6頁 2004.10.1L 〇〇6 1233204 _案號 92119191 月 五、發明說明（4) 特別係透過使用至少一電場放大器結構於至少一 極，用於放大該轉換材質中電場的場強度，該生Page 6 2004.10.1L 〇〇6 1233204 _ Case No. 92119191 May V. Description of the invention (4) Especially by using at least one electric field amplifier structure at least one pole, it is used to amplify the field strength of the electric field in the conversion material.

需的該電壓係很高，係可被大卜& A 件可被首次連結或組合於Κ = =些記憶體元 路。 白用的丰導體電路，例如CMOS電 該電場放大器結構較佳係包含該電極之 出至該轉換材質中，例如係一小尖物（ti 出物/、係犬 或是邊緣（edge)，角度較佳係s9H) 合的非揮發記憶體元件中以特別簡單的= 的電場高峰或電場增加。 飞 了形成所需 該轉換材質較佳係包含飽和的氫非 其亦可使用多層結構，1該電 ：：導體材質’ 關於生產一非揮發記憶體元件的=係》：=材質。 中形成-凹處’以及形成該第一電極，哕」在-輔助層 電傳導材質充填，因此可在後續的步驟=係第一 式形成該電場放大器結構。 特別簡單的方 在此範例中，該電傳導材質較佳 在該凹處區域中生成—銜接凹處，出^方式沉積，其 式’該電傳導材質被回蝕至少至該=由非等向性的蝕刻方 由非等向性的钱刻方式，將該輔η層的表…及藉 部。在此方式中，在第一電極形成I餘至该凹處的底 導致所欲的電場增加’且因而 ^的小尖物（tip)，其 然而，在另一方面，亦可能=生成電壓。 傳導材質後退至少至該輔助層的2磨光的方法造成該電 ’且藉由後續選擇性The required voltage system is very high, and the system can be connected for the first time or can be combined with K = = some memory cells. White conductor circuits, such as CMOS electrical, the structure of the electric field amplifier preferably includes the output of the electrode to the conversion material, such as a small pointed object (ti-out / / dog or edge, angle) Preferably, the non-volatile memory element with s9H) has a particularly simple electric field peak or electric field increase. It is necessary to form the material. The conversion material preferably contains saturated hydrogen. It can also use a multilayer structure. 1 The electrical :: conductor material ’== >>> material for the production of a non-volatile memory element. In the formation of the "recess" and the formation of the first electrode, the "on-auxiliary layer" is filled with electrically conductive material, so the electric field amplifier structure can be formed in a subsequent step. Particularly simple. In this example, the electrically conductive material is preferably generated in the recessed area-connecting the recesses and depositing it in a manner of "the electrically conductive material is etched back at least to the = by anisotropic The non-isotropic money engraving method uses the non-isotropic money engraving method to add the surface of the auxiliary η layer ... and the borrowing part. In this way, forming a small tip at the first electrode to the bottom of the recess results in a desired increase in the electric field 'and thus ^, however, on the other hand, it may also = generate a voltage. The 2 polishing method in which the conductive material recedes at least to the auxiliary layer causes the electricity ′ and through subsequent selectivity

’4· 10· 12· 007 1233204 五 '發明說明（5) 的钱刻方式將該輔助層回钱一預弁 第-電極獲得非常尖的邊緣或角先其^=所，此可，該 大或是電場增加。 〃 ^ 奴的電場放 =另-方面’在該凹處中可藉由蝕刻 少一預先決定量的電傳導材質， Y移除至 構造的電傳導層，其中在該凹處區薄 且最後藉由非等向性蝕刻方法或—間付:妾凹處’ 導層回蝕至少至該輔助戶之Is ]隔物方法，將該電傳 一 乂 表面。在藉由非等向性蝕刿方 / 回蝕^驟之後，該輔助層被回蝕至少至該彳r接二声 的底部區域，可在該轉換材質之 二二 ^ 物結構所造成的電場放大器結二tf::再;;由該間隔 的生成電壓可被大幅降低。構次電场增加’因此該所需 關於記憶體元件排列方面， 列於矩陣形式中，且其連接係藉：排列意=件係排 與排列在列形式的字元線=攔：式的位元線 -電極係經由一歐姆接合或二極；接巧體的第 一半導體基質中所形成的個別 口 接電！·生連接至 貝的表面上的帶狀形式中，將 + V體基 電極進行圖案化。 將形成個別位元線的個別第二 每-個非揮$ u面φ在厂己憶體元件的排列中’對於 擇電晶體，該半導體基質中可形成-選 汲極區域的制層的字元線與作為第一源極/ 區域係電性連接至該記憶體元件的個別第'4 · 10 · 12 · 007 1233204 Five' Description of the invention (5) The money engraving method returns the auxiliary layer to the money.-The electrode obtains a very sharp edge or angle first. ^ = So, this, this big Or the electric field increases. ^ ^ The electric field of the slave = another-aspect. In this recess, a predetermined amount of electrically conductive material can be etched, and Y is removed to the structured electrically conductive layer, where the recess is thin and finally borrowed. The non-isotropic etching method or —intermittent payment: pit recess' conducting layer is etched back to at least the Is] spacer method of the auxiliary household, and the telegraph is transmitted to the surface. After the non-isotropic etching / etchback step, the auxiliary layer is etched back to at least the bottom region of the second sound, which can be caused by the electric field caused by the second material structure of the conversion material. Amplifier junction two tf :: re ;; The voltage generated by this interval can be greatly reduced. The formation of the secondary electric field is increased. Therefore, the required arrangement of the memory elements is listed in a matrix form, and its connection is based on: arrangement meaning = line of elements and word lines arranged in columns = block: The element wire-electrode system is connected through an ohmic junction or a two-pole; the individual ports formed in the first semiconductor matrix of the junction body are connected to electricity! In a strip-like form connected to the surface of the shell, the + V-body-based electrode is patterned. The individual second non-volatile surface of the individual bit lines will be formed in the arrangement of the body memory element. For the selective crystal, the word of the layer of the selective drain region can be formed in the semiconductor matrix. The element line and the individual source / area system are electrically connected to the individual source of the memory element.

1233204 -___年月 日 修正 五、發明說明（6) ' --- 亦可獲得新的高整合性的非揮發記憶體元件排列。 本發明之其他優點係如申請專利範圍依附項中 發明之詳細說明 本發明係藉由根據第一圖A之記憶體元件為基礎，說 明簡化的非揮發記憶體元件，相同的元件符號係指相同或 對應的層或元件。然而，特別地，該轉換材質2亦具有多 層的結構，特別係具有不同摻雜之無定型半導體材質。 第一實施例 根據第三圖A，根據第一實施例該非揮發記憶體元件 SE包含一轉換材質2與兩個電傳導電極1與3於該轉換材質 2，可使用一電壓於該電極，且可在該轉換材質2中產生'一 電場E。在此範例中，該轉換材質2具有特殊的性質，其中 在生成步驟後，至少有兩個不同的傳導性狀態，其中可藉 由使用預先決定的設計電壓重複影響轉換。 曰 飽和的氫非晶矽或對應的多層結構較佳係作為該轉換 材質2，非晶矽的製備係藉由所謂的發光釋放技術（^丨 discharge technique)。再者，該第一電極丨與該第二電 極2係包含合適的電傳導材質，其較佳係具有金屬。 適合作為該第一電極與第二電極丨與3以及該轉換材質 2之可能材料表列如下，仍有其他材質是可接受的：1233204-___ year month day amendment V. Description of the invention (6) '--- A new highly integrated non-volatile memory element arrangement can also be obtained. Other advantages of the present invention are the detailed description of the invention in the appended items of the scope of patent application. The present invention is based on the memory element according to the first figure A to explain a simplified non-volatile memory element. The same element symbols refer to the same Or corresponding layers or elements. However, in particular, the conversion material 2 also has a multi-layered structure, especially an amorphous semiconductor material with different doping. First Embodiment According to the third figure A, according to the first embodiment, the non-volatile memory element SE includes a conversion material 2 and two electrically conductive electrodes 1 and 3 in the conversion material 2. A voltage can be applied to the electrode, and 'An electric field E can be generated in the conversion material 2. In this example, the conversion material 2 has special properties. After the generation step, there are at least two different conductive states, and the conversion can be repeatedly affected by using a predetermined design voltage. A saturated hydrogen amorphous silicon or a corresponding multilayer structure is preferably used as the conversion material 2. The preparation of the amorphous silicon is performed by a so-called light emission discharge technique. Moreover, the first electrode 丨 and the second electrode 2 include a suitable electrically conductive material, and they preferably have a metal. The possible materials suitable for the first and second electrodes 丨 and 3 and the conversion material 2 are listed below. There are still other materials that are acceptable:

2004.10.12.009 1233204 _案號92119191_年月日_ 五、發明說明（7) 第一電極 轉換材質 第二電極 不鏽鋼 p-n-i-接雜的 a-Si : Η 金(Au)或銘(A1) 不鏽鋼 ρ-η-ι-接雜的 a-Si : Η 金(Au)或鋁(A1)或鉻化鎳(NiCr) §S(Cr) p-n-卜摻雜的a-Si : Η 或 n-p-丨-摻雜的a-Si : Η 或 p-i-n-摻雜的 a-Si : Η 錯(ΑΓ)或絡(Cr) 鉻(Cr) Ρ-摻雜的a-Si : Η 釩(V) 鉻(Cr) ρ-摻雜的a-Si : Η 銀(Ag)、鋁(A1)、鉻(Cr)、錳 (Μη)、鐵(Fe)、鎢(W)、釩(V)、 鎳ΓΝΠ ' 姑(Co)、鋁(Mo)、鉛(Pd) 絡(Cr) a-SiC ： Η 鎳(ΜΓ) 絡(Cr) a-SiN : Η 或 a-SiC ： Η 鎳(ΝΓ)或鉬(Mo) ia(Al) 四面體的無定型碳 鋁(AJ) 電化學的鈍陰極 硫硒碲玻璃 (chalcogenide glass)具有 超過30%的銀(Ag) 可氧化的銀(Ag) (陽極） Indium-TiN 氧化物 硫硒硫合金 (Chaicogenide alloy) 金屬 目前為止在該轉換材質2中的製程尚未被完全闡明， 雖然其假設特別是當使用非晶矽時，使用預先決定的電壓 在非晶型材質中形成該轉換材質電傳導或金屬細絲，自使 用相反電壓或相反電流之後，該預先決定的電壓係被破 壞。 本發明的重點在於至少一電極1或3具有至少一電場放 大器結構4，用以放大該轉換材質2中該電場E之電場強 度。因此，根據第三圖A在第一電極1形成一小尖物4作為 電場放大器結構，其造成該轉換材質2中電場E的顯著放 大。此電場的放大造成電場的高峰於該轉換材質2中，其 具有較佳的效應特別係對於上述之生成步驟。 根據第三圖B，如第三圖A中所述的非揮發記憶體元件 SE與電場放大器結構4，一般所需要的生成電壓FA約20伏2004.10.12.009 1233204 _Case No. 92119191_Year_Month__ V. Description of the invention (7) First electrode conversion material Second electrode stainless steel pni-doped a-Si: Η Au (Au) or Ming (A1) stainless steel ρ -η-ι-doped a-Si: Η gold (Au) or aluminum (A1) or nickel chromate (NiCr) §S (Cr) pn-b-doped a-Si: Η or np- 丨- Doped a-Si: Η or pin-doped a-Si: erbium (Al) or complex (Cr) chromium (Cr) P-doped a-Si: Η vanadium (V) chromium (Cr) ρ-doped a-Si: Η silver (Ag), aluminum (A1), chromium (Cr), manganese (Mn), iron (Fe), tungsten (W), vanadium (V), nickel ΓΝΠ ' Co), aluminum (Mo), lead (Pd) complex (Cr) a-SiC: Η nickel (ΜΓ) complex (Cr) a-SiN: Η or a-SiC: Η nickel (NΓ) or molybdenum (Mo) ia (Al) Tetrahedral amorphous carbon aluminum (AJ) electrochemically passive cathode chalcogenide glass with over 30% silver (Ag) oxidizable silver (Ag) (anode) Indium-TiN oxide Selenium-selenium-sulfide alloy (Chaicogenide alloy) The process of the metal in this conversion material 2 has not yet been fully elucidated, although it is assumed that, especially when using amorphous silicon, a predetermined voltage is used Amorphous material is formed in the converter material or the electrically conductive metal filament, the voltage from the line voltage with an opposite or opposing currents after the predetermined been corrupted. The main point of the present invention is that at least one electrode 1 or 3 has at least one electric field amplifier structure 4 for amplifying the electric field strength of the electric field E in the conversion material 2. Therefore, according to the third figure A, a small tip 4 is formed on the first electrode 1 as an electric field amplifier structure, which causes the electric field E in the conversion material 2 to be significantly enlarged. The amplification of this electric field causes the peak of the electric field in the conversion material 2 to have a better effect, especially for the above-mentioned generating step. According to the third diagram B, as shown in the third diagram A, the non-volatile memory element SE and the electric field amplifier structure 4 generally require a generated voltage FA of about 20 volts.

第10頁 2004.10.12.010 1233204 五 、發明說明（8) 特，係轉變至例如降低的生成 可如習用CMOS可用之電㈣圍。’電屢範圍 體元件中該電場放大器結構4 〜非揮發記憶 至習用的半導體元件中，=得此兀件可被首次整合 操作，較佳係低於5伏特。11圍低於10伏特進行 路可被簡r因而可大幅降:二= 根據第二圖C，該揮於守愔鹏一 、 在生成步驟之後具有修飾族κ ::或質2， J低的生成電壓FB。在此範例知 線一族係以κΑ表示。因此，在兮笛 ^ α 1议Α 特性曲 放大結構4，不僅係降低的生在：電弟壓電= 二形成的電場 :2或該非揮發記憶體元職之特 二材 範圍‘。 相反的記號其係延伸至正的電壓 :此，不僅可以降低生成電壓，亦可將該計劃電壓 Verase /、Vwrite用於個另ij的分界條件。 弟一貫施例 J四圖A與第四圖“系根據本發明之第二實施 ::揮务記憶體元件之簡化的區段圖與簡化的u 曲 線，在下列重複的說明中相 萌 的層或元件。 门的凡件付说係指相同或對應 根據第四圖A 僅有-小尖物4Α生成在該第 1 ’該小尖物4Α對面亦有生成對應的小尖物4β，★為= 1233204 五、發明說明（9) 二電極3之電場放大器結構，因此可生成兩方向的電場放 大’亦即正電壓與負電壓。由於該非揮發記憶體元件sE中 ，電場放大器結構4A與4B，可再次降低該生成電壓，根據 四圖B可在正電壓範圍將特性曲線自&壓縮至h。因此， 亦可能不但降低用於存寫或是將傳導性狀態自關⑺改 變到開⑽）的設計電壓Vwme，亦可降低用於消去該非揮發 圮憶體元件SE或用於改變開（0N)傳導性狀態至該關（〇FF) 傳導性狀態的設計電壓。除了大幅降低生成電壓F ， 用於在該轉換材質2中或是非記憶體元件SE中產生該非揮 發記憶體行為，由於該電場放大器，可獲得特性曲線的使 用，特別係降低所需的存寫與消除電壓。在此方式中，可 了解新的非揮發記憶體與大副降低的操作電壓，以及大幅 改善的電流或電力的節省。 田 根據该第一與該第二實施例，一小尖物係生成在該 一電極1與/或該第二電極3，作為電場放大器結構。g 而，在相同的方式中，該電極丨與3的其他突出物，例:妒 成角或是邊緣，亦可作為電場放大器結構，其係突^ 轉換材質2中，且至少局部放大其中該電場£的電場強产二 該電極1與3中該小尖物、角或邊緣的角度，較佳係為ς 角，亦即角度S 90度，因此可利用非常簡單的方式形= 部的電場高峰。然而，如下所示之方法，特 ^ ° 又有效節省成本^法。 ^係其為間單 第三實施例 第五圖Α至第五圖Ε係根據本發明之第三實施例，_ J，間化Page 10 2004.10.12.010 1233204 V. Description of the invention (8) Specially, the system is transformed to, for example, reduced generation, and can be used as a conventional CMOS electrical enclosure. The electric field amplifier structure of the body element is 4 ~ non-volatile memory to the conventional semiconductor element. This element can be integrated and operated for the first time, preferably less than 5 volts. The path between 11 and below 10 volts can be reduced by Jane, so it can be greatly reduced: Second = According to the second figure C, this wave is guarded by Peng Yi. After the generation step, it has the modified family κ ::: or prime 2, J is low Generate voltage FB. In this example, the line family is represented by κA. Therefore, in the Xi Di ^ α 1 discussion A characteristic song magnified structure 4, not only is the reduced life: the electric piezo = the electric field formed by two: 2 or the characteristics of the non-volatile memory elementary two range ‘. The opposite sign extends to a positive voltage: this can not only reduce the generated voltage, but also use the planned voltages Verase /, Vwrite for a separate boundary condition. This is the second embodiment of the present invention. Figure A and Figure 4 are the second embodiment of the present invention: a simplified section diagram and a simplified u-curve of the memory device, in the following repeated description. Or the element of the door means that the same or corresponding according to the fourth figure A only-small tip 4A is generated on the 1 'opposite to the small tip 4A also has a corresponding small tip 4β, ★ is = 1233204 V. Description of the invention (9) The electric field amplifier structure of the two electrodes 3 can generate electric field amplification in two directions' that is, positive voltage and negative voltage. Because of the non-volatile memory element sE, the electric field amplifier structures 4A and 4B, The generated voltage can be lowered again, and the characteristic curve can be compressed from & to h in the positive voltage range according to the four figures B. Therefore, it may not only be used to save or write or change the conduction state from off to on) The design voltage Vwme can also reduce the design voltage used to eliminate the non-volatile memory element SE or to change the ON (0N) conductive state to the OFF (0FF) conductive state. In addition to greatly reducing the generated voltage F, Used in this conversion material 2 Or the non-volatile memory behavior occurs in the non-memory element SE. Because of the electric field amplifier, the use of the characteristic curve can be obtained, especially to reduce the required write and erase voltages. In this way, a new non-volatile memory can be understood According to the first and second embodiments, a small pointed object is generated on the first electrode 1 and / or the second electrode 3 according to the first and the second embodiments. , As the structure of the electric field amplifier. G In the same way, the electrode 丨 and other protrusions of 3, for example: jealous angle or edge, can also be used as the structure of the electric field amplifier, which is converted into the material 2, And at least partially amplify the electric field in which the electric field is generated. The angle of the small tip, angle or edge in the electrodes 1 and 3 is preferably the angle, that is, the angle S 90 degrees, so it can be used very simply. The mode shape = part of the electric field peak. However, the method shown below, especially ^ ° is also effective to save costs ^ method. ^ It is the third embodiment of the fifth figure A to fifth figure E is according to the present invention The third embodiment, _ J, interstitial

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二月生產一非揮發記憶體元件之主要方法步驟， ::說明中相同的元件符號係指相同或對件 =五圖A’首先在一載體材質τ上形成一輔；件且 •口只層中生產一凹處V。、該載體材質τ較佳係一半 (s〇，其中已藉由sti(淺溝渠隔離，Shallow Tren= 土貝 Isolation)方法形成活性區域，且摻雜槽與/或完全 分完成的半導體元件已存在。當然，除了該較佳的/導 體基質之外，亦可使用其他載體材質，例如s〇I或氧化 石夕、藍寶石石夕晶（silicon on sapphire)等。 如同該輔助層ϊ，較佳係一介電質層或絕緣層沉積於 該載體材質Τ的整個區域上且具有凹處V，但是其亦可能係 使用另一材質與電性傳導材質。 此 在形成該凹處ν的過程中，其組成一溝渠或一孔洞於 該輔助層I中，形成一電阻層，而後藉由習用光平板印刷 方法進行圖案化。之後，藉由該圖案化的電阻層（未出示 於圖中）將至少一部分的輔助層I移除，其中根據第五圖 A，該輔助層I係被完全移除至該載體材質τ，且因此生成 一深溝渠或深孔洞做為該凹處V。最後，該電阻層被移 除，且可能進行〆清洗步驟，以移除可能產生的污染物。 較佳係藉由非等向性姓刻，例如反應性的離子蝕刻 (RIE)形成該凹處，因此可獲得該凹處V之垂直壁。 根據第五圖B，在/後續步驟中，以第一電性傳導材質填 充該凹處V，用於形成一第一電極1，其中在該輔助層I的 表面上進行一金屬（如鎢）的化學沉積方法（CVD，化學蒸氣The main method steps for the production of a non-volatile memory device in February. The same component symbols in the description refer to the same or opposite parts = five pictures A 'First form a subsidiary on a carrier material τ; A recess V is produced in the middle. The carrier material τ is preferably half (s0, in which the active region has been formed by the sti (Shallow Trench Isolation) method, and a doped trench and / or a completely completed semiconductor element already exists . Of course, in addition to the preferred / conductor matrix, other carrier materials can also be used, such as SiO or oxidized stone, silicon on sapphire, etc. Like the auxiliary layer ϊ, preferably A dielectric layer or an insulating layer is deposited on the entire area of the carrier material T and has a recess V, but it may also use another material and an electrically conductive material. In the process of forming the recess ν, It is composed of a trench or a hole in the auxiliary layer I to form a resistance layer, and then patterned by the conventional photolithography method. After that, the patterned resistance layer (not shown in the figure) will be at least A part of the auxiliary layer I is removed. According to the fifth figure A, the auxiliary layer I is completely removed to the carrier material τ, and thus a deep trench or deep hole is generated as the recess V. Finally, the resistor Layers removed It is also possible to perform a plutonium cleaning step to remove possible contaminants. The recess is preferably formed by an anisotropic surname, such as reactive ion etching (RIE), so that the recess V can be obtained. Vertical wall. According to the fifth figure B, in / the subsequent steps, the recess V is filled with a first electrically conductive material for forming a first electrode 1, and a metal ( Such as tungsten) chemical deposition methods (CVD, chemical vapor

T233204T233204

沉積，Chemical Vap0r Depositi〇n)，在該凹處v的區域 中，而後在該沉積材質1中生成一銜接的凹處n。 如上所述，如第一電極丨之電性傳導材質，亦可自上 述的表中選擇材質或是藉由其他方式生成。 根據第五圖C ,在後續的步驟中，該電性傳導材質丨係 退縮至少至該輔助層I之表面，亦即至該初始表面的相同 程度’利用非等向钱刻方法特別係作為回钱步驟且該結構 中所示係為該第一電極1。因此，該銜接凹處” 被接官或轉型至該凹處v中。 根據第五圖D，而後造成該轉助層J退縮，誃 係作為電場放大器結構餘該第一電極1中，且大幅：、大 ,輔助層1之上。該輔助層較佳係回蝕至 在 底部區域’其造成（-溝渠之）該小尖物或角或邊緣處^之 2二ί成該輔助層1退縮之過程’較佳係藉由非等向性口 蝕步驟於該第一電極丨之材質。 门丨生回 最後，根據第五圖Ε，在該第一電極丨上形成— ^且在其中形成其電場放大器結構4Α，#中开用成轉換材 進：：Γ戈”ϊ構可被用作為材質。在此範例中較佳表係 、和的氫非晶石夕或對應多層之沉積。 ’、 2之矣為了完成該非揮發記憶體元件SE，最後在該轉換姑哲 中的从面*上形成第二電傳導電極3，原則上亦可使用上诚矣 柽才質。取決於個別的應用，隨可進行該第二傳 電極3之平面化與/或圖案化。 r生傳導 例如’藉由沉積含金屬層而形成該第二電極3。Deposition, Chemical Vapor Deposition), in the region of the recess v, then a contiguous recess n is created in the deposition material 1. As mentioned above, for the electrically conductive material of the first electrode, the material can also be selected from the above table or generated by other methods. According to the fifth figure C, in the subsequent steps, the electrically conductive material is retracted at least to the surface of the auxiliary layer I, that is, to the same extent as the initial surface. This step is shown as the first electrode 1 in this step. Therefore, the connection recess ”is taken over or transformed into the recess v. According to the fifth figure D, then the transfer layer J is retracted, and the actinide system is left in the first electrode 1 as the structure of the electric field amplifier, and greatly :, Large, on the auxiliary layer 1. The auxiliary layer is preferably etched back to the bottom area 'which causes (-of the ditch) the small pointed object or corner or edge ^ 2 to become the auxiliary layer 1 shrinking The process' preferably is the material of the first electrode 丨 through an anisotropic etch step. The gate is finally regenerated, and according to the fifth figure E, it is formed on the first electrode 丨 and formed therein. The electric field amplifier structure 4A, # 中 开 is used as a conversion material :: ΓGe "structure can be used as a material. In this example, the preferred series are hydrogen and amorphous crystalline or corresponding multilayer deposition. In order to complete the non-volatile memory element SE, a second electrically conductive electrode 3 is finally formed on the slave surface * in the conversion element. In principle, it is also possible to use the above-mentioned quality. Depending on the individual application, the planarization and / or patterning of the second electrode 3 can then be performed. The second electrode 3 is formed, for example, by depositing a metal-containing layer.

第14頁 2〇04· 10· 12.014 1233204 五、發明說明（12) 第四實施例 第六圖A至第六圖C係根據本發 說明生產一非揮發記憶體元件 貫施例，簡化 複的說明中與第一圖至第四圖相ϋ驟’在下列重 對應的層或元件。 ° 、凡件符號係指相同或 根據第五圖Α與第五圖Β中繁二给> 施行於第四實施例中，因此可夂f例的製備方法，亦 根據第六圖A，在第四實施例中’考以十二的:明。 該凹處V，用於形成一第一電 =傳導材質充填 進行一平面化方法，以造成傳^^ ” B)’首先 輔助層I之表面。較佳係於該鎢層丨 貝 夕退縮至該 (CMP) ’因此可得第六眼中所示曰的區段2化學機械破壞 根據第六圖B，後續造成誃鍤 二、 sdl，例如藉由回餘步驟，以^ s j退縮預先決定的 於其中的邊緣4A作為電場放大器=。一電極1 ’且形成 根據第六圖C，如第二杂# y t上 極1的表面上，生成—轉：；；2列在:輔助層1與該第-電 3係生成於其上，因此可 古取後5亥弟二電傳導電極 記憶體元件。在此範例中/、=的生成電壓的非揮發 -電極1之右角邊緣4A中。關於電 '放大構係位於該第 】極3之製程’可參考第三實施例成〜轉換材質2與該第二 第五實施例 第七圖A至第七圖D传奸械士 & 〇 說明生產-非揮發纪ί本發明之第五實施例，簡化 非俾’"己^體几件之主要方法步驟，在下列重 1233204 五、發明說明（13) 複的說明中與第一圖至第六圖相同的元 對應的層或元件。 付就係指相同或 根據第七圖A，如第五圖A與第五圖丄 一 實施例，首先在該凹處V中移除該第一弟，、圖A所不之 質1之預先決定的量（d2)。在此範例中1 =性傳^才 蝕刻方法，以回蝕該電性傳導層丨。 又土，丁、使用習用 :據第七圖B，而後形成一薄結構 一銜接凹處VV係保持於該凹處v的區域中。:二，、Page 14 〇04 · 10 · 12.014 1233204 V. Description of the invention (12) The fourth embodiment of the sixth figure A to sixth figure C is an example of the production of a non-volatile memory element according to the present description, which simplifies the complex process. In the description, the layers or elements corresponding to the first to fourth figures are described in the following steps. °, where the symbols refer to the same or according to the fifth and fifth diagrams A and B in the fourth embodiment, so the preparation method of the example can also be described in accordance with the sixth diagram A, in In the fourth embodiment, 'tested with twelve: Ming. The recess V is used to form a first electrically conductive material filling for a planarization method to cause transmission ^^ "B) 'First aids the surface of the layer I. It is preferred that the tungsten layer be retracted to Bei Xi The (CMP) 'can therefore be obtained in the sixth eye of the second section of the chemical mechanical damage according to the sixth figure B, the subsequent cause of the second, sdl, for example, by the back-step, with ^ sj back to the predetermined determined in The edge 4A is used as an electric field amplifier =. An electrode 1 ′ is formed according to the sixth figure C, such as the surface of the second pole # yt on the upper pole 1, which is generated-turned:; 2 are listed in: the auxiliary layer 1 and the first -Electricity 3 is generated on it, so it can be taken after the second electric conductive electrode memory element. In this example, non-volatile of the generated voltage-in the right corner 4A of electrode 1. About electricity ' The enlargement structure is located in the process of the third pole. 'Refer to the third embodiment to convert the material 2 to the second and fifth embodiment. Figure 7A to Figure 7D. The non-volatile period of the fifth embodiment of the present invention simplifies the main method steps of several items of Column weight 1233204 V. Description of the invention (13) The layer or element corresponding to the same element as the first to sixth figures in the description of the complex. Fu means the same or according to the seventh figure A, such as the fifth figure A and the first figure. In the first embodiment of FIG. 5, the first brother is first removed from the recess V, and a predetermined amount (d2) of the quality 1 which is not shown in FIG. A. In this example, 1 = sexual transmission method. In order to etch back the electrically conductive layer, it is also used conventionally: according to the seventh figure B, then a thin structure is formed, and the connecting recess VV is maintained in the area of the recess v.: 2 ,,

貝 且夕層結構形成該第一電極。 傳導，ί ΐ七圖C ’而後藉由非等向姓刻方法，將該電性 下電性傳導層退縮或至少回敍至該輔助層I之 二用二可付該小尖物4Α。纟第七圖β與與第七圖C較佳 ί :4Α ί用的間隔物方法，以形成該第-電極1中的該小 =第七圖D ’係使用第六圖Μ第六圖c中所述的方 :ί二：Ϊ辅助層1係藉由一非等向蝕刻方法，被回蝕至 ^何φ f ^VV的底部區域，且而後形成該轉換材質2與該 =一電極3。為了避免重複贅述，請參考上述實施利之說 ϋ月〇 雷立曰11 = f中’可使用非常簡單的製程步驟’生產具有 冓的非揮發記憶體元件別，因此可大幅降低 所谓的「生成電壓 。The first layer is formed by a layered structure. Conduction, ΐΐVIIC C ′, and then using the non-isotropic last name engraving method, shrink the electrical conductive layer down or at least back to the auxiliary layer I two to pay the small tip 4A.纟 The seventh diagram β and the seventh diagram C are better: 4Α ί The spacer method is used to form the small of the first-electrode 1 = the seventh diagram D ′ uses the sixth diagram M sixth diagram c The method described in the following: ί Two: Auxiliary layer 1 is etched back to the bottom area of φf ^ VV by an anisotropic etching method, and then the conversion material 2 and the = one electrode 3 are formed. . In order to avoid repetition, please refer to the above implementation. 实施 月 〇 雷 立 曰 11 = f 'Can use very simple process steps' to produce non-volatile memory components with 冓, so the "generating voltage" can be greatly reduced. .

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上述非揮發記憶體元件 成’非揮發記憶體 用典型的記憶體元件排列形 弟/、貫施例 < A施例。 一第八圖A係根據本發明之〜 元件排列之簡化的相等電路。六實施例，說明一記憶體 記憶體元件之簡化的區段图圖’且第八圖B係說明相關的 根據第八圖B，具有半導 由摻雜區域可形成字元線：體。材質之該載體材質T中，藉 (STI)彼此隔離。另—'域係藉由淺S渠隔離 ^ 乃尤fe體兀件結構係對應於根據第三 =施例之記憶體元件，該第一電極1之材質選擇，係與該 子疋線WL或該摻雜區域形成二極體接合或Sch〇ttky二極 體0 第八圖A係說明具有多重性的非揮發記憶體元件SE與 配置於矩陣形式中的二極體DI，其連接係經由位於攔邢、 中的位元線BL1、BL2等，以及位於列形式中的字元線 WL1、WL2等，該第一電極j係經由個別二極體接合或是一 極體DI，連接至形成於該半導體基質τ中的個別字元=〜 以及將個別的第二電極3圖案化，以在該輔助層丨的夺、 形成條狀形式的個別位元線。經由此一方式可獲彳卩面上 特別高度整合密度與低生成電壓的記憶體元件排T具有 第七實施例 ° 第九圖Α係根據本發明之第七實施例，說明一圮 元件排列之簡化的相等電路圖，第九圖B係說明其思體 記憶體元件之簡化的區段圖，以下重複的說明中相關的 叫的參The above-mentioned non-volatile memory element is formed into a 'non-volatile memory', and a typical memory element arrangement is used. Examples < A Example. An eighth diagram A is a simplified equivalent circuit of the element arrangement according to the present invention. The sixth embodiment illustrates a simplified block diagram of a memory memory element ', and the eighth diagram B is related. According to the eighth diagram B, a semiconductor device can be formed by doped regions with word lines: a body. The carrier material T of the material is isolated from each other by (STI). In addition, the 'domain' is isolated by shallow S channels. The structure of the physical element corresponds to the memory element according to the third embodiment. The material selection of the first electrode 1 is related to the sub-line WL or This doped region forms a diode junction or a Schottky diode. The eighth figure A illustrates the non-volatile memory element SE with multiplicity and the diode DI arranged in a matrix. The bit lines BL1, BL2, and so on in Xing, and the word lines WL1, WL2, and so on in the column form are connected. The first electrode j is connected to an electrode DI via an individual diode junction or a diode DI. The individual characters in the semiconductor matrix τ = ~, and the individual second electrodes 3 are patterned to capture and form individual bit lines in the form of stripes in the auxiliary layer. In this way, it is possible to obtain a memory element row T with a particularly high integration density and a low generated voltage on the surface, which has a seventh embodiment. The ninth figure A illustrates a component arrangement according to a seventh embodiment of the present invention. Simplified equivalent circuit diagram, Figure 9B is a simplified section diagram illustrating the physical memory components. The related parameters in the following repeated description are called

第17頁 1233204 五、發明說明（15) 考付^虎係指相同的元件或耳 ^ J凡1干A疋對應於第八圖中的元件。 一雷第#九圖B、，一個別的非揮發記憶體元件包含一第 雷m °， ’ '電性連接係經由一歐姆接合或一非反應性的 的第-番接連接至個別的電性傳導字元線WL，U及一個別 3，其被再次的圖案化，以於該輔助層1的表面 ^形成條狀形式的位元線BL。 弟八貫施例 弟十圖A係根據本發明 > 哲 + 亓妓扯以 μ 知a之弟八貫施例，說明一記憶體 ^ ^ ^ ^ ^的才寺電路圖，第十圖B係說明其相關的 σ已1¾體7L件之簡化的區热 考爲$ # 的匚奴圖，以下重複的說明中相同的參 可将5虎係指相同的元株$ Η > 件。 的件或疋對應於第八圖與第九圖中的元 列，ftr的區段圖，此種形式的記憶體元件排 =憶體元細，有-相連的選擇電晶體 極巴二ί) ρΛ气:]㉟，與位元線虬作為第-源極/汲 源極/汲極區域S/D係連接^選擇電晶體ΑΤ之一第二 第-電極！，以及個別的V-/，記憶體元件冗之個別 如共同的源極）。 弟—電極3於共同的參考電位（例 的1 I用3 f I T :式了解記憶體元件排列，應、用於特定 知，若加入串聯選擇的；ί;大幅降低的生成電壓。已 與雜訊的比值叫吏其可建％可獲得大幅改善的信號 上述之本發明係基於所=胞元：列與區段。 、擇的材質，且特別係基於飽和的Page 17 1233204 V. Description of the invention (15) The reference to tiger refers to the same element or ear ^ J 凡 1 干 A 疋 corresponds to the element in the eighth figure.一 雷 第 # 九 图 B., another non-volatile memory element contains a thunder m °, and the electrical connection is connected to an individual electrical connection via an ohmic junction or a non-reactive first connection. The sexually conductive word lines WL, U and one of the three lines are patterned again so that the surface of the auxiliary layer 1 forms a bit line BL in the form of a strip. Brother Hachiman ’s example. Brother Hachiman ’s figure A is according to the invention > Zhe + 亓 Prostitute, with the brother Hachiman ’s example of μ, to illustrate a memory ^ ^ ^ ^ ^ circuit diagram of Caisi Temple. Explain that the related sigma has been reduced to 1 # body and 7L pieces, and the simplified area test is $ #. The same reference in the following repeated description can refer to 5 tigers as the same yuan $$ > pieces. The pieces or 疋 correspond to the meta columns in the eighth and ninth diagrams, the section diagram of ftr, the memory element row of this form = the memory element is thin, and there are-connected selection transistors. ρΛ 气:] ㉟, which is connected to bit line 虬 as the -source / drain source / drain region S / D system ^ Choose one of the second -electrodes of the transistor AT! , As well as individual V- /, redundant individual memory components (such as common source). Brother-electrode 3 uses a common reference potential (example 1 I uses 3 f IT: to understand the memory element arrangement, should be used for specific knowledge, if added in series selection; ί; greatly reduced generated voltage. Has been mixed with miscellaneous The ratio of the information is called its buildable%, which can obtain a greatly improved signal. The above-mentioned invention is based on all cells: columns and sections. The selected material is especially based on saturation.

1233204 案號 92Π9191 臼 修正 五、發明說明（16) 氫非晶矽作為轉換材質。然而，其並不受限，仍可使用其 他的材質，形成具有至少兩個不同傳導狀態的非揮發記憶 體元件。1233204 Case No. 92Π9191 mortar Amendment 5. Description of the invention (16) Hydrogen amorphous silicon is used as conversion material. However, it is not limited, and other materials can still be used to form a non-volatile memory element having at least two different conduction states.

第19頁 2004. 10.12.019 1233204 圖式簡單說明 第一圖A至第一圖C係說明習知技藝之非揮發記憶體元件之 簡化的區段圖與簡化的U- I特性曲線。 第二圖A與第二圖B係說明習知技藝之另一非揮發記憶體元 件之簡化的區段圖與簡化的U- I特性曲線。 第三圖A至第三圖C係根據本發明之第一實施例說明非揮發 記憶體元件之簡化的區段圖與簡化的U- I特性曲線。 第四圖A與第四圖B係根據_本發明之第二實施例說明非揮發 記憶體元件之簡化的區段圖與簡化的U- I特性曲線。Page 19, 2004. 10.12.019 1233204 Brief description of the drawings The first diagram A to the first diagram C are simplified section diagrams and simplified U-I characteristic curves of non-volatile memory elements of the conventional art. The second graph A and the second graph B are simplified section diagrams and simplified U-I characteristic curves of another non-volatile memory element of the conventional art. The third graph A to the third graph C are simplified block diagrams and simplified U-I characteristics of a non-volatile memory device according to the first embodiment of the present invention. The fourth diagram A and the fourth diagram B are simplified section diagrams and simplified U-I characteristic curves of a non-volatile memory element according to the second embodiment of the present invention.

第五圖A至第五圖E係根據本發明之第三實施例簡化說明生 產一非揮發記憶體元件之主要方法步驟。 第六圖A至第六圖C係根據本發明之第四實施例簡化說明生 產一非揮發記憶體元件之主要方法步驟。 第七圖A至第七圖D係根據本發明之第五實施例簡化說明生 產一非揮發記憶體元件之主要方法步驟。 第八圖A與第八圖B係根據本發明之第六實施例說明一記憶 體元件排列之簡化的相等電路圖與相關的記憶體元件之簡 化的區段圖。The fifth and fifth figures A to E are simplified descriptions of the main method steps for producing a non-volatile memory element according to the third embodiment of the present invention. 6A to 6C are simplified descriptions of the main method steps for producing a non-volatile memory device according to the fourth embodiment of the present invention. The seventh diagram A to the seventh diagram D are simplified descriptions of the main method steps for producing a non-volatile memory element according to the fifth embodiment of the present invention. The eighth diagram A and the eighth diagram B are a simplified equivalent circuit diagram of a memory element arrangement and a simplified section diagram of a related memory element according to a sixth embodiment of the present invention.

第九圖A與第九圖B係根據本發明之第七實施例說明一記憶 體元件排列之簡化的相等電路圖與相關的記憶體元件之簡 化的區段圖。 第十圖A與第十圖B係根據本發明之第八實施例說明一記憶 體元件排列之簡化的相等電路圖與相關的記憶體元件之簡 化的區段圖。The ninth figure A and the ninth figure B illustrate a simplified equivalent circuit diagram of a memory element arrangement and a simplified section diagram of related memory elements according to a seventh embodiment of the present invention. The tenth diagram A and the tenth diagram B are a simplified equivalent circuit diagram illustrating a memory element arrangement and a simplified section diagram of a related memory element according to an eighth embodiment of the present invention.

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Claims (1)

1233204 年 月 修正 曰 ^S_92119191 /、、申清專利範圍 1 · 一種非揮發記憶體元件，其具有一轉換材質（2)與兩個 電傳導電極（1，3 )存在於該轉換材質（2 )，且作為該轉換 材質（2)中一電壓的應用與一電場（E)的產生，在一生成步 ，驟之後’該轉換材質（2)中至少有兩個不同的傳導性狀態 (開0N ’關〇FF)，其中可藉由應用預先決定的計劃電壓 (Vwri te，Verase)重複影響轉換，其中至少一電極（1，3) 具有至少一電場放大器結構（4)，用於放大該轉換材質（2) 中該電場（E )的電場強度。 2 ·如申請專利範圍第1項之非揮發記憶體元件，其中該電 %放大器結構構成該電極（1，3 )之一突出物，其係突出至 該轉換材質（2 )。 3 ·如申請專利範圍第2項之非揮發記憶體元件，其中該突 出物係構成碎電極（1，3)之一小尖物、角或邊緣。 4 ·如申請專利範圍第3項之非揮發記憶體元件，其中該小 尖物、角或邊緣的角度係小於等於9 〇度。 其中該轉 其中該轉換 5 ·如申請專利範圍第1項之非揮發記憶體元件 換材質（2 )具有氫飽和的非晶型半導體材質。 6 ·如申請專利範圍第2項之非揮發記憶體元件 材質（2)具有氫飽和的非晶型半導體材質。 7 ·如申請專利範圍第1項至第6項中任一項之非揮發記憶體 元件，其中該轉換材質（2)具有多層結構（2A，2B，2C)。 8 ·如申請專利範圍第1項至第4項中任一項之非揮發記憶體 元件，其中該電極（1，3)具有金屬。 9 · 一種用於製造非揮發記憶體元件之方法，其包含之步驟Revised in 1233204: ^ S_92119191 / 、, Patent application scope 1 · A non-volatile memory element with a conversion material (2) and two electrically conductive electrodes (1, 3) exist in the conversion material (2) And, as an application of a voltage and an electric field (E) in the conversion material (2), in a generation step, after the step 'the conversion material (2) has at least two different conductive states (open 0N 'OFF〇FF), wherein the conversion can be repeatedly affected by applying a predetermined plan voltage (Vwri te, Verase), wherein at least one electrode (1, 3) has at least one electric field amplifier structure (4) for amplifying the conversion The electric field strength of the electric field (E) in the material (2). 2. The non-volatile memory element according to item 1 of the patent application, wherein the electric amplifier structure constitutes a protrusion of the electrode (1, 3), which protrudes to the conversion material (2). 3. The non-volatile memory element according to item 2 of the patent application, wherein the protruding system constitutes a small pointed object, corner or edge of the broken electrode (1, 3). 4. The non-volatile memory element according to item 3 of the patent application, wherein the angle of the small object, corner or edge is 90 degrees or less. Wherein the conversion Where the conversion 5 · For the non-volatile memory element of the first patent application, change the material (2) Amorphous semiconductor material with hydrogen saturation. 6 · Non-volatile memory element as described in item 2 of the patent application Material (2) Amorphous semiconductor material with hydrogen saturation. 7 · The non-volatile memory element according to any one of claims 1 to 6, wherein the conversion material (2) has a multilayer structure (2A, 2B, 2C). 8. The non-volatile memory element according to any one of claims 1 to 4, wherein the electrodes (1, 3) have a metal. 9 · A method for manufacturing a non-volatile memory element, comprising the steps 第22頁 2004.12. 22. 022 1233204 Λ_Μ 修正 曰 案號 921191Q1 六、申請專利範圍 如下： a)製備一載體材質（Τ); b )形成一輔助層u ); c)形成一凹處（v)於該輔助層（1)中； ύ)以第一電性傳導材質充填該凹處（v)，用以形成一第一 電極（1 ); e) 於該第一電極（1 )形成至少一電場放大器結構（4A); f) 形成一轉換材質（2)電場放大器結構（4A)之該第一電極 (1)上，在一生成步驟後，該轉換材質（2)中至少有兩個不 ，的傳導性狀態（開0N，關〇FF)，其中可藉由應用預先決 疋的计劃電壓（Vwrite，Verase)重複影響轉換；以及 g) 在該轉換材質（2)上，形成一第二電性傳導電極（3)。 ι、ο·如申請專利範圍第9項之方法，其中在步驟a)中，一 導體基質被製備作為載體材質（τ)。 11 ·如申請專利範圍第丨0項之方法，其中在步驟a)中，在該 f處（v)區域中’形成字元線（WL)於該載體材質（T)中，該" 子兀線（WL)具有一材質，其與該第一電極（1)之該材質形 成歐姆或二極體接合（di)。 12·如申請專利範圍第9項之方法，其中在步驟a)中，在該 =處（V)區域中’形成字元線（WL)於該載體材質（T)中，該 字兀線（WL)具有一材質，其與該第一電極（1)之該材質形 成歐姆或二極體接合（DI)。 13·如申青專利範圍第9項之方法，其中在步驟a)中，在該 載體材質（τ)中形成具有源極/汲極區域（S/D)之一選擇電Page 22 2004.12. 22. 022 1233204 Λ_M Amendment No. 921191Q1 6. The scope of patent application is as follows: a) Preparation of a carrier material (T); b) Formation of an auxiliary layer u); c) Formation of a recess (v) In the auxiliary layer (1); ύ) filling the recess (v) with a first electrically conductive material to form a first electrode (1); e) forming at least one of the first electrode (1) Electric field amplifier structure (4A); f) forming a switching material (2) on the first electrode (1) of the electric field amplifier structure (4A), after a generating step, at least two of the switching materials (2) are not , A conductive state (on 0N, off 0FF), in which the conversion can be repeatedly affected by applying a predetermined plan voltage (Vwrite, Verase); and g) on the conversion material (2), a first Two electrically conductive electrodes (3). ι, ο · The method according to item 9 of the patent application, wherein in step a), a conductive substrate is prepared as a carrier material (τ). 11 · The method of claim 0 in the scope of patent application, wherein in step a), the word line (WL) is formed in the carrier material (T) in the (v) area at f, the " The WL has a material that forms an ohmic or diode junction (di) with the material of the first electrode (1). 12. The method according to item 9 of the scope of patent application, wherein in step a), the word line (WL) is formed in the carrier material (T) in the (V) area, and the word line ( WL) has a material that forms an ohmic or diode junction (DI) with the material of the first electrode (1). 13. The method according to item 9 of the Shenqing patent scope, wherein in step a), a selective electric circuit having a source / drain region (S / D) is formed in the carrier material (τ). 第23頁 2004.12. 22. 023 1233204 --案號92119191 年月日 修正 六'申請專利範圍 曰曰體（A T )，忒源極/汲極區域（$ / )於該第一電極（1 )形成 一位元線（BL)與一終端區域D 14·如申請專利範圍第1〇項之方法，其中在步驟a)中，在該 載體材質（T)中形成具有源極/汲極區域（S/D)之一選擇電 晶體（AT)，該源極/汲極區域（S/D)於該第一電極（1)形成 一位元線（BL)與一終端區域。 1 5·如申請專利範圍第9項至第1 4項中任一項之方法，其中 在步驟b)中’在該載體材質（τ)的整個面積上，沉積一絕 緣層（I)。 ' 1 6 ·如申請專利範圍第9項至第1 4項中任一項之方法，其中 在步驟c )中， 形成一光阻層，且將其圖案化； 藉由該圖案化的電阻層，將該輔助層（I )之至少一部分移 除； 移除該光阻層；以及 進行一清除步驟。 1 7 ·如申晴專利範圍第1 6項之方法，其中在步驟c )中，進行 一非等向性钱刻，以移除至少一部分的該輔助層（I )。 1 8 ·、如申請專利範圍第9項之方法，其中在步驟c )中，形成 溝渠或疋一孔洞作為凹處（V)。 ,如申。月專利範圍第9項之方法’其中在步驟d )中，沉積 忒電性傳導材質，因此在該凹處（V)的區域中，產生一銜 接凹處（VV)。 2 〇 ·如申凊專利範圍第1 9項之方法，其中在步棘e )中，Page 23 2004.12. 22. 023 1233204-case number 92119191 amended on the 6th of the 6th of the patent application scope (AT), the source / drain region ($ /) is formed on the first electrode (1) A bit line (BL) and a terminal region D 14. The method as described in item 10 of the patent application scope, wherein in step a), a source / drain region (S) is formed in the carrier material (T). / D) selects a transistor (AT), and the source / drain region (S / D) forms a bit line (BL) and a terminal region on the first electrode (1). 15. The method according to any one of claims 9 to 14 in the scope of patent application, wherein in step b), an insulating layer (I) is deposited over the entire area of the carrier material (τ). '1 6 · The method according to any one of claims 9 to 14 in the scope of patent application, wherein in step c), a photoresist layer is formed and patterned; and the patterned resistance layer is used Removing at least a part of the auxiliary layer (I); removing the photoresist layer; and performing a cleaning step. 17 · The method according to item 16 of Shen Qing's patent scope, wherein in step c), an anisotropic money engraving is performed to remove at least a part of the auxiliary layer (I). 1 8. The method according to item 9 of the scope of patent application, wherein in step c), a trench or a hole is formed as the recess (V). , As applied. The method of item 9 of the above-mentioned patent, wherein in step d), an electroconductive conductive material is deposited, so that a connecting recess (VV) is generated in the region of the recess (V). 20. The method of claim 19 in the scope of patent application, wherein in step e), 第24頁 20〇4.12. 22.024 1233204 修正 ，將該電性傳導材質（1)至少 以及 ’將該輔助層（I)回蝕至該銜 i 號 92] 1 men 六、申請專利範圍 e 11 )藉甴非等向性蝕刻方法 回钮至該輔助層（I)之表面； e 1 2 )藉由非等向性蝕刻方法 接凹處（VV)之底部區域。 2 1 ·如申請專利範圍第9項之方法，其中 e21)精由平面化方法，造成該電性傳 至該辅助層（I)之表面； i貝（1)至少退細 由一選擇性的蝕刻方該輔助層⑴係被回蝕-預先決定量（dl)。 了饭U蚀 2 2.如申請專利範圍第9項之方法，其中在步驟y中， e31)藉由一蝕刻方法，移除該凹處（v)中該電性傳導 (1)之至少一預先決定量（d2); e32)形成一薄結構電性傳導層，因此一銜接凹處（vv)仍保 留於該凹處（V)之該區域中； e 3 3 )藉由一非等向性蝕刻方法，將該電性傳導層（丨）至少 回蝕至該輔助層（I)之表面；以及 e 3 4 )藉由非等向性蝕刻方法，將該輔助層（〗）回蝕至該銜 接凹處（VV)之底部區域。 2 3·如申請專利範圍第9項之方法，其中在步驟f)中，以該 電％放大結構（4 ;4A ;4B)沉積一單一或多重氫飽和的非 晶型半導體層於該第一電極（1)上。 2 4 ·如申請專利範圍第9項之方法，其中在步驟g)中，係沉 積鉻（Cr)、金（Au)、鋁（A1)、銅（Cu)、鉻化鎳（NiCr)、銀 (Ag)、鎳（Ni)、鉬（Mo)、釩（V)、鈷（Co)、鐵（Fe)、鎢（W)Page 24 20〇4.12. 22.024 1233204 Amended, the electrical conductive material (1) at least and 'etch back the auxiliary layer (I) to the title i number 92] 1 men VI, patent application scope e 11) borrow甴 The anisotropic etching method is used to push the button back to the surface of the auxiliary layer (I); e 1 2) The bottom region of the recess (VV) is connected by the anisotropic etching method. 2 1 · The method according to item 9 of the patent application scope, wherein e21) is a planarization method, which causes the electrical transmission to the surface of the auxiliary layer (I); i. The auxiliary layer is etched back by an etching process-a predetermined amount (dl). 2. U U 2 2. The method according to item 9 of the patent application scope, wherein in step y, e31) removes at least one of the electrical conduction (1) in the recess (v) by an etching method. A predetermined amount (d2); e32) forms a thin structure electrical conductive layer, so a connecting recess (vv) remains in the area of the recess (V); e 3 3) by an anisotropic Isotropic etching method, at least etch back the electrically conductive layer (丨) to the surface of the auxiliary layer (I); and e 3 4) etch back the auxiliary layer () to The bottom area of the engagement recess (VV). 2 3. The method according to item 9 of the scope of patent application, wherein in step f), a single or multiple hydrogen-saturated amorphous semiconductor layer is deposited on the first with the electrical% amplification structure (4; 4A; 4B). Electrode (1). 2 4 · The method according to item 9 of the scope of patent application, wherein in step g), chromium (Cr), gold (Au), aluminum (A1), copper (Cu), nickel chrome (NiCr), silver (Ag), nickel (Ni), molybdenum (Mo), vanadium (V), cobalt (Co), iron (Fe), tungsten (W) 第25頁 2004.12. 22.025 1233204 曰 ---^^92Π9191 车 六、申請專利範圍 -^ 或二Μ乂層，作為第二電極⑻。 .種夕重性非揮發記憶體 圍弟1項至第6項中任一項之夕牛排列，具有如申請專利範 係排列於矩陣形式中，且可二^性非揮發記憶體元件，其 排列於列之h線（WL)進行列於攔之位元線（BL)與 其中一個別的第—電極（1)係姑 接至形成於半導體基質⑴中：:口體，合⑽電性連 用於形成個^立元線（BL) 固別一子凡線（WL)，以及 層（I」之表面被圖案化成為長條别狀第―電極⑺係在該輔助 2 6.種多重性非揮發記憶體元# μ ^ 圍第1項至第6項中任—項件排列’具有如中請專利範 係排列於矩陣形式中， 性非揮發記憶體元件，其 排列於列之字二排列於搁之位元峨)與 極⑴係經由歐姆接合電性連接至形 ^¥體基I (Τ)中之個別字元線（WL)，以及 用於形成個別位元線（BL)之個別第二 層⑴之表面被圖案化成為長條狀。⑺係在該辅助Page 25 2004.12. 22.025 1233204 said --- ^^ 92Π9191 car 6. Application scope of patent-^ or two Μ 乂 layer, as the second electrode ⑻. The Xixi cattle arrangement of any of the 1st to 6th perimeter of the non-volatile memory of the sire, has the arrangement of the patent application in a matrix form, and can be a non-volatile memory element. The h-line (WL) arranged in the column and the bit-line (BL) arranged in the column and one of the other first electrodes (1) are connected to the semiconductor substrate ：:: mouth body, electrical properties The connection is used to form a ^ Li Yuan line (BL) and a sub-line (WL), and the surface of the layer (I) is patterned into a strip-like shape. The ―electrode‖ is in the auxiliary 2 6. Multiplicity Non-volatile memory element # μ ^ Any of items 1 to 6-item arrangement 'has patents arranged in a matrix form as described above, and non-volatile memory elements are arranged in the second row of the column The bit arrays arranged at the base are electrically connected to the individual word lines (WL) in the body I (T) via ohmic bonding, and the individual word lines (BL) used to form the individual bit lines (BL). The surface of individual second-layer maggots is patterned into strips. In the auxiliary 第26頁 2004.12. 22. 026 1233204 _案號92119191_年月日__ 六、申請專利範圍 (AT)之第二源極/汲極區域（S/D)係電性連接至該記憶體元 件（SE )之第一電極（1 )及位於共同電位之個別第二電極 (3)。Page 26. 2004.12. 22. 026 1233204 _ Case No. 92119191 _ month and year __ VI. The second source / drain region (S / D) of the patent application scope (AT) is electrically connected to the memory element (SE) of the first electrode (1) and individual second electrodes (3) at a common potential. 第27頁 2004.12. 22. 027Page 27 2004.12. 22. 027
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