US20030143782A1 - Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures - Google Patents

Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures Download PDF

Info

Publication number
US20030143782A1
US20030143782A1 US10/061,825 US6182502A US2003143782A1 US 20030143782 A1 US20030143782 A1 US 20030143782A1 US 6182502 A US6182502 A US 6182502A US 2003143782 A1 US2003143782 A1 US 2003143782A1
Authority
US
United States
Prior art keywords
exposing
silver
elemental
method
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/061,825
Inventor
Terry Gilton
Kristy Campbell
John Moore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US10/061,825 priority Critical patent/US20030143782A1/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GILTON, TERRY L., CAMPBELL, KRISTY A., MOORE, JOHN T.
Publication of US20030143782A1 publication Critical patent/US20030143782A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
    • H01L45/1233Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/08Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H01L45/085Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/141Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H01L45/143Selenides, e.g. GeSe
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1641Modification of the switching material, e.g. post-treatment, doping
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1666Patterning of the switching material
    • H01L45/1675Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1666Patterning of the switching material
    • H01L45/1683Patterning of the switching material by filling of openings, e.g. damascene method

Abstract

A method of forming a non-volatile resistance variable device includes forming a patterned mass comprising elemental silver over a substrate. A layer comprising elemental selenium is formed over the substrate and including the patterned mass comprising elemental silver. The substrate is exposed to conditions effective to react only some of the elemental selenium with the elemental silver to form the patterned mass to comprise silver selenide. Unreacted elemental selenium is removed from the substrate. A first conductive electrode is provided in electrical connection with one portion of the patterned mass comprising silver selenide. A germanium selenide comprising material is provided in electrical connection with another portion of the patterned mass comprising silver selenide. A second conductive electrode is provided in electrical connection with the germanium selenide comprising material.

Description

    TECHNICAL FIELD
  • This invention relates to methods of forming non-volatile resistance variable devices, and to methods of forming silver selenide comprising structures. [0001]
  • BACKGROUND OF THE INVENTION
  • Semiconductor fabrication continues to strive to make individual electronic components smaller and smaller, resulting in ever denser integrated circuitry. One type of integrated circuitry comprises memory circuitry where information is stored in the form of binary data. The circuitry can be fabricated such that the data is volatile or non-volatile. Volatile storing memory devices result in loss of data when power is interrupted. Non-volatile memory circuitry retains the stored data even when power is interrupted. [0002]
  • This invention was principally motivated in making improvements to the design and operation of memory circuitry disclosed in U.S. Pat. Nos. 5,761,115; 5,896,312; 5,914,893; and 6,084,796 to Kozicki et al., which ultimately resulted from U.S. patent application Ser. No. 08/652,706, filed on May 30, 1996, disclosing what is referred to as a programmable metallization cell. Such a cell includes opposing electrodes having an insulating dielectric material received therebetween. Received within the dielectric material is a variable resistance material. The resistance of such material can be changed between low resistance and high resistance states. In its normal high resistance state, to perform a write operation, a voltage potential is applied to a certain one of the electrodes, with the other of the electrode being held at zero voltage or ground. The electrode having the voltage applied thereto functions as an anode, while the electrode held at zero or ground functions as a cathode. The nature of the resistance variable material is such that it undergoes a change at a certain applied voltage. With such voltage applied, a low resistance state is induced into the material such that electrical conduction can occur between the top and bottom electrodes. [0003]
  • Once this occurs, the low resistance state is retained when the voltage potentials are removed. Such can effectively result in the resistance of the mass of resistance variable material between the electrodes dropping by a factor of 1,000. Such material can be returned to its highly resistive state by reversing the voltage potential between the anode and cathode. Again, the highly resistive state is maintained once the reverse voltage potentials are removed. Accordingly, such a device can, for example, function as a programmable memory cell of memory circuitry. [0004]
  • The preferred resistance variable material received between the electrodes typically and preferably comprises a chalcogenide material having metal ions diffused therein. One specific example includes one or more layers of germanium selenide having silver ions diffused therein and one or more layers of silver selenide having excess silver ions diffused therein. It is, however, difficult to form silver rich silver selenide. [0005]
  • While the invention was principally motivated in addressing the above issues, it is in no way so limited. The artisan will appreciate applicability of the invention in other aspects unrelated to the above issues, with the invention only being limited by the accompanying claims as literally worded without limiting reference to the specification, and as appropriately interpreted in accordance with the doctrine of equivalents. [0006]
  • SUMMARY
  • The invention includes methods of forming non-volatile resistance variable devices, and methods of forming silver selenide comprising structures. In one implementation, a method of forming a non-volatile resistance variable device includes forming a patterned mass comprising elemental silver over a substrate. A layer comprising elemental selenium is formed over the substrate and including the patterned mass comprising elemental silver. The substrate is exposed to conditions effective to react only some of the elemental selenium with the elemental silver to form the patterned mass to comprise silver selenide. Unreacted elemental selenium is removed from the substrate. A first conductive electrode is provided in electrical connection with one portion of the patterned mass comprising silver selenide. A germanium selenide comprising material is provided in electrical connection with another portion of the patterned mass comprising silver selenide. A second conductive electrode is provided in electrical connection with the germanium selenide comprising material. [0007]
  • In one implementation, a method of forming a silver selenide comprising structure includes forming a substrate comprising a first outer portion and a second outer portion. The first outer portion comprises a patterned mass comprising elemental silver. The second outer portion does not comprise elemental silver. A layer comprising elemental selenium is formed over the first and second outer portions. The substrate is exposed to oxidizing conditions effective to both, a) react elemental selenium received over the first portion with elemental silver to form the patterned mass to comprise silver selenide, and b) remove elemental selenium of the layer over the second outer portion from the substrate. [0008]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0009]
  • FIG. 1 is a diagrammatic perspective view of a semiconductor wafer fragment/section in process in accordance with an aspect of the invention. [0010]
  • FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1. [0011]
  • FIG. 3 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 2. [0012]
  • FIG. 4 is a view of the FIG. 3 wafer fragment at a processing step subsequent to that shown by FIG. 3. [0013]
  • FIG. 5 is an alternate view of the FIG. 3 wafer fragment at an alternate processing step subsequent to that shown by FIG. 3. [0014]
  • FIG. 6 is a view of the FIG. 4 wafer fragment at a processing step subsequent to that shown by FIG. 4. [0015]
  • FIG. 7 is a view of the FIG. 6 wafer fragment at a processing step subsequent to that shown by FIG. 6. [0016]
  • FIG. 8 is an alternate view of the FIG. 3 wafer fragment at an alternate processing step subsequent to that shown by FIG. 3. [0017]
  • FIG. 9 is a diagrammatic perspective view of an alternate embodiment semiconductor wafer fragment/section in process in accordance with an aspect of the invention. [0018]
  • FIG. 10 is a view of the FIG. 9 wafer fragment at a processing step subsequent to that shown by FIG. 9. [0019]
  • FIG. 11 is a view of the FIG. 10 wafer fragment at a processing step subsequent to that shown by FIG. 10. [0020]
  • FIG. 12 is a diagrammatic perspective view of another alternate embodiment semiconductor wafer fragment/section in process in accordance with an aspect of the invention. [0021]
  • FIG. 13 is a view of the FIG. 12 wafer fragment at a processing step subsequent to that shown by FIG. 12. [0022]
  • FIG. 14 is a view of the FIG. 13 wafer fragment at a processing step subsequent to that shown by FIG. 13. [0023]
  • FIG. 15 is a view of the FIG. 14 wafer fragment at a processing step subsequent to that shown by FIG. 14. [0024]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8). [0025]
  • Exemplary embodiment methods of forming a non-volatile resistance variable device are initially described with reference to FIGS. [0026] 1-8. FIG. 1 depicts a substrate fragment 10 comprising a base substrate 12 and a first conductive electrode material 14 formed thereover. Base substrate 12 might comprise any suitable supporting substrate, for example a semiconductor substrate which includes bulk monocrystalline silicon. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated. Exemplary preferred material for layer 14 is elemental tungsten.
  • An insulative material [0027] 16 is formed over first conductive electrode material 14. Such has been patterned by any suitable patterning method (i.e., lithography, such as photolithography) to form an opening 18 therethrough to first conductive electrode material 14. Opening 18 comprises some desired shape of at least a portion of a final resistance setable structure of the device being fabricated, as will be apparent from the continuing discussion.
  • Referring to FIG. 2, opening [0028] 18 has been filled with an elemental silver comprising material 20 in electrical connection with first conductive electrode material 14. An exemplary preferred material for material 20 includes at least 50 molar percent elemental silver, even more preferably at least 95 molar percent elemental silver, and even more preferably greater than 99 molar percent elemental silver. In the illustrated preferred example, insulative material 16 has a substantially planar outermost surface proximate opening 18, and patterned mass/elemental silver comprising material 20 within opening 18 has an outermost surface which is co-planar with the insulative material outer surface. Further, patterned mass 20 can be considered as having some maximum first thickness, with an example thickness range being from about 50 Angstroms to about 2000 Angstroms.
  • One example method of producing the construction illustrated by FIG. 2 would be to deposit a layer of silver comprising material blanketly over the substrate, and then planarizing such layer back at least to the top of outer insulative layer [0029] 16. By way of example only, such deposition might occur by chemical or physical means. Further, the polishing or planarizing could occur by resist etch back, chemical polishing, mechanical polishing or any combination thereof, or by any other existing or yet-to-be-developed method. Further, alternately and by way of example only, the illustrated FIG. 2 construction might be fabricated by an electroless or other deposition of silver comprising material 20 within the illustrated opening such that material 20 effectively only deposits therein and grows upwardly, with the growth preferably being stopped where material 20 approximately reaches the upper surface of insulative material 16. Regardless, FIG. 2 depicts but one example of forming a patterned mass comprising elemental silver over a substrate.
  • Referring to FIG. 3, a layer [0030] 22 comprising elemental selenium is formed over substrate 10 and including patterned mass 20 comprising elemental silver. Preferably, layer 22 comprises elemental selenium of at least 90 molar percent, more preferably at least 95 molar percent elemental selenium, and even more preferably greater than 99 molar percent elemental selenium.
  • Referring to FIG. 4, substrate [0031] 10 has been exposed to conditions effective to react elemental selenium 22 received over the elemental silver of mass 20 to form at least a portion of the filled opening/patterned mass to comprise silver selenide 25. In the depicted and preferred embodiment, such exposing to the conditions are effective to react only some of elemental selenium comprising layer 22, with those portions formed over insulative material 16 being essentially unreacted. In the FIG. 4 depicted and preferred embodiment, the exposing is illustrated as forming the patterned mass to entirely comprise silver selenide material 25. Regardless, the exposing preferably forms that portion of the patterned mass which is transformed to comprise at least 50 molar percent silver selenide, and more preferably at least 80 molar percent silver selenide. Further preferably, that portion which is formed is ideally substantially homogenous.
  • FIG. 5 depicts an alternate embodiment [0032] 10 a. Like numerals from the first embodiment are utilized where appropriate, with differences being indicated by the suffix “a”. FIG. 5 depicts forming an outermost portion 25 a of the patterned mass to comprise silver selenide, while an innermost portion 20 a of the patterned mass remains as the deposited silver comprising material initially formed. By way of example only, the remaining thickness of innermost portion 20 a is preferably from 0 to 10 percent of the total thickness of the illustrated patterned mass. Each of FIGS. 4 and 5 depicts but one embodiment wherein the exposing forms more than one-half of the filled opening to comprise silver selenide. Alternately, by way of example only, one-half or less than one-half might be filled. Further in the preferred embodiment as shown, the exposing forms the patterned mass to have a maximum second thickness which is greater than the maximum first thickness.
  • One example preferred process for the subject exposing includes annealing the substrate at a temperature of from about 40° C. to about 100° C. at a pressure of from about 30 mTorr to 760 Torr for from about one to three hours. Higher temperatures typically result in a higher annealing rate. Conditions and time can be controlled to achieve a desired amount of the mass to be transformed to silver selenide comprising material. Further, by way of example only, annealing in a suitable oxidizing atmosphere is also a possibility, as is more fully described below. [0033]
  • Referring to FIG. 6, unreacted elemental selenium [0034] 22 has been removed from the substrate. The preferred removing, as shown, removes all remaining unreacted elemental selenium from the substrate. One example of removing comprises chemical etching, and preferably in a manner which is selective to remove elemental selenium comprising material 16 selectively relative to silver selenide comprising material 25. An example wet etch for doing so would include utilizing hydrogen peroxide, for example at from room temperature to 50° C. and ambient pressure. An example dry process would include plasma etching using CF4. Further by way of example only, an alternate process for removing unreacted elemental selenium comprises increasing the temperature of the substrate to closer to the melting temperature of selenium, say from 200° C. to 250° C., and at atmospheric pressure for from 10 minutes to one hour, effective to cause evaporation of the unreacted selenium from the substrate.
  • Referring to FIG. 7, a germanium selenide material layer [0035] 26 (i.e., preferably 40 molar percent germanium and 60 molar percent selenium) is formed over and in electrical connection with silver selenide comprising material 25. A second conductive electrode material 28 is formed thereover, and thereby in electrical connection with silver selenide 25 through material 26. Second conductive electrode material 28 might be the same as first conductive electrode material 14, or be different. An exemplary preferred material for electrode 28 in the depicted and described embodiment is elemental silver. Regardless, in the preferred embodiment such provides exemplary processing of providing a first conductive electrode in electrical connection with one portion of patterned mass 25 comprising silver selenide, providing a germanium selenide comprising material in electrical connection with another portion of the patterned mass comprising silver selenide, and providing a second conductive electrode in electrical connection with the germanium selenide comprising material.
  • The above-described exemplary preferred embodiment processes conducted the exposing and the removing in different or separate processing steps. The invention also contemplates conducting the exposing and the removing in the same or single common processing step. FIG. 8 depicts an alternate embodiment [0036] 10 c which depicts an alternate processing of the FIG. 3 wafer which produces a slightly modified construction to that depicted by FIG. 4. In FIG. 8, the exposing and the removing have occurred in a common processing step comprising at least 100° C. and an atmosphere which removes unreacted elemental selenium by oxidation thereof. Preferably, the oxidizing atmosphere utilizes a weak oxidizer or a dilute oxidizer, for example at less than or equal to five percent by volume oxidizer, with less than or equal to one percent being more preferred. An example preferred oxidizing atmosphere comprises at least one of N2O, NOx, O3, F2 and Cl2. By way of example only, preferred conditions include an elevated temperature of from 40° C. to 250°C., a pressure at from 30 mTorr to 760 Torr and from 30 minutes to two hours.
  • The oxidizing conditions and atmosphere are preferably selected to be sufficiently dilute or weak, as identified above, to prevent the complete oxidation of selenium comprising material [0037] 22 over patterned mass 20 prior to driving (either physically or by reacting) elemental selenium into patterned mass 20 such that an effective silver selenide mass 25 c is formed. However, such oxidizing will typically result in some removal of elemental selenium by oxidation at the outermost portion of elemental selenium comprising layer 22 over the patterned mass during the oxidizing. Most preferably in this and any embodiment, the exposing drives at least a majority of that portion of the elemental selenium received over the patterned mass into the patterned mass.
  • The invention further contemplates a method of forming any silver selenide comprising structure regardless of whether such is utilized in the fabrication of a non-volatile resistance variable device. Such method contemplates forming a substrate comprising a first outer portion and a second outer portion, with the first outer portion constituting a patterned mass comprising elemental silver and the second portion not comprising elemental silver. By way of example only and with respect to FIGS. 2 and 3, an outermost portion of patterned mass [0038] 20 comprising elemental silver comprises an exemplary first outer portion, with the outermost portion of insulative 16 constituting an exemplary second outer portion. A layer comprising elemental selenium is formed over the first and second outer portions. The substrate is exposed to oxidizing conditions, by way of example only such as those described above, effective to both a) react elemental selenium received over the first portion with elemental silver to form the patterned mass to comprise silver selenide, and b) remove elemental selenium of a layer over the second outer portion from the substrate. Preferably, the exposing removes all unreacted elemental selenium from the substrate. Further, and in accordance with the above-described preferred embodiment, such exposing will tend to remove some of the elemental selenium of the layer over the first portion from the substrate, but still preferably drive at least a majority of that portion of the elemental selenium received over the first portion into the patterned mass, and more preferably at least 80 molar percent. Further, such exposing preferably forms the patterned mass to have a maximum second thickness which is greater than its maximum first thickness immediately prior to the exposing.
  • The depicted and above-described embodiments show processes wherein at least a majority and in one case essentially all of the material within opening [0039] 18 is formed to comprise elemental silver. FIGS. 9-11 illustrate an alternate embodiment 10 d. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix “d” or with different numerals. FIG. 9 depicts an alternate elemental silver comprising material 20 d received within opening 18. Such comprises a lower exemplary germanium selenide portion 21 (i.e., preferably 40 percent germanium and 60 percent selenium), and an overlying preferred 99 percent-plus pure elemental silver region 23. By way of example only, such could be formed by suitable deposition and planarization relative to insulative layer 16. A selenium comprising layer 22 d is formed thereover.
  • Referring to FIG. 10, substrate [0040] 10 d has been subjected to the preferred exposing and removing processing (either together or in different steps) effective to form a silver selenide mass 25 d and to remove at least some, and preferably all, unreacted elemental selenium from the substrate.
  • Referring to FIG. 11, another germanium selenide layer [0041] 26 d and a second electrode 28 d are formed thereover.
  • The above-described embodiments describe and depict exemplary methods of forming a patterned mass comprising elemental silver. Such embodiments depict forming a patterned opening within insulative material over a substrate, and at least partially filling the opening with an elemental silver comprising material. However, the invention contemplates any method of forming a patterned mass comprising elemental silver. By way of example only, one such alternate process is described with reference to FIGS. [0042] 12-15.
  • FIG. 12 depicts another alternate embodiment [0043] 10 e, with like numerals from the first embodiment being utilized and differences being indicated with the suffix “e” or with different numerals. FIG. 12 depicts the depositing of a silver comprising material 20 e. Material 20 e has been patterned, for example by photopatterning and then subtractively etching after the patterning. Other patterning, such as laser patterning or any other method of patterning, is contemplated, whether existing or yet-to-be-developed.
  • Referring to FIG. 13, an elemental selenium comprising layer [0044] 22 e is formed over patterned mass 20 e.
  • Referring to FIG. 14, the substrate has been exposed to conditions effective to react only some of elemental selenium [0045] 22 e with the elemental silver to form a patterned mass 25 e to comprise silver selenide. Any of the above-described processing, including an oxidation process which removes 22 e from the process during the exposing, is contemplated, of course, and are only preferred examples.
  • Referring to FIG. 15, a preferred germanium selenide layer [0046] 26 e and a preferred second electrode 28 e are formed thereover.
  • The above constructions can be effectively preferably fabricated to form programmable metallization cells over memory and other integrated circuitry. [0047]
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. [0048]

Claims (51)

1. A method of forming a non-volatile resistance variable device, comprising:
forming a patterned mass comprising elemental silver over a substrate;
forming a layer comprising elemental selenium over the substrate and including the patterned mass comprising elemental silver;
exposing the substrate to conditions effective to react only some of the elemental selenium with the elemental silver to form the patterned mass to comprise silver selenide;
removing unreacted elemental selenium from the substrate;
providing a first conductive electrode in electrical connection with one portion of the patterned mass comprising silver selenide;
providing a germanium selenide comprising material in electrical connection with another portion of the patterned mass comprising silver selenide; and
providing a second conductive electrode in electrical connection with the germanium selenide comprising material.
2. The method of claim 1 wherein the patterned mass comprises at least 50 molar percent elemental silver prior to the exposing.
3. The method of claim 1 wherein the patterned mass comprises at least 95 molar percent elemental silver prior to the exposing.
4. The method of claim 1 wherein the layer comprising elemental selenium comprises at least 90 molar percent elemental selenium prior to the exposing.
5. The method of claim 1 wherein the layer comprising elemental selenium comprises at least 95 molar percent elemental selenium prior to the exposing.
6. The method of claim 1 wherein the exposing and the removing occur in a common processing step.
7. The method of claim 1 wherein the exposing and the removing occur in different processing steps.
8. The method of claim 1 wherein the exposing and the removing occur in a common processing step comprising at least 40° C. and an atmosphere which removes unreacted elemental selenium by oxidation thereof.
9. The method of claim 1 wherein the removing of the unreacted elemental selenium comprises chemical etching after the exposing.
10. The method of claim 1 wherein the removing of the unreacted elemental selenium comprises evaporation after the exposing.
11. The method of claim 1 wherein the exposing forms the patterned mass to comprise at least 50 molar percent silver selenide.
12. The method of claim 1 wherein the exposing forms the patterned mass to comprise at least 80 molar percent silver selenide.
13. The method of claim 1 wherein the exposing drives at least a majority of that portion of the elemental selenium received over the patterned mass into the patterned mass.
14. The method of claim 1 wherein the patterned mass comprises greater than 50 molar percent elemental silver prior to the exposing, the exposing forming an outermost portion of the patterned mass to comprise greater than 50 molar percent silver selenide, with an innermost portion of the patterned mass remaining at greater than 50 molar percent elemental silver.
15. The method of claim 1 wherein the patterned mass comprises greater than 90 molar percent elemental silver prior to the exposing, the exposing forming an outermost portion of the patterned mass to comprise greater than 90 molar percent silver selenide, with an innermost portion of the patterned mass remaining at greater than 90 molar percent elemental silver.
16. The method of claim 1 wherein the patterned mass as formed prior to the exposing has a maximum first thickness, the exposing forming the patterned mass to have a maximum second thickness which is greater than the maximum first thickness.
17. The method of claim 1 wherein the removing removes all unreacted elemental selenium from the substrate.
18. The method of claim 1 wherein forming the patterned mass comprising elemental silver comprises depositing an elemental silver comprising material, photopatterning it, and subtractively etching it after the photopatterning.
19. The method of claim 1 wherein forming the patterned mass comprising elemental silver comprises forming a patterned opening within insulative material over the substrate, and at least partially filling the opening with an elemental silver comprising material.
20. A method of forming a non-volatile resistance variable device, comprising:
forming a patterned mass comprising at lest 90 molar percent elemental silver over a substrate and to a first maximum thickness;
forming a layer comprising at least 90 molar percent elemental selenium over the substrate and including the patterned mass comprising elemental silver;
exposing the substrate to conditions effective to react only some of the elemental selenium with the elemental silver to form the patterned mass to comprise silver selenide, the exposing forming the silver selenide to be rich in silver, and forming the patterned mass to have a maximum second thickness which is greater than the maximum first thickness, the exposing forming the patterned mass to comprise at least 80 molar percent silver selenide, the exposing driving at least a majority of that portion of the elemental selenium received over the patterned mass into the patterned mass;
removing all unreacted elemental selenium from the substrate;
providing a first conductive electrode in electrical connection with one portion of the patterned mass comprising silver selenide;
providing a germanium selenide comprising material in electrical connection with another portion of the patterned mass comprising silver selenide; and
providing a second conductive electrode in electrical connection with the germanium selenide comprising material.
21. A method of forming a non-volatile resistance variable device, comprising:
forming a first conductive electrode material over a substrate;
forming an insulative material over the first conductive electrode material and an opening therethrough to the first conductive electrode material, the opening comprising a desired shape of at least a portion of a final resistance setable structure of the device;
filling the opening with an elemental silver comprising material in electrical connection with the first conductive electrode material;
forming a layer comprising elemental selenium over the insulative material and over the elemental silver comprising material within the opening;
exposing the substrate to conditions effective to react elemental selenium received over the elemental silver to form at least a portion of the filled opening to comprise silver selenide;
removing unreacted elemental selenium received over the insulative material from the substrate; and
providing a germanium selenide comprising material in electrical connection with the silver selenide; and
providing a second conductive electrode in electrical connection with the germanium selenide comprising material.
22. The method of claim 21 wherein the exposing forms at least a majority portion of the filled opening to comprise silver selenide.
23. The method of claim 21 wherein the exposing forms less than one half of the filled opening to comprise silver selenide.
24. The method of claim 21 wherein the elemental silver comprising material comprises at least 50 molar percent elemental silver prior to the exposing.
25. The method of claim 21 wherein the elemental silver comprising material comprises at least 95 molar percent elemental silver prior to the exposing.
26. The method of claim 21 wherein the layer comprising elemental selenium comprises at least 90 molar percent elemental selenium prior to the exposing.
27. The method of claim 21 wherein the layer comprising elemental selenium comprises at least 95 molar percent elemental selenium prior to the exposing.
28. The method of claim 21 wherein the exposing and the removing occur in a common processing step.
29. The method of claim 21 wherein the exposing and the removing occur in different processing steps.
30. The method of claim 21 wherein the exposing and the removing occur in a common processing step comprising at least 40° C. and an atmosphere which removes unreacted elemental selenium by oxidation thereof.
31. The method of claim 21 wherein the removing of the unreacted elemental selenium comprises chemical etching after the exposing.
32. The method of claim 21 wherein the removing of the unreacted elemental selenium comprises evaporation after the exposing.
33. The method of claim 21 wherein the exposing forms at least 80% of the filled opening to comprise silver selenide.
34. The method of claim 21 wherein the exposing drives at least a majority of that portion of the elemental selenium received over the elemental silver comprising material into the elemental silver comprising material.
35. The method of claim 21 wherein the filled opening comprises greater than 50 molar percent elemental silver prior to the exposing, the exposing forming an outermost portion of the filled opening to comprise greater than 50 molar percent silver selenide, with an innermost portion of the filled opening remaining at greater than 50 molar percent elemental silver.
36. The method of claim 21 wherein the filled opening comprises greater than 90 molar percent elemental silver prior to the exposing, the exposing forming an outermost portion of the filled opening to comprise greater than 90 molar percent silver selenide, with an innermost portion of the filled opening remaining at greater than 90 molar percent elemental silver.
37. The method of claim 21 wherein the insulative material has a substantially planar outermost surface proximate the opening and the elemental silver comprising material within the filled opening has an outermost surface which is coplanar with the insulative material outer surface prior to the exposing, the elemental silver comprising material within the opening prior to the exposing having a maximum first thickness, the exposing forming the patterned mass to have a maximum second thickness which is greater than the maximum first thickness.
38. The method of claim 21 wherein the removing removes all unreacted elemental selenium from the substrate.
39. A method of forming a silver selenide comprising structure, comprising:
forming a substrate comprising a first outer portion and a second outer portion, the first outer portion comprising a patterned mass comprising elemental silver, the second outer portion not comprising elemental silver;
forming a layer comprising elemental selenium over the first and second outer portions; and
exposing the substrate to oxidizing conditions effective to both, a) react elemental selenium received over the first portion with elemental silver to form the patterned mass to comprise silver selenide, and b) remove elemental selenium of the layer over the second outer portion from the substrate.
40. The method of claim 39 wherein the exposing removes some of the elemental selenium of the layer over the first portion from the substrate.
41. The method of claim 39 wherein the exposing drives at least a majority of that portion of the elemental selenium received over the first portion into the patterned mass.
42. The method of claim 39 wherein the exposing drives at least a 80 molar percent of that portion of the elemental selenium received over the first portion into the patterned mass.
43. The method of claim 39 wherein the exposing comprises a temperature of from about 40° C. to about 250° C.
44. The method of claim 39 wherein the oxidizing conditions comprise an atmosphere comprising at least one of N2O, NOX, O3, F2, and Cl2.
45. The method of claim 39 wherein the exposing removes all elemental selenium of the layer over the second outer portion from the substrate.
46. The method of claim 39 wherein the exposing removes all unreacted elemental selenium from the substrate.
47. The method of claim 39 wherein the patterned mass comprises at least 95 molar percent elemental silver prior to the exposing.
48. The method of claim 39 wherein the layer comprising elemental selenium comprises at least 95 molar percent elemental selenium prior to the exposing.
49. The method of claim 39 wherein the patterned mass as formed prior to the exposing has a maximum first thickness, the exposing forming the patterned mass to have a maximum second thickness which is greater than the maximum first thickness.
50. The method of claim 39 wherein forming the patterned mass comprising elemental silver comprises depositing an elemental silver comprising material, photopatterning it, and subtractively etching it after the photopatterning.
51. The method of claim 39 wherein forming the patterned mass comprising elemental silver comprises forming a patterned opening within insulative material over the substrate, and at least partially filling the opening with an elemental silver comprising material.
US10/061,825 2002-01-31 2002-01-31 Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures Abandoned US20030143782A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/061,825 US20030143782A1 (en) 2002-01-31 2002-01-31 Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US10/061,825 US20030143782A1 (en) 2002-01-31 2002-01-31 Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures
KR20047011805A KR100660245B1 (en) 2002-01-31 2003-01-21 Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures
JP2003564939A JP2005516418A (en) 2002-01-31 2003-01-21 The methods for forming and silver selenide containing structure of the nonvolatile variable resistance device
AT03708848T AT392714T (en) 2002-01-31 2003-01-21 Manufacturing process for non-volatile resistance variable devices and manufacturing processes for silver-selenide-containing structures
DE2003620373 DE60320373T2 (en) 2002-01-31 2003-01-21 Manufacturing process for non-volatile resistance variable devices and manufacturing processes for silver-selenide-containing structures
AU2003212814A AU2003212814A1 (en) 2002-01-31 2003-01-21 Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures
CN 03807655 CN100375284C (en) 2002-01-31 2003-01-21 Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures
EP20030708848 EP1470589B1 (en) 2002-01-31 2003-01-21 Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures
PCT/US2003/001498 WO2003065456A2 (en) 2002-01-31 2003-01-21 Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures
TW92102209A TWI251263B (en) 2002-01-31 2003-01-30 Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures
US10/634,897 US6812087B2 (en) 2002-01-31 2003-08-06 Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/634,897 Continuation US6812087B2 (en) 2002-01-31 2003-08-06 Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures

Publications (1)

Publication Number Publication Date
US20030143782A1 true US20030143782A1 (en) 2003-07-31

Family

ID=27610193

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/061,825 Abandoned US20030143782A1 (en) 2002-01-31 2002-01-31 Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures
US10/634,897 Active US6812087B2 (en) 2002-01-31 2003-08-06 Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures

Family Applications After (1)

Application Number Title Priority Date Filing Date
US10/634,897 Active US6812087B2 (en) 2002-01-31 2003-08-06 Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures

Country Status (10)

Country Link
US (2) US20030143782A1 (en)
EP (1) EP1470589B1 (en)
JP (1) JP2005516418A (en)
KR (1) KR100660245B1 (en)
CN (1) CN100375284C (en)
AT (1) AT392714T (en)
AU (1) AU2003212814A1 (en)
DE (1) DE60320373T2 (en)
TW (1) TWI251263B (en)
WO (1) WO2003065456A2 (en)

Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020168852A1 (en) * 2001-05-11 2002-11-14 Harshfield Steven T. PCRAM memory cell and method of making same
US20030027416A1 (en) * 2001-08-01 2003-02-06 Moore John T. Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry
US20030045049A1 (en) * 2001-08-29 2003-03-06 Campbell Kristy A. Method of forming chalcogenide comprising devices
US20030045054A1 (en) * 2001-08-29 2003-03-06 Campbell Kristy A. Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device
US20030194865A1 (en) * 2002-04-10 2003-10-16 Gilton Terry L. Method of manufacture of programmable conductor memory
US20030206433A1 (en) * 2002-05-03 2003-11-06 Glen Hush Dual write cycle programmable conductor memory system and method of operation
US20030228717A1 (en) * 2002-06-06 2003-12-11 Jiutao Li Co-sputter deposition of metal-doped chalcogenides
US20040038432A1 (en) * 2002-04-10 2004-02-26 Micron Technology, Inc. Programmable conductor memory cell structure and method therefor
US20040071042A1 (en) * 2002-01-04 2004-04-15 John Moore PCRAM rewrite prevention
US6791859B2 (en) 2001-11-20 2004-09-14 Micron Technology, Inc. Complementary bit PCRAM sense amplifier and method of operation
US6791885B2 (en) 2002-02-19 2004-09-14 Micron Technology, Inc. Programmable conductor random access memory and method for sensing same
US6813176B2 (en) 2001-08-30 2004-11-02 Micron Technology, Inc. Method of retaining memory state in a programmable conductor RAM
US20040223390A1 (en) * 2002-02-15 2004-11-11 Campbell Kristy A. Resistance variable memory element having chalcogenide glass for improved switching characteristics
US6825135B2 (en) 2002-06-06 2004-11-30 Micron Technology, Inc. Elimination of dendrite formation during metal/chalcogenide glass deposition
US6833559B2 (en) 2001-02-08 2004-12-21 Micron Technology, Inc. Non-volatile resistance variable device
US20050219901A1 (en) * 2003-09-17 2005-10-06 Gilton Terry L Non-volatile memory structure
US20060104142A1 (en) * 2002-08-29 2006-05-18 Gilton Terry L Software refreshed memory device and method
US20070035041A1 (en) * 2003-03-14 2007-02-15 Li Li Methods of forming and using memory cell structures
US20080093589A1 (en) * 2004-12-22 2008-04-24 Micron Technology, Inc. Resistance variable devices with controllable channels
US20080121859A1 (en) * 2006-10-19 2008-05-29 Boise State University Forced ion migration for chalcogenide phase change memory device
US20100027324A1 (en) * 2008-08-01 2010-02-04 Boise State University Variable integrated analog resistor
US7663137B2 (en) 2005-08-02 2010-02-16 Micron Technology, Inc. Phase change memory cell and method of formation
US7663133B2 (en) 2005-04-22 2010-02-16 Micron Technology, Inc. Memory elements having patterned electrodes and method of forming the same
US7668000B2 (en) 2005-08-15 2010-02-23 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US7682992B2 (en) 2004-08-12 2010-03-23 Micron Technology, Inc. Resistance variable memory with temperature tolerant materials
US7692177B2 (en) 2002-08-29 2010-04-06 Micron Technology, Inc. Resistance variable memory element and its method of formation
US7701760B2 (en) 2005-08-01 2010-04-20 Micron Technology, Inc. Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
US7700422B2 (en) 2005-04-22 2010-04-20 Micron Technology, Inc. Methods of forming memory arrays for increased bit density
US7709885B2 (en) 2005-08-09 2010-05-04 Micron Technology, Inc. Access transistor for memory device
US7723713B2 (en) 2002-02-20 2010-05-25 Micron Technology, Inc. Layered resistance variable memory device and method of fabrication
US7749853B2 (en) 2004-07-19 2010-07-06 Microntechnology, Inc. Method of forming a variable resistance memory device comprising tin selenide
US7785976B2 (en) 2004-08-12 2010-08-31 Micron Technology, Inc. Method of forming a memory device incorporating a resistance-variable chalcogenide element
US7791058B2 (en) 2006-08-29 2010-09-07 Micron Technology, Inc. Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
US7910397B2 (en) 2004-12-22 2011-03-22 Micron Technology, Inc. Small electrode for resistance variable devices
US20110079709A1 (en) * 2009-10-07 2011-04-07 Campbell Kristy A Wide band sensor
US20110159661A1 (en) * 2002-07-26 2011-06-30 Laurent Breuil Nonvolatile Memory Element and Production Method Thereof and Storage Memory Arrangement
US8101936B2 (en) 2005-02-23 2012-01-24 Micron Technology, Inc. SnSe-based limited reprogrammable cell
US8284590B2 (en) 2010-05-06 2012-10-09 Boise State University Integratable programmable capacitive device
US8467236B2 (en) 2008-08-01 2013-06-18 Boise State University Continuously variable resistor
US8619485B2 (en) 2004-03-10 2013-12-31 Round Rock Research, Llc Power management control and controlling memory refresh operations
US9552986B2 (en) 2002-08-29 2017-01-24 Micron Technology, Inc. Forming a memory device using sputtering to deposit silver-selenide film

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109056B2 (en) * 2001-09-20 2006-09-19 Micron Technology, Inc. Electro-and electroless plating of metal in the manufacture of PCRAM devices
DE102004047630A1 (en) 2004-09-30 2006-04-13 Infineon Technologies Ag A method for producing a semiconductor memory CBRAM
JP2007019305A (en) * 2005-07-08 2007-01-25 Elpida Memory Inc Semiconductor storage device
US7825479B2 (en) 2008-08-06 2010-11-02 International Business Machines Corporation Electrical antifuse having a multi-thickness dielectric layer
JP5348108B2 (en) * 2010-10-18 2013-11-20 ソニー株式会社 Memory element
US9478419B2 (en) 2013-12-18 2016-10-25 Asm Ip Holding B.V. Sulfur-containing thin films
US9245742B2 (en) 2013-12-18 2016-01-26 Asm Ip Holding B.V. Sulfur-containing thin films
US9461134B1 (en) 2015-05-20 2016-10-04 Asm Ip Holding B.V. Method for forming source/drain contact structure with chalcogen passivation
US9711350B2 (en) 2015-06-03 2017-07-18 Asm Ip Holding B.V. Methods for semiconductor passivation by nitridation
US9711396B2 (en) 2015-06-16 2017-07-18 Asm Ip Holding B.V. Method for forming metal chalcogenide thin films on a semiconductor device
US9741815B2 (en) 2015-06-16 2017-08-22 Asm Ip Holding B.V. Metal selenide and metal telluride thin films for semiconductor device applications

Family Cites Families (159)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1131740A (en) * 1912-04-11 1915-03-16 Otto C Schwarz Building-block.
US3271591A (en) 1963-09-20 1966-09-06 Energy Conversion Devices Inc Symmetrical current controlling device
US3450967A (en) * 1966-09-07 1969-06-17 Vitautas Balio Tolutis Selenium memory cell containing silver up to 2 atomic percent adjacent the rectifying contact
US3622319A (en) 1966-10-20 1971-11-23 Western Electric Co Nonreflecting photomasks and methods of making same
GB1131740A (en) * 1967-08-24 1968-10-23 Inst Fysiki I Mat Semi-conductor devices
US3868651A (en) 1970-08-13 1975-02-25 Energy Conversion Devices Inc Method and apparatus for storing and reading data in a memory having catalytic material to initiate amorphous to crystalline change in memory structure
US3743847A (en) * 1971-06-01 1973-07-03 Motorola Inc Amorphous silicon film as a uv filter
US4267261A (en) * 1971-07-15 1981-05-12 Energy Conversion Devices, Inc. Method for full format imaging
US3961314A (en) * 1974-03-05 1976-06-01 Energy Conversion Devices, Inc. Structure and method for producing an image
US3966317A (en) * 1974-04-08 1976-06-29 Energy Conversion Devices, Inc. Dry process production of archival microform records from hard copy
US4177474A (en) 1977-05-18 1979-12-04 Energy Conversion Devices, Inc. High temperature amorphous semiconductor member and method of making the same
JPS5620695B2 (en) * 1978-11-07 1981-05-15
DE2901303C2 (en) 1979-01-15 1984-04-19 Max Planck Gesellschaft Zur Foerderung Der Wissenschaften E.V., 3400 Goettingen, De
US4312938A (en) * 1979-07-06 1982-01-26 Drexler Technology Corporation Method for making a broadband reflective laser recording and data storage medium with absorptive underlayer
US4269935A (en) * 1979-07-13 1981-05-26 Ionomet Company, Inc. Process of doping silver image in chalcogenide layer
US4350541A (en) * 1979-08-13 1982-09-21 Nippon Telegraph & Telephone Public Corp. Doping from a photoresist layer
US4316946A (en) * 1979-12-03 1982-02-23 Ionomet Company, Inc. Surface sensitized chalcogenide product and process for making and using the same
JPS6024580B2 (en) 1980-03-10 1985-06-13 Nippon Telegraph & Telephone
US4499557A (en) * 1980-10-28 1985-02-12 Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
US4405710A (en) 1981-06-22 1983-09-20 Cornell Research Foundation, Inc. Ion beam exposure of (g-Gex -Se1-x) inorganic resists
US4410421A (en) 1982-02-08 1983-10-18 Electric Power Research Institute Process for nitrogen removal from hydrocarbonaceous materials
US4737379A (en) * 1982-09-24 1988-04-12 Energy Conversion Devices, Inc. Plasma deposited coatings, and low temperature plasma method of making same
US4545111A (en) * 1983-01-18 1985-10-08 Energy Conversion Devices, Inc. Method for making, parallel preprogramming or field programming of electronic matrix arrays
US4608296A (en) 1983-12-06 1986-08-26 Energy Conversion Devices, Inc. Superconducting films and devices exhibiting AC to DC conversion
US4795657A (en) * 1984-04-13 1989-01-03 Energy Conversion Devices, Inc. Method of fabricating a programmable array
US4843443A (en) * 1984-05-14 1989-06-27 Energy Conversion Devices, Inc. Thin film field effect transistor and method of making same
US4673957A (en) * 1984-05-14 1987-06-16 Energy Conversion Devices, Inc. Integrated circuit compatible thin film field effect transistor and method of making same
US4670763A (en) * 1984-05-14 1987-06-02 Energy Conversion Devices, Inc. Thin film field effect transistor
US4668968A (en) * 1984-05-14 1987-05-26 Energy Conversion Devices, Inc. Integrated circuit compatible thin film field effect transistor and method of making same
US4769338A (en) 1984-05-14 1988-09-06 Energy Conversion Devices, Inc. Thin film field effect transistor and method of making same
US4678679A (en) * 1984-06-25 1987-07-07 Energy Conversion Devices, Inc. Continuous deposition of activated process gases
US4646266A (en) * 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
US4637895A (en) 1985-04-01 1987-01-20 Energy Conversion Devices, Inc. Gas mixtures for the vapor deposition of semiconductor material
US4664939A (en) * 1985-04-01 1987-05-12 Energy Conversion Devices, Inc. Vertical semiconductor processor
US4710899A (en) 1985-06-10 1987-12-01 Energy Conversion Devices, Inc. Data storage medium incorporating a transition metal for increased switching speed
US4671618A (en) * 1986-05-22 1987-06-09 Wu Bao Gang Liquid crystalline-plastic material having submillisecond switch times and extended memory
US4766471A (en) 1986-01-23 1988-08-23 Energy Conversion Devices, Inc. Thin film electro-optical devices
US4818717A (en) * 1986-06-27 1989-04-04 Energy Conversion Devices, Inc. Method for making electronic matrix arrays
US4728406A (en) * 1986-08-18 1988-03-01 Energy Conversion Devices, Inc. Method for plasma - coating a semiconductor body
US4845533A (en) * 1986-08-22 1989-07-04 Energy Conversion Devices, Inc. Thin film electrical devices with amorphous carbon electrodes and method of making same
US4809044A (en) * 1986-08-22 1989-02-28 Energy Conversion Devices, Inc. Thin film overvoltage protection devices
US4788594A (en) 1986-10-15 1988-11-29 Energy Conversion Devices, Inc. Solid state electronic camera including thin film matrix of photosensors
US4853785A (en) 1986-10-15 1989-08-01 Energy Conversion Devices, Inc. Electronic camera including electronic signal storage cartridge
US4847674A (en) * 1987-03-10 1989-07-11 Advanced Micro Devices, Inc. High speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism
US4800526A (en) * 1987-05-08 1989-01-24 Gaf Corporation Memory element for information storage and retrieval system and associated process
US4891330A (en) * 1987-07-27 1990-01-02 Energy Conversion Devices, Inc. Method of fabricating n-type and p-type microcrystalline semiconductor alloy material including band gap widening elements
US4775425A (en) 1987-07-27 1988-10-04 Energy Conversion Devices, Inc. P and n-type microcrystalline semiconductor alloy material including band gap widening elements, devices utilizing same
US5272359A (en) 1988-04-07 1993-12-21 California Institute Of Technology Reversible non-volatile switch based on a TCNQ charge transfer complex
GB8910854D0 (en) 1989-05-11 1989-06-28 British Petroleum Co Plc Semiconductor device
US5159661A (en) 1990-10-05 1992-10-27 Energy Conversion Devices, Inc. Vertically interconnected parallel distributed processor
US5314772A (en) * 1990-10-09 1994-05-24 Arizona Board Of Regents High resolution, multi-layer resist for microlithography and method therefor
JPH0770731B2 (en) * 1990-11-22 1995-07-31 松下電器産業株式会社 Electrical plastic element
US5359205A (en) 1991-11-07 1994-10-25 Energy Conversion Devices, Inc. Electrically erasable memory elements characterized by reduced current and improved thermal stability
US5341328A (en) 1991-01-18 1994-08-23 Energy Conversion Devices, Inc. Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life
US5335219A (en) 1991-01-18 1994-08-02 Ovshinsky Stanford R Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements
US5296716A (en) * 1991-01-18 1994-03-22 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5536947A (en) * 1991-01-18 1996-07-16 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom
US5414271A (en) * 1991-01-18 1995-05-09 Energy Conversion Devices, Inc. Electrically erasable memory elements having improved set resistance stability
US5534711A (en) * 1991-01-18 1996-07-09 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5406509A (en) * 1991-01-18 1995-04-11 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5166758A (en) 1991-01-18 1992-11-24 Energy Conversion Devices, Inc. Electrically erasable phase change memory
US5596522A (en) * 1991-01-18 1997-01-21 Energy Conversion Devices, Inc. Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements
US5534712A (en) * 1991-01-18 1996-07-09 Energy Conversion Devices, Inc. Electrically erasable memory elements characterized by reduced current and improved thermal stability
US5128099A (en) * 1991-02-15 1992-07-07 Energy Conversion Devices, Inc. Congruent state changeable optical memory material and device
US5219788A (en) * 1991-02-25 1993-06-15 Ibm Corporation Bilayer metallization cap for photolithography
US5177567A (en) * 1991-07-19 1993-01-05 Energy Conversion Devices, Inc. Thin-film structure for chalcogenide electrical switching devices and process therefor
US5238862A (en) 1992-03-18 1993-08-24 Micron Technology, Inc. Method of forming a stacked capacitor with striated electrode
US5512328A (en) * 1992-08-07 1996-04-30 Hitachi, Ltd. Method for forming a pattern and forming a thin film used in pattern formation
US5350484A (en) 1992-09-08 1994-09-27 Intel Corporation Method for the anisotropic etching of metal films in the fabrication of interconnects
BE1007902A3 (en) * 1993-12-23 1995-11-14 Philips Electronics Nv Switching element with memory with schottky barrier tunnel.
US5500532A (en) * 1994-08-18 1996-03-19 Arizona Board Of Regents Personal electronic dosimeter
JP2643870B2 (en) * 1994-11-29 1997-08-20 日本電気株式会社 The method of manufacturing a semiconductor memory device
US5543737A (en) 1995-02-10 1996-08-06 Energy Conversion Devices, Inc. Logical operation circuit employing two-terminal chalcogenide switches
US5751012A (en) * 1995-06-07 1998-05-12 Micron Technology, Inc. Polysilicon pillar diode for use in a non-volatile memory cell
US5869843A (en) * 1995-06-07 1999-02-09 Micron Technology, Inc. Memory array having a multi-state element and method for forming such array or cells thereof
US6420725B1 (en) * 1995-06-07 2002-07-16 Micron Technology, Inc. Method and apparatus for forming an integrated circuit electrode having a reduced contact area
DE69614545D1 (en) 1995-06-07 2001-09-20 Micron Technology Inc Stacked buried diode for use with a multi-state material in a non-volatile memory cell
US5789758A (en) 1995-06-07 1998-08-04 Micron Technology, Inc. Chalcogenide memory cell with a plurality of chalcogenide electrodes
US5879955A (en) 1995-06-07 1999-03-09 Micron Technology, Inc. Method for fabricating an array of ultra-small pores for chalcogenide memory cells
US5714768A (en) * 1995-10-24 1998-02-03 Energy Conversion Devices, Inc. Second-layer phase change memory array on top of a logic device
US5694054A (en) 1995-11-28 1997-12-02 Energy Conversion Devices, Inc. Integrated drivers for flat panel displays employing chalcogenide logic elements
US5591501A (en) * 1995-12-20 1997-01-07 Energy Conversion Devices, Inc. Optical recording medium having a plurality of discrete phase change data recording points
US6653733B1 (en) * 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US5687112A (en) 1996-04-19 1997-11-11 Energy Conversion Devices, Inc. Multibit single cell memory element having tapered contact
US5852870A (en) 1996-04-24 1998-12-29 Amkor Technology, Inc. Method of making grid array assembly
US6487106B1 (en) * 1999-01-12 2002-11-26 Arizona Board Of Regents Programmable microelectronic devices and method of forming and programming same
US5761115A (en) * 1996-05-30 1998-06-02 Axon Technologies Corporation Programmable metallization cell structure and method of making same
US5789277A (en) 1996-07-22 1998-08-04 Micron Technology, Inc. Method of making chalogenide memory device
US5998244A (en) * 1996-08-22 1999-12-07 Micron Technology, Inc. Memory cell incorporating a chalcogenide element and method of making same
US6087674A (en) 1996-10-28 2000-07-11 Energy Conversion Devices, Inc. Memory element with memory material comprising phase-change material and dielectric material
US5825046A (en) 1996-10-28 1998-10-20 Energy Conversion Devices, Inc. Composite memory material comprising a mixture of phase-change memory material and dielectric material
US5846889A (en) 1997-03-14 1998-12-08 The United States Of America As Represented By The Secretary Of The Navy Infrared transparent selenide glasses
US5998066A (en) 1997-05-16 1999-12-07 Aerial Imaging Corporation Gray scale mask and depth pattern transfer technique using inorganic chalcogenide glass
US5933365A (en) 1997-06-19 1999-08-03 Energy Conversion Devices, Inc. Memory element with energy control mechanism
US6051511A (en) 1997-07-31 2000-04-18 Micron Technology, Inc. Method and apparatus for reducing isolation stress in integrated circuits
KR100371102B1 (en) 1997-12-04 2003-02-06 엑손 테크놀로지스 코포레이션 Programmable sub-surface aggregating metallization structure and method of making the same
US6011757A (en) * 1998-01-27 2000-01-04 Ovshinsky; Stanford R. Optical recording media having increased erasability
US5912839A (en) * 1998-06-23 1999-06-15 Energy Conversion Devices, Inc. Universal memory element and method of programming same
US6141241A (en) 1998-06-23 2000-10-31 Energy Conversion Devices, Inc. Universal memory element with systems employing same and apparatus and method for reading, writing and programming same
US6297170B1 (en) 1998-06-23 2001-10-02 Vlsi Technology, Inc. Sacrificial multilayer anti-reflective coating for mos gate formation
US6469364B1 (en) 1998-08-31 2002-10-22 Arizona Board Of Regents Programmable interconnection system for electrical circuits
US6388324B2 (en) * 1998-08-31 2002-05-14 Arizona Board Of Regents Self-repairing interconnections for electrical circuits
US6177338B1 (en) * 1999-02-08 2001-01-23 Taiwan Semiconductor Manufacturing Company Two step barrier process
CA2362283A1 (en) 1999-02-11 2000-08-17 Arizona Board Of Regents Programmable microelectronic devices and methods of forming and programming same
US6613604B2 (en) 2001-08-02 2003-09-02 Ovonyx, Inc. Method for making small pore for use in programmable resistance memory element
US6072716A (en) * 1999-04-14 2000-06-06 Massachusetts Institute Of Technology Memory structures and methods of making same
US6143604A (en) 1999-06-04 2000-11-07 Taiwan Semiconductor Manufacturing Company Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM)
US6350679B1 (en) * 1999-08-03 2002-02-26 Micron Technology, Inc. Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry
US6501111B1 (en) 2000-06-30 2002-12-31 Intel Corporation Three-dimensional (3D) programmable device
WO2002021542A1 (en) 2000-09-08 2002-03-14 Axon Technologies Corporation Microelectronic programmable device and methods of forming and programming the same
US6635914B2 (en) 2000-09-08 2003-10-21 Axon Technologies Corp. Microelectronic programmable device and methods of forming and programming the same
US6429064B1 (en) 2000-09-29 2002-08-06 Intel Corporation Reduced contact area of sidewall conductor
US6555860B2 (en) * 2000-09-29 2003-04-29 Intel Corporation Compositionally modified resistive electrode
US6339544B1 (en) * 2000-09-29 2002-01-15 Intel Corporation Method to enhance performance of thermal resistor device
US6563164B2 (en) * 2000-09-29 2003-05-13 Ovonyx, Inc. Compositionally modified resistive electrode
US6404665B1 (en) * 2000-09-29 2002-06-11 Intel Corporation Compositionally modified resistive electrode
US6567293B1 (en) * 2000-09-29 2003-05-20 Ovonyx, Inc. Single level metal memory cell using chalcogenide cladding
US6649928B2 (en) 2000-12-13 2003-11-18 Intel Corporation Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby
US6696355B2 (en) * 2000-12-14 2004-02-24 Ovonyx, Inc. Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory
US6437383B1 (en) 2000-12-21 2002-08-20 Intel Corporation Dual trench isolation for a phase-change memory cell and method of making same
US6569705B2 (en) * 2000-12-21 2003-05-27 Intel Corporation Metal structure for a phase-change memory device
US6646297B2 (en) 2000-12-26 2003-11-11 Ovonyx, Inc. Lower electrode isolation in a double-wide trench
US6534781B2 (en) * 2000-12-26 2003-03-18 Ovonyx, Inc. Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact
US6531373B2 (en) * 2000-12-27 2003-03-11 Ovonyx, Inc. Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements
US6687427B2 (en) * 2000-12-29 2004-02-03 Intel Corporation Optic switch
US6727192B2 (en) * 2001-03-01 2004-04-27 Micron Technology, Inc. Methods of metal doping a chalcogenide material
US6348365B1 (en) * 2001-03-02 2002-02-19 Micron Technology, Inc. PCRAM cell manufacturing
US6818481B2 (en) 2001-03-07 2004-11-16 Micron Technology, Inc. Method to manufacture a buried electrode PCRAM cell
US6825489B2 (en) * 2001-04-06 2004-11-30 Axon Technologies Corporation Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same
EP1397809B1 (en) 2001-05-07 2007-06-27 Advanced Micro Devices Inc. A memory device with a self-assembled polymer film and method of making the same
US6480438B1 (en) 2001-06-12 2002-11-12 Ovonyx, Inc. Providing equal cell programming conditions across a large and high density array of phase-change memory cells
US6589714B2 (en) 2001-06-26 2003-07-08 Ovonyx, Inc. Method for making programmable resistance memory element using silylated photoresist
US6462984B1 (en) 2001-06-29 2002-10-08 Intel Corporation Biasing scheme of floating unselected wordlines and bitlines of a diode-based memory array
US6487113B1 (en) 2001-06-29 2002-11-26 Ovonyx, Inc. Programming a phase-change memory with slow quench time
US6570784B2 (en) * 2001-06-29 2003-05-27 Ovonyx, Inc. Programming a phase-change material memory
US6673700B2 (en) * 2001-06-30 2004-01-06 Ovonyx, Inc. Reduced area intersection between electrode and programming element
US6514805B2 (en) * 2001-06-30 2003-02-04 Intel Corporation Trench sidewall profile for device isolation
US6511862B2 (en) * 2001-06-30 2003-01-28 Ovonyx, Inc. Modified contact for programmable devices
US6511867B2 (en) * 2001-06-30 2003-01-28 Ovonyx, Inc. Utilizing atomic layer deposition for programmable device
US6605527B2 (en) 2001-06-30 2003-08-12 Intel Corporation Reduced area intersection between electrode and programming element
US6642102B2 (en) 2001-06-30 2003-11-04 Intel Corporation Barrier material encapsulation of programmable material
US6951805B2 (en) * 2001-08-01 2005-10-04 Micron Technology, Inc. Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry
US6590807B2 (en) * 2001-08-02 2003-07-08 Intel Corporation Method for reading a structural phase-change memory
US20030047765A1 (en) * 2001-08-30 2003-03-13 Campbell Kristy A. Stoichiometry for chalcogenide glasses useful for memory devices and method of formation
US6507061B1 (en) * 2001-08-31 2003-01-14 Intel Corporation Multiple layer phase-change memory
JP4214055B2 (en) * 2001-09-01 2009-01-28 エナージー コンバーション デバイセス インコーポレイテッドEnergy Conversion Devices, Inc. Increased data storage in an optical data storage and retrieval system using a blue laser and / or plasmon lenses
US6586761B2 (en) 2001-09-07 2003-07-01 Intel Corporation Phase change material memory device
US6545287B2 (en) * 2001-09-07 2003-04-08 Intel Corporation Using selective deposition to form phase-change memory cells
US7109056B2 (en) * 2001-09-20 2006-09-19 Micron Technology, Inc. Electro-and electroless plating of metal in the manufacture of PCRAM devices
US6690026B2 (en) * 2001-09-28 2004-02-10 Intel Corporation Method of fabricating a three-dimensional array of active media
WO2003032392A2 (en) 2001-10-09 2003-04-17 Axon Technologies Corporation Programmable microelectronic device, structure, and system, and method of forming the same
US6566700B2 (en) * 2001-10-11 2003-05-20 Ovonyx, Inc. Carbon-containing interfacial layer for phase-change memory
US6545907B1 (en) * 2001-10-30 2003-04-08 Ovonyx, Inc. Technique and apparatus for performing write operations to a phase change material memory device
US6576921B2 (en) * 2001-11-08 2003-06-10 Intel Corporation Isolating phase change material memory cells
US6667900B2 (en) 2001-12-28 2003-12-23 Ovonyx, Inc. Method and apparatus to operate a memory cell
US6625054B2 (en) 2001-12-28 2003-09-23 Intel Corporation Method and apparatus to program a phase change memory
US6512241B1 (en) * 2001-12-31 2003-01-28 Intel Corporation Phase change material memory device
US6671710B2 (en) 2002-05-10 2003-12-30 Energy Conversion Devices, Inc. Methods of computing with digital multistate phase change materials
US6918382B2 (en) * 2002-08-26 2005-07-19 Energy Conversion Devices, Inc. Hydrogen powered scooter

Cited By (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6833559B2 (en) 2001-02-08 2004-12-21 Micron Technology, Inc. Non-volatile resistance variable device
US20020168852A1 (en) * 2001-05-11 2002-11-14 Harshfield Steven T. PCRAM memory cell and method of making same
US7687793B2 (en) 2001-05-11 2010-03-30 Micron Technology, Inc. Resistance variable memory cells
US7102150B2 (en) 2001-05-11 2006-09-05 Harshfield Steven T PCRAM memory cell and method of making same
US20030027416A1 (en) * 2001-08-01 2003-02-06 Moore John T. Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry
US20030045054A1 (en) * 2001-08-29 2003-03-06 Campbell Kristy A. Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device
US7863597B2 (en) 2001-08-29 2011-01-04 Micron Technology, Inc. Resistance variable memory devices with passivating material
US6881623B2 (en) 2001-08-29 2005-04-19 Micron Technology, Inc. Method of forming chalcogenide comprising devices, method of forming a programmable memory cell of memory circuitry, and a chalcogenide comprising device
US20030045049A1 (en) * 2001-08-29 2003-03-06 Campbell Kristy A. Method of forming chalcogenide comprising devices
US20050157573A1 (en) * 2001-08-29 2005-07-21 Campbell Kristy A. Method of forming non-volatile resistance variable devices
US6813176B2 (en) 2001-08-30 2004-11-02 Micron Technology, Inc. Method of retaining memory state in a programmable conductor RAM
US6791859B2 (en) 2001-11-20 2004-09-14 Micron Technology, Inc. Complementary bit PCRAM sense amplifier and method of operation
US7869249B2 (en) 2001-11-20 2011-01-11 Micron Technology, Inc. Complementary bit PCRAM sense amplifier and method of operation
US20040071042A1 (en) * 2002-01-04 2004-04-15 John Moore PCRAM rewrite prevention
US20040223390A1 (en) * 2002-02-15 2004-11-11 Campbell Kristy A. Resistance variable memory element having chalcogenide glass for improved switching characteristics
US6791885B2 (en) 2002-02-19 2004-09-14 Micron Technology, Inc. Programmable conductor random access memory and method for sensing same
US7723713B2 (en) 2002-02-20 2010-05-25 Micron Technology, Inc. Layered resistance variable memory device and method of fabrication
US8263958B2 (en) 2002-02-20 2012-09-11 Micron Technology, Inc. Layered resistance variable memory device and method of fabrication
US6838307B2 (en) 2002-04-10 2005-01-04 Micron Technology, Inc. Programmable conductor memory cell structure and method therefor
US20030194865A1 (en) * 2002-04-10 2003-10-16 Gilton Terry L. Method of manufacture of programmable conductor memory
US20040038432A1 (en) * 2002-04-10 2004-02-26 Micron Technology, Inc. Programmable conductor memory cell structure and method therefor
US20030206433A1 (en) * 2002-05-03 2003-11-06 Glen Hush Dual write cycle programmable conductor memory system and method of operation
US6731528B2 (en) 2002-05-03 2004-05-04 Micron Technology, Inc. Dual write cycle programmable conductor memory system and method of operation
US7964436B2 (en) 2002-06-06 2011-06-21 Round Rock Research, Llc Co-sputter deposition of metal-doped chalcogenides
US6825135B2 (en) 2002-06-06 2004-11-30 Micron Technology, Inc. Elimination of dendrite formation during metal/chalcogenide glass deposition
US20030228717A1 (en) * 2002-06-06 2003-12-11 Jiutao Li Co-sputter deposition of metal-doped chalcogenides
US20110159661A1 (en) * 2002-07-26 2011-06-30 Laurent Breuil Nonvolatile Memory Element and Production Method Thereof and Storage Memory Arrangement
US8377791B2 (en) * 2002-07-26 2013-02-19 Infineon Technologies Ag Nonvolatile memory element and production method thereof and storage memory arrangement
US20090257299A1 (en) * 2002-08-29 2009-10-15 Gilton Terry L Software refreshed memory device and method
US7944768B2 (en) 2002-08-29 2011-05-17 Micron Technology, Inc. Software refreshed memory device and method
US7768861B2 (en) 2002-08-29 2010-08-03 Micron Technology, Inc. Software refreshed memory device and method
US20070258308A1 (en) * 2002-08-29 2007-11-08 Gilton Terry L Software refreshed memory device and method
US20060104142A1 (en) * 2002-08-29 2006-05-18 Gilton Terry L Software refreshed memory device and method
US7692177B2 (en) 2002-08-29 2010-04-06 Micron Technology, Inc. Resistance variable memory element and its method of formation
US9552986B2 (en) 2002-08-29 2017-01-24 Micron Technology, Inc. Forming a memory device using sputtering to deposit silver-selenide film
US20070035041A1 (en) * 2003-03-14 2007-02-15 Li Li Methods of forming and using memory cell structures
US20050219901A1 (en) * 2003-09-17 2005-10-06 Gilton Terry L Non-volatile memory structure
US8619485B2 (en) 2004-03-10 2013-12-31 Round Rock Research, Llc Power management control and controlling memory refresh operations
US9142263B2 (en) 2004-03-10 2015-09-22 Round Rock Research, Llc Power management control and controlling memory refresh operations
US7749853B2 (en) 2004-07-19 2010-07-06 Microntechnology, Inc. Method of forming a variable resistance memory device comprising tin selenide
US7759665B2 (en) 2004-07-19 2010-07-20 Micron Technology, Inc. PCRAM device with switching glass layer
US7994491B2 (en) 2004-08-12 2011-08-09 Micron Technology, Inc. PCRAM device with switching glass layer
US7785976B2 (en) 2004-08-12 2010-08-31 Micron Technology, Inc. Method of forming a memory device incorporating a resistance-variable chalcogenide element
US8487288B2 (en) 2004-08-12 2013-07-16 Micron Technology, Inc. Memory device incorporating a resistance variable chalcogenide element
US7924603B2 (en) 2004-08-12 2011-04-12 Micron Technology, Inc. Resistance variable memory with temperature tolerant materials
US7682992B2 (en) 2004-08-12 2010-03-23 Micron Technology, Inc. Resistance variable memory with temperature tolerant materials
US8895401B2 (en) 2004-08-12 2014-11-25 Micron Technology, Inc. Method of forming a memory device incorporating a resistance variable chalcogenide element
US8334186B2 (en) 2004-08-12 2012-12-18 Micron Technology, Inc. Method of forming a memory device incorporating a resistance variable chalcogenide element
US7910397B2 (en) 2004-12-22 2011-03-22 Micron Technology, Inc. Small electrode for resistance variable devices
US20080093589A1 (en) * 2004-12-22 2008-04-24 Micron Technology, Inc. Resistance variable devices with controllable channels
US8101936B2 (en) 2005-02-23 2012-01-24 Micron Technology, Inc. SnSe-based limited reprogrammable cell
US7663133B2 (en) 2005-04-22 2010-02-16 Micron Technology, Inc. Memory elements having patterned electrodes and method of forming the same
US7700422B2 (en) 2005-04-22 2010-04-20 Micron Technology, Inc. Methods of forming memory arrays for increased bit density
US7968927B2 (en) 2005-04-22 2011-06-28 Micron Technology, Inc. Memory array for increased bit density and method of forming the same
US7709289B2 (en) 2005-04-22 2010-05-04 Micron Technology, Inc. Memory elements having patterned electrodes and method of forming the same
US7701760B2 (en) 2005-08-01 2010-04-20 Micron Technology, Inc. Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
US7940556B2 (en) 2005-08-01 2011-05-10 Micron Technology, Inc. Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
US7663137B2 (en) 2005-08-02 2010-02-16 Micron Technology, Inc. Phase change memory cell and method of formation
US7709885B2 (en) 2005-08-09 2010-05-04 Micron Technology, Inc. Access transistor for memory device
US8652903B2 (en) 2005-08-09 2014-02-18 Micron Technology, Inc. Access transistor for memory device
US8189366B2 (en) 2005-08-15 2012-05-29 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US7668000B2 (en) 2005-08-15 2010-02-23 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US8611136B2 (en) 2005-08-15 2013-12-17 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US7978500B2 (en) 2005-08-15 2011-07-12 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US8030636B2 (en) 2006-08-29 2011-10-04 Micron Technology, Inc. Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
US7791058B2 (en) 2006-08-29 2010-09-07 Micron Technology, Inc. Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
US7924608B2 (en) 2006-10-19 2011-04-12 Boise State University Forced ion migration for chalcogenide phase change memory device
US8295081B2 (en) 2006-10-19 2012-10-23 Boise State University Forced ion migration for chalcogenide phase change memory device
US8611146B2 (en) 2006-10-19 2013-12-17 Boise State University Forced ion migration for chalcogenide phase change memory device
US20080121859A1 (en) * 2006-10-19 2008-05-29 Boise State University Forced ion migration for chalcogenide phase change memory device
US8238146B2 (en) 2008-08-01 2012-08-07 Boise State University Variable integrated analog resistor
US8467236B2 (en) 2008-08-01 2013-06-18 Boise State University Continuously variable resistor
US20100027324A1 (en) * 2008-08-01 2010-02-04 Boise State University Variable integrated analog resistor
US20110079709A1 (en) * 2009-10-07 2011-04-07 Campbell Kristy A Wide band sensor
US8284590B2 (en) 2010-05-06 2012-10-09 Boise State University Integratable programmable capacitive device

Also Published As

Publication number Publication date
EP1470589A2 (en) 2004-10-27
CN100375284C (en) 2008-03-12
KR100660245B1 (en) 2006-12-20
CN1647278A (en) 2005-07-27
WO2003065456A3 (en) 2003-12-04
US20040029351A1 (en) 2004-02-12
DE60320373T2 (en) 2009-02-19
TW200303040A (en) 2003-08-16
WO2003065456A2 (en) 2003-08-07
JP2005516418A (en) 2005-06-02
TWI251263B (en) 2006-03-11
DE60320373D1 (en) 2008-05-29
AT392714T (en) 2008-05-15
KR20040083432A (en) 2004-10-01
AU2003212814A1 (en) 2003-09-02
EP1470589B1 (en) 2008-04-16
US6812087B2 (en) 2004-11-02

Similar Documents

Publication Publication Date Title
JP4824278B2 (en) Variable resistance material cell and manufacturing method thereof
US8697533B2 (en) Method for obtaining smooth, continuous silver film
CN101461071B (en) A vertical phase change memory cell and methods for manufacturing thereof
US7364935B2 (en) Common word line edge contact phase-change memory
US7608503B2 (en) Side wall active pin memory and manufacturing method
US7332370B2 (en) Method of manufacturing a phase change RAM device utilizing reduced phase change current
US7033856B2 (en) Spacer chalcogenide memory method
US8143089B2 (en) Self-align planerized bottom electrode phase change memory and manufacturing method
US9012307B2 (en) Two terminal resistive switching device structure and method of fabricating
US8008114B2 (en) Phase change memory device and manufacturing method
US6867064B2 (en) Method to alter chalcogenide glass for improved switching characteristics
CN100481389C (en) Programmable resistive RAM and manufacturing method thereof
EP1748488B1 (en) Semiconductor memory
US8637113B2 (en) Methods of forming a non-volatile resistive oxide memory array
JP3896576B2 (en) Non-volatile memory and manufacturing method thereof
US6867996B2 (en) Single-polarity programmable resistance-variable memory element
JP4751880B2 (en) Laminated variable resistance memory devices and a manufacturing method thereof
US7504653B2 (en) Memory cell device with circumferentially-extending memory element
US20070131922A1 (en) Thin Film Fuse Phase Change Cell with Thermal Isolation Pad and Manufacturing Method
JP2519612B2 (en) Method for manufacturing a silicon layer surface area is maximized
US7785920B2 (en) Method for making a pillar-type phase change memory element
US20070158632A1 (en) Method for Fabricating a Pillar-Shaped Phase Change Memory Element
CN101170159B (en) Carbon filament memory and fabrication method
US7579615B2 (en) Access transistor for memory device
JP4067490B2 (en) Method of forming a programmable memory cell forming method and a memory circuit of the nonvolatile resistance variable device

Legal Events

Date Code Title Description
AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GILTON, TERRY L.;CAMPBELL, KRISTY A.;MOORE, JOHN T.;REEL/FRAME:012572/0361;SIGNING DATES FROM 20020124 TO 20020125