US6545907B1 - Technique and apparatus for performing write operations to a phase change material memory device - Google Patents
Technique and apparatus for performing write operations to a phase change material memory device Download PDFInfo
- Publication number
- US6545907B1 US6545907B1 US10/021,469 US2146901A US6545907B1 US 6545907 B1 US6545907 B1 US 6545907B1 US 2146901 A US2146901 A US 2146901A US 6545907 B1 US6545907 B1 US 6545907B1
- Authority
- US
- United States
- Prior art keywords
- memory
- state
- group
- cells
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0076—Write operation performed depending on read result
Definitions
- This invention generally relates to electronic memories, and more particularly, the invention relates to a technique and apparatus for performing write operations to a phase change material memory device.
- phase change material may be used to store the memory state for a memory cell of a semiconductor memory device.
- phase change materials that are used in phase change material memory devices may exhibit at least two different states.
- the states may be called the amorphous and crystalline states. Transitions between these states may be selectively initiated.
- the states may be distinguished because the amorphous state generally exhibits higher resistivity than the crystalline state.
- the amorphous state involves a more disordered atomic structure.
- any phase change material may be utilized to exhibit these two states.
- thin-film chalcogenide alloy materials may be particularly suitable.
- phase change may be induced reversibly. Therefore, the phase change material may change from the amorphous to the crystalline state and may revert back to the amorphous state thereafter, or vice versa, in response to temperature changes.
- the memory cell may be thought of as a programmable resistor, which reversibly changes between higher and lower resistance states.
- the phase change may be induced by resistive heating that is caused by a current that flows through the material.
- the memory cell of a phase change memory device is not limited to just two memory states (i.e., a “1” state and a “0” state), but instead the memory cell may have a large number of states. That is, because each state may be distinguished by its resistance, a number of resistance determined states may be possible, allowing the storage of multiple bits of data in a single memory cell.
- phase change alloys are known.
- chalcogenide alloys contain one or more elements from Column VI of the periodic table.
- One particularly suitable group of alloys is the GeSbTe alloys.
- FIG. 1 depicts temperature profiles that cause a particular phase change material to change states.
- FIG. 1 depicts a crystallizing set pulse 20 that generally extends from about time T 0 to time T 2 to place the phase change material in the crystalline state.
- the set pulse 20 represents a momentary rise in the temperature of the phase change material.
- the set pulse 20 is to be contrasted to the reset pulse 10 , a pulse that is also associated with a higher temperature of the phase change material but has a significantly shorter duration, as the reset pulse 10 extends from about time T 0 to T 1 .
- the reset pulse 10 may be used to transform a phase change material-based memory cell from the crystalline state to the amorphous state, or “reset” the state of the memory cell to “0.”
- the set pulse 20 may be used to set the state of the memory cell to “1.”
- the write set cycle time i.e., the time allocated to force the state of the cell to indicate a set bit, or a “1”
- the write reset cycle time i.e., the time allocated to force the state of the cell to indicate a reset bit, or a “0”.
- a conventional approach for a memory device that exhibits such a discrepancy in time between different types of write cycles is to set the time allocated for a given write cycle to the time needed to perform the slowest possible write cycle.
- the slowest write cycle may effectively establish the write cycle speed of the memory device.
- a conventional way to accommodate a slow memory device is to either use a high speed static random access memory (SRAM) cache or shift registers to buffer a high data rate burst.
- SRAM static random access memory
- several slow speed memories may be mounted in parallel such that alternative pieces of data may be put into the data latch of the first memory, the next piece of data stored in the latch of the second memory, etc.
- a potential difficulty with these approaches is that a large number of memory chips may be required, and thus, there is a greater associated cost per bit.
- FIG. 1 depicts temperature waveforms for setting and resetting a memory cell of a phase change material memory device of the prior art.
- FIG. 2 is a schematic diagram of a computer system according to an embodiment of the invention.
- FIG. 3 is a flow diagram depicting a technique for a block write operation to a phase change material memory device according to an embodiment of the invention.
- FIG. 4 is a schematic diagram of a phase change material memory device according to an embodiment of the invention.
- FIG. 5 is a truth table associated with a row decoder of the phase change material memory device of FIG. 4 according to an embodiment of the invention.
- FIG. 6 is a schematic diagram of a column decoder of the phase change material memory device of FIG. 4 according to an embodiment of the invention.
- FIG. 7 is a schematic diagram of a memory controller of the computer system of FIG. 2 according to an embodiment of the invention.
- an embodiment 30 of a computer system in accordance with the invention includes a phase change material memory 32 that communicates with a memory controller hub 34 via a memory bus 36 .
- the phase change material memory 32 may include various memory devices (semiconductor memory chips, or packages, for example), each of which includes phase change material-based memory cells.
- each memory cell of a particular memory device may include a phase change material (a thin-film chalcogenide alloy material, for example) that exhibits crystalline and amorphous states. These states, in turn, are used to indicate the data states (“1” and “0” states, for example) of the memory cell.
- the memory bus 36 includes communication lines for communicating data to and from the memory 32 as well as control and address lines for controlling the storage and retrieval of data to and from the memory 32 .
- a particular write or read operation may involve concurrently writing data to or reading data from several devices of memory 32 .
- the time to set a bit of the memory 32 is significantly longer than the time to reset the bit of the memory 32 .
- a write operation in accordance with the invention may be performed pursuant to a technique 100 that is depicted in FIG. 3 .
- the memory controller hub 34 furnishes the appropriate signals to the memory bus 36 to preset the memory cells in the selected region, as depicted in block 102 .
- the presetting of a particular memory cell in the phase change material memory 32 is, in general, relatively slow as compared to the resetting of the memory cell, the targeted memory cells may be preset by one or more block write cycles.
- the preset time per memory cell is relatively small due.
- the write operation to the selected region of the memory 32 continues by selectively resetting (block 104 ) bits of the selected region.
- the memory cells that are associated with the “0” bits of write data are reset (via write preset cycles), while the memory cells that are associated with the “1” bits of the data are masked from the write operation, as these memory cells have been preset.
- FIG. 4 depicts a particular memory device 33 of the memory 32 in accordance with some embodiments of the invention.
- the specific structure of the memory device 33 is depicted for purposes of describing at least one out of many possible embodiments of the invention. It is understood that other and different structures may be used, as the scope of the invention is defined by the appended claims.
- the memory device 33 includes memory cells 140 that are addressed via column lines 130 and row lines 132 , as can be appreciated by those skilled in the art.
- Each memory cell 140 includes a phase change material whose state is controlled by write preset/set cycles to store an associated bit of data.
- the memory device 33 may have a significantly larger array of memory cells 140 .
- each memory cell 140 is associated with a particular column line 130 and a particular row line 132 , and the activation of the associated column 130 and row 132 lines selects the cell 140 .
- the memory cell 140 may be coupled to its associated column line 130 and may be coupled through what is effectively a diode 142 (a PNP bipolar junction transistor (BJT), for example) to its associated row line 132 . Therefore, when a particular memory cell 140 is selected, its associated column line 130 is driven high and its associated row line 132 is driven low, a condition that causes a current pulse to flow through the memory cell 140 . It is the magnitude and duration of this current pulse that determines whether the memory cell 140 is being read, set (via a write set pulse) or reset (via a write reset pulse).
- BJT PNP bipolar junction transistor
- the row decoder 124 In response to address signals (called A 0 , A 1 , WB 0 and WB 1 ), the row decoder 124 selects one or more row lines 132 , corresponding to the selection of one, two or four row lines 132 . In this manner, the row decoder 124 , in response to these address signals, selectively drives row select signals (called X 0 , X 1 , X 2 and X 3 ) low to select one or more of the row lines 132 .
- a certain combination of the address signals may cause the row decoder 124 to select two of the row lines
- another combination of the address signals may cause the row decoder 124 to select one of the row lines 132
- another combination of the address signals may cause the row decoder 124 to select four of the row lines 132 , etc.
- the row decoder 124 drives the row line(s) 132 low, this enables a read or write cycle to occur to one or more memory cells 140 , depending on the selections by the column decoder 122 .
- the column decoder 122 in response to its received address selection signals (called A 2 , A 3 , WB 3 and WB 2 ) drives column select signals (called Y 0 , Y 1 , Y 2 and Y 3 ) high to select one or more column lines 130 . In this manner, when one of the column select signals is driven high, the corresponding column line 130 has been selected. Similar to the row decoder 124 , the column decoder 122 may select one, two or four column lines 130 . Thus, the selection of the column line(s) by the column decoder 122 and the row line(s) 132 by the row decoder 124 addresses selected memory cells 140 and may be used to address a block of the memory cells 140 .
- the column decoder 122 receives signals called QUENCH and SET_SLOPE.
- the SET_SLOPE signal establishes a slope in the current/temperature profile that is used to set particular memory cells(s). In this manner, when the SET_SLOPE signal is asserted (driven high, for example) during a write set cycle, the column decoder 122 imparts a trailing edge on the set pulse, as described further below. Conversely when the set SLOPE signal is de-asserted (driven low, for example) during a write reset cycle, the column decoder 122 does not add this trailing edge.
- the QUENCH signal is used to control the time at which the set or reset pulse ends. In this manner, in response to the QUENCH signal being asserted (driven high, for example), the column decoder 122 ends the current reset/set pulses. Conversely, in response to the QUENCH signal being deasserted, the column decoder 122 allows the current reset or set pulses (if occurring) to continue. Thus, the QUENCH signal may be used to end the slope established by the SET_SLOPE signal during a write set cycle.
- FIG. 5 depicts a truth table 110 that illustrates the selection of the row select signals X 0 , X 1 , X 2 and X 3 in response to various states for the address decode signals A 0 , A 1 , WB 0 and WB 1 .
- the row decoder 120 drives only the X 3 row select signal to select one corresponding row line 132 .
- Other individual row lines 132 maybe selected by combinations of the A 0 and A 1 signals, as depicted in rows 1 - 4 of the truth table 110 . For these selections by the A 0 and A 1 signals, it is noted that the WB 0 and WB 1 signals are driven low. Rows 5 and 6 of the truth table 110 depict combinations possible when the WB 0 signal is driven high and the WB 1 signal is driven low. As shown, for these states, two row lines 132 are selected, and the two particular row lines that are selected depend on the state of the A 1 signal. When both the WB 0 and WB 1 signals are driven high, then all of the row lines 132 are selected, as depicted in line 7 of the truth table 110 . Other combinations may be used to select the rows 132 .
- FIG. 6 depicts one out of many possible embodiments for the column decoder 122 .
- the column decoder 122 includes drive circuits 150 (drive circuits 150 a , 150 b , 150 c and 150 d , as examples), each of which is associated with a different column line 130 .
- a particular drive circuit 150 is activated for purposes of selecting and reading/writing data from one or more cells 140 of its associated column line 130 in response to a signal that is provided by a decode circuit 180 .
- the decode circuit 180 receives the column address signals A 2 , A 3 , WB 2 and WB 3 and furnishes decode signals called DECY 0 , DECY 1 , DECY 2 and DECY 3 that are used to activate the decode circuits 150 a , 150 b , 150 c and 150 d , respectively.
- the drive circuit 150 a is activated in response to the assertion of the DECY 0 signal by the decode circuit 180 .
- the drive circuit 150 may have the circuitry that is illustrated in FIG. 6 for the drive circuit 150 a .
- the drive circuit 150 may include a P-channel metal-oxide-semiconductor field-effect-transistor (PMOSFET) 154 that has its source terminal coupled to a positive voltage supply (called VCC) and its drain terminal coupled to the source terminal of a PMOSFET 158 .
- VCC positive voltage supply
- the drain terminal of the PMOSFET 158 is coupled to the column line 130 that is associated with the drive circuit 150 .
- the gate terminal of the PMOSFET 154 receives the corresponding decode signal (DECY 0 , DECY 1 , DECY 2 or DECY 3 ) from the decode circuit 180 .
- the gate terminal of the PMOSFET 154 receives the DECY 0 signal.
- this signal is asserted (driven high, for example) the drain-source path of the PMOSFET 154 conducts a current that, in a write cycle, is established by the PMOSFET 158 .
- the gate terminal of the PMOSFET 158 receives a current sense signal (called S 2 ) that establishes the current through the drain-source path of the PMOSFET 154 , the drain-source path of the PMOSFET 158 and the current that flows into the associated column line 130 .
- S 2 a current sense signal
- the column decoder 122 adjusts the magnitude of the S 2 signal so that each activated drive circuit 150 provides more current to its associated column line 130 when two memory cells 140 per selected column line 130 are being written than when one memory cell 140 per selected column line 130 is being written. Furthermore, in response to the selection of four memory cells 140 per column line 130 , the column decoder 122 adjusts the magnitude of the S 2 signal so that more current is applied to the selected column line 130 than when one memory cell per selected column line 130 is being written.
- the drive circuit 150 includes a PMOSFET 156 .
- the source terminal of PMOSFET 156 is coupled to the drain terminal of the PMOSFET 154
- the drain terminal of the PMOSFET 156 is coupled to the column line 130 that is associated with the drive circuit 150 .
- the gate terminal of PMOSFET 156 receives a current sense called S 1 .
- the column decoder 122 adjusts the magnitude of the S 1 signal to adjust the level of current that flows through the associated column line 130 during a read operation, as the drain-path of the PMOSFET 156 is coupled in series with the drain-source path of the PMOSFET 154 in the column line 130 .
- the other drive circuits 150 b , 150 c and 150 d may have similar designs, in some embodiments of the invention. Other designs are possible for the drive circuit 150 , in other embodiments of the invention.
- the column decoder 122 includes the following circuitry.
- This circuitry includes a PMOSFET 186 that has its gate terminal coupled to ground.
- the source terminal of the PMOSFET 186 is coupled to a positive supply voltage (called VCC), and the drain terminal of the PMOSFET 186 is coupled to the source terminal of a PMOSFET 184 .
- the gate and drain terminals of the PMOSFET 184 are coupled together to furnish the S 2 signal. These terminals are also coupled to one terminal of a resistor 188 .
- the other terminal of the resistor 188 is coupled to the drain terminal of an N-channel MOSFET (NMOSFET) 194 that has its source terminal coupled to ground.
- the gate terminal of the NMOSFET 194 receives a signal called W 4 .
- the NMOSFET 194 conducts, as determined by the resistance of the resister 188 , a current that flows through the PMOSFETs 184 and 186 . This current, in turn establishes the level of the S 2 signal that, in turn, establishes the current that flows through the selected column lines 130 .
- the resistor 188 and the NMOSFET 194 are part of a slope circuit 200 .
- the column decoder 122 includes three such slope circuits 200 a , 200 b and 200 c .
- the differences between the slope circuits are established by the value of the resistance 188 and the signal received at the gate terminal of the NMOSFET 194 .
- the slope circuit 200 b receives a signal called W 2
- the slope circuit 200 c receives a signal called W 1 .
- both the W 1 and W 2 signals are asserted (driven high, for example) to cause twice the level of current to flow than when one memory cell 140 per column line 130 is written through the select column line 130 .
- the W 1 , W 2 , and W 4 signals are all asserted (driven high, for example) to cause additional current to flow through the selected column lines 130 .
- the resistances of the resistors 188 in each of the slope circuits 200 have the appropriate values to implement the necessary binary weighting of the current among the slope circuits 200 .
- each slope circuit 200 includes a MOSFET 190 and a capacitor 192 .
- the gate terminal of the MOSFET 190 receives the SET_SLOPE signal, and the source terminal of the MOSFET 190 is coupled to ground.
- the drain terminal of the MOSFET 190 is coupled to one terminal of a capacitor 192 , and the other terminal of the capacitor 192 is coupled to the drain terminal of the MOSFET 194 .
- the SET_SLOPE signal is asserted to cause both terminals of the capacitor 192 to be coupled to ground. Therefore, when the MOSFET 194 de-activated, the capacitor 192 introduces a time constant to produce the trailing edge of the set pulse. The end of the set pulse may be controlled via the assertion of the QUENCH signal.
- the memory device 33 may include a control circuit 400 to generate signals to control such cycles in the memory device 33 as the read cycles, write preset cycles and write reset cycles.
- the control circuit 400 receives signals (via input lines 401 ) from the memory bus 36 indicative of potential addresses and commands that involve the memory device 33 .
- the control circuit 300 may decode a burst write operation and generate the appropriate signals to control the storage of data associated with the burst write operation in targeted memory cells 140 of the memory device 33 .
- the memory device 33 may also include additional circuitry, such as, for example, a data buffer 402 to temporarily store the data flowing into and out of the memory device 33 and communicates data to the memory bus 36 via data communication lines 405 .
- the memory device 33 may also include an address buffer 408 that communicates with the memory bus via communication lines 407 .
- the address buffer 408 shares the addresses associated with memory operations as well as decodes the addresses and to some extent may generate the address signals (on the communication lines 410 ) that are provided to the row 124 and column 122 decoders.
- the computer system 30 may include other components than the memory controller hub 34 and the memory 32 .
- the computer system 30 may include a processor 42 (one or more microprocessors or controllers, as examples) that is coupled to a system bus 40 .
- the system bus 40 is coupled to the memory controller hub 34 along with an Accelerated Graphics Port (AGP) bus 44 .
- AGP Accelerated Graphics Port
- the AGP is described in detail in the Accelerated Graphics Port Interface Specification, Revision 1.0, published on Jul. 31, 1996, by Intel Corporation of Santa Clara, Calif.
- the computer system 30 may also include a display controller 46 that is coupled to the AGP bus 44 and generates signals to drive a display 48 .
- the memory controller hub 34 is also coupled (via a hub interface 50 ) to an input/output (I/O) hub 52 .
- the I/O hub 52 may provide interfaces to, for example a Peripheral Component Interconnect (PCI) bus 54 and an expansion bus 62 .
- PCI Peripheral Component Interconnect
- the PCI Specification is available from The PCI Special Interest Group, Portland, Oreg. 97214.
- the PCI bus 54 may be coupled to a network interface card (NIC) 56 , and the I/O controller 64 may receive input from a mouse 66 , and the I/O controller 64 may receive input from a mouse 66 and a keyboard 68 , as well as control operation of a floppy disk drive 70 .
- the I/O hub 52 may also control operation of a CD-ROM drive 58 and control operation of a hard disk drive 60 .
- the memory controller hub 34 may include a memory controller 35 .
- the memory controller 35 serves as an interface between the memory bus 36 and the PCI 54 , system 40 and AGP 44 buses.
- the memory controller 35 generates signals to indicate the control signals, address signals and data signals that are associated with a particular write or read operation that targets cells of the phase change material memory 32 .
- the memory controller 35 includes an address buffer 300 that receives (via address lines 302 ) address signals that indicate an address for an associated write or read request, a data buffer 304 that receives (via data lines 306 ) signals that are indicative of data to be written to/read from the memory 32 , and a bus control circuit 310 that receives (via control lines 312 ) signals indicative of the operation to be performed with the memory.
- the memory controller 35 may perform both write and read operations with the memory 32 , the block write operation is discussed below.
- the memory controller 35 includes an address multiplexer 316 that receives a signal indicative of an address from the address buffer 300 targeting the next region of the memory 32 to which a write operation is to be performed.
- the memory controller 35 also includes a memory buffer 320 that receives data (from the data buffer) that is associated with a subsequent write operation to be performed to the memory 32 .
- a control circuit 305 of the memory controller 35 coordinates the operation of the memory controller 35 via its control lines 308 .
- the address multiplexer 316 furnishes signals on its output lines 350 indicative of the address for a particular write operation, and the memory buffer 320 generates signals on its output lines 352 indicative of data to be written to the memory 32 in a particular write operation.
- the memory controller 35 performs a write operation to the memory 32 in response to a write request.
- the write request for a particular block write operation may be received by the memory controller 35 or may alternatively be generated by the memory controller 35 itself.
- the memory controller 35 may queue unconnected write operations until the memory controller 35 gathers data that targets a contiguous region of the memory 32 . In this manner, when the block of write data is accumulated, the memory controller 35 has effectively initiated its own write request.
- each memory device 33 may perform the technique 100 in a manner that is transparent outside of the memory device 33 .
- memory cells 140 of the memory device 33 may be the target of a write operation, such as a burst write operation, for example.
- the memory device 33 presets the targeted memory cells 140 via a block write preset cycle and then subsequently selectively resets the targeted memory cells 140 via write reset cycles.
- the presetting of a block of memory cells 140 may be accomplished through the execution of software instructions by the processor 42 .
- the processor 42 may generate a write request that is communicated to the memory controller 35 for purposes of writing a block of ones to a targeted region of the memory 42 .
- the processor 42 generates a write request that is communicated to the memory controller 35 for purposes of writing the data to be stored in the targeted region.
- the memory devices 33 that are involved in the write operation may mask off the memory cells 140 that are associated with “1” bits from being written in this subsequent write operation.
- the memory controller 35 may perform the technique 100 by, in response to a write request, first generating signals on the memory bus 36 to initiate a write operation to the memory 32 to write a block of “1” bits to a targeted region of the memory 42 . Next, the memory controller 35 generates signals on the memory bus 36 to initiate a memory operation to the memory 32 to write the data to be stored in the targeted region. In this manner, the memory devices 33 that are involved in the write operation may mask off the memory cells 140 that are associated with “1” bits from being written.
- the memory controller 35 initiates the preset and set write cycles in the memory 32 in accordance with the technique 100 . In this manner, to write a block of data to a targeted region of the memory 32 , the memory controller 35 first writes a block of ones to the targeted region. Next, the memory controller 35 may mask off bytes associated with all ones and generates the appropriate write requests to store the block of data in the targeted region. The masking of the one bits may also be performed by each memory device 33 .
- phase change material memory 32 and the associated circuitry to control operation of the memory 32 may be used in systems other than the computer system 30 .
- the above-described circuitry may be used in a cellular telephone, personal assistant, or other devices, as just a few examples.
- the write reset cycle is performed with an optimum current that is a function of the Chalcogenide target used for depositing it, pore size, and height. If a DVD style target is used with a small pore size under 0.2 ⁇ m ⁇ 0.2 ⁇ m, the required current for reset may be about 3 ma, for example.
- the reset pulse is applied with a rapid leading edge under 2 nsec, about 10 nsec of width, and a fast trailing edge of under 2 nsec.
- the write set cycle uses a current of more like 2 ma with fast leading and trailing edges, such as a 3 ma current (like the reset current), a fast leading edge under 2 nsec, and a slow trailing edge between 250 nanoseconds (nsec) and preferably 2 microseconds ( ⁇ s) to assure optimum writing for various material imperfections that may occur.
- a current of more like 2 ma with fast leading and trailing edges such as a 3 ma current (like the reset current), a fast leading edge under 2 nsec, and a slow trailing edge between 250 nanoseconds (nsec) and preferably 2 microseconds ( ⁇ s) to assure optimum writing for various material imperfections that may occur.
- the current for set may be equal to reset.
- a peak current for set that is 10% less, and maybe even 30% less will work equally well for set, even if the reset current is at the minimum that will work.
- Reset is preferably set at the minimum reset current plus at least 30%. Usually the reset level is at least 30% more than that required for set. Hence, good margin is maintained if the set peak current is equal to Reset or 30% less.
- the design is preferably done with peak set current equal to peak reset current.
- the reset height is about 3 ma and at least 30% greater than typical minimums, width is 10 nsec, with a rising edge reasonably fast, say 2-5 nsec, and a trailing edge well less than 10 nsec and preferably less than 5 nsec.
- Set preferably has a rising edge like reset, a peak current preferably equal to but at least within 30% of reset, with a trailing edge 3 times greater than the slope required to write with set current equal to reset current, preferably 1 usec for good margin.
- the technique described herein may be used not just for a high speed burst of a block, but also for presetting a set of words, line, or any sub-block.
- the technique that is described herein may preferably be extended to sequential sets of bursts (which also may be for less than a block). When a sequential bursts are predictably loaded into blocks or sub-blocks within the memory, the next block or sub-block to be written can be pre-set while the current burst of data is being loaded.
- block 1 when frames of video are to be sequentially loaded in blocks 1 - 60 for a video sequence, block 1 can be preset to the set state, and the burst of data loaded into block 1 . While block 1 is loading, block 2 can be preset to the set state so it is ready to load when block 1 is complete. Then, while block 2 is loading, block 3 can be preset.
- the presetting of block N+1 during loading of block N can be extended by one skilled in the art to involve parallel preset of more than one block at once at appropriate times and for appropriate utilization—at reduced risk of premature overlaying a section of memory. By doing presetting in advance, even greater bandwidth may be achieved since a memory need not pause during preset before being loaded.
- pre-set is already complete, continuous loading at the high reset write time per bit(s) can be done, avoiding the “down time” of presetting. Further, by pre-setting in parallel with loading, fewer simultaneous bits per cycle may be preset, reducing the magnitude of the current pulse and need for decoupling transients. This technique of presetting the next block while loading this block may be done automatically or under user explicit command control, a decision that may be controlled by a user input to the memory.
Abstract
Description
Claims (40)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/021,469 US6545907B1 (en) | 2001-10-30 | 2001-10-30 | Technique and apparatus for performing write operations to a phase change material memory device |
KR1020047006453A KR100586351B1 (en) | 2001-10-30 | 2002-08-21 | Technique and apparatus for performing write operations to a phase change material memory device |
PCT/US2002/026672 WO2003038830A1 (en) | 2001-10-30 | 2002-08-21 | Technique and apparatus for performing write operations to a phase change material memory device |
CN02826572.6A CN1610952B (en) | 2001-10-30 | 2002-08-21 | Technique and apparatus for performing write operations to a phase change material memory device |
TW091119854A TWI222064B (en) | 2001-10-30 | 2002-08-30 | Technique and apparatus for performing write operations to a phase change material memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/021,469 US6545907B1 (en) | 2001-10-30 | 2001-10-30 | Technique and apparatus for performing write operations to a phase change material memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
US6545907B1 true US6545907B1 (en) | 2003-04-08 |
US20030081451A1 US20030081451A1 (en) | 2003-05-01 |
Family
ID=21804414
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/021,469 Expired - Lifetime US6545907B1 (en) | 2001-10-30 | 2001-10-30 | Technique and apparatus for performing write operations to a phase change material memory device |
Country Status (5)
Country | Link |
---|---|
US (1) | US6545907B1 (en) |
KR (1) | KR100586351B1 (en) |
CN (1) | CN1610952B (en) |
TW (1) | TWI222064B (en) |
WO (1) | WO2003038830A1 (en) |
Cited By (105)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020116955A1 (en) * | 2001-02-19 | 2002-08-29 | Sumitomo Electric Industries, Ltd. | Method of forming soot preform |
US20020138301A1 (en) * | 2001-03-22 | 2002-09-26 | Thanos Karras | Integration of a portal into an application service provider data archive and/or web based viewer |
US20020168852A1 (en) * | 2001-05-11 | 2002-11-14 | Harshfield Steven T. | PCRAM memory cell and method of making same |
US20030045049A1 (en) * | 2001-08-29 | 2003-03-06 | Campbell Kristy A. | Method of forming chalcogenide comprising devices |
US20030047772A1 (en) * | 2001-03-15 | 2003-03-13 | Jiutao Li | Agglomeration elimination for metal sputter deposition of chalcogenides |
US20030096497A1 (en) * | 2001-11-19 | 2003-05-22 | Micron Technology, Inc. | Electrode structure for use in an integrated circuit |
US20030117831A1 (en) * | 2001-12-20 | 2003-06-26 | Glen Hush | Programmable conductor random access memory and a method for writing thereto |
US20030128612A1 (en) * | 2002-01-04 | 2003-07-10 | John Moore | PCRAM rewrite prevention |
US20030156468A1 (en) * | 2002-02-20 | 2003-08-21 | Campbell Kristy A. | Resistance variable 'on' memory |
US20030155606A1 (en) * | 2002-02-15 | 2003-08-21 | Campbell Kristy A. | Method to alter chalcogenide glass for improved switching characteristics |
US20030156463A1 (en) * | 2002-02-19 | 2003-08-21 | Casper Stephen L. | Programmable conductor random access memory and method for sensing same |
US20030169625A1 (en) * | 2002-03-05 | 2003-09-11 | Glen Hush | Programmable conductor random access memory and method for sensing same |
US20030173558A1 (en) * | 2002-03-14 | 2003-09-18 | Campbell Kristy A. | Methods and apparatus for resistance variable material cells |
US20030193059A1 (en) * | 2002-04-10 | 2003-10-16 | Gilton Terry L. | Programmable conductor memory cell structure and method therefor |
US20030194865A1 (en) * | 2002-04-10 | 2003-10-16 | Gilton Terry L. | Method of manufacture of programmable conductor memory |
US20030193053A1 (en) * | 2002-04-10 | 2003-10-16 | Gilton Terry L. | Thin film diode integrated with chalcogenide memory cell |
US20040007718A1 (en) * | 2001-08-30 | 2004-01-15 | Campbell Kristy A. | Stoichiometry for chalcogenide glasses useful for memory devices and method of formation |
US20040007749A1 (en) * | 2002-07-10 | 2004-01-15 | Campbell Kristy A. | Assemblies displaying differential negative resistance |
US20040029351A1 (en) * | 2002-01-31 | 2004-02-12 | Gilton Terry L. | Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures |
US20040038480A1 (en) * | 2002-08-22 | 2004-02-26 | Moore John T. | Method of manufacture of a PCRAM memory cell |
US20040043553A1 (en) * | 2002-06-06 | 2004-03-04 | Jiutao Li | Elimination of dendrite formation during metal/chalcogenide glass deposition |
US20040040835A1 (en) * | 2002-08-29 | 2004-03-04 | Jiutao Li | Silver selenide film stoichiometry and morphology control in sputter deposition |
US20040040837A1 (en) * | 2002-08-29 | 2004-03-04 | Mcteer Allen | Method of forming chalcogenide sputter target |
US20040043245A1 (en) * | 2002-08-29 | 2004-03-04 | Moore John T. | Method to control silver concentration in a resistance variable memory element |
US20040053461A1 (en) * | 2002-08-29 | 2004-03-18 | Moore John T. | Graded GexSe100-x concentration in PCRAM |
US20040124406A1 (en) * | 2001-08-29 | 2004-07-01 | Campbell Kristy A. | Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device |
US20040130598A1 (en) * | 2002-07-10 | 2004-07-08 | Canon Kabushiki Kaisha | Ink jet record head |
US20040145941A1 (en) * | 2002-10-15 | 2004-07-29 | Rust Thomas F | Phase change media for high density data storage |
US20040157417A1 (en) * | 2002-08-29 | 2004-08-12 | Moore John T. | Methods to form a memory cell with metal-rich metal chalcogenide |
US20040161874A1 (en) * | 2001-03-01 | 2004-08-19 | Moore John T. | Method of forming a non-volatile resistance variable device, and non-volatile resistance variable device |
US20040175859A1 (en) * | 2002-08-29 | 2004-09-09 | Campbell Kristy A. | Single polarity programming of a PCRAM structure |
US20040180533A1 (en) * | 2003-03-14 | 2004-09-16 | Li Li | Method for filling via with metal |
US20040192006A1 (en) * | 2002-02-20 | 2004-09-30 | Campbell Kristy A. | Layered resistance variable memory device and method of fabrication |
US20040202016A1 (en) * | 2003-04-10 | 2004-10-14 | Campbell Kristy A. | Differential negative resistance memory |
US6809362B2 (en) | 2002-02-20 | 2004-10-26 | Micron Technology, Inc. | Multiple data state memory cell |
US20040211957A1 (en) * | 2002-08-29 | 2004-10-28 | Moore John T. | Method and apparatus for controlling metal doping of a chalcogenide memory element |
US6813178B2 (en) | 2003-03-12 | 2004-11-02 | Micron Technology, Inc. | Chalcogenide glass constant current device, and its method of fabrication and operation |
US20040235235A1 (en) * | 2002-06-06 | 2004-11-25 | Jiutao Li | Co-sputter deposition of metal-doped chalcogenides |
US20040246804A1 (en) * | 2003-06-03 | 2004-12-09 | Samsung Electronics Co., Ltd. | Device and method for pulse width control in a phase change memory device |
US6833559B2 (en) | 2001-02-08 | 2004-12-21 | Micron Technology, Inc. | Non-volatile resistance variable device |
US20040264234A1 (en) * | 2003-06-25 | 2004-12-30 | Moore John T. | PCRAM cell operation method to control on/off resistance variation |
US20050017233A1 (en) * | 2003-07-21 | 2005-01-27 | Campbell Kristy A. | Performance PCRAM cell |
US20050018509A1 (en) * | 2001-11-20 | 2005-01-27 | Glen Hush | Complementary bit resistance memory sensor and method of operation |
US20050026433A1 (en) * | 2001-08-30 | 2005-02-03 | Jiutao Li | Integrated circuit device and fabrication using metal-doped chalcogenide materials |
US20050054207A1 (en) * | 2002-08-29 | 2005-03-10 | Micron Technology, Inc. | Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes |
US20050056910A1 (en) * | 2003-09-17 | 2005-03-17 | Gilton Terry L. | Non-volatile memory structure |
US20050117388A1 (en) * | 2003-11-27 | 2005-06-02 | Samsung Electronics Co., Ltd | Write driver circuit in phase change memory device and method for applying write current |
US20050117387A1 (en) * | 2003-03-27 | 2005-06-02 | Young-Nam Hwang | Phase-change memory and method having restore function |
US20050122771A1 (en) * | 2003-12-05 | 2005-06-09 | Bomy Chen | Memory device and method of operating same |
US20050162907A1 (en) * | 2004-01-28 | 2005-07-28 | Campbell Kristy A. | Resistance variable memory elements based on polarized silver-selenide network growth |
US20050162883A1 (en) * | 2002-08-08 | 2005-07-28 | Hasan Nejad | Columnar 1T-nMemory cell structure and its method of formation and operation |
US20050167689A1 (en) * | 2004-01-29 | 2005-08-04 | Campbell Kristy A. | Non-volatile zero field splitting resonance memory |
US20050202588A1 (en) * | 2004-03-10 | 2005-09-15 | Brooks Joseph F. | Method of forming a chalcogenide material containing device |
US20050201174A1 (en) * | 2004-03-10 | 2005-09-15 | Klein Dean A. | Power management control and controlling memory refresh operations |
US20050232061A1 (en) * | 2004-04-16 | 2005-10-20 | Rust Thomas F | Systems for writing and reading highly resolved domains for high density data storage |
US20050232004A1 (en) * | 2004-04-16 | 2005-10-20 | Rust Thomas F | Methods for erasing bit cells in a high density data storage device |
US6961277B2 (en) | 2003-07-08 | 2005-11-01 | Micron Technology, Inc. | Method of refreshing a PCRAM memory device |
US20060002172A1 (en) * | 2004-06-30 | 2006-01-05 | Balasubramanian Venkataraman | Providing current for phase change memories |
US20060007729A1 (en) * | 2004-07-09 | 2006-01-12 | Beak-Hyung Cho | Phase change memories and/or methods of programming phase change memories using sequential reset control |
US20060011910A1 (en) * | 2004-07-19 | 2006-01-19 | Micron Technology, Inc. | PCRAM device with switching glass layer |
US20060012008A1 (en) * | 2004-07-19 | 2006-01-19 | Campbell Kristy A | Resistance variable memory device and method of fabrication |
US20060033094A1 (en) * | 2004-08-12 | 2006-02-16 | Campbell Kristy A | Resistance variable memory with temperature tolerant materials |
US20060035403A1 (en) * | 2004-08-12 | 2006-02-16 | Campbell Kristy A | PCRAM device with switching glass layer |
US20060044906A1 (en) * | 2004-09-01 | 2006-03-02 | Ethan Williford | Sensing of resistance variable memory devices |
US20060104142A1 (en) * | 2002-08-29 | 2006-05-18 | Gilton Terry L | Software refreshed memory device and method |
US20060131556A1 (en) * | 2004-12-22 | 2006-06-22 | Micron Technology, Inc. | Small electrode for resistance variable devices |
US20060131555A1 (en) * | 2004-12-22 | 2006-06-22 | Micron Technology, Inc. | Resistance variable devices with controllable channels |
US20060237707A1 (en) * | 2005-04-22 | 2006-10-26 | Micron Technology, Inc. | Memory array for increased bit density and method of forming the same |
US20060256640A1 (en) * | 2005-05-16 | 2006-11-16 | Micron Technology, Inc. | Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory |
US20060270099A1 (en) * | 2001-08-29 | 2006-11-30 | Micron Technology, Inc. | Method of forming non-volatile resistance variable devices and method of forming a programmable memory cell of memory circuitry |
US20070008768A1 (en) * | 2005-07-08 | 2007-01-11 | Micron Technology, Inc. | Process for erasing chalcogenide variable resistance memory bits |
US20070010054A1 (en) * | 2005-07-08 | 2007-01-11 | Nanochip, Inc. | Method for forming patterned media for a high density data storage device |
US20070007506A1 (en) * | 2002-02-20 | 2007-01-11 | Micron Technology, Inc. | Layered resistance variable memory device and method of fabrication |
US20070006455A1 (en) * | 2005-06-24 | 2007-01-11 | Nanochip, Inc. | Methods for forming high density data storage devices with read/write probes with hollow or reinforced tips |
US20070023744A1 (en) * | 2005-08-01 | 2007-02-01 | Micron Technology, Inc. | Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication |
US20070030554A1 (en) * | 2005-08-02 | 2007-02-08 | Micron Technology, Inc. | Method and apparatus for providing color changing thin film material |
US20070029537A1 (en) * | 2005-08-02 | 2007-02-08 | Micron Technology, Inc. | Phase change memory cell and method of formation |
US20070037316A1 (en) * | 2005-08-09 | 2007-02-15 | Micron Technology, Inc. | Memory cell contact using spacers |
US20070034921A1 (en) * | 2005-08-09 | 2007-02-15 | Micron Technology, Inc. | Access transistor for memory device |
US20070035990A1 (en) * | 2005-08-15 | 2007-02-15 | Micron Technology, Inc. | Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance |
US20070047297A1 (en) * | 2005-08-31 | 2007-03-01 | Campbell Kristy A | Resistance variable memory element with threshold device and method of forming the same |
US20070059882A1 (en) * | 2005-04-22 | 2007-03-15 | Micron Technology, Inc. | Memory elements having patterned electrodes and method of forming the same |
US20070090354A1 (en) * | 2005-08-11 | 2007-04-26 | Micron Technology, Inc. | Chalcogenide-based electrokinetic memory element and method of forming the same |
US20080130351A1 (en) * | 2006-12-04 | 2008-06-05 | Thomas Nirschi | Multi-bit resistive memory |
US20080130352A1 (en) * | 2005-01-19 | 2008-06-05 | Sandisk Corporation | Structure and Method for Biasing Phase Change Memory Array for Reliable Writing |
US7440316B1 (en) * | 2007-04-30 | 2008-10-21 | Super Talent Electronics, Inc | 8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory |
US7460389B2 (en) * | 2005-07-29 | 2008-12-02 | International Business Machines Corporation | Write operations for phase-change-material memory |
US20080298120A1 (en) * | 2007-05-28 | 2008-12-04 | Super Talent Electronics Inc. | Peripheral Devices Using Phase-Change Memory |
US20090059658A1 (en) * | 2003-06-03 | 2009-03-05 | Samsung Electronics Co., Ltd. | Memory system, memory device and apparatus including writing driver circuit for a variable resistive memory |
US20090261316A1 (en) * | 2006-08-29 | 2009-10-22 | Jun Liu | Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication |
US20090279350A1 (en) * | 2008-05-07 | 2009-11-12 | Macronix International Co., Ltd. | Bipolar switching of phase change device |
US20090307410A1 (en) * | 2008-06-06 | 2009-12-10 | Ovonyx, Inc. | Memory controller |
US20090323409A1 (en) * | 2008-06-27 | 2009-12-31 | Macronix International Co., Ltd. | Methods for high speed reading operation of phase change memory and device employing same |
US20110037558A1 (en) * | 2008-08-01 | 2011-02-17 | Boise State University | Continuously variable resistor |
CN101452743B (en) * | 2007-12-05 | 2011-10-26 | 财团法人工业技术研究院 | Writing-in system and method for phase change memory |
US20120002464A1 (en) * | 2010-06-30 | 2012-01-05 | Elpida Memory, Inc. | Semiconductor device equipped with a plurality of memory banks and test method of the semiconductor device |
US8101936B2 (en) | 2005-02-23 | 2012-01-24 | Micron Technology, Inc. | SnSe-based limited reprogrammable cell |
US8624215B2 (en) | 2005-12-20 | 2014-01-07 | University Of Southampton | Phase change memory devices and methods comprising gallium, lanthanide and chalcogenide compounds |
US10629262B2 (en) | 2018-02-27 | 2020-04-21 | Samsung Electronics Co., Ltd. | Method of operating resistive memory device capable of reducing write latency |
US10916306B2 (en) | 2019-03-07 | 2021-02-09 | Western Digital Technologies, Inc. | Burst mode operation conditioning for a memory device |
US11133059B2 (en) | 2018-12-06 | 2021-09-28 | Western Digital Technologies, Inc. | Non-volatile memory die with deep learning neural network |
US11501109B2 (en) | 2019-06-20 | 2022-11-15 | Western Digital Technologies, Inc. | Non-volatile memory die with on-chip data augmentation components for use with machine learning |
US11507835B2 (en) | 2020-06-08 | 2022-11-22 | Western Digital Technologies, Inc. | Neural network data updates using in-place bit-addressable writes within storage class memory |
US11507843B2 (en) | 2020-03-30 | 2022-11-22 | Western Digital Technologies, Inc. | Separate storage and control of static and dynamic neural network data within a non-volatile memory array |
US11520521B2 (en) | 2019-06-20 | 2022-12-06 | Western Digital Technologies, Inc. | Storage controller having data augmentation components for use with non-volatile memory die |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6768665B2 (en) * | 2002-08-05 | 2004-07-27 | Intel Corporation | Refreshing memory cells of a phase change material memory device |
JP4325275B2 (en) * | 2003-05-28 | 2009-09-02 | 株式会社日立製作所 | Semiconductor device |
EP1489622B1 (en) * | 2003-06-16 | 2007-08-15 | STMicroelectronics S.r.l. | Writing circuit for a phase change memory device |
US7236394B2 (en) * | 2003-06-18 | 2007-06-26 | Macronix International Co., Ltd. | Transistor-free random access memory |
KR100564602B1 (en) * | 2003-12-30 | 2006-03-29 | 삼성전자주식회사 | Set programming method of phase-change memory array and writing driver circuit |
US8653495B2 (en) * | 2005-04-11 | 2014-02-18 | Micron Technology, Inc. | Heating phase change material |
KR101281685B1 (en) * | 2007-10-04 | 2013-07-03 | 삼성전자주식회사 | Method for writing and reading data of phase-change random access memory and apparatus thereof |
US20090091968A1 (en) * | 2007-10-08 | 2009-04-09 | Stefan Dietrich | Integrated circuit including a memory having a data inversion circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5625824A (en) * | 1995-03-03 | 1997-04-29 | Compaq Computer Corporation | Circuit for selectively preventing a microprocessor from posting write cycles |
US6247073B1 (en) * | 1994-01-21 | 2001-06-12 | Hitachi, Ltd. | Memory outputting both data and timing signal with output data and timing signal being aligned with each other |
US6373747B1 (en) * | 1989-04-13 | 2002-04-16 | Sandisk Corporation | Flash EEprom system |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1212155B (en) * | 1964-02-05 | 1966-03-10 | Danfoss As | Electric storage |
US5166758A (en) * | 1991-01-18 | 1992-11-24 | Energy Conversion Devices, Inc. | Electrically erasable phase change memory |
US5949088A (en) * | 1996-10-25 | 1999-09-07 | Micron Technology, Inc. | Intermediate SRAM array product and method of conditioning memory elements thereof |
-
2001
- 2001-10-30 US US10/021,469 patent/US6545907B1/en not_active Expired - Lifetime
-
2002
- 2002-08-21 WO PCT/US2002/026672 patent/WO2003038830A1/en not_active Application Discontinuation
- 2002-08-21 KR KR1020047006453A patent/KR100586351B1/en active IP Right Grant
- 2002-08-21 CN CN02826572.6A patent/CN1610952B/en not_active Expired - Lifetime
- 2002-08-30 TW TW091119854A patent/TWI222064B/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6373747B1 (en) * | 1989-04-13 | 2002-04-16 | Sandisk Corporation | Flash EEprom system |
US6247073B1 (en) * | 1994-01-21 | 2001-06-12 | Hitachi, Ltd. | Memory outputting both data and timing signal with output data and timing signal being aligned with each other |
US5625824A (en) * | 1995-03-03 | 1997-04-29 | Compaq Computer Corporation | Circuit for selectively preventing a microprocessor from posting write cycles |
Cited By (245)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6833559B2 (en) | 2001-02-08 | 2004-12-21 | Micron Technology, Inc. | Non-volatile resistance variable device |
US20050019699A1 (en) * | 2001-02-08 | 2005-01-27 | Moore John T. | Non-volatile resistance variable device |
US20020116955A1 (en) * | 2001-02-19 | 2002-08-29 | Sumitomo Electric Industries, Ltd. | Method of forming soot preform |
US20040161874A1 (en) * | 2001-03-01 | 2004-08-19 | Moore John T. | Method of forming a non-volatile resistance variable device, and non-volatile resistance variable device |
US6878569B2 (en) * | 2001-03-15 | 2005-04-12 | Micron Technology, Inc. | Agglomeration elimination for metal sputter deposition of chalcogenides |
US20030047772A1 (en) * | 2001-03-15 | 2003-03-13 | Jiutao Li | Agglomeration elimination for metal sputter deposition of chalcogenides |
US20040144968A1 (en) * | 2001-03-15 | 2004-07-29 | Jiutao Li | Agglomeration elimination for metal sputter deposition of chalcogenides |
US20040144973A1 (en) * | 2001-03-15 | 2004-07-29 | Jiutao Li | Agglomeration elimination for metal sputter deposition of chalcogenides |
US20020138301A1 (en) * | 2001-03-22 | 2002-09-26 | Thanos Karras | Integration of a portal into an application service provider data archive and/or web based viewer |
US7687793B2 (en) | 2001-05-11 | 2010-03-30 | Micron Technology, Inc. | Resistance variable memory cells |
US20070235712A1 (en) * | 2001-05-11 | 2007-10-11 | Harshfield Steven T | Resistance variable memory cells |
US20060099822A1 (en) * | 2001-05-11 | 2006-05-11 | Harshfield Steven T | Method of making a memory cell |
US20020168852A1 (en) * | 2001-05-11 | 2002-11-14 | Harshfield Steven T. | PCRAM memory cell and method of making same |
US20050157573A1 (en) * | 2001-08-29 | 2005-07-21 | Campbell Kristy A. | Method of forming non-volatile resistance variable devices |
US7863597B2 (en) | 2001-08-29 | 2011-01-04 | Micron Technology, Inc. | Resistance variable memory devices with passivating material |
US20060270099A1 (en) * | 2001-08-29 | 2006-11-30 | Micron Technology, Inc. | Method of forming non-volatile resistance variable devices and method of forming a programmable memory cell of memory circuitry |
US20040124406A1 (en) * | 2001-08-29 | 2004-07-01 | Campbell Kristy A. | Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device |
US20030045049A1 (en) * | 2001-08-29 | 2003-03-06 | Campbell Kristy A. | Method of forming chalcogenide comprising devices |
US7348205B2 (en) | 2001-08-29 | 2008-03-25 | Micron Technology, Inc. | Method of forming resistance variable devices |
US20080185574A1 (en) * | 2001-08-29 | 2008-08-07 | Campbell Kristy A | Method of forming non-volatile resistance variable devices |
US6888155B2 (en) | 2001-08-30 | 2005-05-03 | Micron Technology, Inc. | Stoichiometry for chalcogenide glasses useful for memory devices and method of formation |
US20050026433A1 (en) * | 2001-08-30 | 2005-02-03 | Jiutao Li | Integrated circuit device and fabrication using metal-doped chalcogenide materials |
US20040007718A1 (en) * | 2001-08-30 | 2004-01-15 | Campbell Kristy A. | Stoichiometry for chalcogenide glasses useful for memory devices and method of formation |
US6815818B2 (en) * | 2001-11-19 | 2004-11-09 | Micron Technology, Inc. | Electrode structure for use in an integrated circuit |
US20040229423A1 (en) * | 2001-11-19 | 2004-11-18 | Moore John T. | Electrode structure for use in an integrated circuit |
US20040238958A1 (en) * | 2001-11-19 | 2004-12-02 | Moore John T. | Electrode structure for use in an integrated circuit |
US20040232551A1 (en) * | 2001-11-19 | 2004-11-25 | Moore John T. | Electrode structure for use in an integrated circuit |
US20030096497A1 (en) * | 2001-11-19 | 2003-05-22 | Micron Technology, Inc. | Electrode structure for use in an integrated circuit |
US20060245234A1 (en) * | 2001-11-20 | 2006-11-02 | Glen Hush | Method of operating a complementary bit resistance memory sensor and method of operation |
US7869249B2 (en) | 2001-11-20 | 2011-01-11 | Micron Technology, Inc. | Complementary bit PCRAM sense amplifier and method of operation |
US20060023532A1 (en) * | 2001-11-20 | 2006-02-02 | Glen Hush | Method of operating a complementary bit resistance memory sensor |
US20050018509A1 (en) * | 2001-11-20 | 2005-01-27 | Glen Hush | Complementary bit resistance memory sensor and method of operation |
US20030117831A1 (en) * | 2001-12-20 | 2003-06-26 | Glen Hush | Programmable conductor random access memory and a method for writing thereto |
US20030128612A1 (en) * | 2002-01-04 | 2003-07-10 | John Moore | PCRAM rewrite prevention |
US20050146958A1 (en) * | 2002-01-04 | 2005-07-07 | John Moore | Rewrite prevention in a variable resistance memory |
US6812087B2 (en) | 2002-01-31 | 2004-11-02 | Micron Technology, Inc. | Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures |
US20040029351A1 (en) * | 2002-01-31 | 2004-02-12 | Gilton Terry L. | Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures |
US20040223390A1 (en) * | 2002-02-15 | 2004-11-11 | Campbell Kristy A. | Resistance variable memory element having chalcogenide glass for improved switching characteristics |
US20030155606A1 (en) * | 2002-02-15 | 2003-08-21 | Campbell Kristy A. | Method to alter chalcogenide glass for improved switching characteristics |
US20050018493A1 (en) * | 2002-02-19 | 2005-01-27 | Casper Stephen L. | Programmable conductor random access memory and method for sensing same |
US6791885B2 (en) | 2002-02-19 | 2004-09-14 | Micron Technology, Inc. | Programmable conductor random access memory and method for sensing same |
US20030156463A1 (en) * | 2002-02-19 | 2003-08-21 | Casper Stephen L. | Programmable conductor random access memory and method for sensing same |
US20040192006A1 (en) * | 2002-02-20 | 2004-09-30 | Campbell Kristy A. | Layered resistance variable memory device and method of fabrication |
US7723713B2 (en) | 2002-02-20 | 2010-05-25 | Micron Technology, Inc. | Layered resistance variable memory device and method of fabrication |
US20040223357A1 (en) * | 2002-02-20 | 2004-11-11 | Gilton Terry L. | Multiple data state memory cell |
US6809362B2 (en) | 2002-02-20 | 2004-10-26 | Micron Technology, Inc. | Multiple data state memory cell |
US20100219391A1 (en) * | 2002-02-20 | 2010-09-02 | Campbell Kristy A | Layered resistance variable memory device and method of fabrication |
US20030156468A1 (en) * | 2002-02-20 | 2003-08-21 | Campbell Kristy A. | Resistance variable 'on' memory |
US20050157567A1 (en) * | 2002-02-20 | 2005-07-21 | Gilton Terry L. | Multiple data state memory cell |
US20070007506A1 (en) * | 2002-02-20 | 2007-01-11 | Micron Technology, Inc. | Layered resistance variable memory device and method of fabrication |
US8263958B2 (en) | 2002-02-20 | 2012-09-11 | Micron Technology, Inc. | Layered resistance variable memory device and method of fabrication |
US20070128792A1 (en) * | 2002-02-20 | 2007-06-07 | Micron Technology, Inc. | Multiple data state memory cell |
US20030169625A1 (en) * | 2002-03-05 | 2003-09-11 | Glen Hush | Programmable conductor random access memory and method for sensing same |
US20030173558A1 (en) * | 2002-03-14 | 2003-09-18 | Campbell Kristy A. | Methods and apparatus for resistance variable material cells |
US20040171208A1 (en) * | 2002-04-10 | 2004-09-02 | Gilton Terry L. | Method of manufacture of programmable conductor memory |
US20030193059A1 (en) * | 2002-04-10 | 2003-10-16 | Gilton Terry L. | Programmable conductor memory cell structure and method therefor |
US20030193053A1 (en) * | 2002-04-10 | 2003-10-16 | Gilton Terry L. | Thin film diode integrated with chalcogenide memory cell |
US20050101084A1 (en) * | 2002-04-10 | 2005-05-12 | Gilton Terry L. | Thin film diode integrated with chalcogenide memory cell |
US20030194865A1 (en) * | 2002-04-10 | 2003-10-16 | Gilton Terry L. | Method of manufacture of programmable conductor memory |
US20060243973A1 (en) * | 2002-04-10 | 2006-11-02 | Micron Technology, Inc. | Thin film diode integrated with chalcogenide memory cell |
US20040043553A1 (en) * | 2002-06-06 | 2004-03-04 | Jiutao Li | Elimination of dendrite formation during metal/chalcogenide glass deposition |
US20090098717A1 (en) * | 2002-06-06 | 2009-04-16 | Jiutao Li | Co-sputter deposition of metal-doped chalcogenides |
US7964436B2 (en) | 2002-06-06 | 2011-06-21 | Round Rock Research, Llc | Co-sputter deposition of metal-doped chalcogenides |
US20040235235A1 (en) * | 2002-06-06 | 2004-11-25 | Jiutao Li | Co-sputter deposition of metal-doped chalcogenides |
US20040130598A1 (en) * | 2002-07-10 | 2004-07-08 | Canon Kabushiki Kaisha | Ink jet record head |
US20040007749A1 (en) * | 2002-07-10 | 2004-01-15 | Campbell Kristy A. | Assemblies displaying differential negative resistance |
US7879646B2 (en) | 2002-07-10 | 2011-02-01 | Micron Technology, Inc. | Assemblies displaying differential negative resistance, semiconductor constructions, and methods of forming assemblies displaying differential negative resistance |
US20080188034A1 (en) * | 2002-07-10 | 2008-08-07 | Campbell Kristy A | Assemblies displaying differential negative resistance, semiconductor constructions, and methods of forming assemblies displaying differential negative resistance |
US20050247927A1 (en) * | 2002-07-10 | 2005-11-10 | Campbell Kristy A | Assemblies displaying differential negative resistance |
US20050162883A1 (en) * | 2002-08-08 | 2005-07-28 | Hasan Nejad | Columnar 1T-nMemory cell structure and its method of formation and operation |
US20060171224A1 (en) * | 2002-08-08 | 2006-08-03 | Hasan Nejad | 1T-nmemory cell structure and its method of formation and operation |
US20040038480A1 (en) * | 2002-08-22 | 2004-02-26 | Moore John T. | Method of manufacture of a PCRAM memory cell |
US20060234425A1 (en) * | 2002-08-22 | 2006-10-19 | Micron Technology, Inc. | Method of manufacture of a PCRAM memory cell |
US20040238918A1 (en) * | 2002-08-22 | 2004-12-02 | Moore John T. | Method of manufacture of a PCRAM memory cell |
US20040185625A1 (en) * | 2002-08-29 | 2004-09-23 | Moore John T. | Graded GexSe100-x concentration in PCRAM |
US20040175859A1 (en) * | 2002-08-29 | 2004-09-09 | Campbell Kristy A. | Single polarity programming of a PCRAM structure |
US20050148150A1 (en) * | 2002-08-29 | 2005-07-07 | Moore John T. | Memory element and its method of formation |
US20040040835A1 (en) * | 2002-08-29 | 2004-03-04 | Jiutao Li | Silver selenide film stoichiometry and morphology control in sputter deposition |
US7518212B2 (en) | 2002-08-29 | 2009-04-14 | Micron Technology, Inc. | Graded GexSe100-x concentration in PCRAM |
US7944768B2 (en) | 2002-08-29 | 2011-05-17 | Micron Technology, Inc. | Software refreshed memory device and method |
US20040040837A1 (en) * | 2002-08-29 | 2004-03-04 | Mcteer Allen | Method of forming chalcogenide sputter target |
US20070258308A1 (en) * | 2002-08-29 | 2007-11-08 | Gilton Terry L | Software refreshed memory device and method |
US6953720B2 (en) | 2002-08-29 | 2005-10-11 | Micron Technology, Inc. | Methods for forming chalcogenide glass-based memory elements |
US20040043245A1 (en) * | 2002-08-29 | 2004-03-04 | Moore John T. | Method to control silver concentration in a resistance variable memory element |
US20040053461A1 (en) * | 2002-08-29 | 2004-03-18 | Moore John T. | Graded GexSe100-x concentration in PCRAM |
US20090257299A1 (en) * | 2002-08-29 | 2009-10-15 | Gilton Terry L | Software refreshed memory device and method |
US6864521B2 (en) | 2002-08-29 | 2005-03-08 | Micron Technology, Inc. | Method to control silver concentration in a resistance variable memory element |
US20050266635A1 (en) * | 2002-08-29 | 2005-12-01 | Moore John T | Graded GexSe100-x concentration in PCRAM |
US7223627B2 (en) | 2002-08-29 | 2007-05-29 | Micron Technology, Inc. | Memory element and its method of formation |
US20040157417A1 (en) * | 2002-08-29 | 2004-08-12 | Moore John T. | Methods to form a memory cell with metal-rich metal chalcogenide |
US7692177B2 (en) | 2002-08-29 | 2010-04-06 | Micron Technology, Inc. | Resistance variable memory element and its method of formation |
US20050054207A1 (en) * | 2002-08-29 | 2005-03-10 | Micron Technology, Inc. | Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes |
US6856002B2 (en) | 2002-08-29 | 2005-02-15 | Micron Technology, Inc. | Graded GexSe100-x concentration in PCRAM |
US20060252176A1 (en) * | 2002-08-29 | 2006-11-09 | Micron Technology, Inc. | Memory element and its method of formation |
US9552986B2 (en) | 2002-08-29 | 2017-01-24 | Micron Technology, Inc. | Forming a memory device using sputtering to deposit silver-selenide film |
US20040211957A1 (en) * | 2002-08-29 | 2004-10-28 | Moore John T. | Method and apparatus for controlling metal doping of a chalcogenide memory element |
US7768861B2 (en) | 2002-08-29 | 2010-08-03 | Micron Technology, Inc. | Software refreshed memory device and method |
US20050098428A1 (en) * | 2002-08-29 | 2005-05-12 | Jiutao Li | Silver selenide film stoichiometry and morphology control in sputter deposition |
US20060104142A1 (en) * | 2002-08-29 | 2006-05-18 | Gilton Terry L | Software refreshed memory device and method |
US20040145941A1 (en) * | 2002-10-15 | 2004-07-29 | Rust Thomas F | Phase change media for high density data storage |
US6813178B2 (en) | 2003-03-12 | 2004-11-02 | Micron Technology, Inc. | Chalcogenide glass constant current device, and its method of fabrication and operation |
US20040180533A1 (en) * | 2003-03-14 | 2004-09-16 | Li Li | Method for filling via with metal |
US7042760B2 (en) | 2003-03-27 | 2006-05-09 | Samsung Electronics Co., Ltd. | Phase-change memory and method having restore function |
US20050117387A1 (en) * | 2003-03-27 | 2005-06-02 | Young-Nam Hwang | Phase-change memory and method having restore function |
US20040202016A1 (en) * | 2003-04-10 | 2004-10-14 | Campbell Kristy A. | Differential negative resistance memory |
US7745808B2 (en) | 2003-04-10 | 2010-06-29 | Micron Technology, Inc. | Differential negative resistance memory |
US20080128674A1 (en) * | 2003-04-10 | 2008-06-05 | Campbell Kristy A | Differential negative resistance memory |
US7688621B2 (en) * | 2003-06-03 | 2010-03-30 | Samsung Electronics Co., Ltd. | Memory system, memory device and apparatus including writing driver circuit for a variable resistive memory |
US7180771B2 (en) | 2003-06-03 | 2007-02-20 | Samsung Electronics Co., Ltd. | Device and method for pulse width control in a phase change memory device |
US20090059658A1 (en) * | 2003-06-03 | 2009-03-05 | Samsung Electronics Co., Ltd. | Memory system, memory device and apparatus including writing driver circuit for a variable resistive memory |
US20060181932A1 (en) * | 2003-06-03 | 2006-08-17 | Samsung Electronics, Co., Ltd. | Device and method for pulse width control in a phase change memory device |
US7085154B2 (en) * | 2003-06-03 | 2006-08-01 | Samsung Electronics Co., Ltd. | Device and method for pulse width control in a phase change memory device |
US20040246804A1 (en) * | 2003-06-03 | 2004-12-09 | Samsung Electronics Co., Ltd. | Device and method for pulse width control in a phase change memory device |
US20040264234A1 (en) * | 2003-06-25 | 2004-12-30 | Moore John T. | PCRAM cell operation method to control on/off resistance variation |
US6961277B2 (en) | 2003-07-08 | 2005-11-01 | Micron Technology, Inc. | Method of refreshing a PCRAM memory device |
US20050017233A1 (en) * | 2003-07-21 | 2005-01-27 | Campbell Kristy A. | Performance PCRAM cell |
US20050056910A1 (en) * | 2003-09-17 | 2005-03-17 | Gilton Terry L. | Non-volatile memory structure |
US20050059187A1 (en) * | 2003-09-17 | 2005-03-17 | Gilton Terry L. | Non-volatile memory structure |
US6928022B2 (en) * | 2003-11-27 | 2005-08-09 | Samsung Electronics Co., Ltd. | Write driver circuit in phase change memory device and method for applying write current |
US20050117388A1 (en) * | 2003-11-27 | 2005-06-02 | Samsung Electronics Co., Ltd | Write driver circuit in phase change memory device and method for applying write current |
US6937507B2 (en) | 2003-12-05 | 2005-08-30 | Silicon Storage Technology, Inc. | Memory device and method of operating same |
US20050122771A1 (en) * | 2003-12-05 | 2005-06-09 | Bomy Chen | Memory device and method of operating same |
US7153721B2 (en) | 2004-01-28 | 2006-12-26 | Micron Technology, Inc. | Resistance variable memory elements based on polarized silver-selenide network growth |
US20050286294A1 (en) * | 2004-01-28 | 2005-12-29 | Campbell Kristy A | Resistance variable memory elements based on polarized silver-selenide network growth |
US20050162907A1 (en) * | 2004-01-28 | 2005-07-28 | Campbell Kristy A. | Resistance variable memory elements based on polarized silver-selenide network growth |
US7105864B2 (en) | 2004-01-29 | 2006-09-12 | Micron Technology, Inc. | Non-volatile zero field splitting resonance memory |
US20050167689A1 (en) * | 2004-01-29 | 2005-08-04 | Campbell Kristy A. | Non-volatile zero field splitting resonance memory |
US8619485B2 (en) | 2004-03-10 | 2013-12-31 | Round Rock Research, Llc | Power management control and controlling memory refresh operations |
US20090147608A1 (en) * | 2004-03-10 | 2009-06-11 | Klein Dean A | Power management control and controlling memory refresh operations |
US20060246696A1 (en) * | 2004-03-10 | 2006-11-02 | Micron Technology, Inc. | Method of forming a chalcogenide material containing device |
US20050202588A1 (en) * | 2004-03-10 | 2005-09-15 | Brooks Joseph F. | Method of forming a chalcogenide material containing device |
US20050201174A1 (en) * | 2004-03-10 | 2005-09-15 | Klein Dean A. | Power management control and controlling memory refresh operations |
US9142263B2 (en) | 2004-03-10 | 2015-09-22 | Round Rock Research, Llc | Power management control and controlling memory refresh operations |
US20050232061A1 (en) * | 2004-04-16 | 2005-10-20 | Rust Thomas F | Systems for writing and reading highly resolved domains for high density data storage |
US20050232004A1 (en) * | 2004-04-16 | 2005-10-20 | Rust Thomas F | Methods for erasing bit cells in a high density data storage device |
US7359231B2 (en) * | 2004-06-30 | 2008-04-15 | Intel Corporation | Providing current for phase change memories |
US20060002172A1 (en) * | 2004-06-30 | 2006-01-05 | Balasubramanian Venkataraman | Providing current for phase change memories |
US7304885B2 (en) | 2004-07-09 | 2007-12-04 | Samsung Electronics Co., Ltd. | Phase change memories and/or methods of programming phase change memories using sequential reset control |
US20060007729A1 (en) * | 2004-07-09 | 2006-01-12 | Beak-Hyung Cho | Phase change memories and/or methods of programming phase change memories using sequential reset control |
US20080137402A1 (en) * | 2004-07-09 | 2008-06-12 | Samsung Electronics Co., Ltd. | Apparatus and systems using phase change memories |
US20100097850A1 (en) * | 2004-07-09 | 2010-04-22 | Samsung Electronics Co., Ltd. | Apparatus and systems using phase change memories |
US8194442B2 (en) | 2004-07-09 | 2012-06-05 | Samsung Electronics Co., Ltd. | Apparatus and systems using phase change memories |
US7643335B2 (en) | 2004-07-09 | 2010-01-05 | Samsung Electronics Co., Ltd. | Apparatus and systems using phase change memories |
US7944741B2 (en) | 2004-07-09 | 2011-05-17 | Samsung Electronics Co., Ltd. | Apparatus and systems using phase change memories |
US7749853B2 (en) | 2004-07-19 | 2010-07-06 | Microntechnology, Inc. | Method of forming a variable resistance memory device comprising tin selenide |
US20060012008A1 (en) * | 2004-07-19 | 2006-01-19 | Campbell Kristy A | Resistance variable memory device and method of fabrication |
US20060011910A1 (en) * | 2004-07-19 | 2006-01-19 | Micron Technology, Inc. | PCRAM device with switching glass layer |
US20070152204A1 (en) * | 2004-07-19 | 2007-07-05 | Campbell Kristy A | PCRAM device with switching glass layer |
US20070138598A1 (en) * | 2004-07-19 | 2007-06-21 | Campbell Kristy A | Resistance variable memory device and method of fabrication |
US7759665B2 (en) | 2004-07-19 | 2010-07-20 | Micron Technology, Inc. | PCRAM device with switching glass layer |
US20060289851A1 (en) * | 2004-07-19 | 2006-12-28 | Campbell Kristy A | Resistance variable memory device and method of fabrication |
US20100133499A1 (en) * | 2004-08-12 | 2010-06-03 | Campbell Kristy A | Resistance variable memory with temperature tolerant materials |
US7994491B2 (en) | 2004-08-12 | 2011-08-09 | Micron Technology, Inc. | PCRAM device with switching glass layer |
US20060033094A1 (en) * | 2004-08-12 | 2006-02-16 | Campbell Kristy A | Resistance variable memory with temperature tolerant materials |
US20060035403A1 (en) * | 2004-08-12 | 2006-02-16 | Campbell Kristy A | PCRAM device with switching glass layer |
US8895401B2 (en) | 2004-08-12 | 2014-11-25 | Micron Technology, Inc. | Method of forming a memory device incorporating a resistance variable chalcogenide element |
US7785976B2 (en) | 2004-08-12 | 2010-08-31 | Micron Technology, Inc. | Method of forming a memory device incorporating a resistance-variable chalcogenide element |
US8487288B2 (en) | 2004-08-12 | 2013-07-16 | Micron Technology, Inc. | Memory device incorporating a resistance variable chalcogenide element |
US7924603B2 (en) | 2004-08-12 | 2011-04-12 | Micron Technology, Inc. | Resistance variable memory with temperature tolerant materials |
US7682992B2 (en) | 2004-08-12 | 2010-03-23 | Micron Technology, Inc. | Resistance variable memory with temperature tolerant materials |
US8334186B2 (en) | 2004-08-12 | 2012-12-18 | Micron Technology, Inc. | Method of forming a memory device incorporating a resistance variable chalcogenide element |
US20060231824A1 (en) * | 2004-08-12 | 2006-10-19 | Campbell Kristy A | Resistance variable memory with temperature tolerant materials |
US20070145463A1 (en) * | 2004-08-12 | 2007-06-28 | Campbell Kristy A | PCRAM device with switching glass layer |
US20060285381A1 (en) * | 2004-09-01 | 2006-12-21 | Ethan Williford | Sensing of resistance variable memory devices |
US20060044906A1 (en) * | 2004-09-01 | 2006-03-02 | Ethan Williford | Sensing of resistance variable memory devices |
US20060131556A1 (en) * | 2004-12-22 | 2006-06-22 | Micron Technology, Inc. | Small electrode for resistance variable devices |
US20070166983A1 (en) * | 2004-12-22 | 2007-07-19 | Micron Technology, Inc. | Small electrode for resistance variable devices |
US7910397B2 (en) | 2004-12-22 | 2011-03-22 | Micron Technology, Inc. | Small electrode for resistance variable devices |
US20060131555A1 (en) * | 2004-12-22 | 2006-06-22 | Micron Technology, Inc. | Resistance variable devices with controllable channels |
JP4746634B2 (en) * | 2005-01-19 | 2011-08-10 | マトリックス セミコンダクター インコーポレイテッド | Structure and method for biasing a phase change memory array for reliable writing |
US7859884B2 (en) | 2005-01-19 | 2010-12-28 | Sandisk 3D Llc | Structure and method for biasing phase change memory array for reliable writing |
JP2008527613A (en) * | 2005-01-19 | 2008-07-24 | マトリックス セミコンダクター インコーポレイテッド | Structure and method for biasing a phase change memory array for reliable writing |
US8102698B2 (en) | 2005-01-19 | 2012-01-24 | Sandisk 3D Llc | Structure and method for biasing phase change memory array for reliable writing |
US20110110149A1 (en) * | 2005-01-19 | 2011-05-12 | Scheuerlein Roy E | Structure and method for biasing phase change memory array for reliable writing |
US20080130352A1 (en) * | 2005-01-19 | 2008-06-05 | Sandisk Corporation | Structure and Method for Biasing Phase Change Memory Array for Reliable Writing |
US8385141B2 (en) | 2005-01-19 | 2013-02-26 | Sandisk 3D Llc | Structure and method for biasing phase change memory array for reliable writing |
US8101936B2 (en) | 2005-02-23 | 2012-01-24 | Micron Technology, Inc. | SnSe-based limited reprogrammable cell |
US20100171091A1 (en) * | 2005-04-22 | 2010-07-08 | Jon Daley | Memory array for increased bit density and method of forming the same |
US7700422B2 (en) | 2005-04-22 | 2010-04-20 | Micron Technology, Inc. | Methods of forming memory arrays for increased bit density |
US20070059882A1 (en) * | 2005-04-22 | 2007-03-15 | Micron Technology, Inc. | Memory elements having patterned electrodes and method of forming the same |
US20060237707A1 (en) * | 2005-04-22 | 2006-10-26 | Micron Technology, Inc. | Memory array for increased bit density and method of forming the same |
US7709289B2 (en) | 2005-04-22 | 2010-05-04 | Micron Technology, Inc. | Memory elements having patterned electrodes and method of forming the same |
US7968927B2 (en) | 2005-04-22 | 2011-06-28 | Micron Technology, Inc. | Memory array for increased bit density and method of forming the same |
US7663133B2 (en) | 2005-04-22 | 2010-02-16 | Micron Technology, Inc. | Memory elements having patterned electrodes and method of forming the same |
US20070104010A1 (en) * | 2005-05-16 | 2007-05-10 | Micron Technology, Inc. | Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory |
US20060256640A1 (en) * | 2005-05-16 | 2006-11-16 | Micron Technology, Inc. | Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory |
US20070006455A1 (en) * | 2005-06-24 | 2007-01-11 | Nanochip, Inc. | Methods for forming high density data storage devices with read/write probes with hollow or reinforced tips |
US20070008768A1 (en) * | 2005-07-08 | 2007-01-11 | Micron Technology, Inc. | Process for erasing chalcogenide variable resistance memory bits |
US20070010054A1 (en) * | 2005-07-08 | 2007-01-11 | Nanochip, Inc. | Method for forming patterned media for a high density data storage device |
US20080310208A1 (en) * | 2005-07-08 | 2008-12-18 | Jon Daley | Process for erasing chalcogenide variable resistance memory bits |
US7460389B2 (en) * | 2005-07-29 | 2008-12-02 | International Business Machines Corporation | Write operations for phase-change-material memory |
US20100171088A1 (en) * | 2005-08-01 | 2010-07-08 | Campbell Kristy A | Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication |
US20090078925A1 (en) * | 2005-08-01 | 2009-03-26 | Campbell Kristy A | Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication |
US20070023744A1 (en) * | 2005-08-01 | 2007-02-01 | Micron Technology, Inc. | Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication |
US7940556B2 (en) | 2005-08-01 | 2011-05-10 | Micron Technology, Inc. | Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication |
US7701760B2 (en) | 2005-08-01 | 2010-04-20 | Micron Technology, Inc. | Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication |
US7663137B2 (en) | 2005-08-02 | 2010-02-16 | Micron Technology, Inc. | Phase change memory cell and method of formation |
US20080142773A1 (en) * | 2005-08-02 | 2008-06-19 | Micron Technology, Inc. | Phase change memory cell and method of formation |
US20070029537A1 (en) * | 2005-08-02 | 2007-02-08 | Micron Technology, Inc. | Phase change memory cell and method of formation |
US20070030554A1 (en) * | 2005-08-02 | 2007-02-08 | Micron Technology, Inc. | Method and apparatus for providing color changing thin film material |
US20070034921A1 (en) * | 2005-08-09 | 2007-02-15 | Micron Technology, Inc. | Access transistor for memory device |
US7709885B2 (en) | 2005-08-09 | 2010-05-04 | Micron Technology, Inc. | Access transistor for memory device |
US8652903B2 (en) | 2005-08-09 | 2014-02-18 | Micron Technology, Inc. | Access transistor for memory device |
US20100178741A1 (en) * | 2005-08-09 | 2010-07-15 | Jon Daley | Access transistor for memory device |
US20070037316A1 (en) * | 2005-08-09 | 2007-02-15 | Micron Technology, Inc. | Memory cell contact using spacers |
US20070090354A1 (en) * | 2005-08-11 | 2007-04-26 | Micron Technology, Inc. | Chalcogenide-based electrokinetic memory element and method of forming the same |
US8611136B2 (en) | 2005-08-15 | 2013-12-17 | Micron Technology, Inc. | Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance |
US7978500B2 (en) | 2005-08-15 | 2011-07-12 | Micron Technology, Inc. | Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance |
US20070247895A1 (en) * | 2005-08-15 | 2007-10-25 | Glen Hush | Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance |
US8189366B2 (en) | 2005-08-15 | 2012-05-29 | Micron Technology, Inc. | Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance |
US20070035990A1 (en) * | 2005-08-15 | 2007-02-15 | Micron Technology, Inc. | Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance |
US7668000B2 (en) | 2005-08-15 | 2010-02-23 | Micron Technology, Inc. | Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance |
US20070064474A1 (en) * | 2005-08-31 | 2007-03-22 | Micron Technology, Inc. | Resistance variable memory element with threshold device and method of forming the same |
US20070047297A1 (en) * | 2005-08-31 | 2007-03-01 | Campbell Kristy A | Resistance variable memory element with threshold device and method of forming the same |
US8624215B2 (en) | 2005-12-20 | 2014-01-07 | University Of Southampton | Phase change memory devices and methods comprising gallium, lanthanide and chalcogenide compounds |
US9029823B2 (en) | 2005-12-20 | 2015-05-12 | University Of South Hampton | Phase change memory devices and methods comprising gallium, lanthanide and chalcogenide compounds |
US20090261316A1 (en) * | 2006-08-29 | 2009-10-22 | Jun Liu | Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication |
US8030636B2 (en) | 2006-08-29 | 2011-10-04 | Micron Technology, Inc. | Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication |
US7791058B2 (en) | 2006-08-29 | 2010-09-07 | Micron Technology, Inc. | Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication |
US20080130351A1 (en) * | 2006-12-04 | 2008-06-05 | Thomas Nirschi | Multi-bit resistive memory |
US7692949B2 (en) * | 2006-12-04 | 2010-04-06 | Qimonda North America Corp. | Multi-bit resistive memory |
US7440316B1 (en) * | 2007-04-30 | 2008-10-21 | Super Talent Electronics, Inc | 8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory |
US20080266941A1 (en) * | 2007-04-30 | 2008-10-30 | Super Talent Electronics Inc. | 8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory |
US20080298120A1 (en) * | 2007-05-28 | 2008-12-04 | Super Talent Electronics Inc. | Peripheral Devices Using Phase-Change Memory |
US7966429B2 (en) * | 2007-05-28 | 2011-06-21 | Super Talent Electronics, Inc. | Peripheral devices using phase-change memory |
CN101452743B (en) * | 2007-12-05 | 2011-10-26 | 财团法人工业技术研究院 | Writing-in system and method for phase change memory |
US20090279350A1 (en) * | 2008-05-07 | 2009-11-12 | Macronix International Co., Ltd. | Bipolar switching of phase change device |
US8077505B2 (en) | 2008-05-07 | 2011-12-13 | Macronix International Co., Ltd. | Bipolar switching of phase change device |
US20090307410A1 (en) * | 2008-06-06 | 2009-12-10 | Ovonyx, Inc. | Memory controller |
US8363458B2 (en) * | 2008-06-06 | 2013-01-29 | Ovonyx, Inc. | Memory controller |
US20090323409A1 (en) * | 2008-06-27 | 2009-12-31 | Macronix International Co., Ltd. | Methods for high speed reading operation of phase change memory and device employing same |
US8134857B2 (en) | 2008-06-27 | 2012-03-13 | Macronix International Co., Ltd. | Methods for high speed reading operation of phase change memory and device employing same |
TWI407438B (en) * | 2008-06-27 | 2013-09-01 | Macronix Int Co Ltd | Phase change based memory device and operation method thereof |
US20110037558A1 (en) * | 2008-08-01 | 2011-02-17 | Boise State University | Continuously variable resistor |
US8467236B2 (en) | 2008-08-01 | 2013-06-18 | Boise State University | Continuously variable resistor |
US20120002464A1 (en) * | 2010-06-30 | 2012-01-05 | Elpida Memory, Inc. | Semiconductor device equipped with a plurality of memory banks and test method of the semiconductor device |
US8477548B2 (en) * | 2010-06-30 | 2013-07-02 | Elpida Memory, Inc. | Semiconductor device equipped with a plurality of memory banks and test method of the semiconductor device |
US10629262B2 (en) | 2018-02-27 | 2020-04-21 | Samsung Electronics Co., Ltd. | Method of operating resistive memory device capable of reducing write latency |
US11133059B2 (en) | 2018-12-06 | 2021-09-28 | Western Digital Technologies, Inc. | Non-volatile memory die with deep learning neural network |
US11705191B2 (en) | 2018-12-06 | 2023-07-18 | Western Digital Technologies, Inc. | Non-volatile memory die with deep learning neural network |
US10916306B2 (en) | 2019-03-07 | 2021-02-09 | Western Digital Technologies, Inc. | Burst mode operation conditioning for a memory device |
US11501109B2 (en) | 2019-06-20 | 2022-11-15 | Western Digital Technologies, Inc. | Non-volatile memory die with on-chip data augmentation components for use with machine learning |
US11520521B2 (en) | 2019-06-20 | 2022-12-06 | Western Digital Technologies, Inc. | Storage controller having data augmentation components for use with non-volatile memory die |
US11507843B2 (en) | 2020-03-30 | 2022-11-22 | Western Digital Technologies, Inc. | Separate storage and control of static and dynamic neural network data within a non-volatile memory array |
US11507835B2 (en) | 2020-06-08 | 2022-11-22 | Western Digital Technologies, Inc. | Neural network data updates using in-place bit-addressable writes within storage class memory |
Also Published As
Publication number | Publication date |
---|---|
KR20040053230A (en) | 2004-06-23 |
US20030081451A1 (en) | 2003-05-01 |
KR100586351B1 (en) | 2006-06-08 |
CN1610952B (en) | 2015-05-13 |
TWI222064B (en) | 2004-10-11 |
WO2003038830A1 (en) | 2003-05-08 |
CN1610952A (en) | 2005-04-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6545907B1 (en) | Technique and apparatus for performing write operations to a phase change material memory device | |
US7684225B2 (en) | Sequential and video access for non-volatile memory arrays | |
US6768665B2 (en) | Refreshing memory cells of a phase change material memory device | |
US7983104B2 (en) | Page mode access for non-volatile memory arrays | |
US7518904B2 (en) | Method of resetting phase change memory bits through a series of pulses of increasing amplitude | |
US7359231B2 (en) | Providing current for phase change memories | |
JP4112729B2 (en) | Semiconductor device | |
US7038961B2 (en) | Semiconductor device | |
US5632019A (en) | Output buffer with digitally controlled power handling characteristics | |
US6985389B2 (en) | Phase change based memory device and method for operating same | |
US8639903B2 (en) | Staggered programming for resistive memories | |
KR20200026659A (en) | Variable delay word line enable | |
TW202101450A (en) | Nonvolatile memory apparatus for mitigating read disturbance and system using the same | |
US20180061492A1 (en) | Write bandwidth enhancement scheme in phase change memory | |
CN115223613A (en) | Phase change memory device, operation method and memory chip |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTEL CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LOWREY, TYLER A.;PARKINSON, WARD D.;GILL, MANZUR;REEL/FRAME:012396/0927;SIGNING DATES FROM 20011027 TO 20011030 Owner name: OVONYX, INC., MICHIGAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LOWREY, TYLER A.;PARKINSON, WARD D.;GILL, MANZUR;REEL/FRAME:012396/0927;SIGNING DATES FROM 20011027 TO 20011030 |
|
AS | Assignment |
Owner name: OVONYX, INC., IDAHO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:013653/0008 Effective date: 20021204 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: CARLOW INNOVATIONS LLC, VIRGINIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OVONYX, INC.;REEL/FRAME:037244/0954 Effective date: 20150731 |
|
AS | Assignment |
Owner name: OVONYX MEMORY TECHNOLOGY, LLC, VIRGINIA Free format text: CHANGE OF NAME;ASSIGNOR:CARLOW INNOVATIONS, LLC;REEL/FRAME:039379/0077 Effective date: 20160708 |