JP2007311772A - Bidirectional schottky diode having metal/semiconductor/metal laminate structure, and its method of forming - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a bidirectional schottky diode having a metal/semiconductor/metal laminate structure. <P>SOLUTION: The method includes the steps of: depositing a silicon semiconductor layer 110 between a bottom electrode 104 and a top electrode 114; forming a bidirectional schottky diode having a threshold voltage, a breakdown voltage, and an on/off current ratio; and regulating the threshold voltage, breakdown voltage, and on/off current ratio of the bidirectional schottky diode in response to controlling the thickness 112 of the silicon semiconductor layer. Both the threshold voltage and the breakdown voltage are increased in response to increasing the thickness of the silicon semiconductor layer. With respect to the on/off current ratio, there is an optimal thickness of the silicon semiconductor layer. An amorphous silicon or polysilicon semiconductor layer is formed using a chemical vapor deposition method or a DC sputtering method. The silicon semiconductor layer can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to an integrated circuit (IC) manufacturing process, and more particularly, a semiconductor device that functions as a bidirectional Schottky diode and is formed of a silicon semiconductor having a metal / semiconductor / metal (MSM) stacked structure. About.

  The cross-point memory array is composed of memory elements arranged in a matrix, and electrical contacts are arranged along the x-axis (ie, word line) and the y-axis (ie, bit line). In some embodiments, the digital value is stored as a memory resistance (high resistance or low resistance). The storage state of the memory cell is read by applying a voltage to the word line connected to the selected memory element. The resistance or storage state is read as the output voltage of the bit line connected to the selected memory cell.

  The cross-point resistance memory array has a problem that it tends to cause a failure during reading. As part of the read operation, current flows from the selected word line to the bit line via the selected memory cell, but also flows to the unselected word line that intersects the selected bit line. When current flows through the unselected word line, the output impedance decreases, and the output voltage also decreases accordingly. In order to clearly distinguish the memory state, the output voltage needs to be clearly distinguished according to the memory state.

  The problem of unnecessary current flowing through the resistance memory cell can be dealt with by using a diode connected in series. This is because current is difficult to flow in the diode in reverse bias. However, this feature makes it difficult to write to a 1-diode / 1-resistance (1D1R) memory cell configured by connecting a diode in series to a resistive memory element. This is because a write voltage that is reverse biased to the diode cannot be used. Therefore, the 1D1R memory cell is suitable for monopolar type writing (writing in which the writing voltage has the same polarity when the memory resistance is increased and when the resistance is decreased). Furthermore, the diode is preferably formed from single crystal silicon for optimal operation. However, it is difficult to form large crystal grains using a thin film deposition process.

  Many crosspoint resistive memory array structures have been proposed to minimize crosstalk during read in large capacity crosspoint resistive memory arrays. The 1D1R memory cell is very suitable for writing to a monopolar memory array. However, high performance diodes can only be fabricated on single crystal silicon. In a multilayer three-dimensional array, the upper layer diode is formed by recrystallization of the deposited silicon, but the resulting diode usually does not exhibit good electrical characteristics. In addition, it is necessary to form the diode from a considerably thick silicon film.

  Patent Document 1 below proposes a memory cell in which a resistive memory element and a metal / insulator / metal (MIM: Metal Insulator Metal) structure MIM element are connected in series. This MIM element exhibits non-conductivity under a low bias. When the bias voltage is higher than a certain value, its conductivity is greatly increased. This voltage is called “current rise voltage” or “varistor voltage”. In the MIM structure, impact ionization occurs when a high electric field is generated in a high current region. As is widely known, MIM elements become unstable under high current density stress. This is because when a high electric field is applied to the insulator, a deep trap state occurs in the insulator and local avalanche breakdown occurs. As a result, the current-voltage characteristic is reversible only when the current is relatively low. Therefore, the MIM non-ohmic element is not suitable for a cross-point memory cell that requires a large number of write operations. The specific material or manufacturing method of the MIM element is not disclosed in Patent Document 1 below.

US Pat. No. 6,753,561

  Therefore, it would be advantageous if a bidirectional Schottky diode element having high conductivity during forward bias, low during reverse bias and relatively low voltage, and high during reverse bias and high voltage can be easily manufactured at a relatively low temperature.

  Furthermore, the above-described bidirectional Schottky diode is manufactured with a resistive memory device, and bipolar writing with less leakage current (writing in which the writing voltage has a reverse polarity when the memory resistance is increased and when the resistance is decreased) It would be advantageous if a 1D1R cross-point memory array capable of the above could be constructed.

  As a result, current flows in either forward bias or reverse bias voltage application polarity under high voltage (forward and reverse) bias conditions, but current is blocked under low voltage bias conditions. The bidirectional diode element will be described. By connecting the bidirectional diode elements in series, a current limiter can be added to the resistance memory cell. As a result, bipolar writing by applying a high voltage is possible, and current can be prevented from flowing through the non-selected word line at the time of low voltage reading.

  In many conventional cross-point resistive memory arrays, current flows from a selected word line to a bit line via a selected memory cell, and simultaneously flows to an unselected word line that intersects the bit line. There is a possibility that a reading failure occurs. However, in the case of a cross point array having a current limiter in a memory cell, it is possible to minimize the current flowing through the unselected word line and to minimize the output (read) voltage.

  Metal / semiconductor / metal (MSM) bi-directional Schottky barrier devices exhibit non-ohmic characteristics that are symmetric with respect to both positive and negative bias voltages. This MSM element can be used as a memory cell current limiter in a resistive cross-point memory array. Since the conductivity of the semiconductor is high and the trapping cross section in the trap state is small, the element can operate stably in a high electric field. The current density of the MSM element can be several orders of magnitude higher than the MIM element.

  In addition to the application to the 1D1R type cross-point memory array, the MSM element of the present invention can be used for other applications and circuits using current limiting diodes.

  Accordingly, the present invention has been made in view of the problems of the conventional MIM element and the characteristics of the bidirectional Schottky barrier element having the above-mentioned MSM structure. A bidirectional Schottky barrier diode that can be used as a limiter and a method for forming the same are provided.

  In order to achieve the above object, a method for forming a bidirectional Schottky barrier diode according to the present invention is a method for forming a bidirectional Schottky diode having a metal / semiconductor / metal laminated structure from a silicon semiconductor. Depositing a silicon semiconductor layer sandwiched between the upper electrode and the upper electrode; forming the bidirectional Schottky diode having a threshold voltage, a breakdown voltage, and an on / off current ratio; and the bidirectional shot Adjusting the threshold voltage of the key diode, the breakdown voltage, and the on / off current ratio by controlling the film thickness of the silicon semiconductor layer. Here, both the threshold voltage and the breakdown voltage increase as the thickness of the silicon semiconductor layer increases. In addition, an optimum film thickness of the silicon semiconductor layer exists for the on / off current ratio.

  In the method for forming a bidirectional Schottky barrier diode according to the present invention, it is more preferable to use either a chemical vapor deposition method (CVD) or a DC sputtering method to deposit an amorphous silicon or polycrystalline silicon semiconductor. Form a layer. For example, DC sputtering can be used to form an amorphous silicon semiconductor layer. The amorphous silicon semiconductor layer becomes a polycrystalline silicon semiconductor layer when annealed thereafter. Increasing the DC sputtering power or increasing the substrate temperature decreases the threshold voltage, increases the breakdown voltage, and decreases the on / off current ratio. Similarly, increasing the oxygen partial pressure increases the threshold voltage and breakdown voltage. When the silicon semiconductor layer is deposited so as to have an optimum film thickness, when the deposited film thickness of the silicon semiconductor layer is smaller than the optimum film thickness, both the on / off current increases and the on / off current ratio decreases. . Similarly, when the deposited film thickness is larger than the optimum film thickness, both the on / off current decreases and the on / off current ratio also decreases.

  In the method for forming a bidirectional Schottky barrier diode according to the present invention, when a silicon semiconductor layer is deposited using a CVD method, the silicon semiconductor layer can be doped with a group V donor material. The doping decreases the threshold voltage and increases the breakdown voltage. Even when doping is used, it is necessary to study the optimum film thickness of the silicon semiconductor layer with respect to the on / off current ratio.

  Hereinafter, a bidirectional Schottky diode according to the present invention and a method for forming the same (hereinafter, referred to as “the element of the present invention” and “the method of the present invention” as appropriate) will be described with reference to the drawings.

  FIG. 1 is a partial cross-sectional view of a bidirectional Schottky diode (element of the present invention) having a metal / semiconductor / metal laminated structure (MSM structure) formed of a silicon semiconductor. The element 100 of the present invention is configured by sequentially laminating a lower electrode (BE) 104, an amorphous silicon semiconductor layer 110, and an upper electrode (TE) 114 on a silicon substrate. The lower electrode (BE) 104 includes a Pt layer 106 on the substrate 102 and a TiN layer 108 on the Pt layer 106. The amorphous silicon semiconductor layer 110 is stacked on the lower electrode 104 and has a thickness 112 of 10 to 80 nm. The upper electrode (TE) 114 includes a TiN layer 114 stacked on the amorphous silicon semiconductor layer 110.

  The range of the film thickness of the amorphous silicon semiconductor is different from the conventional one, and is considered to be an unexpected value. As will be discussed in detail below, optimal device performance depends on film thickness, which must be balanced against the threshold voltage, breakdown voltage, and on / off current ratio. .

As will be described in detail below, the inventive device 100 has a threshold voltage in the range of about 0.8-2V and a breakdown voltage in the range of about 2.5-6V. When the film thickness 112 of the amorphous silicon semiconductor layer 110 is about 30 nm, the threshold voltage of the element 100 of the present invention is about 1.5 V, the breakdown voltage is about 3.5 V, and the on / off current ratio is the same as that of the lower electrode 104 and the upper part. When the applied voltage between the electrodes 114 is 1V (off state where the applied voltage is less than the threshold voltage), the applied voltage is 3V (the applied voltage is equal to or higher than the threshold voltage), compared to 6 × 10 ⁻² A / cm ² . ON state) at 1.5 × 10 ² A / cm ² and about 3.5 digits (10 ^3.5 ).

  When the amorphous silicon semiconductor layer 110 includes a dopant material that is a group V donor, the threshold voltage of the element 100 of the present invention is in the range of about 2 to 3.5 V and the breakdown voltage is in the range of about 6 to 12 V. When the film thickness 112 of the doped amorphous silicon semiconductor layer 110 is about 30 nm, the threshold voltage of the element 100 of the present invention is about 2.5V and the breakdown voltage is about 6V.

In addition to the above materials, the upper electrode 114 and the lower electrode 104 are made of Pt, Ir, Au, Ag, TiN, AlCu, Pd, W, Ti, Cr, Si, Al, Rh, Ta, Ru, TaN, YBCO, It can be made of a material such as indium tin oxide (ITO), InO ₃ , ZnO, RuO ₂ , La _1-x SrxCoO ₃ . However, in addition to the materials listed here, there are known electrode materials that are used in this field. The substrate 102 is not limited to silicon, but may be a material such as Ge, SiO ₂ , GeAs, glass, quartz, or plastic. Further, the amorphous silicon semiconductor material has been used so far, but in other embodiments, polycrystalline silicon is used as the semiconductor material.

  FIG. 2 is a partial cross-sectional view of a memory cell of a resistance memory device including the element 100 of the present invention. The memory cell 200 includes a lower electrode (MRBE) 202 of a resistive memory element and a memory resistive material (MR) 204 on the lower electrode 202 of the resistive memory element. The element 100 of the present invention is provided on the memory resistance material 204. The element 100 of the present invention is as shown in FIG. 1 and described above, and redundant description is omitted for the sake of brevity.

The memory resistive material 204 on the resistive memory element lower electrode 202 is composed of Pr _0.3 Ca _0.7 MnO ₃ (PCMO), giant magnetoresistive (CMR) film, transition metal oxide, Mott insulator, high temperature superconductor ( HTSC) and perovskite materials.

  The upper electrode 114 of the element 100 of the present invention is also the upper electrode of the memory cell 200, and the upper electrodes 114 of the memory cells adjacent in the x-axis direction are connected to each other to form a word line on the memory array. On the other hand, the resistance memory element lower electrode 202 is also the lower electrode of the memory cell 200, and the lower electrodes 202 of the memory cells adjacent in the y-axis direction are connected to each other to form a bit line on the memory array. In the memory array, as is known in the prior art, a plurality of memory cells 200 are connected to each bit line and each word line, respectively. In FIG. 2, the element 100 of the present invention is formed on the resistance memory element. On the other hand, as another embodiment, the element 100 of the present invention may be formed below the resistance memory element. Good (not shown). That is, in the other embodiment, the lower electrode 104 of the element 100 of the present invention is a bit line, and the lower electrode 202 of the resistive memory element is formed on the upper electrode 114 of the element 100 of the present invention. Further, an upper electrode (not shown) of the resistive memory element is provided on the memory resistive material 204, and this upper electrode (not shown) becomes a word line. As an upper electrode and a lower electrode of the resistance memory element, Pt, Ir, Au, Ag, Ru, TiN, Ti, Al, ALCu, Pd, Rh, W, Cr, conductive oxide, Ag, Au, Pt, Ir A material such as TiN can be used.

  The element 100 of the present invention functions as a current limiter and can be used for a memory cell of a cross-point resistive random access memory (RRAM) as described above, and for other applications. For this application, the amorphous silicon MSM structure, in particular, TiN / with amorphous silicon having a film thickness of about 10 nm to 80 nm with or without arsenic implantation using DC sputtering method. The MSM structure of amorphous silicon semiconductor layer / TiN was examined. The current-voltage (IV) curve of the element of the present invention provided with an amorphous silicon thin film exhibits nonlinear characteristics. As the thickness of the amorphous silicon thin film increases, the threshold voltage and breakdown voltage increase and the current decreases. Interesting data is observed when the film thickness of the amorphous silicon semiconductor layer of the element of the present invention is in the range of about 30-50 nm.

<experimental method>
In the following discussion, the substrate is a P-type silicon (100) wafer. After SC1, SC2 cleaning and immersion in 20: 1 HF (hydrogen fluoride) and etching, a 100 nm thick Pt layer and a 150 nm thick TiN layer are deposited on the silicon wafer, An electrode is formed. For the lower electrode and the upper electrode, metals such as Pt, Ir, Al, AlCu, Au, Ag, Pd, Rh, W, Ti, and Cr can be used to name some examples in addition to TiN. The lower electrode and the upper electrode may be conductive oxides such as YBCO, ITO, InO ₃ , ZnO, RuO ₂ , and La _1-x Sr _x CoO ₃ . Interesting data can be obtained from the TiN / amorphous silicon / TiN structure.

Using the DC sputtering method and the CVD method, it is possible to deposit amorphous silicon thin films having various thicknesses in the range of 10 nm to 80 nm on the TiN layer (lower electrode). Tables 1 and 2 list the film forming conditions of the DC sputtering method and the CVD method. As one trial, arsenic with an injection amount of 10 ¹² atoms / cm ² is injected at 30 keV into half of the wafers having various film thicknesses, and annealing is performed at 500 ° C. for 10 minutes. Further, boron is implanted at a rate of 10 ¹³ atoms / cm ² at 200 keV and arsenic is implanted at a rate of 2 × 10 ¹⁵ atoms / cm ² at 30 keV by a double ion implantation method, and is performed at a temperature of about 700 to 900 ° C. A post-annealing process is performed for ~ 90 minutes to form a polycrystalline silicon film having a thickness of 1200 nm. Finally, an upper electrode made of TiN having a thickness of 150 nm is deposited on the amorphous silicon thin film and patterned to form the element of the present invention having an MSM structure. The element structure of this example is silicon / Pt (100 nm) / TiN (150 nm) / amorphous silicon semiconductor layer / TiN (150 nm).

  The phase of the amorphous silicon film can be confirmed by X-ray diffraction. A scanning electron microscope is used to examine the film thickness and surface morphology. The characteristics of MSM elements having various film thicknesses are measured using a precise semiconductor parameter analyzer (HP4156A).

<Experimental result>
3 (a) to 3 (f) are graphs showing IV curves of the element of the present invention when the amorphous silicon semiconductor layer has various film thicknesses. The element size is 100 μm × 100 μm. The current and voltage between both electrodes from the upper electrode of TiN to the lower electrode of the Pt layer are measured. The IV curve of an MSM element having an amorphous silicon semiconductor layer with a thickness of 10 nm exhibits nonlinear characteristics when the applied voltage is 1 V or less. As shown in FIG. 3A, the threshold voltage is about 0.2V, and the breakdown voltage is about 1V. After breakdown, the MSM element does not exhibit nonlinear characteristics. As the thickness of the amorphous silicon semiconductor layer increases, the threshold voltage and breakdown voltage increase and the current decreases at the same applied voltage. On the other hand, by increasing the film thickness of the amorphous silicon semiconductor layer, the amorphous silicon MSM element, which is the element of the present invention, exhibits non-linear characteristics that are more favorable for application to a current limiter.

  In FIG. 3B, the film thickness of the amorphous silicon semiconductor layer is 15 nm, the threshold voltage is about 0.8V, and the breakdown voltage is larger than 2.5V.

  In FIG. 3C, the film thickness of the amorphous silicon semiconductor layer is 20 nm, the threshold voltage is about 1.3V, and the breakdown voltage is larger than 2.5V. The amorphous silicon MSM element, which is the element of the present invention, exhibits very good non-linear characteristics suitable for application to a current limiter.

  In FIG. 3D, the film thickness of the amorphous silicon semiconductor layer is 25 nm, the threshold voltage is about 1.7V, and the breakdown voltage is larger than 3.5V.

  In FIG. 3E, the film thickness of the amorphous silicon semiconductor layer is 30 nm, the threshold voltage is about 1.5V, and the breakdown voltage is larger than 3.5V.

  In FIG. 3F, the film thickness of the amorphous silicon semiconductor layer is 50 nm, the threshold voltage is about 2V, and the breakdown voltage is larger than 6V.

FIG. 4 is a graph showing the relationship between the threshold voltage, the breakdown voltage, and the film thickness of the amorphous silicon semiconductor layer. The MSM element of FIG. 3 (e) having an amorphous silicon semiconductor layer thickness of 30 nm exhibits interesting current limiting characteristics. The “on” current density when the applied voltage is 3 V is about 1.5 × 10 ² A / cm ² , and the “off” current density when the applied voltage is 1 V is about 6 × 10 ⁻² A / cm ^2. cm ² . The ratio of the “on” current density to the “off” current density is approximately 3.5 orders of magnitude (10 ^3.5 ).

  FIGS. 5A to 5D are graphs showing IV characteristics of an MSM element including a silicon semiconductor layer into which arsenic is implanted. In order to further examine the nonlinear characteristics of the amorphous silicon MSM device for application to a current limiter, a silicon semiconductor layer having a thickness of 30 to 80 nm implanted with arsenic was examined in detail. In FIG. 5A, the film thickness of the amorphous silicon semiconductor layer is 30 nm, the threshold voltage is about 2.5V, and the breakdown voltage is larger than 6V.

  In FIG. 5B, the film thickness of the amorphous silicon semiconductor layer is 50 nm, the threshold voltage is about 3V, and the breakdown voltage is larger than 8V.

  In FIG. 5C, the film thickness of the amorphous silicon semiconductor layer is 65 nm, the threshold voltage is about 4V, and the breakdown voltage is larger than 12V.

  In FIG. 5D, the film thickness of the amorphous silicon semiconductor layer is 80 nm, the threshold voltage is about 3.5V, and the breakdown voltage is larger than 10V.

  FIG. 6 is a graph showing the relationship between the threshold voltage, the breakdown voltage, and the film thickness of the amorphous silicon semiconductor layer when arsenic is implanted as a dopant into the amorphous silicon semiconductor layer. An MSM device having a silicon semiconductor layer implanted with arsenic has a higher threshold voltage and breakdown voltage and a reduced current compared to an MSM device without arsenic implantation, and has very good nonlinear characteristics. Is shown. This is presumably because a surface oxide on the amorphous silicon semiconductor layer is formed during the arsenic implantation and the post-annealing process.

  FIGS. 7A and 7B are graphs showing IV curves of an MSM element having an amorphous silicon semiconductor layer thickness of 1200 nm and an element size of 200 μm × 200 μm. The current and voltage between both electrodes from the upper electrode of Pt to the lower electrode of Pt are measured. From the experimental results, when the thickness of the amorphous silicon semiconductor layer is further increased to 1200 nm, the threshold voltage and the breakdown voltage increase beyond 50V. The current decreases as the amorphous silicon film thickness increases. This means that the resistance of the MSM element increases. When the applied voltage is low, the threshold voltage is very small. However, the threshold voltage increases when high voltage training is performed to switch the element state by applying a high voltage before using a low operating voltage to measure the IV curve. The threshold voltage increases as the applied voltage increases and is not ideal for current limiter applications.

  FIGS. 8A and 8B are graphs showing IV curves of an MSM element having an amorphous silicon semiconductor layer thickness of 1200 nm and an element size of 200 μm × 200 μm. The current and voltage between both electrodes from the upper electrode of Pt to the lower electrode of silicon are measured. As shown in FIG. 8A, the IV curve exhibits nonlinear characteristics with respect to a high applied voltage. However, as shown in FIG. 8B, the IV curve tends to be linear for a low applied voltage. As the applied voltage increases, the threshold voltage also increases. Experimental results show that MSM devices with thick amorphous silicon semiconductor layers are not ideal for current limiter applications.

In summary, the IV curve of the MSM element having an amorphous silicon semiconductor layer shows nonlinear characteristics, and as the film thickness of the amorphous silicon semiconductor layer increases, the threshold voltage and breakdown voltage increase, Decrease. The MSM element in which arsenic is implanted into the silicon semiconductor layer exhibits very good non-linearity as compared with the MSM element without arsenic implantation, and the threshold voltage and breakdown voltage are high and the current is low. This is considered to be caused by the formation of a surface oxide on the amorphous silicon semiconductor layer during the arsenic implantation and the post annealing process. This surface oxide is removed by HF surface cleaning. As shown in FIG. 3E, data suitable for a current limiter can be obtained from an MSM element including amorphous silicon having a thickness of 30 nm. The “on” current density when the applied voltage is 3 V is about 1.5 × 10 ² A / cm ² , and the “off” current density when the applied voltage is 1 V is about 6 × 10 ⁻² A / cm ^2. cm ² . The ratio is about 3.5 digits.

  Cross-point resistive memory arrays require current limiter elements such as diodes connected in series with the individual resistive memory elements to minimize write disturb, write disturb, and read disturb. A cross-point memory array including diodes connected in series with individual resistive memory elements can only perform monopolar writing using voltage pulses of the same polarity. Since a high-quality (ie, single crystal) diode cannot be manufactured on a metal multilayer film, it is possible to integrate a memory cell formed by connecting a diode and a resistance memory element in series to form a resistance cross-point memory array. Impossible. Metal / insulator / metal (MIM) devices are not reliable even when operating at very low current densities, so the MIM current limiter cannot replace the diode. This MIM element reliability problem is caused by the deep trap state of the insulator and the catastrophic breakdown that occurs locally. However, a bidirectional Schottky structure can be formed by replacing the insulator with a semiconductor material.

  The MSM element functions as a bidirectional Schottky diode. The current density depends on the metal barrier height for the semiconductor. The series resistance of the MSM element is reduced by reducing the film thickness and specific resistance of the semiconductor material. If the thickness of the semiconductor is too thin, the leakage current of the element increases and the current at the time of low bias becomes too large, making it unsuitable for application to an actual memory cell. Since the purpose of the MSM element is to limit the current flowing through the non-selected memory cells in the memory array, the IV characteristics of the MSM element need not be symmetric around the zero bias voltage. Therefore, the MSM electrode need not be the same material.

<Description of the method of the present invention>
FIG. 9 is a flowchart schematically showing a method (method of the present invention) for forming a bidirectional Schottky diode (MSM diode) having an MSM structure from a silicon semiconductor. In the method of the present invention, for the sake of clarity, the steps are numbered and shown in numerical order, but the step numbers do not necessarily determine the order of the steps. These steps may be omitted, performed in parallel, or performed without requiring strict ordering. For example, the case where one process is substantially a part of another process is included. The inventive method begins at step 900.

  In step 902, a silicon semiconductor layer sandwiched between the lower electrode and the upper electrode is deposited. In the step 902 of depositing the silicon semiconductor layer, a semiconductor layer selected from amorphous silicon or polycrystalline silicon material is formed by CVD or DC sputtering. In step 904, an MSM diode having a threshold voltage, a breakdown voltage, and an on / off current ratio is formed. In step 906, the threshold voltage, breakdown voltage, and on / off current ratio of the MSM diode are adjusted according to the control of the film thickness of the silicon semiconductor layer.

  In general, when the film thickness of the silicon semiconductor layer is increased in step 902, the threshold voltage and the breakdown voltage increase (step 906), but there is an optimum film thickness for the on / off current ratio. The optimum film thickness refers to a film thickness at which a large on / off current ratio can be obtained. In step 902, the silicon semiconductor layer is deposited to the optimum film thickness (corresponding to the first film thickness), and in step 906, the on / off current ratio of the MSM diode is adjusted. This process has sub-steps. When the thickness of the silicon semiconductor layer becomes thinner than the optimum thickness in step 902, both the on-current and the off-current increase in step 906a. If the film thickness of the silicon semiconductor layer becomes larger than the optimum film thickness in step 902, both the on-current and off-current decrease in step 906b.

  In one embodiment, in step 902, an amorphous silicon semiconductor layer is formed by the following procedure using DC sputtering. The substrate is heated at a temperature of about 20-200 ° C., generating a deposition pressure in the range of about 7.0-9.0 mTorr, using an argon atmosphere, using silicon as the target, and with an output in the range of about 100-300 W. Sputtering is performed to form an amorphous silicon semiconductor layer.

  Subsequent to the formation of the amorphous silicon semiconductor layer, in step 902, a polycrystalline silicon semiconductor layer is formed using a DC sputtering method. Annealing is performed at a temperature exceeding 550 ° C., and as a result, a polycrystalline silicon semiconductor layer is formed.

  In one embodiment, increasing the DC sputtering power at step 902 or increasing the substrate temperature decreases the threshold voltage, increases the breakdown voltage, and decreases the on / off current ratio at step 906.

  In step 902, when an amorphous silicon semiconductor is formed by DC sputtering using an oxygen partial pressure in the range of 0 to 5%, in step 906, the threshold voltage and the breakdown voltage increase as the oxygen partial pressure increases. . In consideration of the thickness of the silicon semiconductor layer deposited in step 902, in step 906, the on / off current ratio of the MSM diode is adjusted as follows in accordance with the increase in oxygen partial pressure. When the thickness of the silicon semiconductor layer is less than the optimum thickness (defined for the on / off current ratio), the on / off current ratio decreases. Similarly, when the film thickness of the silicon semiconductor layer is larger than the optimum film thickness, the on / off current ratio decreases.

In step 902, a silicon semiconductor layer can also be formed using a CVD method as follows. Silane is introduced at a flow rate in the range of about 40-200 sccm (standardized cm ³ / min) and the substrate is heated at a temperature in the range of about 500-600 ° C. to produce a deposition pressure in the range of about 150-250 mTorr. The silicon semiconductor layer is formed by performing deposition for a time in the range of about 10 minutes to 6 hours.

  In another embodiment, in step 903, the silicon semiconductor layer is doped with a Group V donor material. Next, in step 906, the threshold voltage, breakdown voltage, and on / off current ratio are adjusted. Here, as the doping of the silicon semiconductor layer in step 903 progresses, the threshold voltage is decreased and the breakdown voltage is increased.

  In consideration of the thickness of the silicon semiconductor layer deposited in step 902, in step 906, the on / off current ratio of the MSM diode is changed as follows according to the doping of the silicon semiconductor layer. When the thickness of the silicon semiconductor layer is less than the optimum thickness (defined for the on / off current ratio), the on / off current ratio decreases. Similarly, the on / off current ratio decreases when the silicon film is thicker than the optimum film thickness.

In one embodiment, there are two sub-steps 903a, 903b in the doping of the silicon semiconductor layer in step 903. In sub-step 903a, arsenic is implanted at an energy of about 30 keV and an implantation amount of 1 × 10 ¹² atoms / cm ² , and in sub-step 903b, annealing is performed at a temperature of about 500 ° C. for about 10 minutes. In another embodiment, step 902 forms a polycrystalline silicon semiconductor layer having a thickness in the range of about 600-1200 nm. Next, in step 903, the silicon semiconductor layer is doped. In step 903, sub-steps 903c to 903e are provided in place of the sub-steps 903a and 903b. In sub-step 903c, boron is implanted with an energy of about 200 keV and an implantation amount of 1 × 10 ¹³ atoms / cm ^{2. In} step 903d, arsenic is implanted with an energy of about 30 keV and an implantation amount of 2 × 10 ¹⁵ atoms / cm ^2. Implant and anneal in step 903e at a temperature of about 700 ° C. to 900 ° C. for about 30 to 90 minutes.

  FIG. 10 is a flowchart showing another embodiment of the method of the present invention. Another embodiment of the method of the invention begins at step 1000. In step 1002, a silicon substrate is provided. In step 1004, a lower electrode composed of a Pt layer on a silicon substrate and a TiN layer on the Pt layer is formed. In step 1006, an amorphous silicon semiconductor layer is formed on the lower electrode with a thickness in the range of 10 to 80 nm. In step 1008, a TiN upper electrode is formed on the amorphous silicon semiconductor layer. Step 1010 forms an MSM diode having a threshold voltage in the range of about 0.8-2V and a breakdown voltage in the range of about 2.5-6 volts.

In one embodiment, the thickness of the amorphous silicon semiconductor layer formed in step 1006 is about 30 nm. Next, in step 1010, an MSM diode having a threshold voltage of about 1.5V and a breakdown voltage of about 3.5V is formed. The on / off current ratio of the MSM diode formed in step 1010 is “on” when the applied voltage is 3V, while the “off” current density is 6 × 10 ⁻² A / cm ² when the applied voltage is 1V. The current density is about 1.5 × 10 ² A / cm ² and the ratio of the “on” current density to the “off” current density is about 3.5 orders of magnitude (10 ^3.5 ).

  In another embodiment, in step 1007, the amorphous silicon semiconductor layer is doped with a Group V donor material. Next, in step 1010, an MSM diode having a threshold voltage adjusted to a range of about 2 to 3.5V and a breakdown voltage adjusted to a range of about 6 to 12V is formed. When the amorphous silicon semiconductor layer is formed with a thickness of about 30 nm in step 1006, in step 1010, an MSM diode having a threshold voltage of about 2.5V and a breakdown voltage of about 6V is formed.

  The bidirectional Schottky diode (the element of the present invention) having an MSM structure formed from a silicon semiconductor and the manufacturing process (the method of the present invention) have been described above. In order to illustrate the present invention, examples of process details were given. Similarly, although the resistance memory device is shown as an example of application, the present invention is not limited to these examples.

1 is a cross-sectional view of an essential part schematically showing a cross-sectional structure of a bidirectional Schottky diode having a metal / semiconductor / metal laminated structure formed of a silicon semiconductor according to the present invention. 1 is a cross-sectional view of an essential part schematically showing a cross-sectional structure of a resistance memory device including a bidirectional Schottky diode according to the present invention. The figure which shows the current voltage characteristic of the bidirectional Schottky diode of the MSM structure in the film thickness of various amorphous silicon The figure which shows the relationship between the threshold voltage, the breakdown voltage, and the film thickness of the amorphous silicon semiconductor layer The figure which shows the current-voltage characteristic of the bidirectional Schottky diode of the MSM structure provided with the silicon semiconductor layer into which arsenic was implanted The figure which shows the relationship between the threshold voltage, the breakdown voltage, and the film thickness of an amorphous silicon semiconductor layer when arsenic is implanted into an amorphous silicon semiconductor layer as a dopant The figure which shows the current-voltage characteristic of the bidirectional Schottky diode of the MSM structure whose film thickness of an amorphous silicon semiconductor layer is 1200 nm and element size is 200 micrometers x 200 micrometers The figure which shows the current-voltage characteristic of the bidirectional Schottky diode of the MSM structure whose film thickness of an amorphous silicon semiconductor layer is 1200 nm and element size is 200 micrometers x 200 micrometers 1 is a flowchart showing an embodiment of a method for forming a bidirectional Schottky diode having a metal / semiconductor / metal stacked structure from a silicon semiconductor according to the present invention. 6 is a flowchart showing another embodiment of a method for forming a bidirectional Schottky diode having a metal / semiconductor / metal stacked structure from a silicon semiconductor according to the present invention.

Explanation of symbols

100: Bidirectional Schottky diode having a metal / semiconductor / metal laminate structure according to the present invention 102: Silicon substrate 104: Lower electrode (BE)
106: Pt layer 108: TiN layer 110: Amorphous silicon semiconductor layer 112: Silicon semiconductor layer thickness 114: TiN upper electrode (TE)
200: Memory cell of resistance memory device 202: Lower electrode (MRBE) of resistance memory element
204: Memory resistance material (MR)

Claims (26)

A method of forming a bidirectional Schottky diode having a metal / semiconductor / metal laminate structure from a silicon semiconductor,
Depositing a silicon semiconductor layer sandwiched between a lower electrode and an upper electrode;
Forming the bidirectional Schottky diode having a threshold voltage, a breakdown voltage, and an on / off current ratio;
Adjusting the threshold voltage, the breakdown voltage, and the on / off current ratio of the bidirectional Schottky diode by controlling the thickness of the silicon semiconductor layer;
A method for forming a bidirectional Schottky diode, comprising:   2. The method of forming a bidirectional Schottky diode according to claim 1, wherein the silicon semiconductor layer of amorphous silicon or polycrystalline silicon is formed in the step of depositing the silicon semiconductor layer.   3. The method of forming a bidirectional Schottky diode according to claim 2, wherein chemical vapor deposition (CVD) or DC sputtering is used as the deposition method in the step of depositing the silicon semiconductor layer. In the step of depositing the silicon semiconductor layer, when the silicon semiconductor layer of amorphous silicon is formed using the DC sputtering method,
Using a silicon target,
Sputtering with an output in the range of about 100-300 W,
Heating the substrate at a temperature of about 20-200 ° C .;
Producing a deposition pressure in the range of about 7.0 to 9.0 mTorr;
Using an argon atmosphere,
Deposits in a time in the range of about 7 to 150 minutes,
4. The method of forming a bidirectional Schottky diode according to claim 3, wherein amorphous silicon is formed. In the step of depositing the silicon semiconductor layer, when the silicon semiconductor layer of polycrystalline silicon is formed using the DC sputtering,
Following the formation of the amorphous silicon, annealing is performed at a temperature exceeding 550 ° C.
5. The method of forming a bidirectional Schottky diode according to claim 4, wherein polycrystalline silicon is formed.   In the step of adjusting the threshold voltage, the breakdown voltage, and the on / off current ratio of the bidirectional Schottky diode, the threshold voltage is decreased according to an increase in the DC sputtering output, and the breakdown voltage is 5. The method of forming a bidirectional Schottky diode according to claim 4, wherein the on / off current ratio is increased and the on / off current ratio is decreased.   In the step of adjusting the threshold voltage, the breakdown voltage, and the on / off current ratio of the bidirectional Schottky diode, the threshold voltage is decreased and the breakdown voltage is increased as the substrate temperature increases. 5. The method of forming a bidirectional Schottky diode according to claim 4, wherein the on / off current ratio is reduced. In the step of depositing the silicon semiconductor layer, when the silicon semiconductor layer of amorphous silicon is formed using the DC sputtering method, an oxygen partial pressure in the range of 0 to 5% is used.
In the step of adjusting the threshold voltage, the breakdown voltage, and the on / off current ratio of the bidirectional Schottky diode, the threshold voltage and the breakdown voltage are increased according to an increase in the oxygen partial pressure. The method of forming a bidirectional Schottky diode according to claim 4. In the step of depositing the silicon semiconductor layer, when forming the silicon semiconductor layer with a first film thickness as a reference film thickness,
In the step of adjusting the on / off current ratio of the bidirectional Schottky diode according to an increase in the oxygen partial pressure,
When the film thickness of the silicon semiconductor layer is smaller than the first film thickness, the on / off current ratio decreases,
9. The method of forming a bidirectional Schottky diode according to claim 8, wherein the on / off current ratio decreases when the thickness of the silicon semiconductor layer is larger than the first thickness.   In the step of adjusting the threshold voltage, the breakdown voltage, and the on / off current ratio of the bidirectional Schottky diode, the threshold voltage and the breakdown voltage are set according to an increase in the thickness of the silicon semiconductor layer. The method of forming a bidirectional Schottky diode according to claim 1, wherein the number is increased. In the step of depositing the silicon semiconductor layer, when forming the silicon semiconductor layer with a first film thickness as a reference film thickness,
In the step of changing the on / off current ratio of the bidirectional Schottky diode,
As the film thickness of the silicon semiconductor layer decreases below the first film thickness, both on-current and off-current increase,
11. The bidirectional Schottky diode according to claim 10, wherein both the on-current and the off-current decrease as the thickness of the silicon semiconductor layer increases beyond the first thickness. Forming method. In the step of depositing the silicon semiconductor layer,
Using chemical vapor deposition as the deposition method,
Silane is introduced at a flow rate in the range of about 40 to 200 cm ³ / min in terms of standard conditions,
Heating the substrate at a temperature in the range of about 500-600 ° C;
Producing a deposition pressure in the range of about 150-250 mTorr;
4. The method of forming a bidirectional Schottky diode according to claim 3, wherein the silicon semiconductor layer is deposited by deposition for a time in a range of about 10 minutes to 6 hours. Further comprising doping the silicon semiconductor layer with a Group V donor material;
In the step of adjusting the threshold voltage, the breakdown voltage, and the on / off current ratio of the bidirectional Schottky diode, the threshold voltage is decreased as the doping amount of the silicon semiconductor layer increases. 13. The method of forming a bidirectional Schottky diode according to claim 12, wherein the breakdown voltage is increased. In the step of depositing the silicon semiconductor layer, when forming the silicon semiconductor layer with a first film thickness as a reference film thickness,
In the step of changing the on / off current ratio of the bidirectional Schottky diode according to the doping of the silicon semiconductor layer,
When the film thickness of the silicon semiconductor layer is smaller than the first film thickness, the on / off current ratio decreases,
14. The method of forming a bidirectional Schottky diode according to claim 13, wherein the on / off current ratio decreases when the thickness of the silicon semiconductor layer is larger than the first thickness. In the step of doping the silicon semiconductor layer,
Arsenic is implanted with an energy of about 30 keV and an implantation amount of about 1 × 10 ¹² atoms / cm ² ;
The method of forming a bidirectional Schottky diode according to claim 13, wherein annealing is performed at a temperature of about 500 ° C. for about 10 minutes. In the step of depositing the silicon semiconductor layer, a polycrystalline silicon semiconductor layer having a film thickness in the range of about 600 to 1200 nm is formed,
In the step of doping the silicon semiconductor layer,
Boron is implanted with an energy of about 200 keV and an implantation amount of about 1 × 10 ¹³ atoms / cm ² ;
Arsenic is implanted with an energy of about 30 keV and an implantation amount of about 2 × 10 ¹⁵ atoms / cm ² ;
14. The method of forming a bidirectional Schottky diode according to claim 13, wherein annealing is performed at a temperature in the range of about 700 to 900 [deg.] C. for about 30 to 90 minutes. A method of forming a bidirectional Schottky diode having a metal / semiconductor / metal laminate structure from a silicon semiconductor,
Providing a silicon substrate;
Forming a lower electrode with a Pt layer on the substrate and a TiN layer on the Pt layer;
Forming an amorphous silicon semiconductor layer on the lower electrode with a thickness in the range of 10 to 80 nm;
Forming a TiN upper electrode on the amorphous silicon semiconductor layer;
Forming a bidirectional Schottky diode having a threshold voltage in the range of about 0.8-2V and a breakdown voltage of about 2.5-6V;
A method for forming a bidirectional Schottky diode, comprising: In the step of forming the amorphous silicon semiconductor layer, an amorphous silicon film is formed with a thickness of about 30 nm,
18. The bidirectional Schottky diode according to claim 17, wherein forming the bidirectional Schottky diode includes forming a bidirectional Schottky diode having a threshold voltage of about 1.5V and a breakdown voltage of about 3.5V. Method for forming Schottky diode. In the step of forming the bidirectional Schottky diode, an applied voltage between the lower electrode and the upper electrode is 1 V and an off current of about 6 × 10 ⁻² A / cm ² is applied between the lower electrode and the upper electrode. 19. The bidirectional Schottky diode having an on / off current ratio of about 1.5 × 10 ² A / cm ² when an applied voltage of 3V is applied is formed. Method for forming Schottky diode. Further comprising doping the amorphous silicon semiconductor layer with a Group V donor material;
Forming the bidirectional Schottky diode to form a bidirectional Schottky diode having a threshold voltage in a range of about 2 to 3.5 V and a breakdown voltage in a range of about 6 to 12 V; Item 18. A method for forming a bidirectional Schottky diode according to Item 17. In the step of forming the amorphous silicon semiconductor layer, an amorphous silicon film is formed with a thickness of about 30 nm,
21. The bidirectional shot of claim 20, wherein forming the bidirectional Schottky diode includes forming a bidirectional Schottky diode having a threshold voltage of about 2.5V and a breakdown voltage of about 6V. Method for forming a key diode. A bidirectional Schottky diode having a metal / semiconductor / metal laminate structure formed of a silicon semiconductor,
A silicon substrate;
A lower electrode comprising a Pt layer on the substrate and a TiN layer on the Pt layer;
An amorphous silicon semiconductor layer formed on the lower electrode and having a thickness in the range of 10 to 80 nm;
A TiN upper electrode formed on the amorphous silicon semiconductor layer;
A bidirectional Schottky diode comprising:   23. The bidirectional Schottky diode according to claim 22, wherein the bidirectional Schottky diode has a threshold voltage in the range of about 0.8-2V and a breakdown voltage in the range of about 2.5-6V. . The amorphous silicon semiconductor layer has a thickness of about 30 nm;
The bidirectional Schottky diode has a threshold voltage of about 1.5V, a breakdown voltage of about 3.5V, and an applied voltage between the lower electrode and the upper electrode of about 6 × 10 ⁻² A / cm ^{2 at} 1V. The on-off current ratio is such that an applied voltage between the lower electrode and the upper electrode is 3 V and an on-current is about 1.5 × 10 ² A / cm ² with respect to an off-state current of about 1.5 × 10 ^2. 23. A bidirectional Schottky diode according to 22. The amorphous silicon semiconductor layer includes a dopant material of a group V element that serves as a donor,
23. The bidirectional Schottky diode of claim 22, wherein the bidirectional Schottky diode has a threshold voltage in the range of about 2 to 3.5V and a breakdown voltage of about 6 to 12V. The amorphous silicon semiconductor layer has a thickness of about 30 nm;
26. The bidirectional Schottky diode of claim 25, wherein the bidirectional Schottky diode has a threshold voltage of about 2.5V and a breakdown voltage of about 6V.

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