RU208280U1 - Semiconductor protective coating - Google Patents

Abstract

The utility model relates to the field of electronic engineering, in particular to the design of high-voltage semiconductor devices based on silicon. EFFECT: increased breakdown voltage of devices, as a result, an increase in the percentage of yield and an increase in temperature stability. The essence of the utility model lies in the fact that in a high-voltage semiconductor device based on n-type silicon, containing a working transition and a system of guard rings. Directly on the transition and guard rings there is a protective coating consisting of several consecutive layers: amorphous silicon 0.34-0.92 microns thick and silicon nitride 0.10-0.14 microns thick, a passivation layer in the form of silicon oxynitride 1 thick, 3-1.5 microns, while the layer of amorphous silicon has direct contact with the metallization, and also contains oxygen, the content of which is 17-28 atomic percent of the silicon content. 1 ill.

Description

Technology area

The utility model relates to the field of high-power high-voltage semiconductor devices, namely to the construction of silicon-based semiconductor devices, and can be used to create an element base.

State of the art

A known method of manufacturing a semiconductor device [RF patent 2506660, H01L 21/31] with increased breakdown voltage by forming the device by chemical vapor deposition methods with the formation of a passivating coating by successive application of five layers. In this case, the last layer of semi-insulating amorphous silicon is applied at atmospheric pressure and a temperature of 650 ° C, while nitrogen is used as a carrier.

The disadvantages of this method are:

low resistance of the passivating coating to moisture and impurities, which can lead to leaks and breakdown voltage drift, due to the fact that the amorphous silicon layer is applied last (external) and is not protected by anything;

low reproducibility of the layer thickness, since the amorphous silicon layer is applied at atmospheric pressure, as a result of which the layer growth rate is high and it is difficult to control the exact time of the process;

low effect of increasing the breakdown voltage due to the fact that there are several intermediate layers between the silicon surface and the amorphous silicon layer, that is, first, a layer of thermal silicon dioxide with a thickness of 0.54 μm is applied, and then several layers applied by chemical vapor deposition: silicon dioxide, phosphoric -silicate glass (0.4 microns), again silicon dioxide 0.16 microns.

Disclosure of the essence of the utility model

The technical result of the proposed utility model is to increase the breakdown voltage of the devices and, as a consequence, to increase the percentage of yield and increase the temperature stability.

The specified technical result is achieved by the fact that in a semiconductor device based on n-type silicon, containing a working junction and a system of guard rings, on the working junction and guard rings there is a protective coating, which consists of several sequentially located layers: amorphous silicon with a thickness of 0.34 - 0.92 microns, silicon nitride with a thickness of 0.10-0.14 microns and a passivation layer in the form of silicon oxynitride with a thickness of 1.3-1.5 microns, while the amorphous silicon layer has direct contact with metallization, and also contains oxygen, the content of which is 17-28 atomic% of the silicon content.

The amorphous silicon layer does not have a built-in positive charge, as well as mobile charged ions that negatively affect the breakdown voltage of devices. On top of this layer there is a layer of silicon nitride, as well as a layer of passivation in the form of silicon oxynitride with a thickness of 1.3-1.5 microns, which are a barrier to the penetration of ionic contaminants into the underlying layer of amorphous silicon, and also protect from moisture and other impurities. At the same time, the amorphous silicon film has a shielding effect for the electric field created by ionic impurities on the crystal surface during assembly into the package.

The amorphous silicon layer is in direct contact with the metallization of the semiconductor device and thus acts as a potential plate in order to further increase the breakdown voltage. The amorphous silicon layer contains oxygen, the content of which is 17-28 atomic%, which, on the one hand, facilitates the gettering of any accidentally caught impurities, and on the other hand, avoids noticeable leakage currents.

Brief Description of Drawings

The essence of the proposed utility model is shown by the example of a schematic construction of a silicon diode crystal in FIG. 1 and the comparative diffraction patterns of FIG. 2.

The positions in FIG. 1 are marked:

1 - original n-type silicon;

2 - security rings;

3 - working transition;

4 - layer of amorphous silicon;

5 - a layer of silicon nitride;

6 - passivation layer;

7 - metallization.

8 - p-type area.

Implementation of the utility model

On the original n-type silicon wafer, diffusion n- and p-regions are formed in such a way that there is a working junction and a system of guard rings, then on this junction and guard rings several layers of a protective coating are sequentially located, namely: a layer of amorphous silicon with a thickness of 0, 34-0.92 microns, silicon nitride with a thickness of 0.10-0.14 microns, obtained by chemical vapor deposition at low pressure, while a layer of amorphous silicon is obtained at a pressure of 15.0-25.0 Pa and a temperature of 600- 650 ° C, and a passivation layer in the form of silicon oxynitride with a thickness of 1.3-1.5 microns, or silicon dioxide with a thickness of 1.1-1.3 microns, or their combination with a total thickness of 1.1-2.8 microns, applied by the method activated by microwave plasma chemical vapor deposition. Metallization is also formed as electrodes. The layers of protective coating and metallization are located so that there is direct contact between the amorphous silicon layer and the metallization.

The oxygen content in amorphous silicon is 17-28 atomic%. Diffraction patterns of the obtained amorphous silicon are presented in the range of angles 20 from 40 to 80 ° from a DRON-4-07 diffractometer. For comparison, the diffractogram of polycrystalline silicon (poly-Si), which is obtained from the powder by grinding a single-crystal silicon plate in an agate mortar, is shown as a reference. It contains diffraction reflections from planes with indices (111), (220), (311), which coincides with the values of interplanar distances and relative intensities with the international powder diffraction database. X-ray diffraction results of amorphous silicon samples showed no reflection from crystallographic planes and a uniform background, which indicates that its structure has a short-range order, that is, all samples are amorphous (a = Si: O) (see Fig. 2).

According to the proposed utility model, semiconductor devices for different breakdown voltages were manufactured and investigated. The results are presented in the table (Fig. 3).

Experimental studies have shown that the yield of suitable semiconductor devices on wafers, manufactured according to the proposed utility model, increased by 10.5%.

The stability of the breakdown voltage of the devices in the operating temperature range met the requirements, and also increased the reliability of the devices and their resistance to operation up to a temperature of 175 ° C.

EFFECT: increased breakdown voltage of devices, increased percentage of yield, increased temperature stability.

Claims (1)

Protective coating of a semiconductor device based on n-type silicon, containing a working junction and a system of guard rings and having a protective coating directly on the junction and guard rings, characterized in that the coating consists of several successive layers: amorphous silicon 0.34-0 thick, 92 microns and silicon nitride with a thickness of 0.10-0.14 microns, a passivation layer in the form of silicon oxynitride with a thickness of 1.3-1.5 microns, while the amorphous silicon layer has direct contact with metallization, and also contains oxygen, the content of which is 17-28 atomic percent of the silicon content.

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