JP6803232B2 - New laminate - Google Patents

Description

The present invention relates to a laminate, an element including the laminate, an electric circuit including the element, an electric device, and a vehicle.

As a Schottky barrier diode that realizes a large current and high power consumption, an example in which SiC or GaN is epitaxially grown on an inexpensive Si wafer substrate is disclosed (for example, Patent Documents 1 to 3).
Regarding SiC, the crystal structure suitable for a power semiconductor is 4H-SiC, but it is extremely difficult to epitaxially grow it on Si because of the large lattice mismatch. If it is 3C-SiC, it can be epitaxially grown by finely processing a Si wafer or using a Si (211) plane, but it is difficult to obtain a thick film suitable for a power device.

On the other hand, although GaN is not as good as SiC in terms of lattice mismatch with Si, crystal growth is difficult without a buffer layer such as AlN. A sapphire substrate with a close lattice constant is also a good candidate, but it cannot be used for large current applications because it cannot pass current in the vertical direction.
Therefore, in order to use a conductive substrate such as Si, it is necessary to go through a step of laminating a buffer layer on the substrate and further crystal-growing GaN. However, even with this, it was difficult to obtain a complete crystal.

JP-A-2009-164638 Japanese Unexamined Patent Publication No. 2010-40972 Japanese Unexamined Patent Publication No. 2013-227198

The present invention has been made in view of such a problem, and by controlling the natural oxide film to a specific thickness or less and forming a metal oxide having a wide bandgap on the natural oxide film, excellent current-voltage characteristics are obtained. It is an object of the present invention to provide a laminate that exhibits the above.

According to the present invention, the following laminates and the like are provided.
1. 1. A laminate containing a Si layer and a metal oxide layer, in which the film thickness of the SiO ₂ layer on the surface of the Si layer on the metal oxide layer side is 0.0 nm to 15.0 nm.
2. 2. The laminate according to 1, wherein a metal-containing layer is contained between the Si layer and the metal oxide layer.
3. 3. The laminate according to 1 or 2, wherein the metal oxide layer has an amorphous or microcrystalline structure.
4. The laminate according to any one of 1 to 3, wherein the composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3).
0 ≤ x / (x + y + z) ≤ 0.5 (1)
0 ≤ y / (x + y + z) ≤ 0.8 (2)
0.2 ≤ z / (x + y + z) ≤ 1.0 (3)
(In the formula, x, y and z each represent the number of one or more atoms selected from the following elements.
x = In, Sn, Ge, Ti
y = Zn, Y, Sm, Ce, Nd
z = Ga, Al)
5. The laminate according to any one of 1 to 4, wherein the carrier concentration of the metal oxide layer is 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 .
6. The laminate according to any one of 1 to 5, wherein the work function of the Si layer is 3.9 eV to 5.0 eV.
7. The laminate according to any one of 2 to 6, wherein the work function of the metal-containing layer is 3.5 eV to 5.8 eV.
8. Includes metal layer and metal oxide layer
The metal layer is made of a metal M different from the metal of the metal oxide constituting the metal oxide layer.
_M X _{O Y} layer laminate thickness of (respectively integer x and y) is 0.0nm~15.0nm on the surface of the metal oxide layer side of the metal layer.
9. The laminate according to 8, wherein the composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3).
0 ≤ x / (x + y + z) ≤ 0.5 (1)
0 ≤ y / (x + y + z) ≤ 0.8 (2)
0.2 ≤ z / (x + y + z) ≤ 1.0 (3)
(In the formula, x, y and z each represent the number of one or more atoms selected from the following elements.
x = In, Sn, Ge, Ti
y = Zn, Y, Sm, Ce, Nd
z = Ga, Al)
An element containing the laminate according to any one of 10.1 to 9.
11. 10. The device according to 10, which has non-linear electrical conductivity.
12. An electrical circuit or sensor comprising the element according to 10 or 11.
An electrical device or vehicle comprising the element according to 13.10 or 11.

According to the present invention, it is possible to provide a laminate capable of exhibiting excellent current-voltage characteristics. By controlling the natural oxide film to a specific thickness or less and forming a metal oxide having a wide bandgap on the natural oxide film, excellent current-voltage characteristics can be exhibited. Further, since the metal oxide can be formed by a method that is inexpensive and has excellent mass productivity, the productivity can be remarkably improved as compared with the conventional case.

It is a figure which shows one Embodiment (Si layer / SiO ₂ layer / metal oxide layer) of the laminated body of this invention. It is a figure which shows one Embodiment (Si layer / metal oxide layer) of the laminated body of this invention. It is a figure which shows one Embodiment (Si layer / SiO ₂ layer / intermediate metal layer (metal-containing layer) / metal oxide layer) of the laminated body of this invention. It is a figure which shows one Embodiment (Si layer / intermediate metal layer / metal oxide layer) of the laminated body of this invention. It is a figure which shows one Embodiment (Si layer / SiO ₂ layer / metal oxide layer / upper metal (surface metal layer)) of the laminated body of this invention. It is a figure which shows one Embodiment (Si layer / SiO ₂ layer / metal oxide layer / upper metal / protective film) of the laminated body of this invention. It is a figure which shows one Embodiment (Si layer / SiO ₂ layer / metal oxide layer (a guard ring is embedded in the upper electrode side) / upper metal / protective film) of the laminated body of this invention. It is a figure which shows one Embodiment (Si layer / SiO ₂ layer / metal oxide layer (guard ring embedded in the lower electrode side) / upper metal / protective film) of the laminated body of this invention. It is a figure which shows one Embodiment (MPS diode) of the laminated body of this invention. It is a figure which shows one Embodiment (metal M layer / M _{x Oy} layer / metal oxide layer (guard ring embedded in the upper electrode side) / upper metal / protective film) of the laminated body of this invention. An embodiment of the laminate of the present invention (Si layer / SiO ₂ layer / Metal M layer / M _{x Oy} layer / Metal oxide layer (guard ring embedded on the upper electrode side) / Upper metal / protective film) is shown. It is a figure. It is a figure which shows one Embodiment of the manufacturing method of the laminated body of this invention. It is a figure which shows one Embodiment of the manufacturing method of the laminated body of this invention. It is a figure which shows one Embodiment when the laminated body of this invention is used for a planar gate type power MOSFET. It is a figure which shows one Embodiment when the laminated body of this invention is used for a trench gate type power MOSFET. It is a figure which shows one Embodiment of the planar gate type power MOSFET using the laminated body of this invention in the case where the metal oxide is used for a drift region, and polycrystalline silicon is used for a channel region. It is a figure which shows one Embodiment of the module which was configured by combining the elements of this invention. It is a figure which shows the embodiment in the case where the diode and the MOSFET are connected to the copper plate through the back metal and the solder in the module of FIG. 17, and the Si wafer side of the diode is connected to the collector of the MOSFET. It is a figure which shows the embodiment in the case where the diode and the MOSFET are connected to the copper plate through the back metal and the solder in the module of FIG. 17, and the oxide semiconductor side of the diode is connected to the collector of the MOSFET. Is an XRD pattern of _Ga 2 _{O 3} film of 3700nm where the _Ga 2 _{O 3} film of 9700nm obtained in Example 1 was obtained in Example 2. 8 is an electron diffraction image of a Ga ₂ O ₃ film having a film thickness of 9700 nm obtained in Example 1. 3 is a TEM image of the SiO ₂ portion at the Si layer interface of the laminate obtained in Examples 1, 7 and 8. It is a figure which shows the manufacturing process of the Schottky barrier diode manufactured in Example 15.

1. 1. Laminated body The first laminated body of the present invention includes a Si layer and an oxide metal layer. Further, the film thickness of the SiO ₂ layer on the surface of the Si layer on the metal oxide layer side is 0.0 nm to 15.0 nm. That is, the SiO ₂ layer may or may not be present.
The first laminate of the present invention has an excellent current-voltage effect by forming a compound semiconductor having a wide bandgap on an inexpensive Si substrate even if a natural oxide film having a specific thickness exists. The characteristics can be realized.

The second laminate of the present invention includes a metal layer and a metal oxide layer. Here, the metal layer is made of a metal M different from the metal of the metal oxide constituting the metal oxide layer. Further, the film thickness of the M _x O _y layer (x and y are integers, respectively) on the surface of the metal layer on the metal oxide layer side is 0.0 nm to 15.0 nm. The M _x O _y layer is a layer made of an oxide of metal M, and the M _x O _y layer may or may not be present.
The second laminate of the present invention is the same as the first laminate except that the Si layer of the first laminate is a metal M layer, and a natural oxide film having a specific thickness is present on the metal M layer. Even so, excellent current-voltage characteristics can be realized by forming a compound semiconductor with a wide bandgap on it.
Hereinafter, the first laminated body of the present invention and the second laminated body of the present invention may be collectively referred to as the laminated body of the present invention.

An embodiment of the laminate of the present invention is shown in FIGS. 1 and 2.
The laminate 1 shows an embodiment when the laminate of the present invention has a SiO ₂ layer. The SiO ₂ layer 20 is present on the Si layer 10 (substrate), and the metal oxide layer 30 is formed on the SiO ₂ layer 20. ing.
The laminate 2 shows an embodiment in the case where the SiO ₂ layer is not included, and the metal oxide layer 30 is formed on the Si layer 10 (substrate).
Although FIGS. 1 and 2 are drawings corresponding to the first laminated body of the present invention, they also correspond to the second laminated body of the present invention. Specifically, in FIGS. 1 and 2, a metal M layer is used instead of the Si layer 10, and an M _{x Oy} layer is used instead of the SiO ₂ layer 20. The same applies to FIGS. 3 to 9 described later.
Hereinafter, each layer used in the laminated body will be described.

(1-1) Si layer The Si layer is not particularly limited, and a silicon wafer may be used, or a material obtained by depositing Si on an appropriate base material such as glass by a sputtering method or a CVD method may be used. Good. It may also be doped.
The silicon wafer may have either a single crystal structure or a polycrystalline structure. As for the manufacturing method, a Czochralski method, a floating zone method, or the like can be used, and a conventionally known silicon wafer substrate can be used as it is.

Further, the silicon wafer has n-type, i-type, and p-type depending on the presence or absence of doping and the type, but the n-type or p-type having a small electric resistance is preferable in order to pass a current in the vertical direction. Conventionally known B, P, Sb and the like can be used as the dopant. In particular, when it is desired to reduce the resistance, As or red phosphorus may be used as a dopant.

Further, the thickness of the Si layer is not limited and is usually 200 to 1000 μm, but if it is desired to reduce the resistance in the vertical direction, it may be polished by the CMP method or the like. When the warp of the substrate becomes a problem, a TAIKO type structure in which the outer peripheral portion is left can be used. Polishing may be performed before laminating the metal oxides or afterwards.

The work function of the Si layer is preferably 3.9 eV to 5.0 eV, more preferably 4.0 eV to 4.5 eV. The work function of the Si layer is measured by an atmospheric photoelectron spectrometer (for example, RIKEN Keiki AC-3).

(1-2) Metal M layer The metal M constituting the metal M layer is not particularly limited as long as it is a metal different from the metal of the metal oxide constituting the metal oxide layer. The metal M may have, for example, high surface smoothness, and when the film thickness of the metal oxide laminated on the metal M exceeds 1 μm, a material having a coefficient of linear expansion of the metal oxide is preferable. Specifically, the metal M is preferably a metal having a coefficient of linear expansion in the range of 4 to 10 × 10 ^-6 K- ¹ , and the metal is one or more metals selected from Ti, Cr, Nb, Mo and Ta. Can be mentioned. The coefficient of linear expansion of the oxide used in the substrate of the present invention is, for example, in the range of 5 × 10 ^-6 to 8 × 10 ^-6 K ^-1 . Therefore, when heated in a post-process, warpage may occur if the coefficient of linear expansion is significantly different. Specifically, when the coefficient of linear expansion of the metal M is smaller than 4 × 10 ^-6 K ^{-1, the} compressive stress of the metal oxide layer is higher than that of the coefficient of linear expansion of the metal M is 10 × 10 ^-6 K ^-1 . When it is large, tensile stress is applied.
However, if the metal M is a metal having a low melting point or a metal having a high reactivity, it may be contaminated in the manufacturing process of the laminate or the like. Examples of such a metal include Ga, Hg, Cs, K, Na and the like.
The metal M is different from the metal of the metal oxide constituting the metal oxide layer, but "different" here means that the metal M and the metal of the metal oxide layer are completely different, for example, metal oxidation. When the metal of the material layer is an alloy composed of two or more kinds of metals, the metal M and the alloy may partially match.

(2-1) SiO ₂ layer The film thickness of the SiO ₂ layer is 0.0 nm or more and 15.0 nm or less, preferably 0.0 nm or more and 8.0 nm or less, and more preferably 0.0 nm or more and 4.0 nm or less. It is more preferably 0.0 nm or more and 2.5 nm or less, and particularly preferably 0.0 nm or more and 1.5 nm or less. It is preferable that the film thickness of the SiO ₂ layer is thin.
The film thickness of the SiO ₂ layer is measured by TEM (transmission electron microscope) in its cross section. When the SiO ₂ layer is a quadrangle, for example, the measurement points are the intersections of the diagonal lines and the midpoints of the intersections and each vertex, for a total of five visual fields, and the measurement points are measured at equal intervals. The average value of the total of 55 locations is taken as the thickness of the SiO ₂ layer.

Generally, a natural oxide film (SiO ₂ ) is present on the surface of a silicon wafer. Therefore, when a metal oxide is laminated on a Si substrate, a SiO ₂ film is usually present at the interface between the Si layer and the metal oxide layer, but when the thickness of the SiO ₂ film exceeds 15.0 nm, it is in the vertical direction. It acts as a clear electrical resistance component when an electric current is passed. In order to reduce the thickness of the SiO ₂ film to 15.0 nm or less, it is usually necessary to remove a predetermined amount of the natural oxide film in advance before laminating the metal oxide layer.

Examples of the method for removing the natural oxide film (SiO ₂ ) include reverse sputtering, dry etching, annealing under reduced pressure and a reducing atmosphere, and a method of immersing in a hydrofluoric acid solvent.
Further, when an annealing treatment is performed to ensure electrical bonding after laminating the metal oxide layer on the Si layer, the annealing temperature is preferably 300 ° C. or lower. When annealed at a temperature higher than 300 ° C., oxygen in the metal oxide layer reacts with Si to form a SiO ₂ film having a thickness of more than 15.0 nm.

(2-2) M _x O _y layer As in the case of a silicon wafer, a natural oxide film (M _x O _y ) exists on the surface of the metal M layer, and it is natural in advance before laminating the metal oxide layer. It is necessary to remove a predetermined amount of the oxide film.
The thickness of the natural oxide film, the removing method, the annealing treatment after laminating the metal oxide layer, and the like are the same as in the case of the SiO ₂ layer.

(3) Metal-Containing Layer In the laminate of the present invention, a metal-containing layer may be provided between the Si layer and the metal oxide layer. In this way, it becomes easier to control the thickness of the SiO ₂ layer to 0.0 nm or more and 15.0 nm or less. As in the case of the Si layer and the metal oxide layer, a metal-containing layer may be provided between the metal M layer and the metal oxide layer. It is easier to control the thickness of the M _x O _y layer below 15.0nm than 0.0 nm.
The thickness of the metal-containing layer is usually 5 to 100 nm.

Embodiments of the laminate provided with the metal-containing layer are shown in FIGS. 3 and 4.
In the laminated body 3, the SiO ₂ layer 20 exists on the Si layer 10, the metal-containing layer 25 is formed on the SiO ₂ layer 20, and the metal oxide layer 30 is formed on the metal-containing layer 25.
In the laminated body 4, the metal-containing layer 25 is formed on the Si layer 10, and the metal oxide layer 30 is formed on the metal-containing layer 25.

The material used for the metal-containing layer is not particularly limited as long as it is conductive. Here, since the appropriate material differs depending on whether Schottky connection or ohmic connection is used for the metal oxide layer, it will be described below.

(3-1) When the metal-containing layer is Schottky-connected to the metal oxide layer In order to make the Schottky connection to the metal oxide layer, a metal material having a work function of about 4.2 eV to 5.8 eV is required. Preferably, a metal material of 4.4 eV to 5.6 eV is more preferable. Specific examples thereof include Pt, Au, Ag, Cr, Cu, Mo, Ti, W, Ni, Pd and Ru. When there is a problem in adhesion and durability by itself, a conventionally known alloy may be used if necessary. For example, AgPdCu, AgNd, AgCe, MoW, MoTa, MoNi and the like are alloy materials having a high work function and excellent durability. Further, not limited to metals, oxide conductor thin films such as ITO, ZnO, SnO, and IZO (registered trademark) are also excellent as high work function electrodes. Furthermore, when an oxide dielectric thin film such as PbO, PtO, MoO ₃ , or TiO ₂ is formed in contact with a metal oxide at 5 nm or less, a good Schottky barrier can be realized without increasing the on-resistance in the forward direction. Can be done.

(3-2) When the metal-containing layer is ohmic-connected to the metal oxide layer On the other hand, in order to obtain ohmic characteristics for the metal oxide layer, the work function is usually 3.5 to 4.3 eV. A metal material of about 3.5 to 4.2 eV is preferable, and a metal material of 3.6 eV to 4.1 eV is more preferable. Examples thereof include metals such as Hf, In, Mg, Zn, Ti and Al, and alloy materials such as TiN, MgAg and AlLi. If the work function is less than 3.5 eV, it is often lacking in stability and care may be required. If the work function exceeds 4.2 eV, electron injection into the metal oxide layer is hindered, which may lead to Schottky junction. Further, since Ti has good adhesion, it is also suitable as an electron-injected metal. In addition to the above, when In or Zn is used as the metal-containing layer, the conductivity is maintained even when it reacts with oxygen in the metal oxide by heating, so that it is suitable as an ohmic electrode. For the same reason, oxide conductor thin films such as ITO, ZnO, SnO, and IZO (registered trademark) also retain conductivity and are therefore suitable as ohmic electrodes. However, since the work function of the oxide conductor thin film is often 4.4 eV or more, a material having a fermi level close to that of the electrically laminated oxide semiconductor is preferable. Specifically, the material composition constituting the oxide semiconductor preferably contains In ₂ O ₃ , ZnO, and SnO ₂ as main components. Oxide materials such as Ga ₂ O ₃ and Al ₂ O _{3 with} a wide bandgap form an ohmic bond with the oxide conductor thin film when the ratio is suppressed to 20 to 50% of the metal ratio constituting the oxide semiconductor. It will be easier.
By stacking the ohmic electrode on the metal oxide layer, a diode having good rectifying characteristics can be obtained.

The work function of the electrode is an important index indicating the ease of electron injection, but the adhesion to the metal oxide layer is also important. The above metals alone may cause migration or oxidation. For example, when Al is used, problems such as hillock are likely to occur, and thus it can be prevented by a conventionally known additive metal such as Nd or Ce. Further, when a small amount of Li is mixed with Al, the work function can be greatly reduced, which is suitable as an electron-injected metal for the wide-gap metal oxide of the present invention.
The work function is measured using an atmospheric photoelectron spectrometer (for example, AC-3 manufactured by RIKEN Keiki).

When the metal-containing layer is ohmic-bonded to the metal oxide layer, the annealing temperature may exceed 300 ° C. because the metal oxide does not come into direct contact with silicon or metal M. However, depending on the metal type of the metal-containing layer, unevenness is generated by heating, which causes a decrease in the dielectric breakdown electric field. Therefore, the annealing temperature is appropriately selected depending on the material.

(4) Metal Oxide Layer The metal oxide layer is a layer containing one or more metal oxides. Examples of the metal oxide include oxides of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga or Al.

(4-1) Atomic Composition The metal oxide constituting the metal oxide layer preferably satisfies the atomic ratios of the following formulas (1) to (3). With such a composition, a high withstand voltage and a low On resistance can be obtained.
0 ≤ x / (x + y + z) ≤ 0.5 (1)
0 ≤ y / (x + y + z) ≤ 0.8 (2)
0.2 ≤ z / (x + y + z) ≤ 1.0 (3)
(In the formula, x, y and z each represent the number of one or more atoms selected from the following elements.
x = In, Sn, Ge, Ti
y = Zn, Y, Sm, Ce, Nd
z = Ga, Al)

When z is less than 0.2, oxygen in the metal oxide is easily desorbed, which causes variation in electrical characteristics. If the concentration of x exceeds 0.5, the insulating property of the metal oxide becomes low when x is In or Sn, and there is a possibility that Schottky bonding may be difficult to obtain. When x is Ge or Ti, the insulating property of the metal oxide becomes high, which may cause heat generation due to ohm loss.
The composition of the metal oxide is measured by an ICP (Inductively Coupled Plasma) luminescence analyzer, XRF ((X-ray Fluorescence Analysis,)) or SIMS (Secondary Ion Mass Spectrometry).

The above composition ranges (1) and (3) are more preferably represented by the following formulas (1') and (3'), respectively.
0 ≤ x / (x + y + z) ≤ 0.25 (1')
0.3 ≤ z / (x + y + z) ≤ 1.0 (3')
(In the formula, x, y and z are the same as above.)

(4-2) Crystal structure, etc. The metal oxide constituting the metal oxide layer may be amorphous or crystalline, and the crystal may be fine crystal or single crystal, but the metal oxide is amorphous or fine. A crystalline structure is preferred. A single crystal may be used, but in order to convert the metal oxide into a single crystal, it is necessary to grow the crystal starting from the seed crystal or use a method such as MBE (molecular beam epitaxy) or PLD (pulse laser deposition). When crystals are grown on the surface of SiO ₂ or a metal surface, crystal defects are likely to occur, and these crystal defects may cause defects when used as a device that conducts electricity in the vertical direction. When crystal growth is performed on the surface of SiO ₂ or the surface of a metal, it is necessary to appropriately adjust the heating temperature, time, etc. so that the particle size does not become too large.

On the other hand, if it is amorphous, it does not exist as a crystal defect even if there are unbonded hands, so that it is possible to alleviate variations in electrical characteristics and significant deterioration of characteristics. Furthermore, unlike covalent bonds such as Si semiconductors, metal oxides have strong ionic bonds, so the levels formed by unbonded hands are close to those of conductive bands and fillers. Therefore, the metal oxide has a smaller difference in electrical characteristics such as mobility depending on the structure as compared with Si, SiC, and the like. By positively utilizing such properties of metal oxides, it is possible to provide a high current diode and a switching element having high withstand voltage and high reliability regardless of a single crystal with a high yield.

Here, "amorphous" means an electron beam when, for example, when the metal oxide layer is a quadrangle, a total of five points, the intersection of diagonal lines and the midpoint between the intersection and each vertex, are evaluated by electron diffraction. A diffraction image obtained with the diffraction spot size set to 80% of the film thickness does not allow a clear spot to be confirmed. In addition, "amorphous" includes the case where there is a partially crystallized or microcrystallized portion. When a partially crystallized part is irradiated with an electron beam, a diffraction image may be observed.
The "microcrystal structure" means that the size of the crystal grain size is submicron or less and there is no clear grain boundary.
"Polycrystal" means that the size of the crystal grain size exceeds the micron size and a clear grain boundary exists.

For example, the properties required for a diode are high-speed switching, high withstand voltage, and low On resistance, but these characteristics can be compatible with the laminate of the present invention. This is because the metal oxide used in the present invention originally has a wide bandgap and a high withstand voltage. In addition, it is suitable for high-speed switching because it tends to become n-type due to oxygen deficiency and it is difficult to form p-type.

Since it is necessary to increase the mobility in order to reduce the On resistance, it is preferable to crystallize it, but it is better to stop it to the extent that grain boundaries cannot be formed. Pore is often present at the grain boundaries, and polarization occurs when an electric field is applied, and this polarization may reduce the pressure resistance performance. When the withstand voltage is significantly reduced, it is preferable to use it as amorphous. When used as amorphous, the heat treatment conditions may be set, for example, 200 ° C. or lower and 1 hour or less, although it depends on the type of element forming the metal oxide layer. A stable amorphous state can be obtained by heating at a low temperature of 200 ° C. or lower.

The carrier concentration of the metal oxide layer at room temperature is preferably 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 , more preferably 2 × 10 ¹⁴ cm ^{-3 to} 5 × 10 ¹⁶ cm ^-3 . is there. Within this range, good diode characteristics can be exhibited. If the carrier concentration is less than 1 × 10 ¹⁴ cm ^-3 , the on-resistance becomes too high, causing heat generation during operation, which is not preferable. If the carrier concentration exceeds 1 × 10 ¹⁷ cm ^-3 , the resistance may become too low and the leakage current at the time of reverse bias may increase.

The carrier concentration is measured by CV evaluation.
In the CV evaluation, N (carrier concentration) is obtained from the slope of C- ² τsV using the following formula.
C = {qεN / 2 (φ−V)} ^1/2
Each symbol means the following.
C: Bonding capacity of metal and metal oxide
q: Charge element ε: Permittivity of metal oxide φ: Built-in potential due to bonding of metal and metal oxide V: Applied voltage

The metal oxide interface on the side in contact with any of the Si layer, the SiO ₂ layer, and the intermediate metal layer can be easily made to have ohmic characteristics by partially increasing the carrier concentration. The specific carrier concentration is preferably 1 × 10 ¹⁷ cm ^-3 to 1 × 10 ²² cm ^-3 or less. Examples of the method of increasing the carrier concentration include a method of increasing oxygen deficiency and a method of increasing the doping concentration. Metal M layer, M _x O _y layer, the side of the metal oxide interface in contact with one of the intermediate metal layer is the same.
Examples of the method for increasing the oxygen deficiency include a method for forming an oxide semiconductor in a state of lack of oxygen, a method for heating in a reducing atmosphere, and the like.
The method of increasing the doping concentration is a method of activating the dopant mainly by using a polycrystalline oxide semiconductor. For example, tetravalent elements such as Ti, Si, Ge, and Sn may be mixed in the target material from the beginning in the range of 0.1 to 10%, or mixed by ion doping and annealed.

The method for forming the metal oxide layer is not particularly limited, and a known method can be used. In particular, if you want to increase the film thickness to 1 μm or more, in addition to the sputtering method, you can use the doctor blade method, injection method, extrusion method, hot pressurization method, and other ceramic manufacturing methods, as well as the ion plating method, airsol deposition method, and other thick film methods. A conventionally known production method suitable for the above can be used.

The dielectric breakdown electric field of the metal oxide used in the present invention is usually 0.5 to 3.0 MV / cm, and has very excellent performance as compared with conventional silicon-based diodes.
For example, it is known that the theoretical dielectric breakdown electric field of β-Ga ₂ O _{3 of} a single crystal is 8.0 MV / cm or more (APEX5-2012-035502), but there are minute defects and voids. Then it drops significantly. This is because the presence of minute defects or voids in the bulk causes polarization when an electric field is applied, and dielectric breakdown is likely to occur from that point. When the oxide semiconductor used in the present invention has an amorphous or microcrystal structure, in principle, there are no minute defects or voids, so that it does not reach the theoretical value of a single crystal, but a large dielectric breakdown electric field equivalent to it is applied. You can get a good yield.

The film thickness of the metal oxide layer varies depending on the withstand voltage, application and purpose, and is preferably 0.2 μm to 1.2 μm at 60 V withstand voltage and 2 μm to 12 μm at 600 V withstand voltage.

(5) Surface metal layer When the interface of the metal oxide layer in contact with any of the Si layer, SiO ₂ layer, and intermediate metal layer is a shotkey connection, good rectification characteristics can be obtained by laminating an ohmic electrode on the metal oxide layer. A diode having can be obtained. The conditions such as materials for making an ohmic connection are the same as in (3-2) above. Further, in the case of Schottky connection, the conditions such as materials are the same as in (3-1) above.
The same applies to the case of the metal oxide layer in contact with any of the metal M layer, M _{x Oy} layer, and intermediate metal layer.

An embodiment in the case where the surface metal layer is provided is shown in FIG.
In the laminated body 5, the surface metal layer 40 is provided on the Si layer 10, the SiO ₂ layer 20, and the metal oxide layer 30. As for the structure of the laminated body other than the surface metal layer 40, various structures can be used as described above. For example, the SiO ₂ layer 20 may not be provided, and a metal-containing layer may be provided.

2. 2. Elements, Electric Circuits, etc. Elements including the laminate of the present invention can be used in various electric circuits, electric devices, vehicles, and the like. In particular, it is most suitable as a substrate for obtaining a diode or a vertical MOSFET. The diode using the laminate of the present invention can realize high withstand voltage and high speed switching. These will be described below.

(1) Schottky barrier diode A diode is divided into a Schottky barrier diode and a PN diode according to its application. Generally, Schottky barrier diodes using silicon are unipolar and are capable of high-speed switching but inferior in withstand voltage. On the contrary, the PN diode using silicon is bipolar, and although it is inferior in high-speed switching, it is excellent in withstand voltage.

The diode produced by using the laminate of the present invention is unipolar because it uses an oxide semiconductor, and has a wide band gap. Therefore, it is possible to achieve both high-speed switching and high withstand voltage, which were difficult to achieve with silicon.
In the case of SiC and GaN, it is difficult to efficiently obtain a single crystal with few defects, and there is also a problem in yield. In this respect, the diode using the laminate of the present invention has a high manufacturing yield and is industrially effective.

In order to further enhance the performance and stability of the diode, a conventionally known protective film, guard ring structure, mesa structure, field plate structure, and field stop structure can be used. Specifically, by passing the exposed portion of the metal oxide layer with SiO ₂ or the like, it is possible to suppress the formation of surface states and reduce the phenomenon of a decrease in forward current called current collapse. Further, by embedding the guard ring layer in the metal oxide layer, it is possible to suppress the avalanche breakdown, which may damage the diode, when the reverse surge voltage exceeds the protected voltage range.

When the metal oxide layer used in the laminate in the present invention is n-type, it is preferable to use a p-type or i-type semiconductor as the guard ring layer. The guard ring layer can relax the electric field concentration at the junction interface end when biased in the reverse direction, and can increase the withstand voltage.
As the p-type layer, Si doped with B, Al, Ga, In may be used as a conventionally known p-type semiconductor, or p-type oxidation represented by NiO, CuO, or CuTMO ₂ (TM: 3d transition metal). A physical semiconductor can be used.
Further, the guard ring may be designed in double or triple in order to enhance the effect. Here, the p-type semiconductor does not allow holes to flow and does not require high mobility.

When the interface of the metal oxide in contact with any of the Si layer, the SiO ₂ layer, and the intermediate metal layer is a Schottky connection, the guard ring layer may be formed first, and then the metal oxide layer may be laminated. When the interface of the metal oxide in contact with any of the Si layer, the SiO ₂ layer, and the intermediate metal layer is an ohmic connection, the metal oxide layer is first formed, etched in a guard ring shape, and then p-type or A type i semiconductor is formed. Next, after polishing the surface with CMP or the like, a surface metal layer to be an ohmic connection may be formed.
The same applies to the case of the metal oxide in contact with any of the metal M layer, M _{x Oy} layer, and intermediate metal layer.

These protective films and guard ring layers can be formed by conventionally known film forming methods such as vacuum processes such as sputtering, ion plating and PECVD, printing, coating thermal decomposition, mist CVD, and wet processes such as sol-gel. Further, with respect to the guard ring, an element such as Cu or Ni, which is p-type, may be ion-implanted into a desired region. An area mask may be used for the formation, or a conventionally known photolithography method can be used. As the patterning technique, conventionally known wet etching and dry etching can be used. In forming the protective film and the guard ring layer, an optimum process may be combined as appropriate depending on the processing accuracy and the material.

The embodiment when the protective film and / or the guard ring is provided is shown in FIGS. 6 to 8.
In the laminated body 6, a protective film 50 is provided on the metal oxide layer 30 and the surface metal layer 40 so as to cover them. In the laminated body 7, the guard ring 60 is embedded on the upper surface side of the metal oxide layer 30. Further, in the laminated body 8, the guard ring 60 is embedded on the lower surface side of the metal oxide layer 30.
In the laminated bodies 6 to 8, the configurations of the laminated bodies other than the protective film 50 or the guard ring 60 are as described above, and various configurations can be used.

In the Schottky barrier diode using the laminate of the present invention, in order to reduce the contact resistance of the Si layer, it is preferable to laminate the back electrode after removing the natural oxide film of Si by reverse sputtering or hydrofluoric acid. As a combination with good electrical contact, a laminate of Ti-Ni-Au, Ti-Ni-Ag or the like, a Si-doped Al electrode, or the like is used. Since the Schottky barrier diode obtained in this manner is laminated on a silicon wafer, it does not have high hardness and high brittleness unlike SiC. Therefore, it is possible to process with good yield by ordinary dicing technique.

(2) MPS (Merged Pin and Shotky) Diode The laminate of the present invention can be used for an MPS diode. The MPS diode is a diode that has both the energizing capacity of a Pin diode and the advantages of high-speed switching characteristics of a Schottky diode.
When the interface of the metal oxide in contact with any of the Si layer, the SiO ₂ layer, and the intermediate metal layer is a Schottky connection, the p layer or the i layer may be laminated and patterned first, and then the metal oxide may be laminated. .. Metal M layer, M _x O _y layer, a metal oxide in contact with any of the intermediate metal layer in the same manner.

FIG. 9 shows an embodiment when the laminate of the present invention is MPS.
In the laminated body 9, a plurality of p-type semiconductors 70 are formed on the SiO ₂ layer 20. The configuration of the laminate other than the p-type semiconductor 70 is as described above, and various configurations can be used.

When the interface of the metal oxide in contact with any of the Si layer, the SiO ₂ layer, and the intermediate metal layer is an ohmic connection, the metal oxide layer is first formed, the trench is dug, and then the p-type or i-type is formed. A semiconductor is formed. Next, after polishing the surface with CMP or the like, a surface metal layer to be an ohmic connection may be formed.

With such a configuration, it is possible to obtain a laminated body having a small On resistance and a large conventional dielectric breakdown electric field. This property has the effect of improving the withstand voltage region (200 to 600 V) of the Si Schottky barrier diode, which has been difficult to increase in pressure in the past.

FIG. 10 is a diagram showing an embodiment of a laminated body when the support substrate is made of metal M.
The laminate 10 is the same as the laminate 7 except that the Si layer 10 is a metal layer 12 made of Mo and the SiO ₂ layer 20 is an oxide layer 22 of Mo. Since Mo is close to the coefficient of linear expansion of the metal oxide, it is possible to suppress the generation of internal stress in the heating process after laminating the metal oxide. For example, when IGZO (33: 33: 33) is used as the metal oxide layer 30, the linear expansion coefficient of IGZO is 6.5 × 10 ^-6 / K, while the linear expansion coefficient of Mo is 5.1. It is close to × ^10-6 / K. Therefore, even if SiO ₂ is formed at a temperature of 300 ° C. or higher by using a CVD step as a protective film, it is possible to prevent the film from peeling off or cracking. On the other hand, when a Si wafer is used as the support substrate, the coefficient of linear expansion of Si is 2.8 × ^10-6 / K, which is less than half that of IGZO, and the metal oxide layer is peeled off or cracked. It's easy to do.

The laminate 11 of FIG. 11 is different from the laminate 7 except that the metal layer 14 and the metal oxide layer 24 constituting the metal layer 14 are laminated between the SiO ₂ layer 20 and the metal oxide layer 30. It is the same.
As shown in FIG. 11, when the metal oxide layer 30 is laminated on the Si wafer 10, it is better to sandwich the metal layer 14 as a buffer between them. This metal layer is a layer for relieving stress due to the difference in linear expansion coefficient between the support substrate and the metal oxide, and the thickness thereof is appropriately selected depending on the thickness and composition of the metal oxide layer. The thickness of the metal layer is preferably greater than or equal to the metal oxide layer.
Further, the metal used for the support substrate other than Si and the buffer layer is preferably a material having a coefficient of linear expansion larger than Si and smaller than metal oxide. Specifically, in addition to Mo, Ti, Cr, Nb, Ta and the like can be mentioned.
In the laminated body 11, the film thickness of the metal oxide layer 24 (both of which are natural oxide layers) constituting the SiO ₂ layer 20 and the metal layer 14 is preferably 0.0 nm to 15.0 nm, respectively.

12 and 13 are diagrams showing one embodiment of the method for manufacturing the laminated body 11 of FIG. 11, respectively.
In FIG. 12, a laminate is manufactured by joining a laminate formed on the metal layer 14 and a Si wafer. By manufacturing in this way, the Si process can be applied to the post-process, which is advantageous in manufacturing. FIG. 13 shows a case where the laminated body of the metal layer 14 and the metal oxide layer 30 and the Si layer 10 are first bonded, and then the surface metal layer 40, the protective layer 50, the guard ring 60, and the like are laminated.
Bonding techniques include conventionally known SOI and plasma. It should be noted that when dissimilar metals are bonded to each other, cracks and cracks are likely to occur due to the difference in the coefficient of thermal expansion, so it is necessary to ensure temperature uniformity during temperature rise and fall.

The device of the present invention preferably has non-linear electrical conductivity. Non-linear conductivity refers to conductivity that does not obey Ohm's law.

(3) Power MOSFET (Metal-Oxide-Semiconductor Field-Effective Transistor)
The laminate of the present invention can be used for a power MOSFET. The power MOSFET is an insulated gate type field effect transistor that controls the flow of carriers with an electric field via an oxide film. By using the laminate of the present invention, it is possible to obtain a unipolar device having electrons as carriers.

FIG. 14 shows an embodiment when the laminate of the present invention is used in a planar gate type power MOSFET.
FIG. 14 shows a cross-sectional view of a vertical MOSFET using a metal oxide semiconductor. An n-type Si (corresponding to the Si layer 10) is used as the support substrate, and an n-type metal oxide semiconductor (corresponding to the metal oxide layer 30) is connected via Ti, Ni, and In (corresponding to the metal-containing layer 25). It is laminated. The interface between the Si wafer and Ti may or may not have the SiO ₂ layer 20, but if it is present, it must be 15 nm or less.
Ti, Ni, and Au (back surface electrode 26) are laminated on the other surface of the n-type Si, and the layer is in contact with the drain electrode 100 (not shown).

In FIG. 14, the upper portion of the n-type metal oxide semiconductor is formed with recesses (grooves) by dry etching, and then the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration is laminated. Normally, a p-type semiconductor is used in this region (hereinafter referred to as a recess region), but if a wide-gap oxide semiconductor is used, the leak current is small even when the gate 80 is off, so the p-type is not essential.
The fermi level of the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration formed in the recess region is preferably lower than that of the oxide semiconductor used in the laminate of the present invention.

As the p-type semiconductor used in the recess region, conventionally known p-type semiconductor materials such as NiO, PdO, CuO, and boron-doped silicon can be used.
Further, an oxide semiconductor can be used as the n-type semiconductor having a low carrier concentration. Since this region forms a channel when the gate is On, it is preferable that the concentration of the transition metal that can be a scattering source is as small as possible.
Conventionally known low resistance wiring materials such as W, Ti, Mo, Al, and Cr can be used for the source electrode region 90 existing through the gate insulating film 110. Further, in order to suppress the contact resistance, it may be reduced with Ar plasma or the like before the film formation to increase the carrier concentration only in the contact portion.

Both the p-type region and the source electrode region are obtained by patterning a metal oxide layer by photolithography technology and forming it by a method such as magnetron sputtering or plasma CVD. The surface is appropriately smoothed by CMP treatment. An insulating film is laminated on the source electrode thus obtained and a laminate provided with a p-type or low carrier concentration n-type region, and patterned to obtain a gate insulating film.

The material constituting the insulating film is not particularly limited, and any material generally used can be arbitrarily selected as long as the effect of the present invention is not lost. For example, SiO ₂ , SiN _x , Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , MgO, ZrO ₂ , CeO ₂ , K ₂ O, Li ₂ O, Na ₂ O, Rb ₂ O, Sc ₂ O ₃ , Oxides and nitrides such as Y ₂ O ₃ , HfO ₂ , CaHfO ₃ , PbTi ₃ , BaTa ₂ O ₆ , SrTIO ₃ or AlN can be used.
As items required for the insulating film, it is important that the film thickness unevenness is small and that there are no pinholes that cause leakage. As a general gate insulating film, SiO ₂ , SiN _x , Al ₂ O _3, or the like is used.

Finally, the metal is sputtered and patterned into a desired shape to obtain a laminate with a source gate.

If a natural oxide film such as SiO ₂ is formed on the back surface side of the laminate serving as the drain electrode, the metal is laminated in the order of Ti / Ni / Au after being removed by hydrofluoric acid or reverse sputtering. Here, Ti serves as an adhesion layer, Ni serves as a diffusion prevention layer, and Au serves as a low resistance layer.
Since the vertical MOSFET obtained in this way uses a wide-gap oxide semiconductor for the withstand voltage layer, it has excellent withstand voltage, and can achieve both a withstand voltage of 600 V or more, which was difficult with Si, and high-speed switching. Further, since the channel resistance portion uses n-channel conduction by gate bias, the carrier is an electron having high mobility, and low on-resistance can be realized.

FIG. 15 shows an embodiment when the laminate of the present invention is used in a trench gate type power MOSFET.
FIG. 15 shows a cross-sectional view of a trench gate type power MOSFET using an oxide semiconductor. This structure can be miniaturized as compared with the planer structure, and the resistance of the channel can be reduced. It is also possible to increase the density of the trench to create a super junction structure.
In FIG. 15, the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration is formed not in the recess but on the n-type metal oxide semiconductor 30. Further, a source electrode 90 is formed on the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration, and a recess is provided through the source electrode 90 and the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration. The gate 80 is formed in the recess via the gate insulating film 110. Other than these configurations, it is the same as in FIG.

FIG. 16 shows an embodiment of the planar gate type power MOSFET using the laminate of the present invention in the case where a metal oxide is used in the drift region and polycrystalline silicon is used in the channel region.
FIG. 16 shows a power MOSFET that achieves both high withstand voltage and high-speed switching by using a metal oxide in the drift region and polycrystalline silicon in the channel region.

In FIG. 16, a highly doped n-type silicon wafer is used as a substrate (corresponding to the Si layer 10), and the surface is treated with dilute hydrofluoric acid or the like to remove a natural oxide film. Next, an n-type oxide semiconductor (corresponding to the metal oxide layer 30) is formed. When the n-type oxide semiconductor is crystallized and used, it is preferable to anneal it in the range of 150 to 1400 ° C. The appropriate range of annealing is appropriately determined depending on the constituent elements of the oxide semiconductor. If the annealing temperature exceeds 1400 ° C., silicon may melt. If the annealing temperature is lower than 150 ° C., crystallization may not proceed.

After the annealing is completed, amorphous silicon is formed on the n-type oxide semiconductor by a method such as PECVD, and patterning is performed. For patterning, after applying a resist, exposure and development are performed, and dry etching is performed using a halogen-based gas. After stripping the resist, it is polycrystallized using a technique such as laser annealing. Next, the SiO ₂ film 115 is formed by a method such as PECVD. Further, a metal electrode is formed on the metal electrode by sputtering or a vapor deposition method, and the metal electrode is patterned into the shape of the gate electrode 80. Conventionally known methods can be used for patterning both dry and wet, but refractory metals such as W, Cr, Mo, and Ta are preferable because activation annealing described later is performed.

Next, ion doping is performed on p-type Si through the gate electrode 80. Since ion doping is a cap method via a SiO ₂ film, which is an insulating film, it is advisable to confirm the control of the dose amount and its depth by simulation, etc. For example, acceleration of P, Sb, As, etc. by 50 to 500 keV. It is performed under the condition that the dose amount is 10 ¹³ to 10 ¹⁴ cm- ^{2 with} voltage. Since this ion doping uses a self-alignment technique using the gate electrode 80 as a mask, the process can be simplified, the gate capacitance can be reduced, and high-speed switching operation becomes possible.

After ion doping, activation annealing is performed. For activation annealing, high-speed annealing such as flash lamp annealing or laser annealing method is preferable in order to prevent deterioration of the electrode.
The higher the annealing temperature, the higher the activation rate, but the annealing temperature is appropriately selected within a range that does not cause deterioration of the electrodes. The annealing temperature is preferably 600 ° C to 1100 ° C, more preferably 700 to 1000 ° C. In this way, a part of the p-type Si (p region) 120 can be converted into an n-type n + region 130.

Subsequently, a contact hole is formed in a portion corresponding to the source electrode of SiO ₂ by using a photolithography, and finally the source electrode 90 is formed.
Ti, Ni, and Au (back surface electrode 26) are laminated on the high-doped n-type silicon wafer 10 as in FIGS. 14 and 15, and the layer is in contact with the drain electrode 100 (not shown). ..

(3) Module The MOSFET using the laminate of the present invention has a built-in body diode like the conventional Si-based MOSFET, but can also be used in combination with a freewheeling diode.
FIG. 17 is a diagram showing an embodiment of a module configured by combining the elements of the present invention. Both the power MOSFET and the freewheeling diode are composed of elements including the laminate of the present invention. This module includes a Si layer and a metal oxide layer for both the MOSFET and the freewheeling diode, and the thickness of the SiO ₂ layer on the surface of the Si layer on the metal oxide layer side is 0.0 nm to 15.0 nm. Since it is composed of a body, it can achieve both excellent current-voltage characteristics, that is, low on-resistance and high-speed switching.

Here, the freewheeling diode of FIG. 17 has different connection directions depending on whether the Si layer side has an ohmic connection (cathode) or a Schottky connection (anode). FIG. 18 is a diagram showing an embodiment in the case where the diode and the MOSFET are connected to the copper plate via the back metal and the solder in the module of FIG. 17, and the Si wafer side of the diode is connected to the collector of the MOSFET. .. When the Si side is ohmic contact, the Si side is connected to the copper plate of the module. Further, FIG. 19 shows an embodiment in which the diode and the MOSFET are connected to the copper plate via the back metal and the solder in the module of FIG. 17, and the oxide semiconductor side of the diode is connected to the collector of the MOSFET. It is a figure. When the Si side is Schottky connection, the surface metal layer side is connected to the copper plate of the module.
The module may be configured in combination with the diode of the present invention for the purpose of removing excess carriers of conventionally known Si-IGBTs, SiC-MOSFETs, and GaN-MOSFETs. Further, a conventionally known freewheeling diode may be used for the purpose of removing excess carriers of the MOSFET of the present invention.

In addition to the above, examples of electric circuits using the elements of the present invention include step-up / step-down chopper circuits, inverter / converter circuits, power supply circuits, switching regulators, etc., and examples of electrical equipment include mobile phones, personal computers, air conditioners, and refrigerators. , Receivers, lighting fixtures, electromagnetic cookers, etc., and examples of vehicles include bicycles, automobiles, railway vehicles, and the like. Further, the element of the present invention can also be used for an oxygen gas sensor, a photocatalyst, an ultraviolet sensor, an ultraviolet solar cell, a human body sensor, an ultraviolet diode, an ultraviolet laser and the like.

Hereinafter, examples of the present invention will be described with reference to the drawings as appropriate. The present invention is not limited to these examples.

Example 1
An n-type Si substrate (4 inches in diameter) having a resistivity of 0.02 Ω · cm and a slide glass were prepared. These were mounted on a sputtering apparatus (manufactured by ULVAC: CS-200) and first treated in the reverse sputtering mode for 15 seconds to etch a part of the natural oxide film. Next, as a metal oxide, Ga ₂ O ₃ was formed into a 9700 nm film under the conditions of RF 300 W and 19 hours. Further, this substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. for 1 hour.
The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus (FIG. 20). Further, as a result of confirming the electron diffraction, a halo pattern was observed, and it was confirmed that it was also amorphous (FIG. 21). When the film thickness of the natural oxide film was confirmed by TEM, it was 2.4 nm (Fig. 22).

Next, the above-mentioned substrate was set again in the sputtering apparatus together with the area mask, and then the electrodes were sputter-deposited in the order of Ti and Au.
The device (Si / SiO ₂ (natural oxide film) / Ga ₂ O ₃ / Ti / Au) thus obtained was evaluated using SCS-4200 manufactured by Toyo Corporation. The evaluation items were forward rising voltage (Vf), On current, dielectric breakdown electric field (Vbd), and n value. The forward rising voltage (Vf) is the applied voltage when the current density exceeds 10 mA / cm ² , the On current is the current density when the applied voltage is 3 V, and the insulation breakdown electric field (Vbd) is the leak current of 10 ^−. The voltage was taken when it exceeded ⁵ A / cm ² . The results are shown in Table 1.

Example 2
An n-type Si substrate (4 inches in diameter) having a resistivity of 0.02 Ω · cm and a slide glass were prepared. These were mounted on a sputtering apparatus (manufactured by ULVAC: CS-200) and first treated in the reverse sputtering mode for 5 minutes to etch a part of the natural oxide film. Next, as a metal oxide, Ga ₂ O ₃ was formed into a film at 3700 nm under the conditions of RF 300 W and 6 hours. Further, this substrate was taken out of the chamber and annealed in an electric furnace in air at 150 ° C. for 1 hour.
The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus (FIG. 20).

After the above substrate was again set in the sputtering apparatus together with the area mask, the electrodes were sputtered in the order of MgAg and Au.
The device (Si / SiO ₂ (natural oxide film) / Ga ₂ O ₃ / MgAg / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Corporation. The results are shown in Table 1.

Example 3
An n-type polycrystalline Si substrate (4 inches in diameter) having a resistivity of 0.02 Ω · cm and a slide glass were prepared. These were mounted on a sputtering apparatus (manufactured by ULVAC: CS-200), first processed in the reverse sputtering mode, and a part of the natural oxide film was etched. Next, as a metal oxide, Ga ₂ O ₃ was formed into a film of 200 nm under the conditions of RF 300 W and 18 minutes. Further, this substrate was taken out of the chamber and annealed in an electric furnace in air at 150 ° C. for 1 hour.
The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus.

After the above-mentioned substrate was set again in the sputtering apparatus together with the area mask, the electrodes were sputter-deposited in the order of Ti and Au.
The device (Si / SiO ₂ (natural oxide film) / Ga ₂ O ₃ / Ti / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Corporation. The results are shown in Table 1.

Example 4
An n-type polycrystalline Si substrate (4 inches in diameter) having a resistivity of 0.02 Ω · cm and a slide glass were prepared. These were mounted on a sputtering apparatus (manufactured by ULVAC: CS-200), first processed in the reverse sputtering mode, and the natural oxide film was etched. Next, as a metal oxide, IGO (In: Ga = 30: 70) was formed into a 1000 nm film under the conditions of RF 300 W and 90 minutes.
The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus.

After the above-mentioned substrate was set in the sputtering apparatus again together with the area mask, the electrodes were sputter-deposited in the order of AlNd and Au. This substrate was taken out of the chamber and annealed in an electric furnace at 200 ° C. for 1 hour.
The device (Si / SiO ₂ (natural oxide film) / IGO / AlNd / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Corporation. The results are shown in Table 1.

Example 5
An n-type high-doped single crystal Si substrate (diameter 4 inches) with a resistivity of 0.004 Ω · cm and a slide glass were prepared. These were mounted on a sputtering apparatus (manufactured by ULVAC: CS-200), first processed in the reverse sputtering mode, and a part of the natural oxide film was etched. Next, as a metal oxide, GZO (Ga: Zn = 70: 30) was formed into a film at 9700 nm under the conditions of RF100 W and 20 hours. Further, this substrate was taken out of the chamber and annealed in an electric furnace in air at 150 ° C. for 2 hours. As a result of confirming the structure of the element formed on the glass with an XRD apparatus, it was amorphous.

After the above-mentioned substrate was set again in the sputtering apparatus together with the area mask, the electrodes were sputter-deposited in the order of In and Au. This substrate was taken out of the chamber and annealed in an electric furnace at 200 ° C. for 1 hour.
The device (Si / SiO ₂ (natural oxide film) / GZO / In / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Corporation. The results are shown in Table 1.

Example 6
An n-type Si substrate (diameter 4 inches) having a resistivity of 0.02 Ω · cm was prepared. This Si wafer was mounted on a sputtering apparatus (manufactured by ULVAC: CS-200), and the natural oxide film was first etched in the reverse sputtering mode. Next, Mo was formed into a film of 15 nm, and Ga ₂ O ₃ was further formed into a film of 1000 nm. The substrate was removed from the chamber and annealed in an electric furnace in air at 150 ° C. for 1 hour.
Next, the remaining substrate was returned to the chamber again, an area mask having a desired pattern was set, and then the electrodes were sputter-deposited in the order of Ti and Au.
The device (Si / Mo / Ga ₂ O ₃ / Ti / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Corporation. The results are shown in Table 1.

Examples 7-14, Comparative Examples 1 and 2
Hereinafter, while changing the Si substrate, reverse sputtering conditions, metal-containing layer material, and metal oxide layer material as shown in Table 1, a laminate was produced in the same manner as in Example 6, and various characteristics were evaluated. The results are shown in Table 1. Further, the substrates of Examples 7 and 8 were subjected to TEM measurement. A cross-sectional view of the substrate is shown in FIG.
In Comparative Example 2, a SiC layer (Si: C (atomic ratio) = 50: 50) was provided instead of the metal oxide layer.

Examples 15 and 16, Comparative Examples 3 and 4
A laminate was produced in the same manner as in Example 1 while changing the substrate, reverse sputtering conditions, metal oxide layer material, etc. as shown in Table 1, and various characteristics were evaluated. The results are shown in Table 1. Specifically, "ion plating", which is a method for forming a metal oxide layer in Example 15 and Comparative Example 3, was carried out as follows. Ten IGZO tablets (φ20 × 5t) of In: Ga: Zn = 33: 33: 33 as raw materials were set in the ion plating device SIP-800 of Showa Vacuum Co., Ltd., and after vacuuming, the power of the electron beam was 10 kW. Then, an IGZO film having a thickness of 5000 nm was obtained with an oxygen partial pressure of 50%.
Further, in Example 15 and Comparative Example 3, a Mo substrate was used as the substrate. Therefore, the natural oxide film back-etched in Example 15 and Comparative Example 3 is not a SiO ₂ layer but a MoOx layer.

Example 17
A Schottky barrier diode was manufactured by the process shown in FIG. Specifically, an n-type Si substrate (diameter 4 inches) having a resistivity of 0.02 Ω · cm was prepared. This Si wafer was placed in a thermal oxidation furnace to form a 100 nm thermal oxide film. Next, after applying the resist, exposure, development, and etching were performed using a photomask to form contact holes. Further, 10 nm of each of Pd and PdO was formed in this order by a sputtering method using a Pd target. Then, the Pd / PdO laminated portion on SiO ₂ was etched with aqua regia so as to remain concentrically to form a guard ring. Further, IGZO, which is an oxide semiconductor, was formed on the film at 200 nm to form a pressure-resistant layer, and Mo was formed on the film, and finally annealed in air at 300 ° C. for 1 hour. The thermal oxide film existing on the back surface of the Si wafer was removed by covering the front surface with a protective film and then etching with dilute hydrofluoric acid. Then, a film was formed in the order of Ti, Ni, and Au.
The Si wafer side of the obtained laminate was Schottky-bonded to obtain a Schottky barrier diode with a guard ring and a back electrode.
The film thickness of SiO ₂ at the interface between Si and Pd of the Schottky barrier diode thus obtained was evaluated and found to be 0.2 nm. The contact hole is circular, and a total of 5 points are observed at the center of the circle and the midpoint of each apex of the square inscribed in the circle, and the visual field is measured at equal intervals of 10 equal parts. The average value of the locations was taken as the thickness of the SiO ₂ layer.

Example 18
A Ti plate having a film thickness of 500 μm and a diameter of 4 inches φ was prepared as a support. In was formed into a 50 nm film on this Ti wafer. Next, IGZO (In: Ga: Zn = 40: 40: 20 at%) as an oxide semiconductor was formed into a 4 μm film by a sputtering method. Next, a SiO ₂ film was formed into a 100 nm film using a plasma CVD method. A resist was applied to the SiO ₂ / IGZO / In / Ti laminate, exposed using a photomask, developed, and then dry etching was performed to form contact holes in a part of SiO ₂ . CF ₄ was used as the etching gas.
Subsequently, Pd was laminated at 100 nm as a shot key electrode, and the surrounding Pd layer was polished until the SiO ₂ surface appeared by CMP. The back surface of the diode obtained in this manner on the Ti substrate side and the n-type Si substrate (diameter 4 inches) were set in a room temperature wafer bonding apparatus and bonded.
The obtained Schottky diode undergoes a process of exceeding 300 ° C. by plasma CVD on the way, but uses Ti close to the linear expansion coefficient of indium gallium zinc oxide (IGZO) as a support, and warpage and cracks occur. Was not recognized. When the film thickness of TiO ₂ existing at the interface between Ti and IGZO was measured by the same evaluation method as in Example 17, it was 0.5 nm.
Further, by laminating Ti and Si, the conventional Si-based Schottky diode process can be used as it is in the post-processes such as dicing, soldering, and aluminum wire bonding, which is advantageous in production.

The device including the laminate of the present invention can be used as a power device such as a Schottky barrier diode or a MOSFET or a module in which they are combined. Specifically, it can be used for power conversion circuits such as inverters and converters, power supply circuits, and electric circuits using them, such as power conditioners, IPMs, electrical equipment, and vehicles. Furthermore, it can also be used for oxygen gas sensors, photocatalysts, ultraviolet sensors, ultraviolet solar cells, human body sensors, ultraviolet diodes, ultraviolet lasers and the like.

Although some embodiments and / or embodiments of the present invention have been described above in detail, those skilled in the art will be able to demonstrate these embodiments and / or embodiments without substantial departure from the novel teachings and effects of the present invention. It is easy to make many changes to the examples. Therefore, many of these modifications are within the scope of the invention.
All the contents of the Japanese application specification, which is the basis of the priority of Paris in the present application, are incorporated herein by reference.

Claims (14)

The thickness of the SiO ₂ layer on the surface of the Si layer on the side of the metal oxide layer, which includes the Si layer and the metal oxide layer, is 0.0 nm to 15.0 nm, and the metal oxide layer is In, A Schottky barrier diode containing an oxide of one or more metals selected from the group consisting of Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga and Al. The Schottky barrier diode according to claim 1, wherein the film thickness of the SiO ₂ layer is 0.1 nm to 15.0 nm. The Schottky barrier diode according to claim 1 or 2, which includes a metal-containing layer between the SiO ₂ layer and the metal oxide layer. The Schottky barrier diode according to claim 3, wherein the work function of the metal-containing layer is 3.5 eV to 5.8 eV. The Schottky barrier diode according to any one of claims 1 to 4, wherein the metal oxide layer has an amorphous or microcrystalline structure. The Schottky barrier diode according to any one of claims 1 to 5, wherein the composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3).
0 ≤ x / (x + y + z) ≤ 0.5 (1)
0 ≤ y / (x + y + z) ≤ 0.8 (2)
0.2 ≤ z / (x + y + z) ≤ 1.0 (3)
(In the formula, x, y and z each represent the number of one or more atoms selected from the following elements.
x = In, Sn, Ge, Ti
y = Zn, Y, Sm, Ce, Nd
z = Ga, Al) The Schottky barrier diode according to any one of claims 1 to 6, wherein the carrier concentration of the metal oxide layer is 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 . The Schottky barrier diode according to any one of claims 1 to 7, wherein the work function of the Si layer is 3.9 eV to 5.0 eV. Includes metal layer and metal oxide layer
The metal layer is made of a metal M different from the metal of the metal oxide constituting the metal oxide layer.
Wherein _M X _{O Y} layer on the surface of the metal oxide layer side of the metal layer (x and y are each an integer) is the thickness of 0.0Nm～15.0Nm, the metal oxide layer, In, A Schottky barrier diode containing an oxide of one or more metals selected from the group consisting of Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga and Al. Wherein _M X _O film thickness of the _Y layer as claimed in claim 9 is a 2nm~15.0nm Schottky barrier diode. The Schottky barrier diode according to claim 9 or 10, wherein the composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3).
0 ≤ x / (x + y + z) ≤ 0.5 (1)
0 ≤ y / (x + y + z) ≤ 0.8 (2)
0.2 ≤ z / (x + y + z) ≤ 1.0 (3)
(In the formula, x, y and z each represent the number of one or more atoms selected from the following elements.
x = In, Sn, Ge, Ti
y = Zn, Y, Sm, Ce, Nd
z = Ga, Al) The Schottky barrier diode according to claim 1 to 11 , which has non-linear electrical conductivity. An electric circuit or sensor comprising the Schottky barrier diode according to claims 1-12 . An electric device or vehicle including the Schottky barrier diode according to claims 1 to 12 .