WO2016075927A1 - Novel laminate - Google Patents

Novel laminate Download PDF

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Publication number
WO2016075927A1
WO2016075927A1 PCT/JP2015/005605 JP2015005605W WO2016075927A1 WO 2016075927 A1 WO2016075927 A1 WO 2016075927A1 JP 2015005605 W JP2015005605 W JP 2015005605W WO 2016075927 A1 WO2016075927 A1 WO 2016075927A1
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Prior art keywords
layer
metal
metal oxide
laminate
oxide layer
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PCT/JP2015/005605
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French (fr)
Japanese (ja)
Inventor
重和 笘井
絵美 川嶋
紘美 早坂
義弘 上岡
雅敏 柴田
矢野　公規
井上　一吉
隆司 関谷
勇輝 霍間
基浩 竹嶋
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出光興産株式会社
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Priority to JP2016558887A priority Critical patent/JP6803232B2/en
Publication of WO2016075927A1 publication Critical patent/WO2016075927A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a laminate, an element including the laminate, an electric circuit including the element, an electric appliance, and a vehicle.
  • SiC or GaN is epitaxially grown on an inexpensive Si wafer substrate
  • Patent Documents 1 to 3 the crystal structure suitable as a power semiconductor is 4H—SiC.
  • the lattice mismatch is large, it is extremely difficult to grow epitaxially on Si.
  • 3C—SiC it can be epitaxially grown by performing fine processing on the Si wafer or by using the Si (211) plane, but it has been difficult to obtain a thick film that can be applied to a power device.
  • GaN is not as high as SiC in terms of mismatch between Si and lattice, crystal growth is difficult unless a buffer layer such as AlN is used.
  • a sapphire substrate with a close lattice constant is a promising candidate, but it cannot flow in the vertical direction and cannot be used for large current applications. Therefore, in order to use a conductive substrate such as Si, it is necessary to go through a process of laminating a buffer layer on the substrate and further growing a crystal of GaN. However, even with this, it was difficult to obtain perfect crystals.
  • the present invention has been made in view of such problems, and has excellent current-voltage characteristics by controlling a natural oxide film to a specific thickness or less and forming a metal oxide having a wide band gap thereon. It aims at providing the laminated body which exhibits.
  • a laminate comprising a Si layer and a metal oxide layer, wherein the SiO 2 layer on the surface of the Si layer on the metal oxide layer side has a thickness of 0.0 nm to 15.0 nm.
  • the laminate according to 1 comprising a metal-containing layer between the Si layer and the metal oxide layer. 3.
  • the laminate according to 1 or 2 wherein the metal oxide layer has an amorphous or microcrystalline structure. 4).
  • 4. The laminate according to any one of 1 to 3, wherein the composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3).
  • x, y and z each represent the number of one or more atoms selected from the following elements.
  • the metal oxide layer has a carrier concentration of 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 . 6).
  • the metal layer is made of a metal M different from the metal of the metal oxide constituting the metal oxide layer;
  • a laminate in which the M X O Y layer (x and y are integers) on the surface of the metal layer on the metal oxide layer side has a thickness of 0.0 nm to 15.0 nm. 9.
  • a laminate capable of exhibiting excellent current-voltage characteristics can be provided.
  • the natural oxide film By controlling the natural oxide film to a specific thickness or less and forming a metal oxide having a wide band gap thereon, excellent current-voltage characteristics can be exhibited.
  • the metal oxide can be formed by a method that is inexpensive and excellent in mass productivity, the productivity can be significantly improved as compared with the conventional case.
  • It is a diagram showing an embodiment of the laminate of the present invention (Si layer / SiO 2 layer / metal oxide layer). It is a figure which shows one Embodiment (Si layer / metal oxide layer) of the laminated body of this invention. It is a diagram showing an embodiment of the laminate of the present invention (Si layer / SiO 2 layer / intermediate metal layer (metal containing layer) / metal oxide layer). It is a figure which shows one Embodiment (Si layer / intermediate metal layer / metal oxide layer) of the laminated body of this invention. It is a diagram showing an embodiment (Si layer / SiO 2 layer / metal oxide layer / upper metal (surface metal layer)) of the laminate of the present invention.
  • FIG. 1 It is a diagram showing an embodiment of the laminate of the present invention (Si layer / SiO 2 layer / metal oxide layer / upper metal / protective film).
  • the laminate of the present invention is a diagram showing a. Is a diagram showing an embodiment (Si layer / SiO 2 layer / metal oxide layer (guard ring embedded) / upper metal / protective film on the lower electrode side) of the laminate of the present invention. It is a figure which shows one Embodiment (MPS diode) of the laminated body of this invention.
  • FIG. 1 shows an embodiment of a laminate of the present invention (Si layer / SiO 2 layer / metal M layer / M x O y layer / metal oxide layer (guard ring embedded on the upper electrode side) / upper metal / protective film).
  • FIG. It is a figure which shows one Embodiment of the manufacturing method of the laminated body of this invention. It is a figure which shows one Embodiment of the manufacturing method of the laminated body of this invention.
  • FIG. 18 is a diagram showing an embodiment in which the diode and the MOSFET in the module of FIG.
  • FIG. 17 are connected to the copper plate via the back metal and solder, and the Si wafer side of the diode is connected to the collector of the MOSFET.
  • FIG. 18 is a diagram showing an embodiment in which a diode and a MOSFET are connected to a copper plate via a back metal and solder in the module of FIG. 17, and the oxide semiconductor side of the diode is connected to a collector of the MOSFET.
  • 4 is an electron diffraction image of a 9700 nm-thick Ga 2 O 3 film obtained in Example 1.
  • FIG. 2 is a TEM image of the SiO 2 portion at the Si layer interface of the laminate obtained in Examples 1, 7, and 8.
  • FIG. It is a figure which shows a manufacturing process of the Schottky barrier diode manufactured in Example 15.
  • the 1st laminated body of this invention contains Si layer and an oxide metal layer.
  • the film thickness of the SiO 2 layer on the surface of the Si layer on the metal oxide layer side is 0.0 nm to 15.0 nm. That is, the SiO 2 layer may or may not exist. Even if a natural oxide film having a specific thickness is present on an inexpensive Si substrate, the first laminate of the present invention has excellent current-voltage by forming a compound semiconductor having a wide band gap on the natural oxide film. The characteristics can be realized.
  • the second laminate of the present invention includes a metal layer and a metal oxide layer.
  • the metal layer is made of a metal M different from the metal of the metal oxide constituting the metal oxide layer.
  • the thickness of the M x O y layer (x and y are integers) on the surface of the metal layer on the metal oxide layer side is 0.0 nm to 15.0 nm.
  • the M x O y layer is a layer made of an oxide of metal M, and the M x O y layer may or may not exist.
  • the second laminate of the present invention is the same as the first laminate except that the Si layer of the first laminate is a metal M layer, and a natural oxide film having a specific thickness exists on the metal M layer. Even so, an excellent current-voltage characteristic can be realized by forming a compound semiconductor with a wide band gap on it.
  • the first laminate of the present invention and the second laminate of the present invention may be collectively referred to as the laminate of the present invention.
  • the laminated body 1 shows an embodiment in which the laminated body of the present invention has an SiO 2 layer.
  • the SiO 2 layer 20 exists on the Si layer 10 (substrate), and the metal oxide layer 30 is formed thereon.
  • the laminated body 2 shows an embodiment in which an SiO 2 layer is not included, and a metal oxide layer 30 is formed on the Si layer 10 (substrate).
  • 1 and 2 are drawings corresponding to the first laminate of the present invention, but also correspond to the second laminate of the present invention. Specifically, in FIGS. 1 and 2, a metal M layer is used instead of the Si layer 10, and an M x O y layer is used instead of the SiO 2 layer 20. The same applies to FIGS. 3 to 9 described later.
  • each layer used for a laminated body is demonstrated.
  • the Si layer is not particularly limited, and a silicon wafer may be used, or a Si film formed on a suitable base material such as glass by sputtering or CVD. Good. Moreover, it may be doped.
  • the silicon wafer may have either a single crystal structure or a polycrystalline structure.
  • a Czochralski method, a floating zone method, or the like can be used, and a conventionally known silicon wafer substrate can be used as it is.
  • n-type, i-type, and p-type silicon wafers depending on the presence / absence and type of doping
  • n-type or p-type with low electrical resistance is preferable for flowing a current in the vertical direction.
  • Conventionally known B, P, Sb and the like can be used as the dopant.
  • As or red phosphorus may be used as a dopant.
  • the thickness of the Si layer is not limited and is usually 200 to 1000 ⁇ m. However, if the resistance in the vertical direction is to be lowered, it may be polished by a CMP method or the like. When warping of the substrate becomes a problem, a TAIKO type structure that leaves the outer peripheral portion can be used. Polishing may be performed before or after the metal oxide is laminated.
  • the work function of the Si layer is preferably 3.9 eV to 5.0 eV, and more preferably 4.0 eV to 4.5 eV.
  • the work function of the Si layer is measured by an atmospheric photoelectron spectrometer (for example, Riken Keiki AC-3).
  • the metal M constituting the metal M layer is not particularly limited as long as it is a metal different from the metal oxide metal constituting the metal oxide layer.
  • the metal M may have high surface smoothness, and when the thickness of the metal oxide layered thereon exceeds 1 ⁇ m, a material close to the linear expansion coefficient of the metal oxide is preferable.
  • the metal M is preferably a metal having a linear expansion coefficient in the range of 4 to 10 ⁇ 10 ⁇ 6 K ⁇ 1 , and the metal is one or more metals selected from Ti, Cr, Nb, Mo, and Ta. Is mentioned.
  • the linear expansion coefficient of the oxide used for the substrate of the present invention is, for example, in the range of 5 ⁇ 10 ⁇ 6 to 8 ⁇ 10 ⁇ 6 K ⁇ 1 . For this reason, when heated in a subsequent process, warping may occur if the linear expansion coefficients differ greatly. Specifically, when the linear expansion coefficient of the metal M is smaller than 4 ⁇ 10 ⁇ 6 K ⁇ 1, the metal oxide layer has a compressive stress, and the linear expansion coefficient of the metal M is 10 ⁇ 10 ⁇ 6 K ⁇ 1 . When it is too large, tensile stress is applied. However, when the metal M is a low-melting-point metal or a highly reactive metal, there is a risk of contamination in the manufacturing process of the laminate.
  • Examples of such a metal include Ga, Hg, Cs, K, and Na.
  • the metal M is different from the metal of the metal oxide composing the metal oxide layer, but “different” here means that the metal M and the metal of the metal oxide layer are completely different.
  • the metal of the physical layer is an alloy composed of two or more metals, the metal M and the alloy may partially match.
  • the thickness of the SiO 2 layer is from 0.0 nm to 15.0 nm, preferably from 0.0 nm to 8.0 nm, more preferably from 0.0 nm to 4.0 nm. More preferably, it is 0.0 nm or more and 2.5 nm or less, and particularly preferably 0.0 nm or more and 1.5 nm or less. A thinner SiO 2 layer is preferable.
  • the film thickness of the SiO 2 layer is measured by TEM (transmission electron microscope).
  • Measurement points in the case of the SiO 2 layer, for example a square, a diagonal line of intersection, the intersection and the field of five points of the midpoint of each vertex observed, measured at the point of 10 equally dividing its field of view at regular intervals
  • the average value of 55 places in total is the film thickness of the SiO 2 layer.
  • a natural oxide film exists on the surface of a silicon wafer. Therefore, when a metal oxide is laminated on a Si substrate, an SiO 2 film usually exists at the interface between the Si layer and the metal oxide layer. However, when the thickness of the SiO 2 film exceeds 15.0 nm, When current is passed, it acts as a clear electric resistance component. To the thickness of the SiO 2 film below 15.0nm usually before stacking the metal oxide layer, it is necessary to preliminarily remove the natural oxide film a predetermined amount.
  • Examples of the method for removing the natural oxide film (SiO 2 ) include reverse sputtering, dry etching, annealing under reduced pressure / reducing atmosphere, and a method of immersing in a hydrofluoric acid solvent.
  • the annealing temperature is preferably 300 ° C. or lower.
  • oxygen in the metal oxide layer and Si may react to generate a SiO 2 film exceeding 15.0 nm.
  • a natural oxide film (M x O y ) is present on the surface of the metal M layer. It is necessary to remove a predetermined amount of the oxide film.
  • the thickness of the natural oxide film, the removal method, the annealing treatment after laminating the metal oxide layer, etc. are the same as in the case of the SiO 2 layer.
  • a metal-containing layer may be provided between the Si layer and the metal oxide layer. In this way, it becomes easier to control the thickness of the SiO 2 layer to 0.0 nm or more and 15.0 nm or less.
  • a metal-containing layer may be provided between the metal M layer and the metal oxide layer. It becomes easier to control the thickness of the M x O y layer to 0.0 nm or more and 15.0 nm or less.
  • the thickness of the metal-containing layer is usually 5 to 100 nm.
  • the SiO 2 layer 20 exists on the Si layer 10
  • the metal-containing layer 25 is formed thereon
  • the metal oxide layer 30 is formed thereon.
  • a metal-containing layer 25 is formed on the Si layer 10
  • a metal oxide layer 30 is formed thereon.
  • the material used for the metal-containing layer is not particularly limited as long as it has conductivity.
  • an appropriate material differs depending on whether it is a Schottky connection or an ohmic connection to the metal oxide layer, a description will be given below.
  • a metal material having a work function of about 4.2 eV to 5.8 eV is used.
  • a metal material of 4.4 eV to 5.6 eV is more preferable.
  • Pt, Au, Ag, Cr, Cu, Mo, Ti, W, Ni, Pd, Ru, etc. are mentioned.
  • a conventionally known alloy may be used as necessary.
  • AgPdCu, AgNd, AgCe, MoW, MoTa, MoNi, etc. are alloy materials having a high work function and excellent durability.
  • oxide conductor thin films such as ITO, ZnO, SnO, and IZO (registered trademark) are also excellent as high work function electrodes.
  • oxide dielectric thin film such as PbO, PtO, MoO 3 , or TiO 2 is formed in contact with a metal oxide at 5 nm or less, a good Schottky barrier can be realized without increasing the on-resistance in the forward direction. Can do.
  • the work function is usually 3.5 to 4.3 eV, A metal material of about 3.5 to 4.2 eV is preferable, and a metal material of 3.6 eV to 4.1 eV is more preferable. Examples thereof include metals such as Hf, In, Mg, Zn, Ti, and Al, and alloy materials such as TiN, MgAg, and AlLi.
  • the work function is less than 3.5 eV, stability is often lacking, and attention may be required.
  • the work function of the oxide conductor thin film is greater than or equal to 4.4 eV
  • a material having a Fermi level close to that of an electrically stacked oxide semiconductor is preferable.
  • the material composition of the oxide semiconductor is preferably mainly composed of In 2 O 3 , ZnO, and SnO 2 .
  • an oxide material such as Ga 2 O 3 or Al 2 O 3 having a wide band gap is suppressed to 20 to 50% with respect to the metal ratio of the oxide semiconductor, an ohmic junction is formed with the oxide conductor thin film. It becomes easy.
  • an ohmic electrode is stacked on the metal oxide layer, a diode having good rectification characteristics can be obtained.
  • the work function of the electrode is an important index indicating the ease of electron injection, but the adhesion with the metal oxide layer is also important.
  • the above metal alone may cause migration or oxidation.
  • defects such as hillocks are likely to occur, and can be prevented by conventionally known additive metals such as Nd and Ce.
  • the work function can be greatly lowered, which is suitable as the electron-injecting metal of the wide gap metal oxide of the present invention.
  • the work function is measured using an atmospheric photoelectron spectrometer (for example, AC-3 manufactured by Riken Keiki Co., Ltd.).
  • the annealing temperature may exceed 300 ° C. because the metal oxide is not in direct contact with silicon or the metal M.
  • the annealing temperature is appropriately selected depending on the material.
  • Metal oxide layer A metal oxide layer is a layer containing 1 or 2 or more metal oxides.
  • the metal oxide include oxides of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, or Al.
  • the composition of the metal oxide is measured by an ICP (Inductively Coupled Plasma) emission analyzer, XRF ((X-ray Fluorescence Analysis,) or SIMS (Secondary Ion Mass Spectrometry).
  • ICP Inductively Coupled Plasma
  • XRF X-ray Fluorescence Analysis
  • SIMS Secondary Ion Mass Spectrometry
  • composition ranges (1) and (3) are more preferably represented by the following formulas (1 ′) and (3 ′), respectively. 0 ⁇ x / (x + y + z) ⁇ 0.25 (1 ′) 0.3 ⁇ z / (x + y + z) ⁇ 1.0 (3 ′) (Wherein x, y and z are the same as above)
  • the metal oxide constituting the metal oxide layer may be amorphous or crystalline, and the crystal may be microcrystalline or single crystal, but the metal oxide may be amorphous or microcrystalline.
  • a crystal structure is preferred.
  • a single crystal may be used, in order to convert a metal oxide into a single crystal, it is necessary to grow a crystal starting from a seed crystal, or to use a method such as MBE (molecular beam epitaxy) or PLD (pulse laser deposition).
  • MBE mo beam epitaxy
  • PLD pulse laser deposition
  • the metal oxide has strong ionic bonding properties unlike covalent bonds such as Si semiconductors, the levels generated by dangling bonds are close to conductive bands and filled bodies. Accordingly, the metal oxide has a smaller difference in electrical characteristics such as mobility depending on the structure as compared with Si, SiC, and the like. If such a property of the metal oxide is positively used, a high-current diode and a switching element with high breakdown voltage and high reliability can be provided with a high yield regardless of a single crystal.
  • amorphous means that when the metal oxide layer is, for example, a quadrangle, an electron beam diffraction is performed when a total of five points of the intersection of the diagonal lines and the intermediate point between the intersection and each vertex are evaluated by electron beam diffraction. This means that a clear spot cannot be confirmed in a diffraction image obtained by setting the diffraction spot size to 80% of the film thickness.
  • amorphous includes a case where a part is crystallized or microcrystallized. When a partially crystallized portion is irradiated with an electron beam, a diffraction image may be observed.
  • Microcrystalline structure refers to a crystal grain size that is submicron or smaller and has no clear grain boundaries.
  • Polycrystalline refers to a crystal grain size exceeding micron size and having clear grain boundaries.
  • the properties required for a diode are high-speed switching, high breakdown voltage, and low On resistance, but these characteristics can be achieved by using the laminate of the present invention.
  • the metal oxide used in the present invention originally has a wide band gap and a high breakdown voltage.
  • it tends to be n-type due to oxygen vacancies and is difficult to form p-type, which is suitable for high-speed switching.
  • the heat treatment conditions may be set to, for example, 200 ° C. or less and within 1 hour, although depending on the type of element forming the metal oxide layer. A stable amorphous state can be obtained by heating at a low temperature of 200 ° C. or lower.
  • the carrier concentration of the metal oxide layer at room temperature is preferably 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 , more preferably 2 ⁇ 10 14 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 . is there. If it is this range, a favorable diode characteristic can be shown.
  • the carrier concentration is less than 1 ⁇ 10 14 cm ⁇ 3 , the on-resistance becomes too high, and heat is generated during operation, which is not preferable.
  • the carrier concentration exceeds 1 ⁇ 10 17 cm ⁇ 3 , the resistance becomes too low, and the leakage current at the time of reverse bias may increase.
  • the carrier concentration is measured by CV evaluation.
  • N carrier concentration
  • C ⁇ q ⁇ N / 2 ( ⁇ V) ⁇ 1/2
  • C ⁇ q ⁇ N / 2 ( ⁇ V) ⁇ 1/2
  • the metal oxide interface on the side in contact with any one of the Si layer, the SiO 2 layer, and the intermediate metal layer is likely to have ohmic characteristics by partially increasing the carrier concentration.
  • the specific carrier concentration is preferably 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 22 cm ⁇ 3 or less.
  • the method for increasing the carrier concentration include a method for increasing oxygen vacancies and a method for increasing the doping concentration.
  • the metal oxide interface on the side in contact with any of the metal M layer, M x O y layer, and intermediate metal layer As a method for increasing oxygen vacancies, a method of forming a film in a state where oxygen is insufficient when forming an oxide semiconductor, a method of heating in a reducing atmosphere, and the like can be given.
  • the method of increasing the doping concentration is a method of activating the dopant mainly using a polycrystalline oxide semiconductor.
  • a tetravalent element such as Ti, Si, Ge, or Sn may be mixed into the target material from the beginning in the range of 0.1 to 10%, or may be mixed by ion doping and annealed.
  • the method for forming the metal oxide layer is not particularly limited, and a known method can be used.
  • a known method can be used.
  • ceramic methods such as doctor blade method, injection method, extrusion method, hot pressing method, ion plating method, aerosol deposition method, etc.
  • a conventionally known production method suitable for the above can be used.
  • the dielectric breakdown electric field of the metal oxide used in the present invention is usually 0.5 to 3.0 MV / cm, and has very excellent performance as compared with a conventional silicon diode.
  • single-crystal ⁇ -Ga 2 O 3 is known to have a theoretical breakdown electric field of 8.0 MV / cm or more (APEX5-2012-035502), but there are minute defects, voids, etc. Then it is greatly reduced. This is because if there are minute defects or voids in the bulk, polarization occurs when an electric field is applied, and dielectric breakdown is likely to start from there.
  • the oxide semiconductor used in the present invention has an amorphous or microcrystalline structure, since there are no minute defects or voids in principle, it does not reach the theoretical value by a single crystal, but a large dielectric breakdown electric field equivalent to that is applied. It can be obtained with good yield.
  • the film thickness of the metal oxide layer varies depending on the withstand voltage, application and purpose, and is preferably 0.2 ⁇ m to 1.2 ⁇ m for the 60V withstand voltage and 2 ⁇ m to 12 ⁇ m for the 600V withstand voltage.
  • the surface metal layer 40 is provided on the Si layer 10, the SiO 2 layer 20, and the metal oxide layer 30.
  • the SiO 2 layer 20 may not be provided, and a metal-containing layer may be provided.
  • the element including the laminate of the present invention can be used for various electric circuits, electric appliances, vehicles and the like. In particular, it is optimal as a substrate for obtaining a diode or a vertical MOSFET.
  • a diode using the laminate of the present invention can achieve high breakdown voltage and high-speed switching. Hereinafter, these will be described.
  • Schottky barrier diode A diode is divided into a Schottky barrier diode and a PN diode according to the application.
  • a Schottky barrier diode using silicon is unipolar and can perform high-speed switching, but is inferior in breakdown voltage.
  • a PN diode using silicon is bipolar, and high-speed switching is inferior, but it has excellent withstand voltage.
  • a diode manufactured using the stacked body of the present invention is unipolar because an oxide semiconductor is used, and has a wide band gap. Therefore, it is possible to achieve both high-speed switching and high breakdown voltage, which are difficult to realize with silicon. In the case of SiC or GaN, it is difficult to efficiently obtain a single crystal with few defects, and there is a problem in yield. In this respect, a diode using the laminate of the present invention has a high manufacturing yield and is industrially effective.
  • a conventionally known protective film, guard ring structure, mesa structure, field plate structure, and field stop structure can be used.
  • the exposed portion of the metal oxide layer is passivated with SiO 2 or the like, so that the formation of surface states can be suppressed and the forward current reduction phenomenon called current collapse can be reduced.
  • the guard ring layer in the metal oxide layer, it is possible to suppress avalanche breakdown that may damage the diode when the reverse surge voltage exceeds the voltage range to be protected.
  • the guard ring layer is preferably p-type or i-type semiconductor.
  • the guard ring layer can alleviate electric field concentration at the junction interface edge during reverse bias, and can increase the breakdown voltage.
  • the p-type layer may be a conventionally known p-type semiconductor using Si doped with B, Al, Ga, In, or p-type oxidation represented by NiO, CuO, or CuTMO 2 (TM: 3d transition metal).
  • a physical semiconductor can be used.
  • the guard ring may be designed to be double or triple in order to increase the effect.
  • the p-type semiconductor does not flow holes and does not require high mobility.
  • a guard ring layer is formed first, and then the metal oxide layer is stacked. If the interface of the metal oxide in contact with any one of the Si layer, the SiO 2 layer, and the intermediate metal layer is in ohmic connection, the metal oxide layer is first formed, etched into a guard ring shape, and then p-type or An i-type semiconductor is formed. Next, after polishing the surface by CMP or the like, a surface metal layer that forms an ohmic connection may be formed. The same applies to a metal oxide in contact with any of the metal M layer, M x O y layer, and intermediate metal layer.
  • These protective film and guard ring layer can be formed by a conventionally known film forming method such as a vacuum process such as sputtering, ion plating or PECVD, a wet process such as printing, coating pyrolysis, mist CVD or sol-gel.
  • a conventionally known film forming method such as a vacuum process such as sputtering, ion plating or PECVD, a wet process such as printing, coating pyrolysis, mist CVD or sol-gel.
  • the guard ring p-type elements such as Cu and Ni may be ion-implanted into a desired region.
  • an area mask may be used, or a conventionally known photolithography method may be used.
  • wet etching and dry etching can be used.
  • an optimum process may be appropriately combined depending on processing accuracy and material.
  • a protective film 50 is provided on the metal oxide layer 30 and the surface metal layer 40 so as to cover them.
  • a guard ring 60 is embedded on the upper surface side of the metal oxide layer 30.
  • a guard ring 60 is embedded on the lower surface side of the metal oxide layer 30. Note that in the laminates 6 to 8, the configuration of the laminate other than the protective film 50 or the guard ring 60 is as described above, and various configurations can be adopted.
  • the back electrode is preferably laminated after removing the Si native oxide film by reverse sputtering or hydrofluoric acid in order to reduce the contact resistance of the Si layer.
  • a laminate of Ti—Ni—Au, Ti—Ni—Ag, etc., an Al electrode doped with Si, or the like is used. Since the Schottky barrier diode thus obtained is laminated on a silicon wafer, it is not as hard and brittle as SiC. Therefore, it can process with a high yield by a normal dicing technique.
  • the laminate of the present invention can be used for an MPS diode.
  • the MPS diode is a diode that achieves both the current-carrying capability of the Pin diode and the high-speed switching characteristics of the Schottky diode.
  • the p layer or the i layer may be laminated and patterned first, and then the metal oxide may be laminated. .
  • FIG. 9 An embodiment in which the laminate of the present invention is MPS is shown in FIG.
  • a plurality of p-type semiconductors 70 are formed on the SiO 2 layer 20.
  • laminated bodies other than the p-type semiconductor 70 it is as having demonstrated above and can be set as various structures.
  • the metal oxide layer is first formed, and after the trench is dug, the p-type or i-type A semiconductor is formed. Next, after polishing the surface by CMP or the like, a surface metal layer that forms an ohmic connection may be formed.
  • the laminated body with a small On-resistance and a large dielectric breakdown electric field can be obtained.
  • This property has the effect of improving the breakdown voltage region (200 to 600 V) of the Si Schottky barrier diode, which has conventionally been difficult to increase in voltage.
  • FIG. 10 is a view showing an embodiment of a laminate in the case where the support substrate is made of metal M.
  • the laminated body 10 is the same as the laminated body 7 except that the Si layer 10 is a metal layer 12 made of Mo and the SiO 2 layer 20 is an oxide layer 22 of Mo. Since Mo is close to the linear expansion coefficient of the metal oxide, generation of internal stress can be suppressed in the heating process after the metal oxide is laminated. For example, when IGZO (33:33:33) is used as the metal oxide layer 30, the linear expansion coefficient of IGZO is 6.5 ⁇ 10 ⁇ 6 / K, whereas the linear expansion coefficient of Mo is 5.1. It is close to ⁇ 10 ⁇ 6 / K.
  • the linear expansion coefficient of Si is 2.8 ⁇ 10 ⁇ 6 / K, which is less than half that of IGZO, and the metal oxide layer is peeled off and cracks are generated. It's easy to do.
  • the metal layer 14 and the metal oxide layer 24 constituting the metal layer 14 are laminated between the SiO 2 layer 20 and the metal oxide layer 30.
  • This metal layer is a layer for relieving stress due to the difference in coefficient of linear expansion between the support substrate and the metal oxide, and the thickness is appropriately selected depending on the thickness and composition of the metal oxide layer.
  • the thickness of the metal layer is preferably greater than or equal to the metal oxide layer.
  • the metal used for the support substrate other than Si and the buffer layer is preferably a material having a linear expansion coefficient larger than that of Si and smaller than that of the metal oxide.
  • the film thicknesses of the SiO 2 layer 20 and the metal oxide layer 24 (both natural oxide layers) constituting the metal layer 14 are preferably 0.0 nm to 15.0 nm, respectively.
  • FIG. 12 and 13 are diagrams showing an embodiment of a method for manufacturing the laminate 11 of FIG.
  • a laminate is manufactured by bonding a laminate formed on the metal layer 14 and a Si wafer.
  • the Si process can be applied to the subsequent process, which is advantageous in manufacturing.
  • FIG. 13 shows a case where the laminate of the metal layer 14 and the metal oxide layer 30 and the Si layer 10 are first joined, and then the surface metal layer 40, the protective layer 50, the guard ring 60, and the like are laminated.
  • Examples of the bonding technique include conventionally known SOI and plasma. Note that cracking and cracking due to differences in thermal expansion coefficients are likely to occur when different metals are bonded together, so it is necessary to ensure temperature uniformity during temperature rise and fall.
  • the element of the present invention preferably has non-linear electrical conduction.
  • Non-linear electrical conduction refers to electrical conduction that does not follow Ohm's law.
  • the laminate of the present invention can be used for a power MOSFET.
  • the power MOSFET is an insulated gate field effect transistor that controls the flow of carriers with an electric field through an oxide film.
  • the laminated body of this invention it can be set as the unipolar device which uses an electron as a carrier.
  • FIG. 14 shows an embodiment in which the laminate of the present invention is used in a planar gate type power MOSFET.
  • FIG. 14 is a cross-sectional view of a vertical MOSFET using a metal oxide semiconductor.
  • An n-type Si (corresponding to the Si layer 10) is used as a support substrate, and an n-type metal oxide semiconductor (corresponding to the metal oxide layer 30) is formed via Ti, Ni, In (corresponding to the metal-containing layer 25).
  • Ti, Ni, In corresponding to the metal-containing layer 25.
  • the interface between the Si wafer and Ti may or may not be present in the SiO 2 layer 20, but if it is present, 15 nm or less is essential.
  • Ti, Ni, Au back electrode 26
  • this layer is in contact with the drain electrode 100 (not shown).
  • a recess (groove) is formed on the upper portion of an n-type metal oxide semiconductor by dry etching, and then a p-type semiconductor or an n-type semiconductor 75 having a low carrier concentration is stacked.
  • a p-type semiconductor is used for this region (hereinafter referred to as a recess region).
  • the Fermi level of the p-type semiconductor or the low carrier concentration n-type semiconductor 75 formed in the recess region is preferably lower than that of the oxide semiconductor used in the stacked body of the present invention.
  • a conventionally known p-type semiconductor material such as NiO, PdO, CuO, or boron-doped silicon can be used.
  • An oxide semiconductor can be used for the n-type semiconductor with a low carrier concentration. Since this region is a region where a channel is formed with the gate turned on, the concentration of the transition metal that can be a scattering source is preferably as small as possible.
  • a conventionally known low-resistance wiring material such as W, Ti, Mo, Al, or Cr can be used for the source electrode region 90 that exists via the gate insulating film 110. Further, in order to suppress contact resistance, treatment with reducing by Ar plasma or the like before film formation and increasing the carrier concentration only at the contact portion may be performed.
  • Both the p-type region and the source electrode region can be obtained by patterning a metal oxide layer by photolithography and forming it by a method such as magnetron sputtering or plasma CVD. The surface is appropriately smoothed by CMP treatment. An insulating film is stacked on the stacked body including the source electrode thus obtained and the p-type or low carrier concentration n-type region, and patterned to form a gate insulating film.
  • the material forming the insulating film is not particularly limited, and any material generally used can be selected as long as the effects of the present invention are not lost.
  • any material generally used can be selected as long as the effects of the present invention are not lost.
  • An oxide or nitride such as Y 2 O 3 , HfO 2 , CaHfO 3 , PbTi 3 , BaTa 2 O 6 , SrTiO 3, or AlN can be used.
  • SiO 2 , SiN x , Al 2 O 3 or the like is used as a general gate insulating film.
  • a laminated body with a source and gate can be obtained by sputtering a metal and patterning it into a desired shape.
  • the metal is stacked in the order of Ti / Ni / Au.
  • Ti serves as an adhesion layer
  • Ni serves as a diffusion prevention layer
  • Au serves as a low resistance layer.
  • the vertical MOSFET thus obtained has a high breakdown voltage because a wide-gap oxide semiconductor is used for the breakdown voltage layer, and can achieve both a breakdown voltage of 600 V or higher, which is difficult with Si, and high-speed switching.
  • the channel resistance portion uses n-channel conduction by gate bias, carriers are electrons with high mobility and low on-resistance can be realized.
  • FIG. 15 shows an embodiment in which the laminate of the present invention is used for a trench gate type power MOSFET.
  • FIG. 15 shows a cross-sectional view of a trench gate type power MOSFET using an oxide semiconductor. This structure can be miniaturized as compared with the planar structure, and the resistance of the channel can be reduced. It is also possible to increase the density of the trench to obtain a super junction structure.
  • a p-type semiconductor or an n-type semiconductor 75 having a low carrier concentration is formed not on the recess but on the n-type metal oxide semiconductor 30.
  • a source electrode 90 is formed on the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration, and a recess is provided through the source electrode 90 and the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration.
  • a gate 80 is formed in the recess through a gate insulating film 110. Except for these configurations, the configuration is the same as in FIG.
  • FIG. 16 shows an embodiment in which a metal oxide is used for the drift region and polycrystalline silicon is used for the channel region in the planar gate type power MOSFET using the laminate of the present invention.
  • FIG. 16 shows a power MOSFET that achieves both high breakdown voltage and high-speed switching by using metal oxide in the drift region and polycrystalline silicon in the channel region.
  • n-type silicon wafer is used as a substrate (corresponding to the Si layer 10), and the surface is treated with dilute hydrofluoric acid to remove the natural oxide film.
  • an n-type oxide semiconductor (corresponding to the metal oxide layer 30) is formed.
  • an n-type oxide semiconductor is used after being crystallized, it is preferably annealed in the range of 150 to 1400 ° C. An appropriate range of annealing is appropriately determined depending on the constituent elements of the oxide semiconductor. If the annealing temperature exceeds 1400 ° C., silicon may be dissolved. If the annealing temperature is below 150 ° C., crystallization may not proceed.
  • an amorphous silicon film is formed on the n-type oxide semiconductor by a method such as PECVD and patterned.
  • PECVD plasma enhanced chemical vapor deposition
  • a method such as PECVD For patterning, after applying a resist, exposure and development are performed, and dry etching is performed using a halogen-based gas. After removing the resist, it is polycrystallized using a technique such as laser annealing.
  • a SiO 2 film 115 is formed by a method such as PECVD.
  • a metal electrode is formed thereon by sputtering or vapor deposition and patterned into the shape of the gate electrode 80.
  • a conventionally known method can be used for both dry and wet, but a high melting point metal such as W, Cr, Mo, Ta or the like is preferable because activation annealing described later is performed.
  • ion doping is performed on the p-type Si through the gate electrode 80. Since ion doping is a cap method through a SiO 2 film, which is an insulating film, the dose amount and its depth may be controlled by simulation or the like. For example, P, Sb, As, etc. are accelerated by 50 to 500 keV. The process is performed under the condition that the dose is 10 13 to 10 14 cm ⁇ 2 or the like with voltage. Since this ion doping uses a self-alignment technique using the gate electrode 80 as a mask, the process can be simplified, the gate capacitance can be reduced, and a high-speed switching operation can be performed.
  • activation annealing is performed.
  • Activation annealing is preferably performed by high-speed annealing such as flash lamp annealing or laser annealing in order to prevent electrode deterioration.
  • the annealing temperature is appropriately selected within a range in which the activation rate increases as the temperature increases, but the electrode does not deteriorate.
  • the annealing temperature is preferably 600 ° C. to 1100 ° C., more preferably 700 to 1000 ° C. In this way, an n + region 130 in which a part of the p-type Si (p region) 120 is made n-type can be formed.
  • the highly doped n-type silicon wafer 10 is laminated with Ti, Ni, Au (back electrode 26) as in FIGS. 14 and 15, and this layer is in contact with the drain electrode 100 (not shown). .
  • Module A MOSFET using the laminated body of the present invention incorporates a body diode in the same manner as a conventional Si MOSFET, but can also be used in combination with a freewheeling diode.
  • FIG. 17 is a diagram showing an embodiment of a module configured by combining elements of the present invention. Both the power MOSFET and the freewheeling diode are composed of elements including the laminate of the present invention.
  • This module includes both a MOSFET and a free-wheeling diode including a Si layer and a metal oxide layer, and the thickness of the SiO 2 layer on the surface of the Si layer on the metal oxide layer side is 0.0 nm to 15.0 nm. Since it is composed of a body, it can achieve both excellent current-voltage characteristics, that is, low on-resistance and high-speed switching.
  • FIG. 18 is a diagram showing an embodiment in which the diode and the MOSFET in the module of FIG. 17 are connected to the copper plate via the back metal and solder, and the Si wafer side of the diode is connected to the collector of the MOSFET. .
  • the Si side is in ohmic connection
  • the Si side is connected to the copper plate of the module.
  • FIG. 19 shows an embodiment in which the diode and the MOSFET in the module of FIG.
  • the oxide semiconductor side of the diode is connected to the collector of the MOSFET.
  • FIG. When the Si side is a Schottky connection, the surface metal layer side is connected to the copper plate of the module.
  • the module configuration may be combined with the diode of the present invention for the purpose of removing excess carriers of conventionally known Si-IGBT, SiC-MOSFET, and GaN-MOSFET.
  • a conventionally known free-wheeling diode may be used for the purpose of removing excess carriers in the MOSFET of the present invention.
  • examples of the electric circuit using the element of the present invention include a step-up / step-down chopper circuit, an inverter / converter circuit, a power supply circuit, a switching regulator, etc.
  • the electric appliances include a mobile phone, a personal computer, an air conditioner, and a refrigerator.
  • Receivers, lighting fixtures, electromagnetic cookers, and the like, and vehicles include bicycles, automobiles, railway vehicles, and the like.
  • the element of the present invention can be used for oxygen gas sensors, photocatalysts, ultraviolet sensors, ultraviolet solar cells, human body sensors, ultraviolet diodes, ultraviolet lasers, and the like.
  • Example 1 An n-type Si substrate (diameter 4 inches) having a resistivity of 0.02 ⁇ ⁇ cm and a slide glass were prepared. These were mounted in a sputtering apparatus (ULVAC: CS-200), and first treated in a reverse sputtering mode for 15 seconds to partially etch a natural oxide film. Next, 9700 nm of Ga 2 O 3 was formed as a metal oxide under the conditions of RF 300 W and 19 hours. Further, the substrate was taken out of the chamber and annealed for 1 hour in air at 150 ° C. by an electric furnace. The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus (FIG. 20).
  • the substrate was set again in the sputtering apparatus together with the area mask, and electrodes were formed by sputtering in the order of Ti and Au.
  • the thus-obtained element Si / SiO 2 (natural oxide film) / Ga 2 O 3 / Ti / Au
  • the evaluation items were forward rising voltage (Vf), On current, dielectric breakdown electric field (Vbd), and n value.
  • the forward rising voltage (Vf) is the applied voltage when the current density exceeds 10 mA / cm 2
  • the On current is the current density when the applied voltage is 3 V
  • the dielectric breakdown electric field (Vbd) has a leakage current of 10 ⁇
  • the voltage when exceeding 5 A / cm 2 was taken. The results are shown in Table 1.
  • Example 2 An n-type Si substrate (diameter 4 inches) having a resistivity of 0.02 ⁇ ⁇ cm and a slide glass were prepared. These were mounted in a sputtering apparatus (ULVAC: CS-200), and first treated in a reverse sputtering mode for 5 minutes to etch a part of the natural oxide film. Next, 3700 nm of Ga 2 O 3 was deposited as a metal oxide under conditions of RF 300 W and 6 hours. The substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. in air for 1 hour. The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus (FIG. 20).
  • UVAC sputtering apparatus
  • Example 3 An n-type polycrystalline Si substrate (diameter 4 inches) having a resistivity of 0.02 ⁇ ⁇ cm and a slide glass were prepared. These were mounted on a sputtering apparatus (ULVAC: CS-200), and were first processed in the reverse sputtering mode to etch a part of the natural oxide film. Next, a 200 nm film of Ga 2 O 3 was formed as a metal oxide under the conditions of RF 300 W and 18 minutes. The substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. in air for 1 hour. The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus.
  • UVAC sputtering apparatus
  • a sputtering apparatus UVAC: CS-200
  • Example 6 An n-type Si substrate (4 inches in diameter) having a resistivity of 0.02 ⁇ ⁇ cm was prepared. This Si wafer was mounted on a sputtering apparatus (ULVAC: CS-200), and the natural oxide film was first etched in the reverse sputtering mode. Then 15nm deposited Mo, was further 1000nm deposited Ga 2 O 3. The substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. in air for 1 hour. Next, the remaining substrate was returned to the chamber again, and after setting an area mask having a desired pattern, electrodes were formed by sputtering in the order of Ti and Au. The device (Si / Mo / Ga 2 O 3 / Ti / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Technica. The results are shown in Table 1.
  • Example 15 and 16 Comparative Examples 3 and 4 While changing the substrate, reverse sputtering conditions, metal oxide layer material and the like as shown in Table 1, a laminate was prepared in the same manner as in Example 1, and various characteristics were evaluated. The results are shown in Table 1.
  • Example 17 A Schottky barrier diode was manufactured by the process shown in FIG. Specifically, an n-type Si substrate (4 inches in diameter) having a resistivity of 0.02 ⁇ ⁇ cm was prepared. This Si wafer was put into a thermal oxidation furnace to form a 100 nm thermal oxide film. Next, after applying the resist, exposure, development, and etching were performed using a photomask to form contact holes. Further thereon, 10 nm each of Pd and PdO films were formed by sputtering using a Pd target. Then, a Pd / PdO laminated portion on SiO 2 was etched using aqua regia so as to remain concentrically, thereby forming a guard ring.
  • an oxide semiconductor IGZO
  • IGZO oxide semiconductor
  • Mo molybdenum
  • the thermal oxide film present on the back surface of the Si wafer was removed by etching with dilute hydrofluoric acid after the surface was covered with a protective film. Thereafter, films were formed in the order of Ti, Ni, and Au.
  • the Si wafer side of the obtained laminate was used as a Schottky junction to obtain a Schottky barrier diode with a guard ring and a back electrode.
  • the thickness of the SiO 2 film at the interface between Si and Pd of the Schottky barrier diode thus obtained was evaluated to be 0.2 nm. Note that the contact hole is circular, and a total of five points, the center of the circle and the midpoint of each vertex of the square inscribed in the circle, are observed, and the field of view is measured at equally spaced intervals of 10 to obtain a total of 55 The average value of the places was taken as the film thickness of the SiO 2 layer.
  • the element including the laminate of the present invention can be used as a power device such as a Schottky barrier diode or a MOSFET or a module combining them. Specifically, it can be used for power conversion circuits such as inverters and converters, power supply circuits, and electric circuit power conditioners, IPMs, electric appliances and vehicles using them. Furthermore, it can be used for oxygen gas sensors, photocatalysts, ultraviolet sensors, ultraviolet solar cells, human body sensors, ultraviolet diodes, ultraviolet lasers, and the like.

Abstract

A laminate which comprises an Si layer and a metal oxide layer, and wherein the film thickness of an SiO2 layer on the metal oxide layer-side surface of the Si layer is 0.0-15.0 nm.

Description

新規な積層体New laminate
　本発明は、積層体、それを含む素子、その素子を含む電気回路、電器機器及び車両に関する。 The present invention relates to a laminate, an element including the laminate, an electric circuit including the element, an electric appliance, and a vehicle.
　大電流、高消費電力を実現するショットキーバリアダイオードとして、安価なＳｉウェハー基板にＳｉＣやＧａＮエピタキシャル成長させた例が開示されている（例えば特許文献１～３）。
　ＳｉＣに関しては、パワー半導体として好適な結晶構造は４Ｈ－ＳｉＣとされているが、格子の不整合が大きいため、Ｓｉ上にエピタキシャル成長させるのは極めて困難である。３Ｃ－ＳｉＣであれば、Ｓｉウェハーに微細加工を施すか、Ｓｉ（２１１）面を使用することでエピタキシャル成長できるが、パワーデバイスに適用できるほどの厚膜を得るのは困難であった。 Examples of Schottky barrier diodes that realize large current and high power consumption have been disclosed in which SiC or GaN is epitaxially grown on an inexpensive Si wafer substrate (for example, Patent Documents 1 to 3).
Regarding SiC, the crystal structure suitable as a power semiconductor is 4H—SiC. However, since the lattice mismatch is large, it is extremely difficult to grow epitaxially on Si. In the case of 3C—SiC, it can be epitaxially grown by performing fine processing on the Si wafer or by using the Si (211) plane, but it has been difficult to obtain a thick film that can be applied to a power device.
　一方、ＧａＮは、Ｓｉと格子の不整合の点ではＳｉＣほどではないものの、ＡｌＮ等のバッファ層を介さないと結晶成長が困難である。格子定数の近いサファイア基板も有力候補であるが、縦方向に電流を流すことができず、大電流用途には使えない。
　そこで、Ｓｉ等の導電性基板を用いるには、基板上にバッファ層を積層し、さらにＧａＮを結晶成長させるという工程を経る必要がある。しかしこれでも完全な結晶を得るのは困難であった。 On the other hand, although GaN is not as high as SiC in terms of mismatch between Si and lattice, crystal growth is difficult unless a buffer layer such as AlN is used. A sapphire substrate with a close lattice constant is a promising candidate, but it cannot flow in the vertical direction and cannot be used for large current applications.
Therefore, in order to use a conductive substrate such as Si, it is necessary to go through a process of laminating a buffer layer on the substrate and further growing a crystal of GaN. However, even with this, it was difficult to obtain perfect crystals.
特開２００９－１６４６３８号公報JP 2009-164638 A 特開２０１０－４０９７２号公報JP 2010-40972 A 特開２０１３－２２７１９８号公報JP 2013-227198 A
　本発明はこのような課題に鑑みてなされたものであり、自然酸化膜を特定の厚み以下に制御し、その上にバンドギャップの広い金属酸化物を形成することで、優れた電流－電圧特性を発揮する積層体を提供することを目的とする。 The present invention has been made in view of such problems, and has excellent current-voltage characteristics by controlling a natural oxide film to a specific thickness or less and forming a metal oxide having a wide band gap thereon. It aims at providing the laminated body which exhibits.
　本発明によれば、以下の積層体等が提供される。
１．Ｓｉ層及び金属酸化物層を含み、前記Ｓｉ層における前記金属酸化物層側の面上のＳｉＯ２層の膜厚が０．０ｎｍ～１５．０ｎｍである積層体。
２．前記Ｓｉ層と前記金属酸化物層の間に金属含有層を含む１に記載の積層体。
３．前記金属酸化物層が非晶質又は微結晶構造である１又は２に記載の積層体。
４．前記金属酸化物層の組成比（原子比）が下記式（１）～（３）を満たす１～３のいずれかに記載の積層体。
０　　　≦　ｘ／（ｘ＋ｙ＋ｚ）　≦　０．５　（１）
０　　　≦　ｙ／（ｘ＋ｙ＋ｚ）　≦　０．８　（２）
０．２　≦　ｚ／（ｘ＋ｙ＋ｚ）　≦　１．０　（３）
（式中、ｘ、ｙ及びｚは、それぞれ下記の元素から選ばれる１種以上の原子数を表す。
ｘ＝Ｉｎ，Ｓｎ，Ｇｅ，Ｔｉ
ｙ＝Ｚｎ，Ｙ，Ｓｍ，Ｃｅ，Ｎｄ
ｚ＝Ｇａ，Ａｌ）
５．前記金属酸化物層のキャリア濃度が１×１０１４ｃｍ－３～１×１０１７ｃｍ－３である１～４のいずれかに記載の積層体。
６．前記Ｓｉ層の仕事関数が３．９ｅＶ～５．０ｅＶである１～５のいずれかに記載の積層体。
７．前記金属含有層の仕事関数が３．５ｅＶ～５．８ｅＶである２～６のいずれかに記載の積層体。
８．金属層及び金属酸化物層を含み、
　前記金属層が、前記金属酸化物層を構成する金属酸化物の金属とは異なる金属Ｍからなり、
　前記金属層における前記金属酸化物層側の面上のＭＸＯＹ層（ｘ及びｙはそれぞれ整数）の膜厚が０．０ｎｍ～１５．０ｎｍである積層体。
９．前記金属酸化物層の組成比（原子比）が下記式（１）～（３）を満たす８に記載の積層体。
０　　　≦　ｘ／（ｘ＋ｙ＋ｚ）　≦　０．５　（１）
０　　　≦　ｙ／（ｘ＋ｙ＋ｚ）　≦　０．８　（２）
０．２　≦　ｚ／（ｘ＋ｙ＋ｚ）　≦　１．０　（３）
（式中、ｘ、ｙ及びｚは、それぞれ下記の元素から選ばれる１種以上の原子数を表す。
ｘ＝Ｉｎ，Ｓｎ，Ｇｅ，Ｔｉ
ｙ＝Ｚｎ，Ｙ，Ｓｍ，Ｃｅ，Ｎｄ
ｚ＝Ｇａ，Ａｌ）
１０．１～９のいずれかに記載の積層体を含む素子。
１１．非線形の電気伝導を有する１０に記載の素子。
１２．１０又は１１に記載の素子を含む電気回路又はセンサー。
１３．１０又は１１に記載の素子を含む電器機器又は車両。 According to the present invention, the following laminates and the like are provided.
1. A laminate comprising a Si layer and a metal oxide layer, wherein the SiO 2 layer on the surface of the Si layer on the metal oxide layer side has a thickness of 0.0 nm to 15.0 nm.
2. 2. The laminate according to 1, comprising a metal-containing layer between the Si layer and the metal oxide layer.
3. 3. The laminate according to 1 or 2, wherein the metal oxide layer has an amorphous or microcrystalline structure.
4). 4. The laminate according to any one of 1 to 3, wherein the composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3).
0 ≦ x / (x + y + z) ≦ 0.5 (1)
0 ≦ y / (x + y + z) ≦ 0.8 (2)
0.2 ≦ z / (x + y + z) ≦ 1.0 (3)
(In the formula, x, y and z each represent the number of one or more atoms selected from the following elements.
x = In, Sn, Ge, Ti
y = Zn, Y, Sm, Ce, Nd
z = Ga, Al)
5. 5. The laminate according to any one of 1 to 4, wherein the metal oxide layer has a carrier concentration of 1 × 10 14 cm −3 to 1 × 10 17 cm −3 .
6). The laminate according to any one of 1 to 5, wherein a work function of the Si layer is 3.9 eV to 5.0 eV.
7). The laminate according to any one of 2 to 6, wherein a work function of the metal-containing layer is 3.5 eV to 5.8 eV.
8). Including a metal layer and a metal oxide layer;
The metal layer is made of a metal M different from the metal of the metal oxide constituting the metal oxide layer;
A laminate in which the M X O Y layer (x and y are integers) on the surface of the metal layer on the metal oxide layer side has a thickness of 0.0 nm to 15.0 nm.
9. 9. The laminate according to 8, wherein the composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3).
0 ≦ x / (x + y + z) ≦ 0.5 (1)
0 ≦ y / (x + y + z) ≦ 0.8 (2)
0.2 ≦ z / (x + y + z) ≦ 1.0 (3)
(In the formula, x, y and z each represent the number of one or more atoms selected from the following elements.
x = In, Sn, Ge, Ti
y = Zn, Y, Sm, Ce, Nd
z = Ga, Al)
10. A device comprising the laminate according to any one of 10.1 to 9.
11. 11. The device according to 10, which has non-linear electrical conduction.
12. An electric circuit or sensor comprising the element according to 10 or 11.
13. Electric appliance or vehicle including the element according to 10 or 11.
　本発明によれば、優れた電流－電圧特性を発揮できる積層体が提供できる。自然酸化膜を特定の厚み以下に制御し、その上にバンドギャップの広い金属酸化物を形成することで、優れた電流－電圧特性を発揮することができる。さらに、金属酸化物は安価で量産性に優れた方法で形成できるため、従来に比べて生産性を格段に向上することができる。 According to the present invention, a laminate capable of exhibiting excellent current-voltage characteristics can be provided. By controlling the natural oxide film to a specific thickness or less and forming a metal oxide having a wide band gap thereon, excellent current-voltage characteristics can be exhibited. Furthermore, since the metal oxide can be formed by a method that is inexpensive and excellent in mass productivity, the productivity can be significantly improved as compared with the conventional case.
本発明の積層体の一実施形態（Ｓｉ層／ＳｉＯ２層／金属酸化物層）を示す図である。It is a diagram showing an embodiment of the laminate of the present invention (Si layer / SiO 2 layer / metal oxide layer). 本発明の積層体の一実施形態（Ｓｉ層／金属酸化物層）を示す図である。It is a figure which shows one Embodiment (Si layer / metal oxide layer) of the laminated body of this invention. 本発明の積層体の一実施形態（Ｓｉ層／ＳｉＯ２層／中間金属層（金属含有層）／金属酸化物層）を示す図である。It is a diagram showing an embodiment of the laminate of the present invention (Si layer / SiO 2 layer / intermediate metal layer (metal containing layer) / metal oxide layer). 本発明の積層体の一実施形態（Ｓｉ層／中間金属層／金属酸化物層）を示す図である。It is a figure which shows one Embodiment (Si layer / intermediate metal layer / metal oxide layer) of the laminated body of this invention. 本発明の積層体の一実施形態（Ｓｉ層／ＳｉＯ２層／金属酸化物層／上部金属（表面金属層））を示す図である。It is a diagram showing an embodiment (Si layer / SiO 2 layer / metal oxide layer / upper metal (surface metal layer)) of the laminate of the present invention. 本発明の積層体の一実施形態（Ｓｉ層／ＳｉＯ２層／金属酸化物層／上部金属／保護膜）を示す図である。It is a diagram showing an embodiment of the laminate of the present invention (Si layer / SiO 2 layer / metal oxide layer / upper metal / protective film). 本発明の積層体の一実施形態（Ｓｉ層／ＳｉＯ２層／金属酸化物層（上部電極側にガードリング埋込）／上部金属／保護膜）を示す図である。(The Si layer / SiO 2 layer / metal oxide layer (upper electrode side guard ring embedded) / upper metal / protective film) In one embodiment of the laminate of the present invention is a diagram showing a. 本発明の積層体の一実施形態（Ｓｉ層／ＳｉＯ２層／金属酸化物層（下部電極側にガードリング埋込）／上部金属／保護膜）を示す図である。Is a diagram showing an embodiment (Si layer / SiO 2 layer / metal oxide layer (guard ring embedded) / upper metal / protective film on the lower electrode side) of the laminate of the present invention. 本発明の積層体の一実施形態（ＭＰＳダイオード）を示す図である。It is a figure which shows one Embodiment (MPS diode) of the laminated body of this invention. 本発明の積層体の一実施形態（金属Ｍ層／ＭｘＯｙ層／金属酸化物層（上部電極側にガードリング埋込）／上部金属／保護膜）を示す図である。(The metal M layer / M x O y layer / metal oxide layer (upper electrode side guard ring embedded) / upper metal / protective film) In one embodiment of the laminate of the present invention is a diagram showing a. 本発明の積層体の一実施形態（Ｓｉ層／ＳｉＯ２層／金属Ｍ層／ＭｘＯｙ層／金属酸化物層（上部電極側にガードリング埋込）／上部金属／保護膜）を示す図である。1 shows an embodiment of a laminate of the present invention (Si layer / SiO 2 layer / metal M layer / M x O y layer / metal oxide layer (guard ring embedded on the upper electrode side) / upper metal / protective film). FIG. 本発明の積層体の製造方法の一実施形態を示す図である。It is a figure which shows one Embodiment of the manufacturing method of the laminated body of this invention. 本発明の積層体の製造方法の一実施形態を示す図である。It is a figure which shows one Embodiment of the manufacturing method of the laminated body of this invention. 本発明の積層体をプレーナーゲート型パワーＭＯＳＦＥＴに用いた場合の一実施形態を示す図である。It is a figure which shows one Embodiment at the time of using the laminated body of this invention for planar gate type power MOSFET. 本発明の積層体をトレンチゲート型パワーＭＯＳＦＥＴに用いた場合の一実施形態を示す図である。It is a figure which shows one Embodiment at the time of using the laminated body of this invention for a trench gate type power MOSFET. 本発明の積層体を用いたプレーナーゲート型パワーＭＯＳＦＥＴのうち、ドリフト領域に金属酸化物を用い、チャネル領域に多結晶シリコンを用いた場合の一実施形態を示す図である。It is a figure which shows one Embodiment at the time of using a polycrystalline silicon for a channel region among metal oxides for a drift region among the planar gate type power MOSFETs using the laminated body of this invention. 本発明の素子を組合せて構成したモジュールの一実施形態を示す図である。It is a figure which shows one Embodiment of the module comprised combining the element of this invention. 図１７のモジュールにおいてダイオードとＭＯＳＦＥＴが、裏面金属とはんだを介して銅板に接続しており、ダイオードのＳｉウェハー側がＭＯＳＦＥＴのコレクタと接続している場合の実施形態を示す図である。FIG. 18 is a diagram showing an embodiment in which the diode and the MOSFET in the module of FIG. 17 are connected to the copper plate via the back metal and solder, and the Si wafer side of the diode is connected to the collector of the MOSFET. 図１７のモジュールにおいてダイオードとＭＯＳＦＥＴが、裏面金属とはんだを介して銅板に接続しており、ダイオードの酸化物半導体側がＭＯＳＦＥＴのコレクタと接続している場合の実施形態を示す図である。FIG. 18 is a diagram showing an embodiment in which a diode and a MOSFET are connected to a copper plate via a back metal and solder in the module of FIG. 17, and the oxide semiconductor side of the diode is connected to a collector of the MOSFET. 実施例１で得た９７００ｎｍのＧａ２Ｏ３膜と実施例２で得た３７００ｎｍのＧａ２Ｏ３膜のＸＲＤパターンである。Is an XRD pattern of Ga 2 O 3 film of 3700nm where the Ga 2 O 3 film of 9700nm obtained in Example 1 was obtained in Example 2. 実施例１で得た膜厚９７００ｎｍのＧａ２Ｏ３膜の電子線回折像である。4 is an electron diffraction image of a 9700 nm-thick Ga 2 O 3 film obtained in Example 1. FIG. 実施例１、７、８で得た積層体のＳｉ層界面のＳｉＯ２部分のＴＥＭ像である。 2 is a TEM image of the SiO 2 portion at the Si layer interface of the laminate obtained in Examples 1, 7, and 8. FIG. 実施例１５で製造したショットキーバリアダイオードを製造プロセスを示す図である。It is a figure which shows a manufacturing process of the Schottky barrier diode manufactured in Example 15. FIG.
１．積層体
　本発明の第１の積層体はＳｉ層及び酸化物金属層を含む。また、Ｓｉ層の金属酸化物層側の面上のＳｉＯ２層の膜厚が０．０ｎｍ～１５．０ｎｍである。即ち、ＳｉＯ２層は存在してもよいし、しなくてもよい。
　本発明の第１の積層体は、安価なＳｉ基板上に特定の厚みの自然酸化膜が存在していても、その上にバンドギャップの広い化合物半導体を形成することで、優れた電流－電圧特性を実現できる。 1. Laminated body The 1st laminated body of this invention contains Si layer and an oxide metal layer. The film thickness of the SiO 2 layer on the surface of the Si layer on the metal oxide layer side is 0.0 nm to 15.0 nm. That is, the SiO 2 layer may or may not exist.
Even if a natural oxide film having a specific thickness is present on an inexpensive Si substrate, the first laminate of the present invention has excellent current-voltage by forming a compound semiconductor having a wide band gap on the natural oxide film. The characteristics can be realized.
　本発明の第２の積層体は金属層及び金属酸化物層を含む。ここで金属層は、金属酸化物層を構成する金属酸化物の金属とは異なる金属Ｍからなる。また、金属層の金属酸化物層側の面上のＭｘＯｙ層（ｘ及びｙはそれぞれ整数）の膜厚が０．０ｎｍ～１５．０ｎｍである。ＭｘＯｙ層は、金属Ｍの酸化物からなる層であり、当該ＭｘＯｙ層は存在してもよいし、しなくてもよい。
　本発明の第２の積層体は、第１の積層体のＳｉ層が金属Ｍ層である他は第１の積層体と同じであり、金属Ｍ層上に特定の厚みの自然酸化膜が存在していても、その上にバンドギャップの広い化合物半導体を形成することで、優れた電流－電圧特性を実現できる。
　以下、本発明の第１の積層体及び本発明の第２の積層体をまとめて本発明の積層体という場合がある。 The second laminate of the present invention includes a metal layer and a metal oxide layer. Here, the metal layer is made of a metal M different from the metal of the metal oxide constituting the metal oxide layer. The thickness of the M x O y layer (x and y are integers) on the surface of the metal layer on the metal oxide layer side is 0.0 nm to 15.0 nm. The M x O y layer is a layer made of an oxide of metal M, and the M x O y layer may or may not exist.
The second laminate of the present invention is the same as the first laminate except that the Si layer of the first laminate is a metal M layer, and a natural oxide film having a specific thickness exists on the metal M layer. Even so, an excellent current-voltage characteristic can be realized by forming a compound semiconductor with a wide band gap on it.
Hereinafter, the first laminate of the present invention and the second laminate of the present invention may be collectively referred to as the laminate of the present invention.
　本発明の積層体の一実施形態を図１、２に示す。
　積層体１は、本発明の積層体がＳｉＯ２層を有する場合の実施形態を示し、Ｓｉ層１０（基板）上にＳｉＯ２層２０が存在し、その上に金属酸化物層３０が形成されている。
　積層体２はＳｉＯ２層を含まない場合の実施形態を示し、Ｓｉ層１０（基板）上に金属酸化物層３０が形成されている。
　尚、図１及び図２は本発明の第１の積層体に対応する図面であるが、本発明の第２の積層体にも対応する。具体的には、図１及び２において、Ｓｉ層１０の代わりに金属Ｍ層とし、ＳｉＯ２層２０の代わりにＭｘＯｙ層とする。後述する図３～９についても同様である。
　以下、積層体に用いる各層について説明する。 One embodiment of the laminate of the present invention is shown in FIGS.
The laminated body 1 shows an embodiment in which the laminated body of the present invention has an SiO 2 layer. The SiO 2 layer 20 exists on the Si layer 10 (substrate), and the metal oxide layer 30 is formed thereon. ing.
The laminated body 2 shows an embodiment in which an SiO 2 layer is not included, and a metal oxide layer 30 is formed on the Si layer 10 (substrate).
1 and 2 are drawings corresponding to the first laminate of the present invention, but also correspond to the second laminate of the present invention. Specifically, in FIGS. 1 and 2, a metal M layer is used instead of the Si layer 10, and an M x O y layer is used instead of the SiO 2 layer 20. The same applies to FIGS. 3 to 9 described later.
Hereinafter, each layer used for a laminated body is demonstrated.
（１－１）Ｓｉ層
　Ｓｉ層は特に制限されず、シリコンウェハーを用いてもよいし、ガラス等の適当な基材の上にスパッタ法やＣＶＤ法によってＳｉを成膜したものを用いてもよい。また、ドーピングされていてもよい。
　シリコンウェハーは単結晶及び多結晶のいずれの構造でもよい。製法に関しても、チョクラルスキー法やフローティングゾーン法等を用いることができ、従来公知のシリコンウェハー基板をそのまま用いることができる。 (1-1) Si layer The Si layer is not particularly limited, and a silicon wafer may be used, or a Si film formed on a suitable base material such as glass by sputtering or CVD. Good. Moreover, it may be doped.
The silicon wafer may have either a single crystal structure or a polycrystalline structure. Regarding the manufacturing method, a Czochralski method, a floating zone method, or the like can be used, and a conventionally known silicon wafer substrate can be used as it is.
　また、シリコンウェハーはドーピングの有無、種類によってｎ型、ｉ型、ｐ型が存在するが、縦方向に電流を流す上では、電気抵抗の小さいｎ型又はｐ型が好ましい。ドーパントとしては従来公知のＢ，Ｐ，Ｓｂ等を用いることができる。特に抵抗を下げたい場合は、Ａｓや赤リンをドーパントとしてもよい。 In addition, although there are n-type, i-type, and p-type silicon wafers depending on the presence / absence and type of doping, n-type or p-type with low electrical resistance is preferable for flowing a current in the vertical direction. Conventionally known B, P, Sb and the like can be used as the dopant. In particular, when it is desired to lower the resistance, As or red phosphorus may be used as a dopant.
　また、Ｓｉ層の厚みに制限はなく、通常、２００～１０００μｍであるが、縦方向の抵抗を下げたい場合にはＣＭＰ法等により研磨してもよい。基板の反りが問題になる場合は、外周部を残したＴＡＩＫＯ型の構造を用いることができる。研磨は金属酸化物を積層する前に行ってもよいし、後に行ってもよい。 The thickness of the Si layer is not limited and is usually 200 to 1000 μm. However, if the resistance in the vertical direction is to be lowered, it may be polished by a CMP method or the like. When warping of the substrate becomes a problem, a TAIKO type structure that leaves the outer peripheral portion can be used. Polishing may be performed before or after the metal oxide is laminated.
　Ｓｉ層の仕事関数は、好ましくは３．９ｅＶ～５．０ｅＶであり、より好ましくは４．０ｅＶ～４．５ｅＶである。Ｓｉ層の仕事関数は、大気中光電子分光装置（例えば、理研計器ＡＣ－３）によって測定する。 The work function of the Si layer is preferably 3.9 eV to 5.0 eV, and more preferably 4.0 eV to 4.5 eV. The work function of the Si layer is measured by an atmospheric photoelectron spectrometer (for example, Riken Keiki AC-3).
（１－２）金属Ｍ層
　金属Ｍ層を構成する金属Ｍは、金属酸化物層を構成する金属酸化物の金属と異なる金属であれば特に限定されない。金属Ｍは、例えば表面平滑性が高いものであるとよく、上に積層する金属酸化物の膜厚が１μｍを超える場合は、金属酸化物の線膨張係数に近い材料が好ましい。具体的には金属Ｍは、線膨張係数が４～１０×１０－６Ｋ－1の範囲の金属が好ましく、当該金属としてはＴｉ、Ｃｒ、Ｎｂ、Ｍｏ及びＴａから選択される１以上の金属が挙げられる。本発明の基板に使用される酸化物の線膨張係数は、例えば５×１０－６～８×１０－６Ｋ－１の範囲である。そのため、後工程のプロセスで加熱した場合、線膨張係数が大きく異なると反りが生じるおそれがある。具体的には、金属Ｍの線膨張係数が４×１０－６Ｋ－1よりも小さい時は金属酸化物層は圧縮応力が、金属Ｍの線膨張係数が１０×１０－６Ｋ－1よりも大きい時は引っ張り応力がかかる。
　但し、金属Ｍが低融点な金属、又は反応性の高い金属である場合、積層体の製造工程等で汚染されるおそれがある。このような金属としては、Ｇａ、Ｈｇ、Ｃｓ、Ｋ，Ｎａ等が挙げられる。
　金属Ｍは、金属酸化物層を構成する金属酸化物の金属とは異なるが、ここで「異なる」とは、金属Ｍと金属酸化物層の金属とが完全に異なることをいい、例えば金属酸化物層の金属が２種以上の金属からなる合金である場合、金属Ｍと合金は一部一致してもよい。 (1-2) Metal M Layer The metal M constituting the metal M layer is not particularly limited as long as it is a metal different from the metal oxide metal constituting the metal oxide layer. For example, the metal M may have high surface smoothness, and when the thickness of the metal oxide layered thereon exceeds 1 μm, a material close to the linear expansion coefficient of the metal oxide is preferable. Specifically, the metal M is preferably a metal having a linear expansion coefficient in the range of 4 to 10 × 10 −6 K −1 , and the metal is one or more metals selected from Ti, Cr, Nb, Mo, and Ta. Is mentioned. The linear expansion coefficient of the oxide used for the substrate of the present invention is, for example, in the range of 5 × 10 −6 to 8 × 10 −6 K −1 . For this reason, when heated in a subsequent process, warping may occur if the linear expansion coefficients differ greatly. Specifically, when the linear expansion coefficient of the metal M is smaller than 4 × 10 −6 K −1, the metal oxide layer has a compressive stress, and the linear expansion coefficient of the metal M is 10 × 10 −6 K −1 . When it is too large, tensile stress is applied.
However, when the metal M is a low-melting-point metal or a highly reactive metal, there is a risk of contamination in the manufacturing process of the laminate. Examples of such a metal include Ga, Hg, Cs, K, and Na.
The metal M is different from the metal of the metal oxide composing the metal oxide layer, but “different” here means that the metal M and the metal of the metal oxide layer are completely different. When the metal of the physical layer is an alloy composed of two or more metals, the metal M and the alloy may partially match.
（２－１）ＳｉＯ２層
　ＳｉＯ２層の膜厚は０．０ｎｍ以上１５．０ｎｍ以下であり、好ましくは０．０ｎｍ以上８．０ｎｍ以下であり、より好ましくは０．０ｎｍ以上４．０ｎｍ以下であり、さらに好ましくは０．０ｎｍ以上２．５ｎｍ以下であり、特に好ましくは０．０ｎｍ以上１．５ｎｍ以下である。ＳｉＯ２層の膜厚は薄い方が好ましい。
　ＳｉＯ２層の膜厚は、その断面をＴＥＭ（透過型電子顕微鏡）により測定する。測定箇所は、ＳｉＯ２層が例えば四角形の場合は、対角線の交点と、交点と各頂点の中間点の計５点の視野を観察し、その視野を等間隔に１０等分する箇所で測定し、その計５５か所の平均値をＳｉＯ２層の膜厚とする。 (2-1) SiO 2 layer The thickness of the SiO 2 layer is from 0.0 nm to 15.0 nm, preferably from 0.0 nm to 8.0 nm, more preferably from 0.0 nm to 4.0 nm. More preferably, it is 0.0 nm or more and 2.5 nm or less, and particularly preferably 0.0 nm or more and 1.5 nm or less. A thinner SiO 2 layer is preferable.
The film thickness of the SiO 2 layer is measured by TEM (transmission electron microscope). Measurement points, in the case of the SiO 2 layer, for example a square, a diagonal line of intersection, the intersection and the field of five points of the midpoint of each vertex observed, measured at the point of 10 equally dividing its field of view at regular intervals The average value of 55 places in total is the film thickness of the SiO 2 layer.
　一般に、シリコンウェハーの表面には自然酸化膜（ＳｉＯ２）が存在する。従って、Ｓｉ基板上に金属酸化物を積層すると、通常、Ｓｉ層と金属酸化物層の界面にＳｉＯ２膜が存在するが、ＳｉＯ２膜の厚さが１５．０ｎｍを超えると、縦方向に電流を流す場合に明確な電気抵抗成分として作用してしまう。ＳｉＯ２膜の厚さを１５．０ｎｍ以下にするためには、通常、金属酸化物層を積層する前に、予め自然酸化膜を所定量除去する必要がある。 In general, a natural oxide film (SiO 2 ) exists on the surface of a silicon wafer. Therefore, when a metal oxide is laminated on a Si substrate, an SiO 2 film usually exists at the interface between the Si layer and the metal oxide layer. However, when the thickness of the SiO 2 film exceeds 15.0 nm, When current is passed, it acts as a clear electric resistance component. To the thickness of the SiO 2 film below 15.0nm usually before stacking the metal oxide layer, it is necessary to preliminarily remove the natural oxide film a predetermined amount.
　自然酸化膜（ＳｉＯ２）を除去する方法としては、逆スパッタ、ドライエッチング、減圧下・還元雰囲気下でのアニーリング、フッ酸系の溶媒に浸漬する方法等が挙げられる。
　また、Ｓｉ層に金属酸化物層を積層した後に、電気的な接合を確実にするためにアニール処理を行う場合、アニール温度は３００℃以下にすることが好ましい。３００℃を超えてアニールすると、金属酸化物層の酸素とＳｉとが反応し、１５．０ｎｍを超えるＳｉＯ２膜が生成する場合がある。 Examples of the method for removing the natural oxide film (SiO 2 ) include reverse sputtering, dry etching, annealing under reduced pressure / reducing atmosphere, and a method of immersing in a hydrofluoric acid solvent.
In addition, when annealing is performed to ensure electrical bonding after the metal oxide layer is stacked on the Si layer, the annealing temperature is preferably 300 ° C. or lower. When annealing is performed at a temperature exceeding 300 ° C., oxygen in the metal oxide layer and Si may react to generate a SiO 2 film exceeding 15.0 nm.
（２－２）ＭｘＯｙ層
　シリコンウェハーの場合と同様に、金属Ｍ層の表面には自然酸化膜（ＭｘＯｙ）が存在し、金属酸化物層を積層する前に、予め自然酸化膜を所定量除去する必要がある。
　自然酸化膜の厚さ、除去方法、金属酸化物層を積層後のアニール処理等は、ＳｉＯ２層の場合と同じである。 (2-2) M x O y layer As in the case of a silicon wafer, a natural oxide film (M x O y ) is present on the surface of the metal M layer. It is necessary to remove a predetermined amount of the oxide film.
The thickness of the natural oxide film, the removal method, the annealing treatment after laminating the metal oxide layer, etc. are the same as in the case of the SiO 2 layer.
（３）金属含有層
　本発明の積層体において、Ｓｉ層と金属酸化物層の間に金属含有層を設けてもよい。このようにすると、ＳｉＯ２層の厚さを０．０ｎｍ以上１５．０ｎｍ以下に制御することがより容易になる。Ｓｉ層と金属酸化物層の場合と同様に、金属Ｍ層と金属酸化物層の間にも金属含有層を設けてもよい。ＭｘＯｙ層の厚さを０．０ｎｍ以上１５．０ｎｍ以下に制御することがより容易になる。
　金属含有層の厚さは、通常、５～１００ｎｍである。 (3) Metal-containing layer In the laminate of the present invention, a metal-containing layer may be provided between the Si layer and the metal oxide layer. In this way, it becomes easier to control the thickness of the SiO 2 layer to 0.0 nm or more and 15.0 nm or less. Similarly to the case of the Si layer and the metal oxide layer, a metal-containing layer may be provided between the metal M layer and the metal oxide layer. It becomes easier to control the thickness of the M x O y layer to 0.0 nm or more and 15.0 nm or less.
The thickness of the metal-containing layer is usually 5 to 100 nm.
　金属含有層を設けた積層体の実施形態を図３，４に示す。
　積層体３において、Ｓｉ層１０上にＳｉＯ２層２０が存在し、その上に金属含有層２５が形成され、その上に金属酸化物層３０が形成されている。
　積層体４において、Ｓｉ層１０上に金属含有層２５が形成され、その上に金属酸化物層３０が形成されている。 An embodiment of a laminate provided with a metal-containing layer is shown in FIGS.
In the laminate 3, the SiO 2 layer 20 exists on the Si layer 10, the metal-containing layer 25 is formed thereon, and the metal oxide layer 30 is formed thereon.
In the stacked body 4, a metal-containing layer 25 is formed on the Si layer 10, and a metal oxide layer 30 is formed thereon.
　金属含有層に用いる材料は、導電性があれば特に制限されない。ここで、金属酸化物層に対してショットキー接続とするか、オーミック接続とするかによって適切な材料が異なるため、以下、説明する。 The material used for the metal-containing layer is not particularly limited as long as it has conductivity. Here, since an appropriate material differs depending on whether it is a Schottky connection or an ohmic connection to the metal oxide layer, a description will be given below.
（３－１）金属含有層を金属酸化物層に対してショットキー接続させる場合
　金属酸化物層に対してショットキー接続させるには、仕事関数が４．２ｅＶ～５．８ｅＶ程度の金属材料が好ましく、４．４ｅＶ～５．６ｅＶの金属材料がより好ましい。具体的には、Ｐｔ、Ａｕ、Ａｇ、Ｃｒ、Ｃｕ、Ｍｏ、Ｔｉ、Ｗ、Ｎｉ、Ｐｄ、Ｒｕ等が挙げられる。単体で密着性や耐久性に問題がある場合は、必要に応じて従来公知の合金を用いてもよい。例えば、ＡｇＰｄＣｕ、ＡｇＮｄ、ＡｇＣｅ、ＭｏＷ、ＭｏＴａ，ＭｏＮｉ等は高仕事関数で耐久性に優れた合金材料である。また、金属に限るものではなく、ＩＴＯ、ＺｎＯ、ＳｎＯ、ＩＺＯ（登録商標）等の酸化物導電体薄膜も高仕事関数電極として優れている。さらに、ＰｂＯ，ＰｔＯ，ＭｏＯ３、ＴｉＯ２などの酸化物誘電体薄膜を５ｎｍ以下で金属酸化物に接して形成すると、順方向のオン抵抗を上げずに、良好なショットキーバリアを実現することができる。 (3-1) When the metal-containing layer is Schottky connected to the metal oxide layer In order to make a Schottky connection to the metal oxide layer, a metal material having a work function of about 4.2 eV to 5.8 eV is used. A metal material of 4.4 eV to 5.6 eV is more preferable. Specifically, Pt, Au, Ag, Cr, Cu, Mo, Ti, W, Ni, Pd, Ru, etc. are mentioned. If there is a problem with adhesion and durability as a single substance, a conventionally known alloy may be used as necessary. For example, AgPdCu, AgNd, AgCe, MoW, MoTa, MoNi, etc. are alloy materials having a high work function and excellent durability. Moreover, it is not restricted to metals, and oxide conductor thin films such as ITO, ZnO, SnO, and IZO (registered trademark) are also excellent as high work function electrodes. Furthermore, when an oxide dielectric thin film such as PbO, PtO, MoO 3 , or TiO 2 is formed in contact with a metal oxide at 5 nm or less, a good Schottky barrier can be realized without increasing the on-resistance in the forward direction. Can do.
（３－２）金属含有層を金属酸化物層に対してオーミック接続させる場合
　一方、金属酸化物層に対してオーミック特性を得るには、仕事関数が通常３．５～４．３ｅＶであり、３．５～４．２ｅＶ程度の金属材料が好ましく、３．６ｅＶ～４．１ｅＶの金属材料がより好ましい。例えば、Ｈｆ，Ｉｎ，Ｍｇ，Ｚｎ，Ｔｉ，Ａｌ等の金属や、ＴｉＮ，ＭｇＡｇ，ＡｌＬｉ等の合金材料が挙げられる。仕事関数が３．５ｅＶを下回る場合は、安定性に欠ける場合が多く、注意が必要となる場合がある。仕事関数が４．２ｅＶを超えると、金属酸化物層への電子注入が阻害され、ショットキー接合になりやすいおそれがある。また、Ｔｉは密着性がよいため、同様に電子注入金属として好適である。上記のほか、金属含有層としてＩｎやＺｎを用いると、加熱により金属酸化物中の酸素と反応しても導電性が保持されるため、オーミック電極として適している。同様の理由で、ＩＴＯ、ＺｎＯ、ＳｎＯ、ＩＺＯ（登録商標）等の酸化物導電体薄膜も導電性が保持されるため、オーミック電極として適している。ただし、酸化物導電体薄膜の仕事関数は４．４ｅＶ以上が多いため、電気的に積層する酸化物半導体のフェルミレベルもそれに近い材料が好ましい。具体的には酸化物半導体を構成する材料組成はＩｎ２Ｏ３、ＺｎＯ、ＳｎＯ２を主成分とすることが好ましい。バンドギャップの広いＧａ２Ｏ３やＡｌ２Ｏ３等の酸化物材料は、酸化物半導体を構成する金属比に対して２０～５０％に抑えると、上記酸化物導電体薄膜とオーミック接合を取りやすくなる。
　金属酸化物層の上にオーミック電極を積層すると、良好な整流特性を有するダイオードを得ることができる。 (3-2) When the metal-containing layer is ohmic-connected to the metal oxide layer On the other hand, to obtain ohmic characteristics for the metal oxide layer, the work function is usually 3.5 to 4.3 eV, A metal material of about 3.5 to 4.2 eV is preferable, and a metal material of 3.6 eV to 4.1 eV is more preferable. Examples thereof include metals such as Hf, In, Mg, Zn, Ti, and Al, and alloy materials such as TiN, MgAg, and AlLi. When the work function is less than 3.5 eV, stability is often lacking, and attention may be required. When the work function exceeds 4.2 eV, electron injection into the metal oxide layer is hindered and a Schottky junction may be easily formed. Ti is also suitable as an electron injecting metal because it has good adhesion. In addition to the above, when In or Zn is used for the metal-containing layer, conductivity is maintained even if it reacts with oxygen in the metal oxide by heating, so that it is suitable as an ohmic electrode. For the same reason, an oxide conductor thin film such as ITO, ZnO, SnO, or IZO (registered trademark) is also suitable as an ohmic electrode because it retains conductivity. However, since the work function of the oxide conductor thin film is greater than or equal to 4.4 eV, a material having a Fermi level close to that of an electrically stacked oxide semiconductor is preferable. Specifically, the material composition of the oxide semiconductor is preferably mainly composed of In 2 O 3 , ZnO, and SnO 2 . When an oxide material such as Ga 2 O 3 or Al 2 O 3 having a wide band gap is suppressed to 20 to 50% with respect to the metal ratio of the oxide semiconductor, an ohmic junction is formed with the oxide conductor thin film. It becomes easy.
When an ohmic electrode is stacked on the metal oxide layer, a diode having good rectification characteristics can be obtained.
　尚、電極の仕事関数は電子注入のし易さを表す重要な指標であるが、金属酸化物層との密着性も重要である。上記の金属は単独ではマイグレーションを起こしたり、酸化したりする場合がある。例えばＡｌを用いるとヒロック等の不具合が生じやすいので、ＮｄやＣｅ等従来公知の添加金属により防止することができる。また、Ａｌに微量のＬｉを混ぜると仕事関数を大きく下げることができ、本発明のワイドギャップ金属酸化物の電子注入金属として好適である。
　仕事関数は、大気中光電子分光装置（例えば、理研計器製ＡＣ－３）を用いて測定する。 The work function of the electrode is an important index indicating the ease of electron injection, but the adhesion with the metal oxide layer is also important. The above metal alone may cause migration or oxidation. For example, when Al is used, defects such as hillocks are likely to occur, and can be prevented by conventionally known additive metals such as Nd and Ce. In addition, when a small amount of Li is mixed with Al, the work function can be greatly lowered, which is suitable as the electron-injecting metal of the wide gap metal oxide of the present invention.
The work function is measured using an atmospheric photoelectron spectrometer (for example, AC-3 manufactured by Riken Keiki Co., Ltd.).
　金属含有層を金属酸化物層に対してオーミック接合させる場合は、金属酸化物がシリコン又は金属Ｍと直接接しないので、アニール温度は３００℃を超えても構わない。ただし、金属含有層の金属種によっては加熱により凹凸が発生し、絶縁破壊電界の低下を招くので、アニール温度は材料によって適宜選択される。 When the metal-containing layer is ohmic-bonded to the metal oxide layer, the annealing temperature may exceed 300 ° C. because the metal oxide is not in direct contact with silicon or the metal M. However, depending on the metal species of the metal-containing layer, unevenness is generated by heating, leading to a decrease in the dielectric breakdown electric field, so the annealing temperature is appropriately selected depending on the material.
（４）金属酸化物層
　金属酸化物層は、１又は２以上の金属酸化物を含む層である。金属酸化物としては、Ｉｎ，Ｓｎ，Ｇｅ，Ｔｉ、Ｚｎ，Ｙ，Ｓｍ，Ｃｅ、Ｎｄ、Ｇａ又はＡｌの酸化物等が挙げられる。 (4) Metal oxide layer A metal oxide layer is a layer containing 1 or 2 or more metal oxides. Examples of the metal oxide include oxides of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, or Al.
（４－１）原子組成
　金属酸化物層を構成する金属酸化物は、下記式（１）～（３）の原子比を満たすと好ましい。このような組成であると、高耐圧、低Ｏｎ抵抗とすることができる。
０　　　≦　ｘ／（ｘ＋ｙ＋ｚ）　≦　０．５　（１）
０　　　≦　ｙ／（ｘ＋ｙ＋ｚ）　≦　０．８　（２）
０．２　≦　ｚ／（ｘ＋ｙ＋ｚ）　≦　１．０　（３）
（式中、ｘ、ｙ及びｚは、それぞれ下記の元素から選ばれる１種以上の原子数を表す。
ｘ＝Ｉｎ，Ｓｎ，Ｇｅ，Ｔｉ
ｙ＝Ｚｎ，Ｙ，Ｓｍ，Ｃｅ，Ｎｄ
ｚ＝Ｇａ，Ａｌ） (4-1) Atomic composition The metal oxide constituting the metal oxide layer preferably satisfies the atomic ratios of the following formulas (1) to (3). With such a composition, a high breakdown voltage and a low On resistance can be obtained.
0 ≦ x / (x + y + z) ≦ 0.5 (1)
0 ≦ y / (x + y + z) ≦ 0.8 (2)
0.2 ≦ z / (x + y + z) ≦ 1.0 (3)
(In the formula, x, y and z each represent the number of one or more atoms selected from the following elements.
x = In, Sn, Ge, Ti
y = Zn, Y, Sm, Ce, Nd
z = Ga, Al)
　ｚが０．２を下回ると、金属酸化物中の酸素が脱離しやすくなり、電気的特性のバラつきの原因となる。ｘの濃度が０．５を超えると、ｘがＩｎ又はＳｎの場合は金属酸化物の絶縁性が低くなり、ショットキー接合が得にくくなるおそれがある。ｘがＧｅ又はＴｉの場合は、金属酸化物の絶縁性が高くなり、オーム損による発熱の原因となるおそれがある。
　金属酸化物の組成は、ＩＣＰ（Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）発光分析装置やＸＲＦ（（Ｘ－ｒａｙ　Ｆｌｕｏｒｅｓｃｅｎｃｅ　Ａｎａｌｙｓｉｓ，）又はＳＩＭＳ（Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）によって測定する。 When z is less than 0.2, oxygen in the metal oxide is easily desorbed, which causes variations in electrical characteristics. When the concentration of x exceeds 0.5, when x is In or Sn, the insulating property of the metal oxide is lowered, and it may be difficult to obtain a Schottky junction. When x is Ge or Ti, the insulating property of the metal oxide is increased, which may cause heat generation due to ohmic loss.
The composition of the metal oxide is measured by an ICP (Inductively Coupled Plasma) emission analyzer, XRF ((X-ray Fluorescence Analysis,) or SIMS (Secondary Ion Mass Spectrometry).
　上記の組成範囲（１）及び（３）は、より好ましくはそれぞれ下記式（１’）及び（３’）で表される。
０　　　≦　ｘ／（ｘ＋ｙ＋ｚ）　≦　０．２５　（１’）
０．３　≦　ｚ／（ｘ＋ｙ＋ｚ）　≦　１．０　　（３’）
（式中、ｘ、ｙ及びｚは上記と同じである。） The composition ranges (1) and (3) are more preferably represented by the following formulas (1 ′) and (3 ′), respectively.
0 ≦ x / (x + y + z) ≦ 0.25 (1 ′)
0.3 ≦ z / (x + y + z) ≦ 1.0 (3 ′)
(Wherein x, y and z are the same as above)
（４－２）結晶構造等
　金属酸化物層を構成する金属酸化物は、非晶質でも結晶質でもよく、結晶は、微結晶でも単結晶でもよいが、金属酸化物は非晶質又は微結晶構造が好ましい。単結晶でもよいが、金属酸化物を単結晶にするには、種結晶を起点として結晶成長させるか、ＭＢＥ（分子線エピタキシー）やＰＬＤ（パルスレーザー堆積）等の方法を用いる必要がある。ＳｉＯ２表面や金属表面上で結晶成長させると、結晶欠陥が発生しやすく、縦方向に電気を流すデバイスとして使用した時に、この結晶欠陥が不具合の原因となるおそれがある。ＳｉＯ２表面や金属表面上で結晶成長させる場合は、粒径が大きくなりすぎないように、加熱温度、時間等を適切に調整する必要がある。 (4-2) Crystal structure and the like The metal oxide constituting the metal oxide layer may be amorphous or crystalline, and the crystal may be microcrystalline or single crystal, but the metal oxide may be amorphous or microcrystalline. A crystal structure is preferred. Although a single crystal may be used, in order to convert a metal oxide into a single crystal, it is necessary to grow a crystal starting from a seed crystal, or to use a method such as MBE (molecular beam epitaxy) or PLD (pulse laser deposition). When a crystal is grown on the SiO 2 surface or metal surface, crystal defects are likely to occur, and when used as a device for flowing electricity in the vertical direction, the crystal defects may cause a defect. When crystal growth is performed on the SiO 2 surface or metal surface, it is necessary to appropriately adjust the heating temperature, time, and the like so that the particle size does not become too large.
　一方、非晶質であれば、未結合手が存在しても結晶欠陥として存在しないため、電気特性のバラつきや大幅な特性劣化を緩和することができる。さらに金属酸化物はＳｉ半導体等の共有結合と異なりイオン結合性が強いため、未結合手によってできる準位は導電帯や充満体に近い。従って、金属酸化物は、ＳｉやＳｉＣ等と比較して、構造による移動度等の電気特性の差が小さい。金属酸化物のこのような性質を積極的に利用すると、単結晶に拘らずとも、高耐圧で信頼性の高い大電流ダイオードやスイッチング素子を高い歩留まりで提供することができる。 On the other hand, if it is amorphous, even if dangling bonds exist, it does not exist as a crystal defect, so that variation in electric characteristics and significant characteristic deterioration can be alleviated. Furthermore, since metal oxides have strong ionic bonding properties unlike covalent bonds such as Si semiconductors, the levels generated by dangling bonds are close to conductive bands and filled bodies. Accordingly, the metal oxide has a smaller difference in electrical characteristics such as mobility depending on the structure as compared with Si, SiC, and the like. If such a property of the metal oxide is positively used, a high-current diode and a switching element with high breakdown voltage and high reliability can be provided with a high yield regardless of a single crystal.
　ここで、「非晶質」とは、金属酸化物層が例えば四角形の場合は、対角線の交点と、交点と各頂点の中間点の計５点を電子線回折で評価した場合に、電子線回折のスポットサイズを膜厚の８０％として得られた回折像に明確なスポットが確認できないものを言う。また、「非晶質」は一部に結晶化や微結晶化した部分がある場合も含む。一部結晶化した部分に電子線を照射すると、回折像が認められることがある。
　「微結晶構造」とは、結晶粒径のサイズがサブミクロン以下であり、明解な粒界が存在しないものを言う。
　「多結晶」とは、結晶粒径のサイズがミクロンサイズを超え、明解な粒界が存在するものを言う。 Here, the term “amorphous” means that when the metal oxide layer is, for example, a quadrangle, an electron beam diffraction is performed when a total of five points of the intersection of the diagonal lines and the intermediate point between the intersection and each vertex are evaluated by electron beam diffraction. This means that a clear spot cannot be confirmed in a diffraction image obtained by setting the diffraction spot size to 80% of the film thickness. In addition, “amorphous” includes a case where a part is crystallized or microcrystallized. When a partially crystallized portion is irradiated with an electron beam, a diffraction image may be observed.
“Microcrystalline structure” refers to a crystal grain size that is submicron or smaller and has no clear grain boundaries.
“Polycrystalline” refers to a crystal grain size exceeding micron size and having clear grain boundaries.
　例えば、ダイオードに求められる性質は、高速スイッチングや高耐圧、低Ｏｎ抵抗であるが、本発明の積層体を用いればこれらの特性を両立することができる。本発明で用いる金属酸化物は元来バンドギャップが広く、高耐圧であるからである。また、酸素欠損によりｎ型になりやすく、ｐ型ができにくいことも高速スイッチングに向いている。 For example, the properties required for a diode are high-speed switching, high breakdown voltage, and low On resistance, but these characteristics can be achieved by using the laminate of the present invention. This is because the metal oxide used in the present invention originally has a wide band gap and a high breakdown voltage. In addition, it tends to be n-type due to oxygen vacancies and is difficult to form p-type, which is suitable for high-speed switching.
　Ｏｎ抵抗を下げるには移動度を高める必要があるため結晶化させるとよいが、結晶粒界ができない程度に止める方がよい。結晶粒界にはしばしばポアが存在し、電界がかかった時に分極が生じ、この分極が耐圧性能を低下させるおそれがある。耐電圧の低下が著しい場合は、非晶質のままで用いる方が好ましい。非晶質として用いる場合は、金属酸化物層を形成する元素の種類にもよるが、加熱処理条件を例えば２００℃以下、１時間以内に設定すればよい。２００℃以下の低温で加熱することで、安定な非晶質状態を得ることができる。 It is better to crystallize because it is necessary to increase the mobility in order to reduce the On resistance, but it is better to stop it to such an extent that no crystal grain boundary is formed. There are often pores in the grain boundaries, and polarization occurs when an electric field is applied, and this polarization may reduce pressure resistance. When the withstand voltage is remarkably lowered, it is preferable to use it as it is. When used as an amorphous material, the heat treatment conditions may be set to, for example, 200 ° C. or less and within 1 hour, although depending on the type of element forming the metal oxide layer. A stable amorphous state can be obtained by heating at a low temperature of 200 ° C. or lower.
　金属酸化物層の室温におけるキャリア濃度は、好ましくは１×１０１４ｃｍ－３～１×１０１７ｃｍ－３であり、より好ましくは２×１０１４ｃｍ－３～５×１０１６ｃｍ－３である。この範囲であれば、良好なダイオード特性を示すことができる。キャリア濃度が１×１０１４ｃｍ－３未満の場合、オン抵抗が高くなりすぎ、動作時に発熱を招き、好ましくない。キャリア濃度が１×１０１７ｃｍ－３を超えた場合、抵抗が低くなりすぎ、逆バイアス時のリーク電流が上昇するおそれがある。 The carrier concentration of the metal oxide layer at room temperature is preferably 1 × 10 14 cm −3 to 1 × 10 17 cm −3 , more preferably 2 × 10 14 cm −3 to 5 × 10 16 cm −3 . is there. If it is this range, a favorable diode characteristic can be shown. When the carrier concentration is less than 1 × 10 14 cm −3 , the on-resistance becomes too high, and heat is generated during operation, which is not preferable. When the carrier concentration exceeds 1 × 10 17 cm −3 , the resistance becomes too low, and the leakage current at the time of reverse bias may increase.
　キャリア濃度は、Ｃ－Ｖ評価によって測定する。
　Ｃ－Ｖ評価は、下記式を用いて、Ｃ－２τｓＶの傾きからＮ（キャリア濃度）を求める。
Ｃ＝｛ｑεＮ／２（φ－Ｖ）｝１／２
　各記号は下記を意味する。
Ｃ：金属と金属酸化物の接合容量
q：電荷素量
ε：金属酸化物の誘電率
φ：金属と金属酸化物の接合による内蔵電位
Ｖ：印加電圧 The carrier concentration is measured by CV evaluation.
In the CV evaluation, N (carrier concentration) is obtained from the slope of C −2 τsV using the following formula.
C = {qεN / 2 (φ−V)} 1/2
Each symbol means the following.
C: Junction capacity of metal and metal oxide
q: Elementary amount of charge ε: Dielectric constant of metal oxide φ: Built-in potential at junction of metal and metal oxide V: Applied voltage
　尚、Ｓｉ層、ＳｉＯ２層、中間金属層の何れかに接する側の金属酸化物界面は、部分的にキャリア濃度を多くすることで、オーミック特性にしやすくなる。具体的なキャリア濃度は１×１０１７ｃｍ－３～１×１０２２ｃｍ－３以下が好ましい。キャリア濃度を多くする方法は、酸素欠損を増加させる方法やドーピング濃度を増加させる方法が挙げられる。金属Ｍ層、ＭｘＯｙ層、中間金属層の何れかに接する側の金属酸化物界面も同様である。
　酸素欠損を増加させる方法としては、酸化物半導体の成膜時に、酸素が不足した状態で成膜する方法、還元雰囲気で加熱する方法等が挙げられる。
　ドーピング濃度を増加させる方法は、主に多結晶の酸化物半導体を使用して、ドーパントを活性化させる方法である。例えば、Ｔｉ，Ｓｉ，Ｇｅ，Ｓｎ等の４価の元素を０．１～１０％の範囲でターゲット材料に最初から混入させるか、イオンドーピングにより混入させ、アニールするとよい。 Note that the metal oxide interface on the side in contact with any one of the Si layer, the SiO 2 layer, and the intermediate metal layer is likely to have ohmic characteristics by partially increasing the carrier concentration. The specific carrier concentration is preferably 1 × 10 17 cm −3 to 1 × 10 22 cm −3 or less. Examples of the method for increasing the carrier concentration include a method for increasing oxygen vacancies and a method for increasing the doping concentration. The same applies to the metal oxide interface on the side in contact with any of the metal M layer, M x O y layer, and intermediate metal layer.
As a method for increasing oxygen vacancies, a method of forming a film in a state where oxygen is insufficient when forming an oxide semiconductor, a method of heating in a reducing atmosphere, and the like can be given.
The method of increasing the doping concentration is a method of activating the dopant mainly using a polycrystalline oxide semiconductor. For example, a tetravalent element such as Ti, Si, Ge, or Sn may be mixed into the target material from the beginning in the range of 0.1 to 10%, or may be mixed by ion doping and annealed.
　金属酸化物層の成膜方法は特に制限されず、公知の方法を用いることができる。特に膜厚を１μｍ以上にしたい場合は、スパッタリング法以外に、ドクターブレード法，射出法，押出し法，熱間加圧法等のセラミックスの製法や、イオンプレーティング法、エアルゾルデポジション法等、厚膜に適した従来公知の製法を利用することができる。 The method for forming the metal oxide layer is not particularly limited, and a known method can be used. In particular, when it is desired to increase the film thickness to 1 μm or more, in addition to the sputtering method, ceramic methods such as doctor blade method, injection method, extrusion method, hot pressing method, ion plating method, aerosol deposition method, etc. A conventionally known production method suitable for the above can be used.
　本発明に用いる金属酸化物の絶縁破壊電界は、通常、０．５～３．０ＭＶ／ｃｍであり、従来のシリコン系ダイオードと比較して非常に優れた性能を有する。
　例えば、単結晶のβ―Ｇａ２Ｏ３では理論的な絶縁破壊電界が８．０ＭＶ／ｃｍ以上であることが知られている（ＡＰＥＸ５－２０１２－０３５５０２）が、微小な欠陥やボイド等が存在すると大きく低下する。これは、バルク中の微小な欠陥やボイドが存在すると、電界をかけたときに分極が生じ、そこを起点に絶縁破壊しやすくなるためである。本発明で用いる酸化物半導体が非晶質又は微結晶構造である場合、原理的に微小な欠陥やボイドが存在しないため、単結晶による理論値には及ばないが、それに準ずる大きな絶縁破壊電界を歩留まりよく得ることができる。 The dielectric breakdown electric field of the metal oxide used in the present invention is usually 0.5 to 3.0 MV / cm, and has very excellent performance as compared with a conventional silicon diode.
For example, single-crystal β-Ga 2 O 3 is known to have a theoretical breakdown electric field of 8.0 MV / cm or more (APEX5-2012-035502), but there are minute defects, voids, etc. Then it is greatly reduced. This is because if there are minute defects or voids in the bulk, polarization occurs when an electric field is applied, and dielectric breakdown is likely to start from there. In the case where the oxide semiconductor used in the present invention has an amorphous or microcrystalline structure, since there are no minute defects or voids in principle, it does not reach the theoretical value by a single crystal, but a large dielectric breakdown electric field equivalent to that is applied. It can be obtained with good yield.
　金属酸化物層の膜厚は、耐圧、用途や目的に応じて異なり、６０Ｖ耐圧では０．２μｍ～１．２μｍ、６００Ｖ耐圧では２μｍ～１２μｍが好ましい。 The film thickness of the metal oxide layer varies depending on the withstand voltage, application and purpose, and is preferably 0.2 μm to 1.2 μm for the 60V withstand voltage and 2 μm to 12 μm for the 600V withstand voltage.
（５）表面金属層
　Ｓｉ層、ＳｉＯ２層、中間金属層の何れかと接する金属酸化物層の界面がショットキー接続の場合、金属酸化物層の上にオーミック電極を積層すると良好な整流特性を有するダイオードを得ることができる。オーミック接続とする場合の材料等の条件は上記（３－２）と同様である。また、ショットキー接続とする場合、材料等の条件は上記（３－１）と同様である。
　金属Ｍ層、ＭｘＯｙ層、中間金属層の何れかと接する金属酸化物層の場合も上記と同様である。 (5) Surface metal layer When the interface of the metal oxide layer in contact with any one of the Si layer, the SiO 2 layer, and the intermediate metal layer is a Schottky connection, good rectification characteristics can be obtained by stacking an ohmic electrode on the metal oxide layer. A diode having the same can be obtained. The conditions for the material and the like for the ohmic connection are the same as in (3-2) above. In the case of Schottky connection, the conditions for materials and the like are the same as in (3-1) above.
The same applies to the metal oxide layer in contact with any of the metal M layer, M x O y layer, and intermediate metal layer.
　表面金属層を設けた場合の実施形態を図５に示す。
　積層体５において、Ｓｉ層１０、ＳｉＯ２層２０及び金属酸化物層３０の上に、表面金属層４０が設けられている。尚、表面金属層４０以外の積層体の構成については、上記で説明した通り種々の構成とすることができる。例えば、ＳｉＯ２層２０はなくてもよく、金属含有層を設けてもよい。 An embodiment in which a surface metal layer is provided is shown in FIG.
In the stacked body 5, the surface metal layer 40 is provided on the Si layer 10, the SiO 2 layer 20, and the metal oxide layer 30. In addition, about the structure of laminated bodies other than the surface metal layer 40, it can be set as various structures as demonstrated above. For example, the SiO 2 layer 20 may not be provided, and a metal-containing layer may be provided.
２．素子、電気回路等
　本発明の積層体を含む素子は、多様な電気回路や電器機器、車両等に用いることができる。特に、ダイオードや縦型ＭＯＳＦＥＴを得るための基板として最適である。本発明の積層体を用いたダイオードは、高耐圧かつ高速スイッチングを実現できる。以下、これらについて説明する。 2. Element, Electric Circuit, etc. The element including the laminate of the present invention can be used for various electric circuits, electric appliances, vehicles and the like. In particular, it is optimal as a substrate for obtaining a diode or a vertical MOSFET. A diode using the laminate of the present invention can achieve high breakdown voltage and high-speed switching. Hereinafter, these will be described.
（１）ショットキーバリアダイオード
　ダイオードにはその用途に応じて、ショットキーバリアダイオードと、ＰＮダイオードに２分される。一般にシリコンを用いたショットキーバリアダイオードはユニポーラであり、高速スイッチングが可能であるが耐圧に劣る。逆にシリコンを用いたＰＮダイオードはバイポーラであり、高速スイッチングは劣るが、耐圧性に優れる。 (1) Schottky barrier diode A diode is divided into a Schottky barrier diode and a PN diode according to the application. In general, a Schottky barrier diode using silicon is unipolar and can perform high-speed switching, but is inferior in breakdown voltage. Conversely, a PN diode using silicon is bipolar, and high-speed switching is inferior, but it has excellent withstand voltage.
　本発明の積層体を用いて作製したダイオードは、酸化物半導体を用いるためユニポーラであり、バンドギャップが広い。従って、シリコンでは実現の難しかった高速スイッチングと高耐圧を両立することができる。
　ＳｉＣやＧａＮの場合、いずれも欠陥の少ない単結晶を効率よく得ることは困難であり、歩留まりにも問題があった。この点で本発明の積層体を用いたダイオードは製造歩留まりも高く、産業的に有効である。 A diode manufactured using the stacked body of the present invention is unipolar because an oxide semiconductor is used, and has a wide band gap. Therefore, it is possible to achieve both high-speed switching and high breakdown voltage, which are difficult to realize with silicon.
In the case of SiC or GaN, it is difficult to efficiently obtain a single crystal with few defects, and there is a problem in yield. In this respect, a diode using the laminate of the present invention has a high manufacturing yield and is industrially effective.
　ダイオードとしての性能や安定性をさらに高めるためには、従来公知の保護膜やガードリング構造、メサ構造、フィールドプレート構造、及びフィールドストップ構造を使用することができる。具体的には、金属酸化物層の露出部分をＳｉＯ２等でパッシベーションすることで、表面準位の形成を抑制し、電流コラプスと呼ばれる順方向電流の低下現象を低減することができる。また、金属酸化物層にガードリング層を埋め込むことで、逆方向サージ電圧が防護される電圧範囲を超えた場合に、ダイオードの破損のおそれがあるアバランシェ降伏を抑制することができる。 In order to further improve the performance and stability as a diode, a conventionally known protective film, guard ring structure, mesa structure, field plate structure, and field stop structure can be used. Specifically, the exposed portion of the metal oxide layer is passivated with SiO 2 or the like, so that the formation of surface states can be suppressed and the forward current reduction phenomenon called current collapse can be reduced. Further, by embedding the guard ring layer in the metal oxide layer, it is possible to suppress avalanche breakdown that may damage the diode when the reverse surge voltage exceeds the voltage range to be protected.
　本発明に積層体の使用される金属酸化物層がｎ型である場合、ガードリング層はｐ型か、ｉ型半導体を用いることが好ましい。ガードリング層によって逆方向バイアス時に接合界面端部の電界集中を緩和することができ、耐圧を上げることができる。
　ｐ型層は従来公知のｐ型半導体としてＢ，Ａｌ，Ｇａ，ＩｎをドープしたＳｉを用いてもよいし、ＮｉＯやＣｕＯ、もしくはＣｕＴＭＯ２（ＴＭ：３ｄ遷移金属）で表されるｐ型酸化物半導体を用いることができる。
　また、ガードリングはその効果を上げるために、２重、３重に設計してもよい。ここでｐ型半導体は正孔を流すものではなく、高移動度は必要としない。 When the metal oxide layer used in the laminate in the present invention is n-type, the guard ring layer is preferably p-type or i-type semiconductor. The guard ring layer can alleviate electric field concentration at the junction interface edge during reverse bias, and can increase the breakdown voltage.
The p-type layer may be a conventionally known p-type semiconductor using Si doped with B, Al, Ga, In, or p-type oxidation represented by NiO, CuO, or CuTMO 2 (TM: 3d transition metal). A physical semiconductor can be used.
The guard ring may be designed to be double or triple in order to increase the effect. Here, the p-type semiconductor does not flow holes and does not require high mobility.
　Ｓｉ層、ＳｉＯ２層、中間金属層の何れかと接する金属酸化物の界面がショットキー接続の場合は、先にガードリング層を形成し、次に金属酸化物層を積層すればよい。また、Ｓｉ層、ＳｉＯ２層、中間金属層の何れかと接する金属酸化物の界面がオーミック接続の場合は、先に金属酸化物層を成膜し、ガードリング状にエッチングした後、ｐ型もしくはｉ型半導体を成膜する。次にＣＭＰ等により表面を研摩後、オーミック接続となる表面金属層を成膜すればよい。
　金属Ｍ層、ＭｘＯｙ層、中間金属層の何れかと接する金属酸化物の場合も上記と同様である。 When the interface of the metal oxide in contact with any one of the Si layer, the SiO 2 layer, and the intermediate metal layer is a Schottky connection, a guard ring layer is formed first, and then the metal oxide layer is stacked. If the interface of the metal oxide in contact with any one of the Si layer, the SiO 2 layer, and the intermediate metal layer is in ohmic connection, the metal oxide layer is first formed, etched into a guard ring shape, and then p-type or An i-type semiconductor is formed. Next, after polishing the surface by CMP or the like, a surface metal layer that forms an ohmic connection may be formed.
The same applies to a metal oxide in contact with any of the metal M layer, M x O y layer, and intermediate metal layer.
　これら保護膜及びガードリング層は、スパッタリング、イオンプレーティング、ＰＥＣＶＤ等の真空プロセス、印刷、塗布熱分解、ミストＣＶＤ、ゾルゲル等の湿式プロセス等、従来公知の成膜法で形成することができる。また、ガードリングに関しては所望とする領域にｐ型となるＣｕやＮｉ等の元素をイオン注入してもよい。形成にあたっては、エリアマスクを用いてもよいし、従来公知のフォトリソ法を用いることができる。パターニング技術についても、従来公知のウェットエッチング、ドライエッチングが使用できる。保護膜及びガードリング層の形成にあたっては、加工精度と材質によって適宜最適なプロセスを組み合せて実施すればよい。 These protective film and guard ring layer can be formed by a conventionally known film forming method such as a vacuum process such as sputtering, ion plating or PECVD, a wet process such as printing, coating pyrolysis, mist CVD or sol-gel. As for the guard ring, p-type elements such as Cu and Ni may be ion-implanted into a desired region. In the formation, an area mask may be used, or a conventionally known photolithography method may be used. Also for the patterning technique, conventionally known wet etching and dry etching can be used. In forming the protective film and the guard ring layer, an optimum process may be appropriately combined depending on processing accuracy and material.
　保護膜及び／又はガードリングを設けた場合の実施形態を図６～８に示す。
　積層体６において、金属酸化物層３０及び表面金属層４０の上に、これらを覆うように保護膜５０が設けられている。積層体７において、金属酸化物層３０の上面側にガードリング６０が埋め込まれている。また、積層体８において、金属酸化物層３０の下面側にガードリング６０が埋め込まれている。
　尚、積層体６～８において、保護膜５０又はガードリング６０以外の積層体の構成については、上記で説明した通りであり、種々の構成とすることができる。 An embodiment in which a protective film and / or a guard ring is provided is shown in FIGS.
In the laminated body 6, a protective film 50 is provided on the metal oxide layer 30 and the surface metal layer 40 so as to cover them. In the stacked body 7, a guard ring 60 is embedded on the upper surface side of the metal oxide layer 30. In the stacked body 8, a guard ring 60 is embedded on the lower surface side of the metal oxide layer 30.
Note that in the laminates 6 to 8, the configuration of the laminate other than the protective film 50 or the guard ring 60 is as described above, and various configurations can be adopted.
　本発明の積層体を用いたショットキーバリアダイオードは、Ｓｉ層の接触抵抗を下げるために、Ｓｉの自然酸化膜を逆スパッタやフッ酸で除去した後に、裏面電極を積層するとよい。電気的な接触が良好な組み合わせとしては、Ｔｉ－Ｎｉ－Ａｕ，Ｔｉ－Ｎｉ－Ａｇ等の積層体や、ＳｉをドープしたＡｌ電極等が用いられる。このようにして得られたショットキーバリアダイオードはシリコンウェハー上に積層してなるため、ＳｉＣのように高硬度、高脆性ではない。よって、通常のダイシング技術により歩留りよく加工することができる。 In the Schottky barrier diode using the laminate of the present invention, the back electrode is preferably laminated after removing the Si native oxide film by reverse sputtering or hydrofluoric acid in order to reduce the contact resistance of the Si layer. As a combination having good electrical contact, a laminate of Ti—Ni—Au, Ti—Ni—Ag, etc., an Al electrode doped with Si, or the like is used. Since the Schottky barrier diode thus obtained is laminated on a silicon wafer, it is not as hard and brittle as SiC. Therefore, it can process with a high yield by a normal dicing technique.
（２）ＭＰＳ（Ｍｅｒｇｅｄ　Ｐｉｎ　ａｎｄ　Ｓｈｏｔｔｋｙ）ダイオード
　本発明の積層体はＭＰＳダイオードに用いることができる。ＭＰＳダイオードは、Ｐｉｎダイオードの通電能力とショットキーダイオードの高速スイッチング特性の長所を両立したダイオードである。
　Ｓｉ層、ＳｉＯ２層、中間金属層の何れかと接する金属酸化物の界面がショットキー接続の場合は、先にｐ層又はｉ層を積層・パターニングし、次に金属酸化物を積層すればよい。金属Ｍ層、ＭｘＯｙ層、中間金属層の何れかと接する金属酸化物も同様である。 (2) MPS (Merged Pin and Shotky) Diode The laminate of the present invention can be used for an MPS diode. The MPS diode is a diode that achieves both the current-carrying capability of the Pin diode and the high-speed switching characteristics of the Schottky diode.
When the interface of the metal oxide in contact with any one of the Si layer, the SiO 2 layer, and the intermediate metal layer is Schottky connection, the p layer or the i layer may be laminated and patterned first, and then the metal oxide may be laminated. . The same applies to the metal oxide in contact with any of the metal M layer, the M x O y layer, and the intermediate metal layer.
　本発明の積層体をＭＰＳとした場合の実施形態を図９に示す。
　積層体９において、ＳｉＯ２層２０の上に、複数のｐ型半導体７０が形成されている。尚、ｐ型半導体７０以外の積層体の構成については、上記で説明した通りであり、種々の構成とすることができる。 An embodiment in which the laminate of the present invention is MPS is shown in FIG.
In the stacked body 9, a plurality of p-type semiconductors 70 are formed on the SiO 2 layer 20. In addition, about the structure of laminated bodies other than the p-type semiconductor 70, it is as having demonstrated above and can be set as various structures.
　また、Ｓｉ層、ＳｉＯ２層、中間金属層の何れかと接する金属酸化物の界面がオーミック接続の場合は、先に金属酸化物層を成膜し、トレンチを掘った後に、ｐ型もしくはｉ型半導体を成膜する。次にＣＭＰ等により表面を研摩後、オーミック接続となる表面金属層を成膜すればよい。 When the interface of the metal oxide in contact with any one of the Si layer, the SiO 2 layer, and the intermediate metal layer is in ohmic connection, the metal oxide layer is first formed, and after the trench is dug, the p-type or i-type A semiconductor is formed. Next, after polishing the surface by CMP or the like, a surface metal layer that forms an ohmic connection may be formed.
　そして、このような構成とすることで、Ｏｎ抵抗が小さく、従来の絶縁破壊電界が大きい積層体を得ることがでる。この性質は、従来高圧化が困難だったＳｉショットキーバリアダイオードの耐圧領域（２００～６００Ｖ）を改善する効果がある。 And by setting it as such a structure, the laminated body with a small On-resistance and a large dielectric breakdown electric field can be obtained. This property has the effect of improving the breakdown voltage region (200 to 600 V) of the Si Schottky barrier diode, which has conventionally been difficult to increase in voltage.
　図１０は、支持基板が金属Ｍからなる場合の積層体の一実施形態を示す図である。
　積層体１０は、Ｓｉ層１０がＭｏからなる金属層１２であって、ＳｉＯ２層２０がＭｏの酸化物の層２２である他は、積層体７と同じである。Ｍｏは金属酸化物の線膨張係数に近いため、金属酸化物積層後の加熱プロセスにおいて内部応力の発生を抑制することができる。例えば、金属酸化物層３０として、ＩＧＺＯ（３３：３３：３３）を使用した場合、ＩＧＺＯの線膨張係数は６．５×１０－６／Ｋに対して、Ｍｏの線膨張係数は５．１×１０－６／Ｋと近い。このため、保護膜としてＣＶＤ工程を用いてＳｉＯ２を３００℃以上の温度で形成しても、膜はがれやクラックの発生を防止することができる。一方、支持基板としてＳｉウェハーを用いた場合、Ｓｉの線膨張係数は２．８×１０－６／Ｋと、ＩＧＺＯと比較して半分以下であり、金属酸化物層の膜はがれやクラックが発生しやすい。 FIG. 10 is a view showing an embodiment of a laminate in the case where the support substrate is made of metal M. FIG.
The laminated body 10 is the same as the laminated body 7 except that the Si layer 10 is a metal layer 12 made of Mo and the SiO 2 layer 20 is an oxide layer 22 of Mo. Since Mo is close to the linear expansion coefficient of the metal oxide, generation of internal stress can be suppressed in the heating process after the metal oxide is laminated. For example, when IGZO (33:33:33) is used as the metal oxide layer 30, the linear expansion coefficient of IGZO is 6.5 × 10 −6 / K, whereas the linear expansion coefficient of Mo is 5.1. It is close to × 10 −6 / K. For this reason, even if SiO 2 is formed at a temperature of 300 ° C. or higher by using a CVD process as a protective film, it is possible to prevent the film from peeling or cracking. On the other hand, when a Si wafer is used as the support substrate, the linear expansion coefficient of Si is 2.8 × 10 −6 / K, which is less than half that of IGZO, and the metal oxide layer is peeled off and cracks are generated. It's easy to do.
　図１１の積層体１１は、ＳｉＯ２層２０及び金属酸化物層３０の間に金属層１４及び当該金属層１４を構成する金属の酸化物層２４が積層している他は、積層体７と同じである。
　図１１に示すように、Ｓｉウェハー１０上に金属酸化物層３０を積層する場合は、間にバッファとなる金属層１４を挟む方がよい。この金属層は支持基板と金属酸化物の線膨張係数の違いによる応力を緩和するための層であり、その厚さは、金属酸化物層の厚さや組成によって適宜選択される。金属層の厚さは金属酸化物層以上の厚さであることが好ましい。
　また、Ｓｉ以外の支持基板や、バッファ層に使用する金属は、線膨張係数がＳｉよりも大きく、金属酸化物よりも小さい材料が好ましい。具体的には、Ｍｏの他、Ｔｉ，Ｃｒ，Ｎｂ、Ｔａ等が挙げられる。
　積層体１１において、ＳｉＯ２層２０及び金属層１４を構成する金属の酸化物層２４（いずれも自然酸化物層）の膜厚は、それぞれ０．０ｎｍ～１５．０ｎｍとするとよい。 11 is the same as the laminate 7 except that the metal layer 14 and the metal oxide layer 24 constituting the metal layer 14 are laminated between the SiO 2 layer 20 and the metal oxide layer 30. The same.
As shown in FIG. 11, when the metal oxide layer 30 is laminated on the Si wafer 10, it is better to sandwich the metal layer 14 serving as a buffer therebetween. This metal layer is a layer for relieving stress due to the difference in coefficient of linear expansion between the support substrate and the metal oxide, and the thickness is appropriately selected depending on the thickness and composition of the metal oxide layer. The thickness of the metal layer is preferably greater than or equal to the metal oxide layer.
Further, the metal used for the support substrate other than Si and the buffer layer is preferably a material having a linear expansion coefficient larger than that of Si and smaller than that of the metal oxide. Specific examples include Mo, Ti, Cr, Nb, Ta, and the like.
In the stacked body 11, the film thicknesses of the SiO 2 layer 20 and the metal oxide layer 24 (both natural oxide layers) constituting the metal layer 14 are preferably 0.0 nm to 15.0 nm, respectively.
　図１２及び１３は、それぞれ図１１の積層体１１の製造方法の一実施形態を示す図である。
　図１２は、金属層１４上に形成した積層体とＳｉウェハーとを接合させることで積層体を製造している。このように製造にすることで、後工程にＳｉプロセスを適用することができ、製造上有利である。図１３は金属層１４と金属酸化物層３０の積層体とＳｉ層１０をまず接合した後、表面金属層４０，保護層５０及びガードリング６０等を積層する場合である。
　接合技術には、従来公知のＳＯＩやプラズマ等がある。尚、異種金属同士の貼り合わせでは熱膨張係数の差によるワレやクラックが発生しやすくなるため、昇降温時の温度均一性を確保する必要がある。 12 and 13 are diagrams showing an embodiment of a method for manufacturing the laminate 11 of FIG.
In FIG. 12, a laminate is manufactured by bonding a laminate formed on the metal layer 14 and a Si wafer. By manufacturing in this way, the Si process can be applied to the subsequent process, which is advantageous in manufacturing. FIG. 13 shows a case where the laminate of the metal layer 14 and the metal oxide layer 30 and the Si layer 10 are first joined, and then the surface metal layer 40, the protective layer 50, the guard ring 60, and the like are laminated.
Examples of the bonding technique include conventionally known SOI and plasma. Note that cracking and cracking due to differences in thermal expansion coefficients are likely to occur when different metals are bonded together, so it is necessary to ensure temperature uniformity during temperature rise and fall.
　本発明の素子は、好ましくは非線形の電気伝導を有する。非線形の電気伝導とは、オームの法則に従わない電気伝導をいう。 The element of the present invention preferably has non-linear electrical conduction. Non-linear electrical conduction refers to electrical conduction that does not follow Ohm's law.
（３）パワーＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ－Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）
　本発明の積層体はパワーＭＯＳＦＥＴに用いることができる。パワーＭＯＳＦＥＴはキャリアの流れを酸化膜を介して電界で制御する絶縁ゲート型の電界効果トランジスタである。本発明の積層体を用いることで、電子をキャリアとするユニポーラデバイスとすることができる。 (3) Power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)
The laminate of the present invention can be used for a power MOSFET. The power MOSFET is an insulated gate field effect transistor that controls the flow of carriers with an electric field through an oxide film. By using the laminated body of this invention, it can be set as the unipolar device which uses an electron as a carrier.
　本発明の積層体をプレーナーゲート型パワーＭＯＳＦＥＴに用いた場合の一実施形態を図１４に示す。
　図１４は金属酸化物半導体を用いた縦型ＭＯＳＦＥＴの断面図を示したものである。支持基板としてｎ型Ｓｉ（Ｓｉ層１０に対応）を使用し、Ｔｉ、Ｎｉ，Ｉｎ（金属含有層２５に対応）を介してｎ型の金属酸化物半導体（金属酸化物層３０に対応）が積層されている。ＳｉウェハーとＴｉの界面はＳｉＯ２層２０が存在しても存在しなくてもよいが、存在する場合１５ｎｍ以下が必須となる。
　ｎ型Ｓｉは他方の面にはＴｉ、Ｎｉ、Ａｕ（裏面電極２６）が積層しており、当該層はドレイン電極１００（図示せず）と接している。 FIG. 14 shows an embodiment in which the laminate of the present invention is used in a planar gate type power MOSFET.
FIG. 14 is a cross-sectional view of a vertical MOSFET using a metal oxide semiconductor. An n-type Si (corresponding to the Si layer 10) is used as a support substrate, and an n-type metal oxide semiconductor (corresponding to the metal oxide layer 30) is formed via Ti, Ni, In (corresponding to the metal-containing layer 25). Are stacked. The interface between the Si wafer and Ti may or may not be present in the SiO 2 layer 20, but if it is present, 15 nm or less is essential.
In the n-type Si, Ti, Ni, Au (back electrode 26) is laminated on the other surface, and this layer is in contact with the drain electrode 100 (not shown).
　図１４において、ｎ型の金属酸化物半導体の上部はドライエッチングによりリセス（溝）を形成した後、ｐ型半導体もしくは低キャリア濃度のｎ型半導体７５を積層する。通常この領域（以下リセス領域）にはｐ型半導体が用いられるが、ワイドギャップの酸化物半導体を用いれば、ゲート８０がＯｆｆの状態でもリーク電流は小さいため、ｐ型が必須ではない。
　リセス領域に形成されるｐ型半導体もしくは低キャリア濃度のｎ型半導体７５のフェルミレベルは、本発明の積層体に用いられる酸化物半導体よりも低いことが好ましい。 In FIG. 14, a recess (groove) is formed on the upper portion of an n-type metal oxide semiconductor by dry etching, and then a p-type semiconductor or an n-type semiconductor 75 having a low carrier concentration is stacked. Normally, a p-type semiconductor is used for this region (hereinafter referred to as a recess region). However, if a wide gap oxide semiconductor is used, the leak current is small even when the gate 80 is off, so that the p-type is not essential.
The Fermi level of the p-type semiconductor or the low carrier concentration n-type semiconductor 75 formed in the recess region is preferably lower than that of the oxide semiconductor used in the stacked body of the present invention.
　リセス領域に用いられるｐ型半導体としては、ＮｉＯ、ＰｄＯ、ＣｕＯ、ホウ素ドープシリコン等、従来公知のｐ型半導体材料が使用できる。
　また、低キャリア濃度のｎ型半導体には、酸化物半導体を用いることができる。当該領域はゲートがＯｎの状態でチャネルを形成する領域のため、散乱源と成り得る遷移金属の濃度はできるだけ小さい方が好ましい。
　ゲート絶縁膜１１０を介して存在するソース電極領域９０にはＷ，Ｔｉ，Ｍｏ，Ａｌ，Ｃｒ等の従来公知の低抵抗配線材料を用いることができる。また、接触抵抗を抑制するためには成膜前にＡｒプラズマ等で還元し、接触部分だけキャリア濃度を上げる処理を行ってもよい。 As the p-type semiconductor used in the recess region, a conventionally known p-type semiconductor material such as NiO, PdO, CuO, or boron-doped silicon can be used.
An oxide semiconductor can be used for the n-type semiconductor with a low carrier concentration. Since this region is a region where a channel is formed with the gate turned on, the concentration of the transition metal that can be a scattering source is preferably as small as possible.
A conventionally known low-resistance wiring material such as W, Ti, Mo, Al, or Cr can be used for the source electrode region 90 that exists via the gate insulating film 110. Further, in order to suppress contact resistance, treatment with reducing by Ar plasma or the like before film formation and increasing the carrier concentration only at the contact portion may be performed.
　ｐ型領域、ソース電極領域ともフォトリソ技術により金属酸化物層をパターニングし、マグネトロンスパッタやプラズマＣＶＤ等の方法により形成して得られる。表面はＣＭＰ処理を行って適宜平滑にする。このようにして得たソース電極、及びｐ型もしくは低キャリア濃度ｎ型領域を具備した積層体上に絶縁膜を積層し、パターニングを行ってゲート絶縁膜とする。 Both the p-type region and the source electrode region can be obtained by patterning a metal oxide layer by photolithography and forming it by a method such as magnetron sputtering or plasma CVD. The surface is appropriately smoothed by CMP treatment. An insulating film is stacked on the stacked body including the source electrode thus obtained and the p-type or low carrier concentration n-type region, and patterned to form a gate insulating film.
　絶縁膜を構成する材料は特に制限はなく、本発明の効果を失わない範囲で一般に用いられているものを任意に選択できる。例えば、ＳｉＯ２，ＳｉＮｘ，Ａｌ２Ｏ３，Ｔａ２Ｏ５，ＴｉＯ２，ＭｇＯ，ＺｒＯ２，ＣｅＯ２，Ｋ２Ｏ，Ｌｉ２Ｏ，Ｎａ２Ｏ，Ｒｂ２Ｏ，Ｓｃ２Ｏ３，Ｙ２Ｏ３，ＨｆＯ2，ＣａＨｆＯ３，ＰｂＴｉ３，ＢａＴａ２Ｏ６，ＳｒＴｉＯ３又はＡｌＮ等の酸化物や窒化物を用いることができる。
　尚、絶縁膜に要求される項目として、膜厚ムラが小さいこと、リークの原因となるピンホールが存在しないことが重要である。一般的なゲート絶縁膜としては、ＳｉＯ２，ＳｉＮｘ，Ａｌ２Ｏ３等が用いられる。 The material forming the insulating film is not particularly limited, and any material generally used can be selected as long as the effects of the present invention are not lost. For example, SiO 2, SiN x, Al 2 O 3, Ta 2 O 5, TiO 2, MgO, ZrO 2, CeO 2, K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O 3, An oxide or nitride such as Y 2 O 3 , HfO 2 , CaHfO 3 , PbTi 3 , BaTa 2 O 6 , SrTiO 3, or AlN can be used.
It should be noted that as the items required for the insulating film, it is important that the film thickness non-uniformity is small and that there is no pinhole that causes leakage. As a general gate insulating film, SiO 2 , SiN x , Al 2 O 3 or the like is used.
　最後に、金属をスパッタして所望の形状にパターニングすることで、ソース・ゲート付の積層体を得ることができる。 Finally, a laminated body with a source and gate can be obtained by sputtering a metal and patterning it into a desired shape.
　また、ドレイン電極となる積層体の裏面側は、ＳｉＯ２等自然酸化膜ができる場合には、フッ酸や逆スパッタ等で除去後、Ｔｉ／Ｎｉ／Ａｕの順で金属を積層する。ここでＴｉは密着層、Ｎｉは拡散防止層、Ａｕは低抵抗層としての役割がある。
　このようにして得られた縦型ＭＯＳＦＥＴは、耐圧層にワイドギャップ酸化物半導体を用いているため耐圧に優れ、Ｓｉでは困難だった６００Ｖ以上の耐圧と、高速スイッチングとを両立することができる。また、チャネル抵抗部分はゲートバイアスによるｎチャネル伝導を用いるため、キャリアは高移動度の電子であり低オン抵抗を実現することができる。 Further, when a natural oxide film such as SiO 2 can be formed on the back surface side of the stacked body to be the drain electrode, after removing by hydrofluoric acid or reverse sputtering, the metal is stacked in the order of Ti / Ni / Au. Here, Ti serves as an adhesion layer, Ni serves as a diffusion prevention layer, and Au serves as a low resistance layer.
The vertical MOSFET thus obtained has a high breakdown voltage because a wide-gap oxide semiconductor is used for the breakdown voltage layer, and can achieve both a breakdown voltage of 600 V or higher, which is difficult with Si, and high-speed switching. In addition, since the channel resistance portion uses n-channel conduction by gate bias, carriers are electrons with high mobility and low on-resistance can be realized.
　本発明の積層体をトレンチゲート型パワーＭＯＳＦＥＴに用いた場合の一実施形態を図１５に示す。
　図１５は、酸化物半導体を用いたトレンチゲート型パワーＭＯＳＦＥＴの断面図を示したものである。本構造はプレーナー構造と比較して微細化が可能であり、チャネルの抵抗を下げることが可能である。トレンチの密度を上げてスーパージャンクション構造とすることもできる。
　図１５において、ｐ型半導体もしくは低キャリア濃度のｎ型半導体７５は、リセス内ではなくｎ型金属酸化物半導体３０上に形成されている。また、ｐ型半導体もしくは低キャリア濃度のｎ型半導体７５上にはソース電極９０が形成されており、当該ソース電極９０及びｐ型半導体もしくは低キャリア濃度のｎ型半導体７５を貫通してリセスが設けられ、当該リセス内にゲート絶縁膜１１０を介してゲート８０が形成されている。これら構成以外は図１４と同じである。 FIG. 15 shows an embodiment in which the laminate of the present invention is used for a trench gate type power MOSFET.
FIG. 15 shows a cross-sectional view of a trench gate type power MOSFET using an oxide semiconductor. This structure can be miniaturized as compared with the planar structure, and the resistance of the channel can be reduced. It is also possible to increase the density of the trench to obtain a super junction structure.
In FIG. 15, a p-type semiconductor or an n-type semiconductor 75 having a low carrier concentration is formed not on the recess but on the n-type metal oxide semiconductor 30. A source electrode 90 is formed on the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration, and a recess is provided through the source electrode 90 and the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration. In addition, a gate 80 is formed in the recess through a gate insulating film 110. Except for these configurations, the configuration is the same as in FIG.
　本発明の積層体を用いたプレーナーゲート型パワーＭＯＳＦＥＴのうち、ドリフト領域に金属酸化物を用い、チャネル領域に多結晶シリコンを用いた場合の一実施形態を図１６に示す。
　図１６は、ドリフト領域に金属酸化物を用い、チャネル領域に多結晶シリコンを用いることで、高耐圧と高速スイッチングを両立するパワーＭＯＳＦＥＴを示している。 FIG. 16 shows an embodiment in which a metal oxide is used for the drift region and polycrystalline silicon is used for the channel region in the planar gate type power MOSFET using the laminate of the present invention.
FIG. 16 shows a power MOSFET that achieves both high breakdown voltage and high-speed switching by using metal oxide in the drift region and polycrystalline silicon in the channel region.
　図１６において、高ドープｎ型シリコンウェハーを基板（Ｓｉ層１０に対応）として使用し、表面を希フッ酸等で処理して自然酸化膜を除去する。次にｎ型酸化物半導体（金属酸化物層３０に対応）を成膜する。ｎ型酸化物半導体を結晶化して用いる場合は、１５０～１４００℃の範囲でアニールするとよい。アニールの適正な範囲は酸化物半導体の構成元素に依存して適宜決められる。アニール温度が１４００℃を超えるとシリコンが溶解するおそれがある。アニール温度が１５０℃を下回ると結晶化が進行しないおそれがある。 In FIG. 16, a highly doped n-type silicon wafer is used as a substrate (corresponding to the Si layer 10), and the surface is treated with dilute hydrofluoric acid to remove the natural oxide film. Next, an n-type oxide semiconductor (corresponding to the metal oxide layer 30) is formed. When an n-type oxide semiconductor is used after being crystallized, it is preferably annealed in the range of 150 to 1400 ° C. An appropriate range of annealing is appropriately determined depending on the constituent elements of the oxide semiconductor. If the annealing temperature exceeds 1400 ° C., silicon may be dissolved. If the annealing temperature is below 150 ° C., crystallization may not proceed.
　アニール終了後、ｎ型酸化物半導体上にＰＥＣＶＤ等の方法でアモルファスシリコンを成膜し、パターニングを行う。パターニングはレジストを塗布後、露光、現像を行い、ハロゲン系のガスを用いてドライエッチングする。レジスト剥離後、レーザーアニール等の手法を用いて多結晶化する。次にＰＥＣＶＤ等の方法でＳｉＯ２膜１１５を成膜する。さらにこの上に金属電極をスパッタや蒸着法を用いて成膜し、ゲート電極８０の形状にパターニングする。パターニングはドライ・ウェットとも従来公知の方法が利用できるが、後述の活性化アニールを行うため、Ｗ，Ｃｒ，Ｍｏ，Ｔａ等の高融点金属が好ましい。 After the annealing is completed, an amorphous silicon film is formed on the n-type oxide semiconductor by a method such as PECVD and patterned. For patterning, after applying a resist, exposure and development are performed, and dry etching is performed using a halogen-based gas. After removing the resist, it is polycrystallized using a technique such as laser annealing. Next, a SiO 2 film 115 is formed by a method such as PECVD. Further, a metal electrode is formed thereon by sputtering or vapor deposition and patterned into the shape of the gate electrode 80. For the patterning, a conventionally known method can be used for both dry and wet, but a high melting point metal such as W, Cr, Mo, Ta or the like is preferable because activation annealing described later is performed.
　次に、このゲート電極８０越しに、イオンドーピングをｐ型Ｓｉに対して行う。イオンドーピングは絶縁膜であるＳｉＯ２膜を介したキャップ方式となるため、ドーズ量とその深さの制御はシミュレーション等で確認するとよいが、例えば、Ｐ，Ｓｂ，Ａｓ等を５０～５００ｋｅＶの加速電圧でドーズ量が１０１３～１０１４ｃｍ－２等の条件で行われる。このイオンドーピングはゲート電極８０をマスクとする自己整合技術を用いるため、プロセスを簡素化できるとともに、ゲート容量を減らし、高速スイッチング動作が可能になる。 Next, ion doping is performed on the p-type Si through the gate electrode 80. Since ion doping is a cap method through a SiO 2 film, which is an insulating film, the dose amount and its depth may be controlled by simulation or the like. For example, P, Sb, As, etc. are accelerated by 50 to 500 keV. The process is performed under the condition that the dose is 10 13 to 10 14 cm −2 or the like with voltage. Since this ion doping uses a self-alignment technique using the gate electrode 80 as a mask, the process can be simplified, the gate capacitance can be reduced, and a high-speed switching operation can be performed.
　イオンドーピング後、活性化アニールを行う。活性化アニールは電極の劣化を防止する上では、フラッシュランプアニール等の高速アニールや、レーザーアニール法が好ましい。
　アニール温度は高温ほど活性化率が上昇するが、電極の劣化を生じない範囲で適宜選択される。アニール温度は６００℃～１１００℃が好ましく、７００～１０００℃がより好ましい。このようにして、ｐ型Ｓｉ（ｐ領域）１２０の一部をｎ型化したｎ＋領域１３０することができる。 After ion doping, activation annealing is performed. Activation annealing is preferably performed by high-speed annealing such as flash lamp annealing or laser annealing in order to prevent electrode deterioration.
The annealing temperature is appropriately selected within a range in which the activation rate increases as the temperature increases, but the electrode does not deteriorate. The annealing temperature is preferably 600 ° C. to 1100 ° C., more preferably 700 to 1000 ° C. In this way, an n + region 130 in which a part of the p-type Si (p region) 120 is made n-type can be formed.
　続いてＳｉＯ２のソース電極に相当する部分にフォトリソを用いてコンタクトホールを形成し、最後にソース電極９０を形成する。
　尚、高ドープｎ型シリコンウェハー１０には、図１４及び１５と同様にＴｉ、Ｎｉ、Ａｕ（裏面電極２６）が積層しており、当該層はドレイン電極１００（図示せず）と接している。 Subsequently, a contact hole is formed in the portion corresponding to the source electrode of SiO 2 using photolithography, and finally the source electrode 90 is formed.
The highly doped n-type silicon wafer 10 is laminated with Ti, Ni, Au (back electrode 26) as in FIGS. 14 and 15, and this layer is in contact with the drain electrode 100 (not shown). .
（３）モジュール
　本発明の積層体を用いたＭＯＳＦＥＴは、従来のＳｉ系ＭＯＳＦＥＴと同様にボディーダイオードを内蔵するが、還流ダイオードと組み合わせて使用することもできる。
　図１７は、本発明の素子を組合せて構成したモジュールの一実施形態を示す図である。パワーＭＯＳＦＥＴ、還流ダイオードともに本発明の積層体を含む素子で構成されている。このモジュールは、ＭＯＳＦＥＴ、還流ダイオードともにＳｉ層及び金属酸化物層を含み、前記Ｓｉ層における前記金属酸化物層側の面上のＳｉＯ２層の膜厚が０．０ｎｍ～１５．０ｎｍである積層体からなるため、優れた電流―電圧特性、すなわち低いオン抵抗と高速スイッチングを両立することができる。 (3) Module A MOSFET using the laminated body of the present invention incorporates a body diode in the same manner as a conventional Si MOSFET, but can also be used in combination with a freewheeling diode.
FIG. 17 is a diagram showing an embodiment of a module configured by combining elements of the present invention. Both the power MOSFET and the freewheeling diode are composed of elements including the laminate of the present invention. This module includes both a MOSFET and a free-wheeling diode including a Si layer and a metal oxide layer, and the thickness of the SiO 2 layer on the surface of the Si layer on the metal oxide layer side is 0.0 nm to 15.0 nm. Since it is composed of a body, it can achieve both excellent current-voltage characteristics, that is, low on-resistance and high-speed switching.
　ここで、図１７の還流ダイオードは、Ｓｉ層側がオーミック接続（カソード）の場合とショットキー接続（アノード）とでは接続の向きが異なる。図１８は、図１７のモジュールにおいてダイオードとＭＯＳＦＥＴが、裏面金属とはんだを介して銅板に接続しており、ダイオードのＳｉウェハー側がＭＯＳＦＥＴのコレクタと接続している場合の実施形態を示す図である。Ｓｉ側がオーミック接続の場合は、Ｓｉ側がモジュールの銅板と接続される。また、図１９は、図１７のモジュールにおいてダイオードとＭＯＳＦＥＴが、裏面金属とはんだを介して銅板に接続しており、ダイオードの酸化物半導体側がＭＯＳＦＥＴのコレクタと接続している場合の実施形態を示す図である。Ｓｉ側がショットキー接続の場合は、表面金属層側がモジュールの銅板と接続される。
　なお、モジュールの構成に当たっては、従来公知のＳｉ－ＩＧＢＴ，ＳｉＣ－ＭＯＳＦＥＴ，ＧａＮ－ＭＯＳＦＥＴの過剰キャリアを除去する目的として、本発明のダイオードと組み合わせてもよい。また、本発明のＭＯＳＦＥＴの過剰キャリアを除去する目的として、従来公知の還流ダイオードを用いてもよい。 Here, the direction of connection of the free-wheeling diode of FIG. 17 differs between the case where the Si layer side is in ohmic connection (cathode) and the Schottky connection (anode). FIG. 18 is a diagram showing an embodiment in which the diode and the MOSFET in the module of FIG. 17 are connected to the copper plate via the back metal and solder, and the Si wafer side of the diode is connected to the collector of the MOSFET. . When the Si side is in ohmic connection, the Si side is connected to the copper plate of the module. FIG. 19 shows an embodiment in which the diode and the MOSFET in the module of FIG. 17 are connected to the copper plate via the back metal and solder, and the oxide semiconductor side of the diode is connected to the collector of the MOSFET. FIG. When the Si side is a Schottky connection, the surface metal layer side is connected to the copper plate of the module.
Note that the module configuration may be combined with the diode of the present invention for the purpose of removing excess carriers of conventionally known Si-IGBT, SiC-MOSFET, and GaN-MOSFET. A conventionally known free-wheeling diode may be used for the purpose of removing excess carriers in the MOSFET of the present invention.
　上記の他、本発明の素子を用いた電気回路としては、昇圧・降圧チョッパ回路、インバータ・コンバータ回路、電源回路、スイッチングレギュレータ等が挙げられ、電器機器としては、携帯電話、パソコン、エアコン、冷蔵庫、受像機、照明器具、電磁調理器等が挙げられ、車両としては、自転車、自動車、鉄道車両等が挙げられる。さらに本発明の素子は、酸素ガスセンサー、光触媒、紫外センサー、紫外太陽電池、人体センサー、紫外ダイオード、紫外レーザー等へも使用できる。 In addition to the above, examples of the electric circuit using the element of the present invention include a step-up / step-down chopper circuit, an inverter / converter circuit, a power supply circuit, a switching regulator, etc., and the electric appliances include a mobile phone, a personal computer, an air conditioner, and a refrigerator. Receivers, lighting fixtures, electromagnetic cookers, and the like, and vehicles include bicycles, automobiles, railway vehicles, and the like. Furthermore, the element of the present invention can be used for oxygen gas sensors, photocatalysts, ultraviolet sensors, ultraviolet solar cells, human body sensors, ultraviolet diodes, ultraviolet lasers, and the like.
　以下、適宜図面を参照しながら本発明の実施例を説明する。本発明は、これら実施例によってなんら限定されるものではない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings as appropriate. The present invention is not limited by these examples.
実施例１
　抵抗率０．０２Ω・ｃｍのｎ型Ｓｉ基板（直径４インチ）とスライドガラスを用意した。これらをスパッタリング装置（ＵＬＶＡＣ製：ＣＳ－２００）に装着し、最初に逆スパッタモードで１５秒処理し、自然酸化膜の一部をエッチングした。次に金属酸化物として、ＲＦ３００Ｗ、１９時間の条件でＧａ２Ｏ３を９７００ｎｍ成膜した。また、この基板をチャンバーから取り出して、電気炉によって空気中１５０℃の条件で１時間アニールした。
　スライドガラス上に成膜した素子は、ＸＲＤ装置にて構造を確認した結果、非晶質であった（図２０）。また、電子線回折を確認した結果、ハローパターンが観測され、同様に非晶質であることを確認した（図２１）。ＴＥＭにて自然酸化膜の膜厚を確認したところ、２．４ｎｍであった（図２２）。 Example 1
An n-type Si substrate (diameter 4 inches) having a resistivity of 0.02 Ω · cm and a slide glass were prepared. These were mounted in a sputtering apparatus (ULVAC: CS-200), and first treated in a reverse sputtering mode for 15 seconds to partially etch a natural oxide film. Next, 9700 nm of Ga 2 O 3 was formed as a metal oxide under the conditions of RF 300 W and 19 hours. Further, the substrate was taken out of the chamber and annealed for 1 hour in air at 150 ° C. by an electric furnace.
The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus (FIG. 20). Further, as a result of confirming the electron beam diffraction, a halo pattern was observed, and it was confirmed that it was similarly amorphous (FIG. 21). When the film thickness of the natural oxide film was confirmed by TEM, it was 2.4 nm (FIG. 22).
　次に、上記の基板を再度スパッタ装置にエリアマスクとともにセットした後、Ｔｉ、Ａｕの順に電極をスパッタ成膜した。
　このようにして得た素子（Ｓｉ／ＳｉＯ２（自然酸化膜）／Ｇａ２Ｏ３／Ｔｉ／Ａｕ）について、東陽テクニカ製ＳＣＳ－４２００を用いて評価した。評価項目は、順方向立上り電圧（Ｖｆ）、Ｏｎ電流、絶縁破壊電界（Ｖｂｄ）及びｎ値とした。尚、順方向立上り電圧（Ｖｆ）は電流密度が１０ｍＡ／ｃｍ２を超えた時の印加電圧、Ｏｎ電流は印加電圧が３Ｖの時の電流密度、絶縁破壊電界（Ｖｂｄ）はリーク電流が１０－５Ａ／ｃｍ２を超えた時の電圧とした。結果を表１に示す。 Next, the substrate was set again in the sputtering apparatus together with the area mask, and electrodes were formed by sputtering in the order of Ti and Au.
The thus-obtained element (Si / SiO 2 (natural oxide film) / Ga 2 O 3 / Ti / Au), was evaluated using a Toyo Ltd. SCS-4200. The evaluation items were forward rising voltage (Vf), On current, dielectric breakdown electric field (Vbd), and n value. The forward rising voltage (Vf) is the applied voltage when the current density exceeds 10 mA / cm 2 , the On current is the current density when the applied voltage is 3 V, and the dielectric breakdown electric field (Vbd) has a leakage current of 10 − The voltage when exceeding 5 A / cm 2 was taken. The results are shown in Table 1.
実施例２
　抵抗率０．０２Ω・ｃｍのｎ型Ｓｉ基板（直径４インチ）とスライドガラスを用意した。これらをスパッタリング装置（ＵＬＶＡＣ製：ＣＳ－２００）に装着し、最初に逆スパッタモードで５分処理し、自然酸化膜の一部をエッチングした。次に金属酸化物として、ＲＦ３００Ｗ、６時間の条件でＧａ２Ｏ３を３７００ｎｍ成膜した。また、この基板をチャンバーから取り出して、電気炉で空気中１５０℃の条件で１時間アニールした。
　スライドガラス上に成膜した素子は、ＸＲＤ装置にて構造を確認した結果、非晶質であった（図２０）。 Example 2
An n-type Si substrate (diameter 4 inches) having a resistivity of 0.02 Ω · cm and a slide glass were prepared. These were mounted in a sputtering apparatus (ULVAC: CS-200), and first treated in a reverse sputtering mode for 5 minutes to etch a part of the natural oxide film. Next, 3700 nm of Ga 2 O 3 was deposited as a metal oxide under conditions of RF 300 W and 6 hours. The substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. in air for 1 hour.
The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus (FIG. 20).
　上記の基板を再度スパッタ装置にエリアマスクとともにセットした後、ＭｇＡｇ、Ａｕの順に電極をスパッタ成膜した。
　このようにして得た素子（Ｓｉ／ＳｉＯ２（自然酸化膜）／Ｇａ２Ｏ３／ＭｇＡｇ／Ａｕ）について、東陽テクニカ製ＳＣＳ－４２００を用いて実施例１と同様に評価した。結果を表１に示す。 After the substrate was set on the sputtering apparatus together with the area mask, electrodes were formed by sputtering in the order of MgAg and Au.
The device (Si / SiO 2 (natural oxide film) / Ga 2 O 3 / MgAg / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Technica. The results are shown in Table 1.
実施例３
　抵抗率０．０２Ω・ｃｍのｎ型多結晶Ｓｉ基板（直径４インチ）とスライドガラスを用意した。これらをスパッタリング装置（ＵＬＶＡＣ製：ＣＳ－２００）に装着し、最初に逆スパッタモードで処理し、自然酸化膜の一部をエッチングした。次に金属酸化物として、ＲＦ３００Ｗ、１８分の条件でＧａ２Ｏ３を２００ｎｍ成膜した。また、この基板をチャンバーから取り出して、電気炉で空気中１５０℃の条件で１時間アニールした。
　スライドガラス上に成膜した素子は、ＸＲＤ装置にて構造を確認した結果、非晶質であった。 Example 3
An n-type polycrystalline Si substrate (diameter 4 inches) having a resistivity of 0.02 Ω · cm and a slide glass were prepared. These were mounted on a sputtering apparatus (ULVAC: CS-200), and were first processed in the reverse sputtering mode to etch a part of the natural oxide film. Next, a 200 nm film of Ga 2 O 3 was formed as a metal oxide under the conditions of RF 300 W and 18 minutes. The substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. in air for 1 hour.
The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus.
　上記の基板を再度スパッタ装置にエリアマスクとともにセットした後、Ｔｉ、Ａｕの順に電極をスパッタ成膜した。
　このようにして得た素子（Ｓｉ／ＳｉＯ２（自然酸化膜）／Ｇａ２Ｏ３／Ｔｉ／Ａｕ）について、東陽テクニカ製ＳＣＳ－４２００を用いて実施例１と同様に評価した。結果を表１に示す。 After the above substrate was set in the sputtering apparatus together with the area mask, electrodes were formed by sputtering in the order of Ti and Au.
The device (Si / SiO 2 (natural oxide film) / Ga 2 O 3 / Ti / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Technica. The results are shown in Table 1.
実施例４
　抵抗率０．０２Ω・ｃｍのｎ型多結晶Ｓｉ基板（直径４インチ）とスライドガラスを用意した。これらをスパッタリング装置（ＵＬＶＡＣ製：ＣＳ－２００）に装着し、最初に逆スパッタモードで処理し、自然酸化膜をエッチングした。次に金属酸化物として、ＲＦ３００Ｗ、９０分の条件でＩＧＯ（Ｉｎ：Ｇａ＝３０：７０）を１０００ｎｍ成膜した。
　スライドガラス上に成膜した素子は、ＸＲＤ装置にて構造を確認した結果、非晶質であった。 Example 4
An n-type polycrystalline Si substrate (diameter 4 inches) having a resistivity of 0.02 Ω · cm and a slide glass were prepared. These were installed in a sputtering apparatus (ULVAC: CS-200), and were first processed in the reverse sputtering mode to etch the natural oxide film. Next, as a metal oxide, an IGO (In: Ga = 30: 70) film having a thickness of 1000 nm was formed under conditions of RF 300 W and 90 minutes.
The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus.
　上記の基板を再度スパッタ装置にエリアマスクとともにセットした後、ＡｌＮｄ、Ａｕの順に電極をスパッタ成膜した。この基板をチャンバーから取り出して、電気炉で空気中２００℃、１時間の条件でアニールした。
　このようにして得た素子（Ｓｉ／ＳｉＯ２（自然酸化膜）／ＩＧＯ／ＡｌＮｄ／Ａｕ）について、東陽テクニカ製ＳＣＳ－４２００を用いて実施例１と同様に評価した。結果を表１に示す。 After the above substrate was set in the sputtering apparatus together with the area mask, electrodes were formed by sputtering in the order of AlNd and Au. The substrate was taken out of the chamber and annealed in an electric furnace at 200 ° C. for 1 hour in air.
The device (Si / SiO 2 (natural oxide film) / IGO / AlNd / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Technica. The results are shown in Table 1.
実施例５
　抵抗率０．００４Ω・ｃｍのｎ型高ドープ単結晶Ｓｉ基板（直径４インチ）とスライドガラスを用意した。これらをスパッタリング装置（ＵＬＶＡＣ製：ＣＳ－２００）に装着し、最初に逆スパッタモードで処理し、自然酸化膜の一部をエッチングした。次に金属酸化物として、ＲＦ１００Ｗ、２０時間の条件でＧＺＯ（Ｇａ：Ｚｎ＝７０：３０）を９７００ｎｍ成膜した。また、この基板をチャンバーから取り出して、電気炉で空気中１５０℃の条件で２時間アニールした。ガラス上に成膜した素子は、ＸＲＤ装置にて構造を確認した結果、非晶質であった。 Example 5
An n-type highly doped single crystal Si substrate (4 inches in diameter) having a resistivity of 0.004 Ω · cm and a slide glass were prepared. These were mounted on a sputtering apparatus (ULVAC: CS-200), and were first processed in the reverse sputtering mode to etch a part of the natural oxide film. Next, 9700 nm of GZO (Ga: Zn = 70: 30) was formed as a metal oxide under the conditions of RF 100 W and 20 hours. The substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. in air for 2 hours. The element formed on the glass was amorphous as a result of confirming the structure with an XRD apparatus.
　上記の基板を再度スパッタ装置にエリアマスクとともにセットした後、Ｉｎ、Ａｕの順に電極をスパッタ成膜した。この基板をチャンバーから取り出して、電気炉で空気中２００℃、１時間の条件でアニールした。
　このようにして得た素子（Ｓｉ／ＳｉＯ２（自然酸化膜）／ＧＺＯ／Ｉｎ／Ａｕ）について、東陽テクニカ製ＳＣＳ－４２００を用いて実施例１と同様に評価した。結果を表１に示す。 After the substrate was set on the sputtering apparatus together with the area mask, electrodes were formed by sputtering in the order of In and Au. The substrate was taken out of the chamber and annealed in an electric furnace at 200 ° C. for 1 hour in air.
The device (Si / SiO 2 (natural oxide film) / GZO / In / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Technica. The results are shown in Table 1.
実施例６
　抵抗率０．０２Ω・ｃｍのｎ型Ｓｉ基板（直径４インチ）を用意した。このＳｉウェハーをスパッタリング装置（ＵＬＶＡＣ製：ＣＳ－２００）に装着し、最初に逆スパッタモードで自然酸化膜をエッチングした。次にＭｏを１５ｎｍ成膜し、さらにＧａ２Ｏ３を１０００ｎｍ成膜した。この基板をチャンバーから取り出して、電気炉で空気中１５０℃の条件で１時間アニールした。
　次に、残りの基板を再びチャンバーに戻し、所望のパターンを有するエリアマスクをセットした後、Ｔｉ、Ａｕの順に電極をスパッタ成膜した。
　このようにして得た素子（Ｓｉ／Ｍｏ／Ｇａ２Ｏ３／Ｔｉ／Ａｕ）について、東陽テクニカ製ＳＣＳ－４２００を用いて実施例１と同様に評価した。結果を表１に示す。 Example 6
An n-type Si substrate (4 inches in diameter) having a resistivity of 0.02 Ω · cm was prepared. This Si wafer was mounted on a sputtering apparatus (ULVAC: CS-200), and the natural oxide film was first etched in the reverse sputtering mode. Then 15nm deposited Mo, was further 1000nm deposited Ga 2 O 3. The substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. in air for 1 hour.
Next, the remaining substrate was returned to the chamber again, and after setting an area mask having a desired pattern, electrodes were formed by sputtering in the order of Ti and Au.
The device (Si / Mo / Ga 2 O 3 / Ti / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Technica. The results are shown in Table 1.
実施例７～１４、比較例１、２
　以下、Ｓｉ基板、逆スパッタ条件、金属含有層材料、金属酸化物層材料を表１のように変更しながら、実施例６と同様に積層体を作製し、各種特性を評価した。結果を表１に示す。また、実施例７、８の基板はＴＥＭ測定を行った。基板の断面図を図２２に示す。
　尚、比較例２では金属酸化物層の代わりにＳｉＣ層（Ｓｉ：Ｃ（原子比）＝５０：５０）を設けた。 Examples 7 to 14, Comparative Examples 1 and 2
Hereinafter, while changing the Si substrate, the reverse sputtering condition, the metal-containing layer material, and the metal oxide layer material as shown in Table 1, a laminate was produced in the same manner as in Example 6, and various characteristics were evaluated. The results are shown in Table 1. Further, the substrates of Examples 7 and 8 were subjected to TEM measurement. A cross-sectional view of the substrate is shown in FIG.
In Comparative Example 2, an SiC layer (Si: C (atomic ratio) = 50: 50) was provided instead of the metal oxide layer.
実施例１５、１６、比較例３、４
　基板、逆スパッタ条件、金属酸化物層材料などを表１のように変更しながら、実施例１と同様に積層体を作製し、各種特性を評価した。結果を表１に示す。尚、実施例１５及び比較例３の金属酸化物層の成膜方法である「イオンプレーティング」は、具体的には以下のように実施した。原料としてＩｎ：Ｇａ：Ｚｎ＝３３：３３：３３のＩＧＺＯタブレット（φ２０×５ｔ）を１０個、昭和真空社のイオンプレーティング装置ＳＩＰ－８００にセットし、真空引き後、電子ビームのパワーを１０ｋＷとし、酸素分圧５０％として、厚さ５０００ｎｍのＩＧＺＯ膜を得た。
　また、実施例１５及び比較例３では基板としてＭｏ基板を用いた。従って、実施例１５及び比較例３で逆エッチングした自然酸化膜はＳｉＯ２層ではなくＭｏＯｘ層である。 Examples 15 and 16, Comparative Examples 3 and 4
While changing the substrate, reverse sputtering conditions, metal oxide layer material and the like as shown in Table 1, a laminate was prepared in the same manner as in Example 1, and various characteristics were evaluated. The results are shown in Table 1. The “ion plating” which is a method for forming the metal oxide layer of Example 15 and Comparative Example 3 was specifically performed as follows. Ten IGZO tablets (φ20 × 5t) of In: Ga: Zn = 33: 33: 33 as raw materials were set in the ion plating apparatus SIP-800 of Showa Vacuum, and the power of the electron beam was 10 kW after evacuation. Then, an IGZO film having a thickness of 5000 nm was obtained with an oxygen partial pressure of 50%.
In Example 15 and Comparative Example 3, a Mo substrate was used as the substrate. Therefore, the natural oxide film reverse-etched in Example 15 and Comparative Example 3 is not a SiO 2 layer but a MoOx layer.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
実施例１７
　図２３に示すプロセスでショットキーバリアダイオードを製造した。具体的には、抵抗率０．０２Ω・ｃｍのｎ型Ｓｉ基板（直径４インチ）を用意した。このＳｉウェハーを熱酸化炉に入れて１００ｎｍの熱酸化膜を形成した。次に、レジスト塗布後、フォトマスクを用いて露光、現像、エッチングを行ってコンタクトホールを形成した。さらにその上に、Ｐｄターゲットを用いてスパッタリング法により、Ｐｄ及びＰｄＯの順にそれぞれ１０ｎｍずつ成膜した。そして、ＳｉＯ２上のＰｄ／ＰｄＯ積層部分を同心円状に残るように王水を用いてエッチングして、ガードリングを形成した。さらにその上に、酸化物半導体であるＩＧＺＯを２００ｎｍ成膜して、耐圧層を形成するとともに、Ｍｏを成膜し、最後に空気中、３００℃、１時間の条件でアニールした。Ｓｉウェハーの裏面に存在する熱酸化膜は、表面を保護膜で覆った後に、希フッ酸でエッチングして除去した。その後、Ｔｉ，Ｎｉ，Ａｕの順序で成膜した。
　得られた積層体のＳｉウェハー側をショットキー接合とし、ガードリング並びに裏面電極付のショットキーバリアダイオードを得た。
　このようにして得られたショットキーバリアダイオードのＳｉとＰｄの界面のＳｉＯ２の膜厚を評価したところ０．２ｎｍであった。なお、コンタクトホールは円形であり、円の中心と円に内接する正方形の各頂点の中間点の計５点を観察し、その視野を等間隔に１０等分する箇所で測定し、その計５５か所の平均値をＳｉＯ２層の膜厚とした。 Example 17
A Schottky barrier diode was manufactured by the process shown in FIG. Specifically, an n-type Si substrate (4 inches in diameter) having a resistivity of 0.02 Ω · cm was prepared. This Si wafer was put into a thermal oxidation furnace to form a 100 nm thermal oxide film. Next, after applying the resist, exposure, development, and etching were performed using a photomask to form contact holes. Further thereon, 10 nm each of Pd and PdO films were formed by sputtering using a Pd target. Then, a Pd / PdO laminated portion on SiO 2 was etched using aqua regia so as to remain concentrically, thereby forming a guard ring. Further thereon, an oxide semiconductor, IGZO, was formed to a thickness of 200 nm to form a pressure-resistant layer, and Mo was formed, and finally annealed in air at 300 ° C. for 1 hour. The thermal oxide film present on the back surface of the Si wafer was removed by etching with dilute hydrofluoric acid after the surface was covered with a protective film. Thereafter, films were formed in the order of Ti, Ni, and Au.
The Si wafer side of the obtained laminate was used as a Schottky junction to obtain a Schottky barrier diode with a guard ring and a back electrode.
The thickness of the SiO 2 film at the interface between Si and Pd of the Schottky barrier diode thus obtained was evaluated to be 0.2 nm. Note that the contact hole is circular, and a total of five points, the center of the circle and the midpoint of each vertex of the square inscribed in the circle, are observed, and the field of view is measured at equally spaced intervals of 10 to obtain a total of 55 The average value of the places was taken as the film thickness of the SiO 2 layer.
実施例１８
　膜厚５００μｍ、直径４インチφのＴｉ板を支持体として準備した。このＴｉウェハー上にＩｎを５０ｎｍ成膜した。次に、酸化物半導体としてＩＧＺＯ（Ｉｎ：Ｇａ：Ｚｎ＝４０：４０：２０　ａｔ％）をスパッタ法を用いて４μｍ成膜した。次に、ＳｉＯ２膜をプラズマＣＶＤ法を用いて１００ｎｍ成膜した。このＳｉＯ２／ＩＧＺＯ／Ｉｎ／Ｔｉ積層体にレジストを塗布し、フォトマスクを用いて露光、現像後、ドライエッチングによりＳｉＯ２の一部にコンタクトホールを形成した。エッチングガスにはＣＦ４を用いた。
　続いてショットキー電極として、Ｐｄを１００ｎｍ積層し、ＣＭＰによりＳｉＯ２面が現れるまで、周辺のＰｄ層を研摩した。このようにして得たダイオードのＴｉ基板側の裏面とｎ型Ｓｉ基板（直径４インチ）を、常温ウェハー接合装置にセットして接合した。
　得られたショットキーダイオードは、途中にプラズマＣＶＤによる３００℃を超える工程を経るが、支持体としてインジウムガリウム亜鉛酸化物（ＩＧＺＯ）の線膨張係数に近いＴｉを用いており、反りやクラックの発生は認められなかった。ＴｉとＩＧＺＯとの界面に存在するＴｉＯ２の膜厚を実施例１７と同様の評価法で測定したところ、０．５ｎｍであった。
　また、ＴｉとＳｉとを貼り合わせることにより、ダイシング、はんだづけ、アルミワイヤボンディング等の後工程は、従来のＳｉ系ショットキーダイオードの工程をそのまま使用することができ、生産上有利である。 Example 18
A Ti plate having a thickness of 500 μm and a diameter of 4 inches was prepared as a support. An In film of 50 nm was formed on this Ti wafer. Next, IGZO (In: Ga: Zn = 40: 40: 20 at%) was formed as an oxide semiconductor to a thickness of 4 μm by a sputtering method. Next, a SiO 2 film was formed to a thickness of 100 nm using a plasma CVD method. A resist was applied to this SiO 2 / IGZO / In / Ti laminate, and after exposure and development using a photomask, contact holes were formed in a part of SiO 2 by dry etching. The etching gas used CF 4.
Subsequently, 100 nm of Pd was stacked as a Schottky electrode, and the surrounding Pd layer was polished until the SiO 2 surface appeared by CMP. The back surface of the diode thus obtained on the Ti substrate side and the n-type Si substrate (4 inches in diameter) were set and bonded to a room temperature wafer bonding apparatus.
The resulting Schottky diode undergoes a process exceeding 300 ° C. by plasma CVD in the middle, but uses Ti that is close to the linear expansion coefficient of indium gallium zinc oxide (IGZO) as a support and generates warpage and cracks. Was not recognized. When the film thickness of TiO 2 present at the interface between Ti and IGZO was measured by the same evaluation method as in Example 17, it was 0.5 nm.
Further, by bonding Ti and Si, the subsequent processes such as dicing, soldering, and aluminum wire bonding can use the conventional Si-based Schottky diode process as it is, which is advantageous in production.
　本発明の積層体を含む素子は、ショットキーバリアダイオードやＭＯＳＦＥＴなどのパワーデバイスやそれらを組み合わせたモジュールとして使用できる。具体的には、インバータやコンバータ等の電力変換回路、電源回路、並びにそれらを使用した電気回路パワコン、ＩＰＭ、電器機器や車両に使用できる。またさらに、酸素ガスセンサー、光触媒、紫外センサー、紫外太陽電池、人体センサー、紫外ダイオード、紫外レーザー等にも使用できる。 The element including the laminate of the present invention can be used as a power device such as a Schottky barrier diode or a MOSFET or a module combining them. Specifically, it can be used for power conversion circuits such as inverters and converters, power supply circuits, and electric circuit power conditioners, IPMs, electric appliances and vehicles using them. Furthermore, it can be used for oxygen gas sensors, photocatalysts, ultraviolet sensors, ultraviolet solar cells, human body sensors, ultraviolet diodes, ultraviolet lasers, and the like.
　上記に本発明の実施形態及び／又は実施例を幾つか詳細に説明したが、当業者は、本発明の新規な教示及び効果から実質的に離れることなく、これら例示である実施形態及び／又は実施例に多くの変更を加えることが容易である。従って、これらの多くの変更は本発明の範囲に含まれる。
　本願のパリ優先の基礎となる日本出願明細書の内容を全てここに援用する。 Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will appreciate that these exemplary embodiments and / or embodiments are substantially without departing from the novel teachings and advantages of the present invention. It is easy to make many changes to the embodiment. Accordingly, many of these modifications are within the scope of the present invention.
All the contents of the Japanese application specification that is the basis of the priority of Paris in this application are incorporated herein.

Claims (13)

  1. 　Ｓｉ層及び金属酸化物層を含み、前記Ｓｉ層における前記金属酸化物層側の面上のＳｉＯ２層の膜厚が０．０ｎｍ～１５．０ｎｍである積層体。 A laminate comprising a Si layer and a metal oxide layer, wherein the SiO 2 layer on the surface of the Si layer on the metal oxide layer side has a thickness of 0.0 nm to 15.0 nm.
  2. 　前記Ｓｉ層と前記金属酸化物層の間に金属含有層を含む請求項１に記載の積層体。 The laminate according to claim 1, comprising a metal-containing layer between the Si layer and the metal oxide layer.
  3. 　前記金属酸化物層が非晶質又は微結晶構造である請求項１又は２に記載の積層体。 The laminate according to claim 1 or 2, wherein the metal oxide layer has an amorphous or microcrystalline structure.
  4. 　前記金属酸化物層の組成比（原子比）が下記式（１）～（３）を満たす請求項１～３のいずれかに記載の積層体。
    ０　　　≦　ｘ／（ｘ＋ｙ＋ｚ）　≦　０．５　（１）
    ０　　　≦　ｙ／（ｘ＋ｙ＋ｚ）　≦　０．８　（２）
    ０．２　≦　ｚ／（ｘ＋ｙ＋ｚ）　≦　１．０　（３）
    （式中、ｘ、ｙ及びｚは、それぞれ下記の元素から選ばれる１種以上の原子数を表す。
    ｘ＝Ｉｎ，Ｓｎ，Ｇｅ，Ｔｉ
    ｙ＝Ｚｎ，Ｙ，Ｓｍ，Ｃｅ，Ｎｄ
    ｚ＝Ｇａ，Ａｌ）     The laminate according to any one of claims 1 to 3, wherein a composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3).
    0 ≦ x / (x + y + z) ≦ 0.5 (1)
    0 ≦ y / (x + y + z) ≦ 0.8 (2)
    0.2 ≦ z / (x + y + z) ≦ 1.0 (3)
    (In the formula, x, y and z each represent the number of one or more atoms selected from the following elements.
    x = In, Sn, Ge, Ti
    y = Zn, Y, Sm, Ce, Nd
    z = Ga, Al)
  5. 　前記金属酸化物層のキャリア濃度が１×１０１４ｃｍ－３～１×１０１７ｃｍ－３である請求項１～４のいずれかに記載の積層体。 The laminate according to any one of claims 1 to 4, wherein a carrier concentration of the metal oxide layer is 1 × 10 14 cm -3 to 1 × 10 17 cm -3 .
  6. 　前記Ｓｉ層の仕事関数が３．９ｅＶ～５．０ｅＶである請求項１～５のいずれかに記載の積層体。 The laminate according to any one of claims 1 to 5, wherein a work function of the Si layer is 3.9 eV to 5.0 eV.
  7. 　前記金属含有層の仕事関数が３．５ｅＶ～５．８ｅＶである請求項２～６のいずれかに記載の積層体。 The laminate according to any one of claims 2 to 6, wherein a work function of the metal-containing layer is 3.5 eV to 5.8 eV.
  8. 　金属層及び金属酸化物層を含み、
    　前記金属層が、前記金属酸化物層を構成する金属酸化物の金属とは異なる金属Ｍからなり、
    　前記金属層における前記金属酸化物層側の面上のＭＸＯＹ層（ｘ及びｙはそれぞれ整数）の膜厚が０．０ｎｍ～１５．０ｎｍである積層体。     Including a metal layer and a metal oxide layer;
    The metal layer is made of a metal M different from the metal of the metal oxide constituting the metal oxide layer;
    A laminate in which the M X O Y layer (x and y are integers) on the surface of the metal layer on the metal oxide layer side has a thickness of 0.0 nm to 15.0 nm.
  9. 　前記金属酸化物層の組成比（原子比）が下記式（１）～（３）を満たす請求項８に記載の積層体。
    ０　　　≦　ｘ／（ｘ＋ｙ＋ｚ）　≦　０．５　（１）
    ０　　　≦　ｙ／（ｘ＋ｙ＋ｚ）　≦　０．８　（２）
    ０．２　≦　ｚ／（ｘ＋ｙ＋ｚ）　≦　１．０　（３）
    （式中、ｘ、ｙ及びｚは、それぞれ下記の元素から選ばれる１種以上の原子数を表す。
    ｘ＝Ｉｎ，Ｓｎ，Ｇｅ，Ｔｉ
    ｙ＝Ｚｎ，Ｙ，Ｓｍ，Ｃｅ，Ｎｄ
    ｚ＝Ｇａ，Ａｌ）     The laminate according to claim 8, wherein a composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3).
    0 ≦ x / (x + y + z) ≦ 0.5 (1)
    0 ≦ y / (x + y + z) ≦ 0.8 (2)
    0.2 ≦ z / (x + y + z) ≦ 1.0 (3)
    (In the formula, x, y and z each represent the number of one or more atoms selected from the following elements.
    x = In, Sn, Ge, Ti
    y = Zn, Y, Sm, Ce, Nd
    z = Ga, Al)
  10. 　請求項１～９のいずれかに記載の積層体を含む素子。 An element comprising the laminate according to any one of claims 1 to 9.
  11. 　非線形の電気伝導を有する請求項１０に記載の素子。 The device according to claim 10, which has non-linear electrical conduction.
  12. 　請求項１０又は１１に記載の素子を含む電気回路又はセンサー。 An electric circuit or sensor comprising the element according to claim 10 or 11.
  13. 　請求項１０又は１１に記載の素子を含む電器機器又は車両。

          The electrical equipment or vehicle containing the element of Claim 10 or 11.

PCT/JP2015/005605 2014-11-11 2015-11-10 Novel laminate WO2016075927A1 (en)

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