WO2016075927A1 - Nouveau laminé - Google Patents

Nouveau laminé Download PDF

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Publication number
WO2016075927A1
WO2016075927A1 PCT/JP2015/005605 JP2015005605W WO2016075927A1 WO 2016075927 A1 WO2016075927 A1 WO 2016075927A1 JP 2015005605 W JP2015005605 W JP 2015005605W WO 2016075927 A1 WO2016075927 A1 WO 2016075927A1
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layer
metal
metal oxide
laminate
oxide layer
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PCT/JP2015/005605
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English (en)
Japanese (ja)
Inventor
重和 笘井
絵美 川嶋
紘美 早坂
義弘 上岡
雅敏 柴田
矢野　公規
井上　一吉
隆司 関谷
勇輝 霍間
基浩 竹嶋
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出光興産株式会社
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Priority to JP2016558887A priority Critical patent/JP6803232B2/ja
Publication of WO2016075927A1 publication Critical patent/WO2016075927A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a laminate, an element including the laminate, an electric circuit including the element, an electric appliance, and a vehicle.
  • SiC or GaN is epitaxially grown on an inexpensive Si wafer substrate
  • Patent Documents 1 to 3 the crystal structure suitable as a power semiconductor is 4H—SiC.
  • the lattice mismatch is large, it is extremely difficult to grow epitaxially on Si.
  • 3C—SiC it can be epitaxially grown by performing fine processing on the Si wafer or by using the Si (211) plane, but it has been difficult to obtain a thick film that can be applied to a power device.
  • GaN is not as high as SiC in terms of mismatch between Si and lattice, crystal growth is difficult unless a buffer layer such as AlN is used.
  • a sapphire substrate with a close lattice constant is a promising candidate, but it cannot flow in the vertical direction and cannot be used for large current applications. Therefore, in order to use a conductive substrate such as Si, it is necessary to go through a process of laminating a buffer layer on the substrate and further growing a crystal of GaN. However, even with this, it was difficult to obtain perfect crystals.
  • the present invention has been made in view of such problems, and has excellent current-voltage characteristics by controlling a natural oxide film to a specific thickness or less and forming a metal oxide having a wide band gap thereon. It aims at providing the laminated body which exhibits.
  • a laminate comprising a Si layer and a metal oxide layer, wherein the SiO 2 layer on the surface of the Si layer on the metal oxide layer side has a thickness of 0.0 nm to 15.0 nm.
  • the laminate according to 1 comprising a metal-containing layer between the Si layer and the metal oxide layer. 3.
  • the laminate according to 1 or 2 wherein the metal oxide layer has an amorphous or microcrystalline structure. 4).
  • 4. The laminate according to any one of 1 to 3, wherein the composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3).
  • x, y and z each represent the number of one or more atoms selected from the following elements.
  • the metal oxide layer has a carrier concentration of 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 . 6).
  • the metal layer is made of a metal M different from the metal of the metal oxide constituting the metal oxide layer;
  • a laminate in which the M X O Y layer (x and y are integers) on the surface of the metal layer on the metal oxide layer side has a thickness of 0.0 nm to 15.0 nm. 9.
  • a laminate capable of exhibiting excellent current-voltage characteristics can be provided.
  • the natural oxide film By controlling the natural oxide film to a specific thickness or less and forming a metal oxide having a wide band gap thereon, excellent current-voltage characteristics can be exhibited.
  • the metal oxide can be formed by a method that is inexpensive and excellent in mass productivity, the productivity can be significantly improved as compared with the conventional case.
  • It is a diagram showing an embodiment of the laminate of the present invention (Si layer / SiO 2 layer / metal oxide layer). It is a figure which shows one Embodiment (Si layer / metal oxide layer) of the laminated body of this invention. It is a diagram showing an embodiment of the laminate of the present invention (Si layer / SiO 2 layer / intermediate metal layer (metal containing layer) / metal oxide layer). It is a figure which shows one Embodiment (Si layer / intermediate metal layer / metal oxide layer) of the laminated body of this invention. It is a diagram showing an embodiment (Si layer / SiO 2 layer / metal oxide layer / upper metal (surface metal layer)) of the laminate of the present invention.
  • FIG. 1 It is a diagram showing an embodiment of the laminate of the present invention (Si layer / SiO 2 layer / metal oxide layer / upper metal / protective film).
  • the laminate of the present invention is a diagram showing a. Is a diagram showing an embodiment (Si layer / SiO 2 layer / metal oxide layer (guard ring embedded) / upper metal / protective film on the lower electrode side) of the laminate of the present invention. It is a figure which shows one Embodiment (MPS diode) of the laminated body of this invention.
  • FIG. 1 shows an embodiment of a laminate of the present invention (Si layer / SiO 2 layer / metal M layer / M x O y layer / metal oxide layer (guard ring embedded on the upper electrode side) / upper metal / protective film).
  • FIG. It is a figure which shows one Embodiment of the manufacturing method of the laminated body of this invention. It is a figure which shows one Embodiment of the manufacturing method of the laminated body of this invention.
  • FIG. 18 is a diagram showing an embodiment in which the diode and the MOSFET in the module of FIG.
  • FIG. 17 are connected to the copper plate via the back metal and solder, and the Si wafer side of the diode is connected to the collector of the MOSFET.
  • FIG. 18 is a diagram showing an embodiment in which a diode and a MOSFET are connected to a copper plate via a back metal and solder in the module of FIG. 17, and the oxide semiconductor side of the diode is connected to a collector of the MOSFET.
  • 4 is an electron diffraction image of a 9700 nm-thick Ga 2 O 3 film obtained in Example 1.
  • FIG. 2 is a TEM image of the SiO 2 portion at the Si layer interface of the laminate obtained in Examples 1, 7, and 8.
  • FIG. It is a figure which shows a manufacturing process of the Schottky barrier diode manufactured in Example 15.
  • the 1st laminated body of this invention contains Si layer and an oxide metal layer.
  • the film thickness of the SiO 2 layer on the surface of the Si layer on the metal oxide layer side is 0.0 nm to 15.0 nm. That is, the SiO 2 layer may or may not exist. Even if a natural oxide film having a specific thickness is present on an inexpensive Si substrate, the first laminate of the present invention has excellent current-voltage by forming a compound semiconductor having a wide band gap on the natural oxide film. The characteristics can be realized.
  • the second laminate of the present invention includes a metal layer and a metal oxide layer.
  • the metal layer is made of a metal M different from the metal of the metal oxide constituting the metal oxide layer.
  • the thickness of the M x O y layer (x and y are integers) on the surface of the metal layer on the metal oxide layer side is 0.0 nm to 15.0 nm.
  • the M x O y layer is a layer made of an oxide of metal M, and the M x O y layer may or may not exist.
  • the second laminate of the present invention is the same as the first laminate except that the Si layer of the first laminate is a metal M layer, and a natural oxide film having a specific thickness exists on the metal M layer. Even so, an excellent current-voltage characteristic can be realized by forming a compound semiconductor with a wide band gap on it.
  • the first laminate of the present invention and the second laminate of the present invention may be collectively referred to as the laminate of the present invention.
  • the laminated body 1 shows an embodiment in which the laminated body of the present invention has an SiO 2 layer.
  • the SiO 2 layer 20 exists on the Si layer 10 (substrate), and the metal oxide layer 30 is formed thereon.
  • the laminated body 2 shows an embodiment in which an SiO 2 layer is not included, and a metal oxide layer 30 is formed on the Si layer 10 (substrate).
  • 1 and 2 are drawings corresponding to the first laminate of the present invention, but also correspond to the second laminate of the present invention. Specifically, in FIGS. 1 and 2, a metal M layer is used instead of the Si layer 10, and an M x O y layer is used instead of the SiO 2 layer 20. The same applies to FIGS. 3 to 9 described later.
  • each layer used for a laminated body is demonstrated.
  • the Si layer is not particularly limited, and a silicon wafer may be used, or a Si film formed on a suitable base material such as glass by sputtering or CVD. Good. Moreover, it may be doped.
  • the silicon wafer may have either a single crystal structure or a polycrystalline structure.
  • a Czochralski method, a floating zone method, or the like can be used, and a conventionally known silicon wafer substrate can be used as it is.
  • n-type, i-type, and p-type silicon wafers depending on the presence / absence and type of doping
  • n-type or p-type with low electrical resistance is preferable for flowing a current in the vertical direction.
  • Conventionally known B, P, Sb and the like can be used as the dopant.
  • As or red phosphorus may be used as a dopant.
  • the thickness of the Si layer is not limited and is usually 200 to 1000 ⁇ m. However, if the resistance in the vertical direction is to be lowered, it may be polished by a CMP method or the like. When warping of the substrate becomes a problem, a TAIKO type structure that leaves the outer peripheral portion can be used. Polishing may be performed before or after the metal oxide is laminated.
  • the work function of the Si layer is preferably 3.9 eV to 5.0 eV, and more preferably 4.0 eV to 4.5 eV.
  • the work function of the Si layer is measured by an atmospheric photoelectron spectrometer (for example, Riken Keiki AC-3).
  • the metal M constituting the metal M layer is not particularly limited as long as it is a metal different from the metal oxide metal constituting the metal oxide layer.
  • the metal M may have high surface smoothness, and when the thickness of the metal oxide layered thereon exceeds 1 ⁇ m, a material close to the linear expansion coefficient of the metal oxide is preferable.
  • the metal M is preferably a metal having a linear expansion coefficient in the range of 4 to 10 ⁇ 10 ⁇ 6 K ⁇ 1 , and the metal is one or more metals selected from Ti, Cr, Nb, Mo, and Ta. Is mentioned.
  • the linear expansion coefficient of the oxide used for the substrate of the present invention is, for example, in the range of 5 ⁇ 10 ⁇ 6 to 8 ⁇ 10 ⁇ 6 K ⁇ 1 . For this reason, when heated in a subsequent process, warping may occur if the linear expansion coefficients differ greatly. Specifically, when the linear expansion coefficient of the metal M is smaller than 4 ⁇ 10 ⁇ 6 K ⁇ 1, the metal oxide layer has a compressive stress, and the linear expansion coefficient of the metal M is 10 ⁇ 10 ⁇ 6 K ⁇ 1 . When it is too large, tensile stress is applied. However, when the metal M is a low-melting-point metal or a highly reactive metal, there is a risk of contamination in the manufacturing process of the laminate.
  • Examples of such a metal include Ga, Hg, Cs, K, and Na.
  • the metal M is different from the metal of the metal oxide composing the metal oxide layer, but “different” here means that the metal M and the metal of the metal oxide layer are completely different.
  • the metal of the physical layer is an alloy composed of two or more metals, the metal M and the alloy may partially match.
  • the thickness of the SiO 2 layer is from 0.0 nm to 15.0 nm, preferably from 0.0 nm to 8.0 nm, more preferably from 0.0 nm to 4.0 nm. More preferably, it is 0.0 nm or more and 2.5 nm or less, and particularly preferably 0.0 nm or more and 1.5 nm or less. A thinner SiO 2 layer is preferable.
  • the film thickness of the SiO 2 layer is measured by TEM (transmission electron microscope).
  • Measurement points in the case of the SiO 2 layer, for example a square, a diagonal line of intersection, the intersection and the field of five points of the midpoint of each vertex observed, measured at the point of 10 equally dividing its field of view at regular intervals
  • the average value of 55 places in total is the film thickness of the SiO 2 layer.
  • a natural oxide film exists on the surface of a silicon wafer. Therefore, when a metal oxide is laminated on a Si substrate, an SiO 2 film usually exists at the interface between the Si layer and the metal oxide layer. However, when the thickness of the SiO 2 film exceeds 15.0 nm, When current is passed, it acts as a clear electric resistance component. To the thickness of the SiO 2 film below 15.0nm usually before stacking the metal oxide layer, it is necessary to preliminarily remove the natural oxide film a predetermined amount.
  • Examples of the method for removing the natural oxide film (SiO 2 ) include reverse sputtering, dry etching, annealing under reduced pressure / reducing atmosphere, and a method of immersing in a hydrofluoric acid solvent.
  • the annealing temperature is preferably 300 ° C. or lower.
  • oxygen in the metal oxide layer and Si may react to generate a SiO 2 film exceeding 15.0 nm.
  • a natural oxide film (M x O y ) is present on the surface of the metal M layer. It is necessary to remove a predetermined amount of the oxide film.
  • the thickness of the natural oxide film, the removal method, the annealing treatment after laminating the metal oxide layer, etc. are the same as in the case of the SiO 2 layer.
  • a metal-containing layer may be provided between the Si layer and the metal oxide layer. In this way, it becomes easier to control the thickness of the SiO 2 layer to 0.0 nm or more and 15.0 nm or less.
  • a metal-containing layer may be provided between the metal M layer and the metal oxide layer. It becomes easier to control the thickness of the M x O y layer to 0.0 nm or more and 15.0 nm or less.
  • the thickness of the metal-containing layer is usually 5 to 100 nm.
  • the SiO 2 layer 20 exists on the Si layer 10
  • the metal-containing layer 25 is formed thereon
  • the metal oxide layer 30 is formed thereon.
  • a metal-containing layer 25 is formed on the Si layer 10
  • a metal oxide layer 30 is formed thereon.
  • the material used for the metal-containing layer is not particularly limited as long as it has conductivity.
  • an appropriate material differs depending on whether it is a Schottky connection or an ohmic connection to the metal oxide layer, a description will be given below.
  • a metal material having a work function of about 4.2 eV to 5.8 eV is used.
  • a metal material of 4.4 eV to 5.6 eV is more preferable.
  • Pt, Au, Ag, Cr, Cu, Mo, Ti, W, Ni, Pd, Ru, etc. are mentioned.
  • a conventionally known alloy may be used as necessary.
  • AgPdCu, AgNd, AgCe, MoW, MoTa, MoNi, etc. are alloy materials having a high work function and excellent durability.
  • oxide conductor thin films such as ITO, ZnO, SnO, and IZO (registered trademark) are also excellent as high work function electrodes.
  • oxide dielectric thin film such as PbO, PtO, MoO 3 , or TiO 2 is formed in contact with a metal oxide at 5 nm or less, a good Schottky barrier can be realized without increasing the on-resistance in the forward direction. Can do.
  • the work function is usually 3.5 to 4.3 eV, A metal material of about 3.5 to 4.2 eV is preferable, and a metal material of 3.6 eV to 4.1 eV is more preferable. Examples thereof include metals such as Hf, In, Mg, Zn, Ti, and Al, and alloy materials such as TiN, MgAg, and AlLi.
  • the work function is less than 3.5 eV, stability is often lacking, and attention may be required.
  • the work function of the oxide conductor thin film is greater than or equal to 4.4 eV
  • a material having a Fermi level close to that of an electrically stacked oxide semiconductor is preferable.
  • the material composition of the oxide semiconductor is preferably mainly composed of In 2 O 3 , ZnO, and SnO 2 .
  • an oxide material such as Ga 2 O 3 or Al 2 O 3 having a wide band gap is suppressed to 20 to 50% with respect to the metal ratio of the oxide semiconductor, an ohmic junction is formed with the oxide conductor thin film. It becomes easy.
  • an ohmic electrode is stacked on the metal oxide layer, a diode having good rectification characteristics can be obtained.
  • the work function of the electrode is an important index indicating the ease of electron injection, but the adhesion with the metal oxide layer is also important.
  • the above metal alone may cause migration or oxidation.
  • defects such as hillocks are likely to occur, and can be prevented by conventionally known additive metals such as Nd and Ce.
  • the work function can be greatly lowered, which is suitable as the electron-injecting metal of the wide gap metal oxide of the present invention.
  • the work function is measured using an atmospheric photoelectron spectrometer (for example, AC-3 manufactured by Riken Keiki Co., Ltd.).
  • the annealing temperature may exceed 300 ° C. because the metal oxide is not in direct contact with silicon or the metal M.
  • the annealing temperature is appropriately selected depending on the material.
  • Metal oxide layer A metal oxide layer is a layer containing 1 or 2 or more metal oxides.
  • the metal oxide include oxides of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, or Al.
  • the composition of the metal oxide is measured by an ICP (Inductively Coupled Plasma) emission analyzer, XRF ((X-ray Fluorescence Analysis,) or SIMS (Secondary Ion Mass Spectrometry).
  • ICP Inductively Coupled Plasma
  • XRF X-ray Fluorescence Analysis
  • SIMS Secondary Ion Mass Spectrometry
  • composition ranges (1) and (3) are more preferably represented by the following formulas (1 ′) and (3 ′), respectively. 0 ⁇ x / (x + y + z) ⁇ 0.25 (1 ′) 0.3 ⁇ z / (x + y + z) ⁇ 1.0 (3 ′) (Wherein x, y and z are the same as above)
  • the metal oxide constituting the metal oxide layer may be amorphous or crystalline, and the crystal may be microcrystalline or single crystal, but the metal oxide may be amorphous or microcrystalline.
  • a crystal structure is preferred.
  • a single crystal may be used, in order to convert a metal oxide into a single crystal, it is necessary to grow a crystal starting from a seed crystal, or to use a method such as MBE (molecular beam epitaxy) or PLD (pulse laser deposition).
  • MBE mo beam epitaxy
  • PLD pulse laser deposition
  • the metal oxide has strong ionic bonding properties unlike covalent bonds such as Si semiconductors, the levels generated by dangling bonds are close to conductive bands and filled bodies. Accordingly, the metal oxide has a smaller difference in electrical characteristics such as mobility depending on the structure as compared with Si, SiC, and the like. If such a property of the metal oxide is positively used, a high-current diode and a switching element with high breakdown voltage and high reliability can be provided with a high yield regardless of a single crystal.
  • amorphous means that when the metal oxide layer is, for example, a quadrangle, an electron beam diffraction is performed when a total of five points of the intersection of the diagonal lines and the intermediate point between the intersection and each vertex are evaluated by electron beam diffraction. This means that a clear spot cannot be confirmed in a diffraction image obtained by setting the diffraction spot size to 80% of the film thickness.
  • amorphous includes a case where a part is crystallized or microcrystallized. When a partially crystallized portion is irradiated with an electron beam, a diffraction image may be observed.
  • Microcrystalline structure refers to a crystal grain size that is submicron or smaller and has no clear grain boundaries.
  • Polycrystalline refers to a crystal grain size exceeding micron size and having clear grain boundaries.
  • the properties required for a diode are high-speed switching, high breakdown voltage, and low On resistance, but these characteristics can be achieved by using the laminate of the present invention.
  • the metal oxide used in the present invention originally has a wide band gap and a high breakdown voltage.
  • it tends to be n-type due to oxygen vacancies and is difficult to form p-type, which is suitable for high-speed switching.
  • the heat treatment conditions may be set to, for example, 200 ° C. or less and within 1 hour, although depending on the type of element forming the metal oxide layer. A stable amorphous state can be obtained by heating at a low temperature of 200 ° C. or lower.
  • the carrier concentration of the metal oxide layer at room temperature is preferably 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 , more preferably 2 ⁇ 10 14 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 . is there. If it is this range, a favorable diode characteristic can be shown.
  • the carrier concentration is less than 1 ⁇ 10 14 cm ⁇ 3 , the on-resistance becomes too high, and heat is generated during operation, which is not preferable.
  • the carrier concentration exceeds 1 ⁇ 10 17 cm ⁇ 3 , the resistance becomes too low, and the leakage current at the time of reverse bias may increase.
  • the carrier concentration is measured by CV evaluation.
  • N carrier concentration
  • C ⁇ q ⁇ N / 2 ( ⁇ V) ⁇ 1/2
  • C ⁇ q ⁇ N / 2 ( ⁇ V) ⁇ 1/2
  • the metal oxide interface on the side in contact with any one of the Si layer, the SiO 2 layer, and the intermediate metal layer is likely to have ohmic characteristics by partially increasing the carrier concentration.
  • the specific carrier concentration is preferably 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 22 cm ⁇ 3 or less.
  • the method for increasing the carrier concentration include a method for increasing oxygen vacancies and a method for increasing the doping concentration.
  • the metal oxide interface on the side in contact with any of the metal M layer, M x O y layer, and intermediate metal layer As a method for increasing oxygen vacancies, a method of forming a film in a state where oxygen is insufficient when forming an oxide semiconductor, a method of heating in a reducing atmosphere, and the like can be given.
  • the method of increasing the doping concentration is a method of activating the dopant mainly using a polycrystalline oxide semiconductor.
  • a tetravalent element such as Ti, Si, Ge, or Sn may be mixed into the target material from the beginning in the range of 0.1 to 10%, or may be mixed by ion doping and annealed.
  • the method for forming the metal oxide layer is not particularly limited, and a known method can be used.
  • a known method can be used.
  • ceramic methods such as doctor blade method, injection method, extrusion method, hot pressing method, ion plating method, aerosol deposition method, etc.
  • a conventionally known production method suitable for the above can be used.
  • the dielectric breakdown electric field of the metal oxide used in the present invention is usually 0.5 to 3.0 MV / cm, and has very excellent performance as compared with a conventional silicon diode.
  • single-crystal ⁇ -Ga 2 O 3 is known to have a theoretical breakdown electric field of 8.0 MV / cm or more (APEX5-2012-035502), but there are minute defects, voids, etc. Then it is greatly reduced. This is because if there are minute defects or voids in the bulk, polarization occurs when an electric field is applied, and dielectric breakdown is likely to start from there.
  • the oxide semiconductor used in the present invention has an amorphous or microcrystalline structure, since there are no minute defects or voids in principle, it does not reach the theoretical value by a single crystal, but a large dielectric breakdown electric field equivalent to that is applied. It can be obtained with good yield.
  • the film thickness of the metal oxide layer varies depending on the withstand voltage, application and purpose, and is preferably 0.2 ⁇ m to 1.2 ⁇ m for the 60V withstand voltage and 2 ⁇ m to 12 ⁇ m for the 600V withstand voltage.
  • the surface metal layer 40 is provided on the Si layer 10, the SiO 2 layer 20, and the metal oxide layer 30.
  • the SiO 2 layer 20 may not be provided, and a metal-containing layer may be provided.
  • the element including the laminate of the present invention can be used for various electric circuits, electric appliances, vehicles and the like. In particular, it is optimal as a substrate for obtaining a diode or a vertical MOSFET.
  • a diode using the laminate of the present invention can achieve high breakdown voltage and high-speed switching. Hereinafter, these will be described.
  • Schottky barrier diode A diode is divided into a Schottky barrier diode and a PN diode according to the application.
  • a Schottky barrier diode using silicon is unipolar and can perform high-speed switching, but is inferior in breakdown voltage.
  • a PN diode using silicon is bipolar, and high-speed switching is inferior, but it has excellent withstand voltage.
  • a diode manufactured using the stacked body of the present invention is unipolar because an oxide semiconductor is used, and has a wide band gap. Therefore, it is possible to achieve both high-speed switching and high breakdown voltage, which are difficult to realize with silicon. In the case of SiC or GaN, it is difficult to efficiently obtain a single crystal with few defects, and there is a problem in yield. In this respect, a diode using the laminate of the present invention has a high manufacturing yield and is industrially effective.
  • a conventionally known protective film, guard ring structure, mesa structure, field plate structure, and field stop structure can be used.
  • the exposed portion of the metal oxide layer is passivated with SiO 2 or the like, so that the formation of surface states can be suppressed and the forward current reduction phenomenon called current collapse can be reduced.
  • the guard ring layer in the metal oxide layer, it is possible to suppress avalanche breakdown that may damage the diode when the reverse surge voltage exceeds the voltage range to be protected.
  • the guard ring layer is preferably p-type or i-type semiconductor.
  • the guard ring layer can alleviate electric field concentration at the junction interface edge during reverse bias, and can increase the breakdown voltage.
  • the p-type layer may be a conventionally known p-type semiconductor using Si doped with B, Al, Ga, In, or p-type oxidation represented by NiO, CuO, or CuTMO 2 (TM: 3d transition metal).
  • a physical semiconductor can be used.
  • the guard ring may be designed to be double or triple in order to increase the effect.
  • the p-type semiconductor does not flow holes and does not require high mobility.
  • a guard ring layer is formed first, and then the metal oxide layer is stacked. If the interface of the metal oxide in contact with any one of the Si layer, the SiO 2 layer, and the intermediate metal layer is in ohmic connection, the metal oxide layer is first formed, etched into a guard ring shape, and then p-type or An i-type semiconductor is formed. Next, after polishing the surface by CMP or the like, a surface metal layer that forms an ohmic connection may be formed. The same applies to a metal oxide in contact with any of the metal M layer, M x O y layer, and intermediate metal layer.
  • These protective film and guard ring layer can be formed by a conventionally known film forming method such as a vacuum process such as sputtering, ion plating or PECVD, a wet process such as printing, coating pyrolysis, mist CVD or sol-gel.
  • a conventionally known film forming method such as a vacuum process such as sputtering, ion plating or PECVD, a wet process such as printing, coating pyrolysis, mist CVD or sol-gel.
  • the guard ring p-type elements such as Cu and Ni may be ion-implanted into a desired region.
  • an area mask may be used, or a conventionally known photolithography method may be used.
  • wet etching and dry etching can be used.
  • an optimum process may be appropriately combined depending on processing accuracy and material.
  • a protective film 50 is provided on the metal oxide layer 30 and the surface metal layer 40 so as to cover them.
  • a guard ring 60 is embedded on the upper surface side of the metal oxide layer 30.
  • a guard ring 60 is embedded on the lower surface side of the metal oxide layer 30. Note that in the laminates 6 to 8, the configuration of the laminate other than the protective film 50 or the guard ring 60 is as described above, and various configurations can be adopted.
  • the back electrode is preferably laminated after removing the Si native oxide film by reverse sputtering or hydrofluoric acid in order to reduce the contact resistance of the Si layer.
  • a laminate of Ti—Ni—Au, Ti—Ni—Ag, etc., an Al electrode doped with Si, or the like is used. Since the Schottky barrier diode thus obtained is laminated on a silicon wafer, it is not as hard and brittle as SiC. Therefore, it can process with a high yield by a normal dicing technique.
  • the laminate of the present invention can be used for an MPS diode.
  • the MPS diode is a diode that achieves both the current-carrying capability of the Pin diode and the high-speed switching characteristics of the Schottky diode.
  • the p layer or the i layer may be laminated and patterned first, and then the metal oxide may be laminated. .
  • FIG. 9 An embodiment in which the laminate of the present invention is MPS is shown in FIG.
  • a plurality of p-type semiconductors 70 are formed on the SiO 2 layer 20.
  • laminated bodies other than the p-type semiconductor 70 it is as having demonstrated above and can be set as various structures.
  • the metal oxide layer is first formed, and after the trench is dug, the p-type or i-type A semiconductor is formed. Next, after polishing the surface by CMP or the like, a surface metal layer that forms an ohmic connection may be formed.
  • the laminated body with a small On-resistance and a large dielectric breakdown electric field can be obtained.
  • This property has the effect of improving the breakdown voltage region (200 to 600 V) of the Si Schottky barrier diode, which has conventionally been difficult to increase in voltage.
  • FIG. 10 is a view showing an embodiment of a laminate in the case where the support substrate is made of metal M.
  • the laminated body 10 is the same as the laminated body 7 except that the Si layer 10 is a metal layer 12 made of Mo and the SiO 2 layer 20 is an oxide layer 22 of Mo. Since Mo is close to the linear expansion coefficient of the metal oxide, generation of internal stress can be suppressed in the heating process after the metal oxide is laminated. For example, when IGZO (33:33:33) is used as the metal oxide layer 30, the linear expansion coefficient of IGZO is 6.5 ⁇ 10 ⁇ 6 / K, whereas the linear expansion coefficient of Mo is 5.1. It is close to ⁇ 10 ⁇ 6 / K.
  • the linear expansion coefficient of Si is 2.8 ⁇ 10 ⁇ 6 / K, which is less than half that of IGZO, and the metal oxide layer is peeled off and cracks are generated. It's easy to do.
  • the metal layer 14 and the metal oxide layer 24 constituting the metal layer 14 are laminated between the SiO 2 layer 20 and the metal oxide layer 30.
  • This metal layer is a layer for relieving stress due to the difference in coefficient of linear expansion between the support substrate and the metal oxide, and the thickness is appropriately selected depending on the thickness and composition of the metal oxide layer.
  • the thickness of the metal layer is preferably greater than or equal to the metal oxide layer.
  • the metal used for the support substrate other than Si and the buffer layer is preferably a material having a linear expansion coefficient larger than that of Si and smaller than that of the metal oxide.
  • the film thicknesses of the SiO 2 layer 20 and the metal oxide layer 24 (both natural oxide layers) constituting the metal layer 14 are preferably 0.0 nm to 15.0 nm, respectively.
  • FIG. 12 and 13 are diagrams showing an embodiment of a method for manufacturing the laminate 11 of FIG.
  • a laminate is manufactured by bonding a laminate formed on the metal layer 14 and a Si wafer.
  • the Si process can be applied to the subsequent process, which is advantageous in manufacturing.
  • FIG. 13 shows a case where the laminate of the metal layer 14 and the metal oxide layer 30 and the Si layer 10 are first joined, and then the surface metal layer 40, the protective layer 50, the guard ring 60, and the like are laminated.
  • Examples of the bonding technique include conventionally known SOI and plasma. Note that cracking and cracking due to differences in thermal expansion coefficients are likely to occur when different metals are bonded together, so it is necessary to ensure temperature uniformity during temperature rise and fall.
  • the element of the present invention preferably has non-linear electrical conduction.
  • Non-linear electrical conduction refers to electrical conduction that does not follow Ohm's law.
  • the laminate of the present invention can be used for a power MOSFET.
  • the power MOSFET is an insulated gate field effect transistor that controls the flow of carriers with an electric field through an oxide film.
  • the laminated body of this invention it can be set as the unipolar device which uses an electron as a carrier.
  • FIG. 14 shows an embodiment in which the laminate of the present invention is used in a planar gate type power MOSFET.
  • FIG. 14 is a cross-sectional view of a vertical MOSFET using a metal oxide semiconductor.
  • An n-type Si (corresponding to the Si layer 10) is used as a support substrate, and an n-type metal oxide semiconductor (corresponding to the metal oxide layer 30) is formed via Ti, Ni, In (corresponding to the metal-containing layer 25).
  • Ti, Ni, In corresponding to the metal-containing layer 25.
  • the interface between the Si wafer and Ti may or may not be present in the SiO 2 layer 20, but if it is present, 15 nm or less is essential.
  • Ti, Ni, Au back electrode 26
  • this layer is in contact with the drain electrode 100 (not shown).
  • a recess (groove) is formed on the upper portion of an n-type metal oxide semiconductor by dry etching, and then a p-type semiconductor or an n-type semiconductor 75 having a low carrier concentration is stacked.
  • a p-type semiconductor is used for this region (hereinafter referred to as a recess region).
  • the Fermi level of the p-type semiconductor or the low carrier concentration n-type semiconductor 75 formed in the recess region is preferably lower than that of the oxide semiconductor used in the stacked body of the present invention.
  • a conventionally known p-type semiconductor material such as NiO, PdO, CuO, or boron-doped silicon can be used.
  • An oxide semiconductor can be used for the n-type semiconductor with a low carrier concentration. Since this region is a region where a channel is formed with the gate turned on, the concentration of the transition metal that can be a scattering source is preferably as small as possible.
  • a conventionally known low-resistance wiring material such as W, Ti, Mo, Al, or Cr can be used for the source electrode region 90 that exists via the gate insulating film 110. Further, in order to suppress contact resistance, treatment with reducing by Ar plasma or the like before film formation and increasing the carrier concentration only at the contact portion may be performed.
  • Both the p-type region and the source electrode region can be obtained by patterning a metal oxide layer by photolithography and forming it by a method such as magnetron sputtering or plasma CVD. The surface is appropriately smoothed by CMP treatment. An insulating film is stacked on the stacked body including the source electrode thus obtained and the p-type or low carrier concentration n-type region, and patterned to form a gate insulating film.
  • the material forming the insulating film is not particularly limited, and any material generally used can be selected as long as the effects of the present invention are not lost.
  • any material generally used can be selected as long as the effects of the present invention are not lost.
  • An oxide or nitride such as Y 2 O 3 , HfO 2 , CaHfO 3 , PbTi 3 , BaTa 2 O 6 , SrTiO 3, or AlN can be used.
  • SiO 2 , SiN x , Al 2 O 3 or the like is used as a general gate insulating film.
  • a laminated body with a source and gate can be obtained by sputtering a metal and patterning it into a desired shape.
  • the metal is stacked in the order of Ti / Ni / Au.
  • Ti serves as an adhesion layer
  • Ni serves as a diffusion prevention layer
  • Au serves as a low resistance layer.
  • the vertical MOSFET thus obtained has a high breakdown voltage because a wide-gap oxide semiconductor is used for the breakdown voltage layer, and can achieve both a breakdown voltage of 600 V or higher, which is difficult with Si, and high-speed switching.
  • the channel resistance portion uses n-channel conduction by gate bias, carriers are electrons with high mobility and low on-resistance can be realized.
  • FIG. 15 shows an embodiment in which the laminate of the present invention is used for a trench gate type power MOSFET.
  • FIG. 15 shows a cross-sectional view of a trench gate type power MOSFET using an oxide semiconductor. This structure can be miniaturized as compared with the planar structure, and the resistance of the channel can be reduced. It is also possible to increase the density of the trench to obtain a super junction structure.
  • a p-type semiconductor or an n-type semiconductor 75 having a low carrier concentration is formed not on the recess but on the n-type metal oxide semiconductor 30.
  • a source electrode 90 is formed on the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration, and a recess is provided through the source electrode 90 and the p-type semiconductor or the n-type semiconductor 75 having a low carrier concentration.
  • a gate 80 is formed in the recess through a gate insulating film 110. Except for these configurations, the configuration is the same as in FIG.
  • FIG. 16 shows an embodiment in which a metal oxide is used for the drift region and polycrystalline silicon is used for the channel region in the planar gate type power MOSFET using the laminate of the present invention.
  • FIG. 16 shows a power MOSFET that achieves both high breakdown voltage and high-speed switching by using metal oxide in the drift region and polycrystalline silicon in the channel region.
  • n-type silicon wafer is used as a substrate (corresponding to the Si layer 10), and the surface is treated with dilute hydrofluoric acid to remove the natural oxide film.
  • an n-type oxide semiconductor (corresponding to the metal oxide layer 30) is formed.
  • an n-type oxide semiconductor is used after being crystallized, it is preferably annealed in the range of 150 to 1400 ° C. An appropriate range of annealing is appropriately determined depending on the constituent elements of the oxide semiconductor. If the annealing temperature exceeds 1400 ° C., silicon may be dissolved. If the annealing temperature is below 150 ° C., crystallization may not proceed.
  • an amorphous silicon film is formed on the n-type oxide semiconductor by a method such as PECVD and patterned.
  • PECVD plasma enhanced chemical vapor deposition
  • a method such as PECVD For patterning, after applying a resist, exposure and development are performed, and dry etching is performed using a halogen-based gas. After removing the resist, it is polycrystallized using a technique such as laser annealing.
  • a SiO 2 film 115 is formed by a method such as PECVD.
  • a metal electrode is formed thereon by sputtering or vapor deposition and patterned into the shape of the gate electrode 80.
  • a conventionally known method can be used for both dry and wet, but a high melting point metal such as W, Cr, Mo, Ta or the like is preferable because activation annealing described later is performed.
  • ion doping is performed on the p-type Si through the gate electrode 80. Since ion doping is a cap method through a SiO 2 film, which is an insulating film, the dose amount and its depth may be controlled by simulation or the like. For example, P, Sb, As, etc. are accelerated by 50 to 500 keV. The process is performed under the condition that the dose is 10 13 to 10 14 cm ⁇ 2 or the like with voltage. Since this ion doping uses a self-alignment technique using the gate electrode 80 as a mask, the process can be simplified, the gate capacitance can be reduced, and a high-speed switching operation can be performed.
  • activation annealing is performed.
  • Activation annealing is preferably performed by high-speed annealing such as flash lamp annealing or laser annealing in order to prevent electrode deterioration.
  • the annealing temperature is appropriately selected within a range in which the activation rate increases as the temperature increases, but the electrode does not deteriorate.
  • the annealing temperature is preferably 600 ° C. to 1100 ° C., more preferably 700 to 1000 ° C. In this way, an n + region 130 in which a part of the p-type Si (p region) 120 is made n-type can be formed.
  • the highly doped n-type silicon wafer 10 is laminated with Ti, Ni, Au (back electrode 26) as in FIGS. 14 and 15, and this layer is in contact with the drain electrode 100 (not shown). .
  • Module A MOSFET using the laminated body of the present invention incorporates a body diode in the same manner as a conventional Si MOSFET, but can also be used in combination with a freewheeling diode.
  • FIG. 17 is a diagram showing an embodiment of a module configured by combining elements of the present invention. Both the power MOSFET and the freewheeling diode are composed of elements including the laminate of the present invention.
  • This module includes both a MOSFET and a free-wheeling diode including a Si layer and a metal oxide layer, and the thickness of the SiO 2 layer on the surface of the Si layer on the metal oxide layer side is 0.0 nm to 15.0 nm. Since it is composed of a body, it can achieve both excellent current-voltage characteristics, that is, low on-resistance and high-speed switching.
  • FIG. 18 is a diagram showing an embodiment in which the diode and the MOSFET in the module of FIG. 17 are connected to the copper plate via the back metal and solder, and the Si wafer side of the diode is connected to the collector of the MOSFET. .
  • the Si side is in ohmic connection
  • the Si side is connected to the copper plate of the module.
  • FIG. 19 shows an embodiment in which the diode and the MOSFET in the module of FIG.
  • the oxide semiconductor side of the diode is connected to the collector of the MOSFET.
  • FIG. When the Si side is a Schottky connection, the surface metal layer side is connected to the copper plate of the module.
  • the module configuration may be combined with the diode of the present invention for the purpose of removing excess carriers of conventionally known Si-IGBT, SiC-MOSFET, and GaN-MOSFET.
  • a conventionally known free-wheeling diode may be used for the purpose of removing excess carriers in the MOSFET of the present invention.
  • examples of the electric circuit using the element of the present invention include a step-up / step-down chopper circuit, an inverter / converter circuit, a power supply circuit, a switching regulator, etc.
  • the electric appliances include a mobile phone, a personal computer, an air conditioner, and a refrigerator.
  • Receivers, lighting fixtures, electromagnetic cookers, and the like, and vehicles include bicycles, automobiles, railway vehicles, and the like.
  • the element of the present invention can be used for oxygen gas sensors, photocatalysts, ultraviolet sensors, ultraviolet solar cells, human body sensors, ultraviolet diodes, ultraviolet lasers, and the like.
  • Example 1 An n-type Si substrate (diameter 4 inches) having a resistivity of 0.02 ⁇ ⁇ cm and a slide glass were prepared. These were mounted in a sputtering apparatus (ULVAC: CS-200), and first treated in a reverse sputtering mode for 15 seconds to partially etch a natural oxide film. Next, 9700 nm of Ga 2 O 3 was formed as a metal oxide under the conditions of RF 300 W and 19 hours. Further, the substrate was taken out of the chamber and annealed for 1 hour in air at 150 ° C. by an electric furnace. The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus (FIG. 20).
  • the substrate was set again in the sputtering apparatus together with the area mask, and electrodes were formed by sputtering in the order of Ti and Au.
  • the thus-obtained element Si / SiO 2 (natural oxide film) / Ga 2 O 3 / Ti / Au
  • the evaluation items were forward rising voltage (Vf), On current, dielectric breakdown electric field (Vbd), and n value.
  • the forward rising voltage (Vf) is the applied voltage when the current density exceeds 10 mA / cm 2
  • the On current is the current density when the applied voltage is 3 V
  • the dielectric breakdown electric field (Vbd) has a leakage current of 10 ⁇
  • the voltage when exceeding 5 A / cm 2 was taken. The results are shown in Table 1.
  • Example 2 An n-type Si substrate (diameter 4 inches) having a resistivity of 0.02 ⁇ ⁇ cm and a slide glass were prepared. These were mounted in a sputtering apparatus (ULVAC: CS-200), and first treated in a reverse sputtering mode for 5 minutes to etch a part of the natural oxide film. Next, 3700 nm of Ga 2 O 3 was deposited as a metal oxide under conditions of RF 300 W and 6 hours. The substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. in air for 1 hour. The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus (FIG. 20).
  • UVAC sputtering apparatus
  • Example 3 An n-type polycrystalline Si substrate (diameter 4 inches) having a resistivity of 0.02 ⁇ ⁇ cm and a slide glass were prepared. These were mounted on a sputtering apparatus (ULVAC: CS-200), and were first processed in the reverse sputtering mode to etch a part of the natural oxide film. Next, a 200 nm film of Ga 2 O 3 was formed as a metal oxide under the conditions of RF 300 W and 18 minutes. The substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. in air for 1 hour. The element formed on the slide glass was amorphous as a result of confirming the structure with an XRD apparatus.
  • UVAC sputtering apparatus
  • a sputtering apparatus UVAC: CS-200
  • Example 6 An n-type Si substrate (4 inches in diameter) having a resistivity of 0.02 ⁇ ⁇ cm was prepared. This Si wafer was mounted on a sputtering apparatus (ULVAC: CS-200), and the natural oxide film was first etched in the reverse sputtering mode. Then 15nm deposited Mo, was further 1000nm deposited Ga 2 O 3. The substrate was taken out of the chamber and annealed in an electric furnace at 150 ° C. in air for 1 hour. Next, the remaining substrate was returned to the chamber again, and after setting an area mask having a desired pattern, electrodes were formed by sputtering in the order of Ti and Au. The device (Si / Mo / Ga 2 O 3 / Ti / Au) thus obtained was evaluated in the same manner as in Example 1 using SCS-4200 manufactured by Toyo Technica. The results are shown in Table 1.
  • Example 15 and 16 Comparative Examples 3 and 4 While changing the substrate, reverse sputtering conditions, metal oxide layer material and the like as shown in Table 1, a laminate was prepared in the same manner as in Example 1, and various characteristics were evaluated. The results are shown in Table 1.
  • Example 17 A Schottky barrier diode was manufactured by the process shown in FIG. Specifically, an n-type Si substrate (4 inches in diameter) having a resistivity of 0.02 ⁇ ⁇ cm was prepared. This Si wafer was put into a thermal oxidation furnace to form a 100 nm thermal oxide film. Next, after applying the resist, exposure, development, and etching were performed using a photomask to form contact holes. Further thereon, 10 nm each of Pd and PdO films were formed by sputtering using a Pd target. Then, a Pd / PdO laminated portion on SiO 2 was etched using aqua regia so as to remain concentrically, thereby forming a guard ring.
  • an oxide semiconductor IGZO
  • IGZO oxide semiconductor
  • Mo molybdenum
  • the thermal oxide film present on the back surface of the Si wafer was removed by etching with dilute hydrofluoric acid after the surface was covered with a protective film. Thereafter, films were formed in the order of Ti, Ni, and Au.
  • the Si wafer side of the obtained laminate was used as a Schottky junction to obtain a Schottky barrier diode with a guard ring and a back electrode.
  • the thickness of the SiO 2 film at the interface between Si and Pd of the Schottky barrier diode thus obtained was evaluated to be 0.2 nm. Note that the contact hole is circular, and a total of five points, the center of the circle and the midpoint of each vertex of the square inscribed in the circle, are observed, and the field of view is measured at equally spaced intervals of 10 to obtain a total of 55 The average value of the places was taken as the film thickness of the SiO 2 layer.
  • the element including the laminate of the present invention can be used as a power device such as a Schottky barrier diode or a MOSFET or a module combining them. Specifically, it can be used for power conversion circuits such as inverters and converters, power supply circuits, and electric circuit power conditioners, IPMs, electric appliances and vehicles using them. Furthermore, it can be used for oxygen gas sensors, photocatalysts, ultraviolet sensors, ultraviolet solar cells, human body sensors, ultraviolet diodes, ultraviolet lasers, and the like.

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Abstract

Laminé comprenant une couche de Si et une couche d'oxyde métallique, l'épaisseur du feuil d'une couche de SiO2 appliquée sur la surface, côté couche d'oxyde métallique, de la couche de Si est de 0,0 à 15,0 nm.
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