WO2022114171A1 - Procédé de fabrication d'un dispositif semi-conducteur et dispositif mosfet vertical - Google Patents

Procédé de fabrication d'un dispositif semi-conducteur et dispositif mosfet vertical Download PDF

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WO2022114171A1
WO2022114171A1 PCT/JP2021/043576 JP2021043576W WO2022114171A1 WO 2022114171 A1 WO2022114171 A1 WO 2022114171A1 JP 2021043576 W JP2021043576 W JP 2021043576W WO 2022114171 A1 WO2022114171 A1 WO 2022114171A1
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substrate
thin film
semiconductor element
back surface
main surface
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English (en)
Japanese (ja)
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光治 加藤
兆 嶋田
孝幸 古澤
幹土 砂入
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有限会社Mtec
アスカコーポレーション株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a method for manufacturing a semiconductor element and a MOSFET element. More specifically, the present invention relates to a method for manufacturing a semiconductor element suitable for face-down mounting and a vertical MOSFET element, which comprises a thin Si layer on which a semiconductor element is formed and a substrate portion made of a metal material.
  • the Si semiconductor device is preferably formed as a chip size package.
  • a thin metal layer is formed on the back surface of the vertical element and a through electrode is formed so that the drain electrode on the back surface of the vertical element is placed on the main surface.
  • a through electrode is formed so that the drain electrode on the back surface of the vertical element is placed on the main surface.
  • FIG. 11A shows an example of the structure of a chip size package of a conventional vertical MOSFET element.
  • the vertical MOSFET element 300 is provided with a source electrode 301 and a gate electrode 302 on the element main surface 311 of the Si substrate 310 which is the substrate of the element, and the drain 303 is on the back surface side of the Si substrate 310.
  • a metal layer 320 is formed on the back surface of the element.
  • the drain 303 reaches the drain electrode 304 on the main surface of the device through the metal layer 320, and the source electrode 301, the gate electrode 302, and the drain electrode 304 are present on the main surface of the device.
  • the current i flows from the drain electrode 304 to the source electrode 301 via the metal layer 320.
  • the impedance from the drain electrode to the source electrode which is an important characteristic of the MOSFET element, is the bulk resistance r1 from the drain electrode to the drain metal on the back surface, the resistance r2 from the back metal portion, and the drift from the drain 303 to the MOS gate. It is the sum of the resistance r3 and the channel resistance r4 (not shown).
  • the bulk resistance r1 depends on the thickness of the Si substrate 310.
  • the back metal portion resistance r2 can be ignored if the thickness of the metal layer 320 is a certain value or more.
  • the drift resistance r3 from the drain 303 to the MOS gate portion depends on the impurity concentration of the Si layer determined by the element withstand voltage of the drift portion and the thickness of the Si substrate 310.
  • the channel resistance r4 is a value determined by the withstand voltage of the MOSFET and the like.
  • FIG. 3B shows an example in which the vertical MOSFET element 300 of the chip size package is mounted on the printed circuit board 200 by the face-down technique.
  • the structural elements are r1 and r3, and in order to reduce this, the thickness of the Si substrate 310 is used. It is important to make it thinner.
  • Patent Document 1 A method of using a metal for the substrate portion of a Si semiconductor element is known (see, for example, Patent Document 1).
  • molybdenum having a high melting point is bonded to a metal at a high temperature of 1000 ° C., and bonding is performed by mutual diffusion of molybdenum and Si at the interface.
  • a method of metallizing the bonded surface of the Si substrate using high melting point solder and bonding it to the copper substrate at about 400 ° C is conceivable, but face-down bonding is performed by soldering at about 220 ° C. Soldering the Si substrate and the copper substrate requires soldering using high melting point solder, which has a higher temperature.
  • the practical temperature of the face-down mounted element is generally-. Since the temperature is about 40 ° C. to + 85 ° C., stress is generated due to the difference between the temperature at the time of joining and the temperature in the practical state, and warpage occurs.
  • connection life and the element life of the connection interface it is not preferable that a large stress is generated at the bonding interface because of the connection life and the element life of the connection interface.
  • the thinner the Si layer the greater the internal stress generated at the bonding interface, and the greater the effect on the elements formed on the Si surface.
  • the withstand voltage required for the MOSFET element and the thickness of the Si substrate are in a proportional relationship. That is, when a high withstand voltage is required, it is necessary to increase the thickness of the Si substrate. When the withstand voltage is low, the thinner the Si substrate, the better for various characteristics. In recent years, with the evolution of mobile devices, the demand for elements with a low withstand voltage of 20 V has increased, and in the case of a withstand voltage of 20 V, it is preferable that the thickness of the Si substrate is as thin as about 10 ⁇ m. As described above, for example, in a MOSFET element, it is important to reduce the thickness of the Si substrate in order to reduce the resistance loss.
  • FIG. 12 is a diagram showing the relationship between the thickness D of the Si substrate and the value of the series resistance component (r1 + r3) of the MOSFET element.
  • the value of the resistance component (r1 + r3) is expressed as a relative value with the case where the thickness of the Si substrate is 100 ⁇ m as 1.
  • the series resistance component (r1 + r3) of the MOSFET element decreases in proportion to the thickness, and preferable characteristics can be obtained. Further, FIG.
  • the thickness of the element is 3 mm ⁇ 6 mm
  • the basic element structure is that the thickness of the Si substrate is 100 ⁇ m and the thickness of the metal layer on the back surface is 10 ⁇ m.
  • the metal layer on the back surface is formed by silver plating, and the thicker the thickness, the more the Si substrate is warped due to stress, and the resistance component of the back surface electrode does not require 10 ⁇ m or more.
  • the thickness of silver plating is 10 ⁇ m.
  • the figure shows the warp size d of the Si substrate when the thickness D of the Si substrate is changed from 100 ⁇ m to 10 ⁇ m.
  • the warp size d is about 10 ⁇ m, but when the thickness D of the Si substrate is 10 ⁇ m, the strength of the Si substrate is lowered and the warp d is about 100 ⁇ m. Will grow up to. In particular, when the thickness of the Si substrate is 50 ⁇ m or less, the magnitude of warpage becomes remarkable. It is important to reduce the warp because the generation of the warp causes a problem that the MOSFET element of the chip size package cannot be face-down mounted. Further, if the thickness of the plating, which is the metal layer on the back surface, is increased, the warp becomes large due to the stress of the film-formed metal layer.
  • the warp of the element becomes large due to the temperature rise, and the mounting cannot be performed. Therefore, it is necessary to reduce the warp of the element before face-down mounting, and to make the element structure so that the warp does not become larger due to the temperature rise even if the warp is small.
  • An object of the present invention is to provide a method for manufacturing a semiconductor element suitable for face-down mounting and a vertical MOSFET element, which comprises a thin Si layer on which a semiconductor element is formed and a base portion made of a metal material.
  • the point of view for solving the above problems is to change from a structure in which the Si substrate is the substrate and a metal layer attached to the back surface thereof to a structure in which the metal layer is used as the substrate and the Si layer is attached.
  • the bonding temperature is set to be in the range of ⁇ 40 ° C. to + 85 ° C., which is the operating temperature range of the semiconductor element.
  • the present invention is as follows. 1. 1. The first joining step of joining the main surface side of the Si substrate on which the components of the semiconductor element are formed on the surface layer and the temporary substrate, By removing the back surface side of the Si substrate while leaving a thickness corresponding to the depth of the surface layer portion, a Si thin film in which the components of the semiconductor element are formed is formed on the main surface side thereof. Process and The second joining step of joining the back surface side of the Si thin film and the metal substrate at a temperature not exceeding the upper limit of the operating temperature of the semiconductor element. The peeling step for removing the temporary substrate and A method for manufacturing a semiconductor device, which comprises. 2. 2. The thickness of the Si thin film is 100 ⁇ m or less. The method for manufacturing a semiconductor device according to the description. 3. 3. 3.
  • the metal substrate is a copper substrate. Or 2.
  • a barrier metal layer forming step of forming a barrier metal layer made of a barrier metal on the back surface of the Si thin film is included.
  • the Si thin film and the metal substrate are joined via the barrier metal layer.
  • a separation step of separating the semiconductor element into individual chips after performing the peeling step is included.
  • An adhesive tape coated with an adhesive on a base material made of resin is attached to the back surface of the metal substrate. The chip separated in the separation step is fixed by the adhesive tape.
  • To 4. The method for manufacturing a semiconductor device according to any one of the above. 6.
  • the semiconductor element is a MOSFET having a vertical structure, and a source electrode, a gate electrode, and a drain electrode are formed on the main surface of the Si substrate. ⁇ 5.
  • the semiconductor element is a MOSFET having a vertical structure, and a source electrode and a gate electrode are formed on the main surface of the Si substrate, and a drain electrode is formed on the back surface side. ⁇ 5.
  • the method for manufacturing a semiconductor device according to the above. 8 The semiconductor element is a MOSFET having a vertical structure, and at least two independent source electrodes and gate electrodes are formed on the main surface of the Si substrate. ⁇ 5.
  • the metal substrate is a copper substrate.
  • a source electrode, a gate electrode and a drain electrode are formed on the main surface of the Si thin film.
  • the Si thin film has at least two independent source electrodes and gate electrodes formed on the main surface thereof, and a drain electrode formed on the back surface thereof. Or 10.
  • a first joining step of joining a temporary substrate and a main surface side of a Si substrate in which a component of a semiconductor element is formed on a surface layer portion, and a depth of the surface layer portion Since it includes a Si thinning step of forming a Si thin film by removing the back surface side of the Si substrate while leaving a thickness corresponding to the above, the Si substrate is prevented from warping by the temporary substrate and the semiconductor element is formed. It is possible to obtain a Si thin film having a minimum thickness capable of exhibiting the element function corresponding to the depth of the surface layer portion of the above.
  • the back surface of the Si thin film includes a second joining step of joining the back surface of the Si thin film and the metal substrate at a temperature not exceeding the upper limit of the operating temperature of the semiconductor element and a peeling step of removing the temporary substrate. It is joined so that the stress generated at the joining interface between the metal substrate and the metal substrate is extremely small, the quality of the joining interface can be improved, and the occurrence of warpage can be suppressed. In addition, deterioration of the Si semiconductor device due to stress generated at the bonding interface can be suppressed.
  • the vertical MOSFET element of the present invention has a Si thin film having at least a source electrode and a gate electrode formed on its main surface and a source portion and a gate portion formed on a surface layer portion on the main surface side, and the Si thin film.
  • the back surface of the silicon substrate is provided with a metal substrate bonded via a barrier metal layer, the thickness of the Si thin film is 100 ⁇ m or less, and the metal substrate is a substrate that supports an element, and is therefore suitable for face-down mounting.
  • a MOSFET element having a vertical structure can be configured.
  • the metal substrate suppresses the occurrence of warpage, and by setting the bonding temperature below the upper limit of the element operating temperature, the stress generated at the bonding interface between the Si thin film and the metal substrate during device use can be reduced. This can contribute to improving the reliability of the bonding interface and improving the quality of the Si element.
  • the first junction for joining the main surface (11) side of the Si substrate (100) on which the component of the semiconductor element is formed on the surface layer portion and the temporary substrate (6) By removing the back surface side (92) of the Si substrate (100) while leaving the thickness corresponding to the depth of the surface layer portion in the step, the constituent elements of the semiconductor element are formed on the main surface (11) side thereof.
  • the back surface (12) of the Si thin film (10) and the metal substrate (20) are joined at a temperature not exceeding the upper limit of the operating temperature of the semiconductor element in the Si thinning step of forming the Si thin film (10). It is characterized by including a second joining step and a peeling step of removing the temporary substrate (6) (see FIGS.
  • the depth of the surface layer portion of the Si substrate (100) on which the constituent elements of the semiconductor element are formed is determined according to the impurity concentration of the impurity layer constituting the semiconductor element, the required withstand voltage, and the like. ..
  • the standard thickness of the Si substrate is 725 ⁇ m.
  • the depth of the depletion layer due to the impurity layer is about 10 ⁇ m for the low withstand voltage element and about 100 ⁇ m for the high withstand voltage element.
  • the depth of the surface layer corresponds to the depth of this depletion layer.
  • the thickness of the Si thin film (10) obtained by thinly processing the Si substrate (100) is preferably about 10 to 100 ⁇ m depending on the withstand voltage of the element.
  • the warp increases when the thickness of the Si substrate is 100 ⁇ m or less, but the Si substrate is thinned by using the temporary substrate (6) and joining the metal substrate (20) in this manufacturing method. Warpage is prevented. Therefore, in the present embodiment, the thickness corresponding to the depth of the surface layer portion, that is, the thickness of the Si thin film (10) is 100 ⁇ m or less (10 to 100 ⁇ m), and in the case of a low withstand voltage element, 50 ⁇ m or less (10). ⁇ 50 ⁇ m).
  • the thickness of the metal substrate (20) may be appropriately set according to the strength of the material and the thickness of the Si thin film (10). For example, when a copper substrate is used as the metal substrate (20), the thickness may be set.
  • the strength can be about 50 to 300 ⁇ m.
  • a MOSFET element is taken as an example as a semiconductor element, but the present invention is not limited to this.
  • the semiconductor element may be, for example, a MOSFET element (50, 51, 52) having a vertical structure.
  • the vertical structure MOSFET element (50) has a source electrode (1) and a gate electrode (2) formed on its main surface (11), and a source portion and a gate portion formed on a surface layer portion on the main surface (11) side.
  • the Si thin film (10) is provided with a metal substrate (20) bonded to the back surface (12) of the Si thin film (10) via a barrier metal layer (8), and the thickness of the Si thin film (10) is provided.
  • the width is 50 ⁇ m or less, and the metal substrate (20) serves as a substrate for supporting the element (see FIG. 1 (a)).
  • a drain electrode (4) may be provided on the main surface (11) of the Si thin film (10) in addition to the source electrode (1) and the gate electrode (2). Further, the thickness of the Si thin film (10) can be reduced to a thickness corresponding to the depth of the surface layer portion and ensuring the required withstand voltage. Further, the vertical structure MOSFET element (51) is provided with at least two independent source electrodes and gate electrodes on the main surface (11) of the Si thin film (10) (see FIG. 1 (b)). In the vertical MOSFET element (51) of this example, one source electrode (1a) and a gate electrode (2a), and another source electrode (1b) and a gate electrode are formed on the main surface (11) of the Si thin film (10).
  • an adhesive tape (22) made of an adhesive and a base material is bonded to the back surface of the metal substrate (20) (see FIG. 1 (c)). With this adhesive tape (22), the semiconductor element can be supported and fixed when the semiconductor element formed in the wafer state is separated into individual chips. If the adhesive tape (22) is peeled off after separating into each chip, the structure is similar to that of the elements shown in FIGS. (A) and (b).
  • FIG. 1 shows an example of the structure of an N-channel vertical MOSFET element (50, 51, 52) in a chip size package manufactured by the manufacturing method.
  • the Si thin film 10 is formed with a source portion, a gate portion, and a drift (N ⁇ ) layer, which are constituent elements of a MOSFET composed of an N + layer, a P layer, and the like.
  • the vertical MOSFET element (50, 51, 52) has a Si thin film 10 having a minimum thickness (for example, about 10 ⁇ m) capable of ensuring the withstand voltage of the element and exhibiting its function, and a thickness required for mounting as a substrate. It is a multi-layer element structure in which the metal substrate 20 is bonded to the metal substrate 20 having the above.
  • the source electrode 1 and the gate electrode 2 are formed on the main surface 11 of the Si thin film 10, and the drain 3 is the gate portion on the back surface 12 side of the Si thin film 10. It is in the part facing the.
  • a metal substrate 20 is bonded to the back surface 12 of the Si thin film 10.
  • the drain 3 reaches the drain electrode 4 formed on the main surface 11 of the Si thin film 10 through the metal substrate 20, and the source electrode 1, the gate electrode 2, and the drain electrode 4 are present on the main surface 11 of the Si thin film 10. .
  • a barrier metal layer 8 on the back surface 12 of the Si thin film 10 in order to prevent the copper from diffusing into the Si layer after bonding (shown). figure).
  • the impedance from the drain electrode to the source electrode which is an important characteristic of the MOSFET, is from the bulk resistance r1 from the drain electrode 4 to the metal substrate 20 bonded to the back surface, the resistance r2 from the metal substrate 20, and the drain 3. It is the sum of the drift resistance r3 reaching the MOS gate portion and the channel resistance r4 (not shown).
  • the bulk resistance r1 depends on the thickness of the Si thin film 10, and can be minimized by reducing the thickness of the Si thin film 10 to the minimum. Since the resistance r2 of the 20 parts of the metal substrate is small, it can be ignored.
  • the drift resistance r3 from the drain 3 to the MOS gate portion depends on the impurity concentration of the Si thin film 10 determined by the element withstand voltage of the drift portion and the thickness of the Si thin film 10, but by reducing the thickness of the Si thin film 10. Can be minimized.
  • the channel resistance r4 is a value determined by the withstand voltage of the MOSFET or the like. In this way, it is possible to minimize r1 + r2 + r3 + r4 by reducing the thickness of the Si thin film 10 to a value determined by the device withstand voltage.
  • the N-channel vertical MOSFET element 51 shown in FIG. 1B is an example in which two MOSFETs in which the drain portion of the MOSFET is common and the source and the gate are independent are formed. Two components of the MOSFET (N + layer, source portion formed by P layer, gate portion, and drift (N ⁇ ) layer) are independently formed.
  • the vertical MOSFET element 51 is a Si thin film 10 having a minimum thickness (for example, about 10 ⁇ m) capable of ensuring the withstand voltage of the MOSFET element and exhibiting its function, and a metal substrate 20 having a thickness necessary for mounting as a substrate. It is a multi-layer element structure in which and is joined.
  • a source electrode (1a, 1b) and a gate electrode (2a, 2b) are formed on the main surface 11 of the Si thin film 10, and the drain 3 is a gate on the back surface 12 side of the Si thin film 10. It is in the part facing the part.
  • a metal substrate 20 is bonded to the back surface 12 side of the Si thin film 10.
  • the drains (3a and 3b) have a common potential through the metal substrate 20.
  • the structure is such that two independent source electrodes (1a and 1b) and gate electrodes (2a and 2b) are present on the main surface 11 of the Si thin film 10.
  • a barrier metal layer 8 is formed on the back surface 12 of the Si thin film 10 in order to prevent the copper from diffusing into the Si layer after bonding (not shown). ..
  • the drain is common, and the two sources and the gate are independently formed.
  • Such an element structure is suitable when the drain is used as a current source or when the drain is used in a floating state.
  • the vertical MOSFET element 51 is sealed in a small surface mount package, and the drain on the back surface is mounted so that the source and gate on the front surface are on the same surface, and the two MOSFET elements are mounted. Will have the same drain.
  • the two MOSFETs may be configured to have a common source and drain as one MOSFET element.
  • the drain when used as a floating element, it can be a bidirectional element in which one source and one gate are one terminal, and the other source and the other gate are the other terminals. This makes the structure suitable for power supply elements as a switch with a backflow prevention function.
  • the warp generated by reducing the thickness of the Si substrate has been a problem.
  • a MOSFET element in which the substrate supporting the element structure is not a Si substrate but a metal substrate and a Si thin film is bonded to the metal substrate as the substrate can be manufactured. Due to this structure, warpage is significantly suppressed even if the thickness of the Si thin film is reduced.
  • the metal substrate 20 as a support substrate has a thickness of about 150 ⁇ m
  • the Si thin film 10 has a thickness of about 10 ⁇ m.
  • the metal substrate 20 and the Si thin film 10 by joining the metal substrate 20 and the Si thin film 10 at a temperature (normal temperature) that does not exceed the upper limit of the operating temperature of the element, it occurs at the bonding interface between the metal substrate 20 and the Si thin film 10 when the element is used.
  • the stress can be reduced, thereby significantly reducing the warpage of the substrate, and the stress generated at the bonding interface due to the temperature cycle or the like generated in a practical state can be reduced, thereby increasing the reliability of the bonding. It is possible.
  • the manufacturing process in the method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 2 to 7.
  • Each manufacturing process performs processing in the state of a wafer (for example, an 8-inch size wafer), and each figure shows a cross section of a portion corresponding to one vertical MOSEFT element (50, 51, 52).
  • the basic manufacturing process is the same for the vertical MOSFET elements 51 and 52.
  • the first joining step is a step of joining the main surface (11) side of the Si substrate (100) on which the components of the semiconductor element are formed on the surface layer portion and the temporary substrate (6).
  • the constituent elements of the semiconductor element are an impurity layer, an oxide film layer, a conductor layer (electrode) and the like constituting the semiconductor element.
  • FIG. 2 shows a state in which a semiconductor element is formed on the surface of the Si substrate 100 on the main surface 11 side and on the surface layer portion, and the main surface 11 side and the temporary substrate 6 are bonded in the first joining step. ing.
  • a vertical MOSFET as a semiconductor element is shown, in which a source electrode 1, a gate oxide film layer and a gate electrode 2, and a drain electrode 4 are provided on a main surface 11 of an N-type Si substrate 100.
  • An impurity layer (N + layer, P layer) constituting the source portion is formed on the surface layer portion.
  • the material of the temporary substrate 6 is not particularly limited, and for example, a transparent glass substrate can be used.
  • the main surface 11 side of the Si substrate 100 and the temporary substrate 6 can be bonded by applying a UV release resin that is peeled off by ultraviolet light as a bonding material to the bonding surface.
  • a later step the flatness of the bonding is required in order to polish the Si substrate 100 thinly, but the flatness can be ensured by applying the UV release resin and then pressurizing it while keeping it parallel.
  • an adhesive resin tape as the temporary substrate 6. Due to the rigidity of the resin tape, the Si substrate 100 can be thinly polished in the subsequent Si thinning step.
  • the Si thin film thinning step is a step of forming a Si thin film (10) by removing the back surface (92) side of the Si substrate (100) while leaving a thickness corresponding to the depth of the surface layer portion.
  • FIG. 3A shows a state in which the Si thin film 10 using the Si substrate 100 as a base material is formed by removing the back surface side 92 of the Si substrate 100 bonded to the temporary substrate 6 by the Si thin film step. Represents.
  • the method of removing the back surface side of the Si substrate 100 is not particularly limited, and for example, the thickness can be reduced to about 10 ⁇ m by grinding and polishing the back surface side of the Si substrate 100 with the temporary substrate 6 as a support.
  • the thickness corresponding to the depth of the surface layer portion depends on the withstand voltage required for the element, and is about 10 ⁇ m for the low withstand voltage element and about 100 ⁇ m for the high withstand voltage element. Therefore, for example, in the case of an 8-inch wafer, a surface layer portion having a thickness of 10 to 100 ⁇ m on the main surface side of the Si substrate (100) having a thickness of 725 ⁇ m is left as a Si thin film (10). The portion having a certain thickness on the main surface 11 side of the Si substrate 100 left in this way becomes the Si thin film 10.
  • the back surface 12 of the Si thin film 10 is polished to a surface roughness Ra of about 0.5 nm for later bonding with the metal substrate 20.
  • the barrier metal layer forming step is a step of forming a barrier metal layer (8) made of a barrier metal on the back surface (12) of the Si thin film (10) after performing the Si thinning step.
  • a barrier metal layer (8) made of a barrier metal on the back surface (12) of the Si thin film (10) after performing the Si thinning step.
  • the back surface 12 of the Si thin film 10 is used.
  • the barrier metal layer 8 Ni, Ta, or the like can be used as the barrier metal, and the barrier metal layer 8 having a thickness of about 10 nm can be formed on the back surface 12 of the Si thin film 10 by sputtering or the like.
  • the second joining step is a step of joining the back surface side of the Si thin film (10) and the metal substrate (20) at a temperature not exceeding the upper limit of the operating temperature of the target semiconductor element.
  • FIG. 4A shows a state in which the back surface 12 of the Si thin film 10 and the metal substrate 20 are bonded in the second bonding step.
  • the operating temperature of the semiconductor element is about ⁇ 20 ° C. to + 85 ° C. Therefore, the Si thin film 10 and the metal substrate 20 are joined at 85 ° C. or lower, which is the upper limit of the operating temperature range. In practice, it is preferable to perform the bonding at room temperature.
  • the material of the metal substrate 20 is not particularly limited, but for example, a copper substrate that is inexpensive and has excellent thermal conductivity can be used.
  • the barrier metal layer 8 is formed on the back surface of the Si thin film 10, the Si thin film 10 and the metal substrate 20 are joined via the barrier metal layer 8 as shown in FIG.
  • the method of joining at room temperature is not particularly limited, but for example, a method of activating both sides to be joined by an argon beam using a FAB (Fast Atomic Beam) gun can be applied.
  • a FAB Fast Atomic Beam
  • the Si thin film 10 and the metal substrate (copper substrate) 20 can be joined by using a FAB gun.
  • both sides to be joined are activated by irradiating an argon beam obtained from an argon beam source 200, and then pressurized at room temperature for joining.
  • the feature of this joining method is that if the joining surface has a flatness of 0.5 nm level, it can be directly joined at room temperature.
  • the figure is a schematic diagram of the main part of the bonding device.
  • FIG. 9 shows a TEM (transmission electron microscope) image of the bonding interface between the Si thin film 10 and the copper substrate 20. It can be seen that the Si thin film 10 and the copper substrate 20 are bonded at the atomic level.
  • a method of forming a gold thin film with a thickness of about 10 nm on the surface for joining has also been developed.
  • the Si thin film 10 and the metal substrate 20 can also be joined via such a gold thin film.
  • the peeling step is a step of removing the temporary substrate (6).
  • the temporary substrate 6 made of transparent glass and the main surface 11 side of the Si thin film 10 are bonded with a UV release resin, the bonding interface can be separated by irradiating ultraviolet rays from the glass substrate side.
  • the transparent glass substrate can be reused.
  • a resin tape having adhesiveness is used as the temporary substrate 6, it can be peeled off from the end face of the resin tape, and the resin tape can be disposable.
  • FIG. 5A shows a state in which the temporary substrate 6 bonded to the main surface 11 side of the Si thin film 10 is peeled off after the second bonding step.
  • a vertical MOSFET element 50 is formed in which the metal substrate 20 is used as a substrate and the Si thin film 10 on which the MOSFET is formed is bonded.
  • FIG. (B) shows a vertical MOSFET element 50 in which a Si thin film 10 is bonded to a metal substrate 20 via a barrier metal layer 8.
  • the method for manufacturing the semiconductor element includes a separation step of separating the semiconductor element (50, 51, 52) into individual chips after performing the peeling step, and the back surface of the metal substrate (20) is made of a resin base material.
  • An adhesive tape (22) coated with an adhesive is attached to the chip, and the chip separated in the separation step can be configured to be fixed by the adhesive tape (22).
  • the Si thin film 10 and the metal substrate (20) are joined in a wafer state.
  • the Si thin film 10 is first separated (so-called scribe cut), and then the metal substrate 20 is separated (scribe cut), and the chips of the individual semiconductor elements (50, 51, 52) are separated. It is formed.
  • the adhesive tape 22 is attached to the back surface of the metal substrate 20, the adhesive tape 22 can be used as a support (base) for performing this scribe cut. After each separated chip is picked up, the underlying adhesive tape 22 becomes unnecessary.
  • FIG. 6A shows a state in which the back surface side of the Si thin film 10 and the metal substrate 20 are bonded by the second bonding step.
  • An adhesive tape (22) is attached to the back surface of the metal substrate 20 (the surface opposite to the Si thin film 10).
  • FIG. 7A shows a state in which the temporary substrate 6 bonded to the main surface 11 side of the Si thin film 10 is peeled off by the peeling step.
  • FIG. (B) shows a vertical MOSFET element 52 in which a Si thin film 10 is bonded to a metal substrate 20 via a barrier metal layer 8. If the adhesive tape 22 is attached to the back surface of the metal substrate 20 in this way, the adhesive tape 22 can be used as a support in the element manufacturing process, and the thickness of the metal substrate 20 is increased by the rigidity of the adhesive tape 22. It is also possible to make it thinner.
  • FIG. 10 shows an example in which the vertical MOSFET element 50 of the chip size package is face-down mounted on the printed circuit board 200.
  • a copper substrate is used as the metal substrate 20, and the thickness thereof is 150 ⁇ m.
  • the thickness of the Si thin film 10 on which the MOSFET is formed is 10 ⁇ m. Since the Si thin film 10 is bonded to the metal substrate 20, there is no warp, and stable soldering is possible even in face-down mounting.
  • the warp increases when the thickness of the Si substrate is reduced (see FIG. 13).
  • the semiconductor device in which the Si layer is bonded to the metal substrate at room temperature significantly suppresses the influence of stress generated at the bonding interface when the semiconductor element is used, as compared with the case where the Si layer is bonded to the metal substrate at high temperature. be able to.
  • the thickness of the metal substrate made of copper is 300 ⁇ m
  • the thickness of the Si layer (Si thin film) is 10 ⁇ m
  • the operating temperature of the semiconductor element is 85 ° C.
  • the coefficient of linear expansion is copper: 16.8 ⁇ 10-6
  • the difference is 14.4.
  • the Si layer and the copper substrate have been bonded at a high temperature. Assuming that the Si layer and the copper substrate are bonded at 400 ° C., a temperature difference of 315 ° C. occurs between the temperature at the time of bonding and the temperature at 85 ° C. when the semiconductor element is used.
  • the Si layer (Si thin film) and the copper substrate are bonded at 25 ° C., the temperature difference from the temperature of 85 ° C. at the time of using the semiconductor element is only 60 ° C.
  • a multi-layer element structure using a metal substrate as a substrate is effective for a chip size package instead of the conventional element structure using a Si substrate as an element substrate.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention concerne : un procédé de fabrication d'un dispositif à semi-conducteur approprié pour une mise en œuvre face-à-bas comprenant une couche mince de Si sur laquelle est formé un dispositif à semi-conducteur, et une partie de base constituée d'un matériau métallique ; et un dispositif MOSFET vertical. Le procédé de fabrication du dispositif à semi-conducteur est caractérisé en ce qu'il comprend : une première étape de liaison pour lier un côté surface principale d'un substrat de Si 100 dans la partie de couche supérieure duquel est formé un élément constitutif du dispositif à semi-conducteur, avec un substrat provisoire 6 ; une étape d'amincissement de film de Si pour retirer un côté surface arrière du substrat de Si tout en conservant une épaisseur correspondant à la profondeur de la partie de couche supérieure, de sorte à former un film mince de Si 10 sur un côté surface principale 11 duquel est formé l'élément constitutif du dispositif à semi-conducteur ; une seconde étape de liaison pour lier la surface arrière du film mince de Si avec un substrat métallique 20 à une température ne dépassant pas une température d'utilisation du dispositif à semi-conducteur ; et une étape de pelage pour retirer le substrat provisoire.
PCT/JP2021/043576 2020-11-30 2021-11-29 Procédé de fabrication d'un dispositif semi-conducteur et dispositif mosfet vertical WO2022114171A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102023200956A1 (de) 2023-02-07 2024-08-08 Robert Bosch Gesellschaft mit beschränkter Haftung Halbleiterbauelement mit Metallisierungsschicht

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003069019A (ja) * 2001-08-29 2003-03-07 Toshiba Corp 半導体装置およびその製造方法
JP4700264B2 (ja) * 2003-05-21 2011-06-15 財団法人国際科学振興財団 半導体装置
JP2015153893A (ja) * 2014-02-14 2015-08-24 公立大学法人大阪市立大学 半導体装置、及びその半導体装置の製造方法
WO2016075927A1 (fr) * 2014-11-11 2016-05-19 出光興産株式会社 Nouveau laminé
JP2017112335A (ja) * 2015-12-18 2017-06-22 株式会社テンシックス 半導体素子の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003069019A (ja) * 2001-08-29 2003-03-07 Toshiba Corp 半導体装置およびその製造方法
JP4700264B2 (ja) * 2003-05-21 2011-06-15 財団法人国際科学振興財団 半導体装置
JP2015153893A (ja) * 2014-02-14 2015-08-24 公立大学法人大阪市立大学 半導体装置、及びその半導体装置の製造方法
WO2016075927A1 (fr) * 2014-11-11 2016-05-19 出光興産株式会社 Nouveau laminé
JP2017112335A (ja) * 2015-12-18 2017-06-22 株式会社テンシックス 半導体素子の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102023200956A1 (de) 2023-02-07 2024-08-08 Robert Bosch Gesellschaft mit beschränkter Haftung Halbleiterbauelement mit Metallisierungsschicht

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