CN110114888B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN110114888B
CN110114888B CN201780080128.5A CN201780080128A CN110114888B CN 110114888 B CN110114888 B CN 110114888B CN 201780080128 A CN201780080128 A CN 201780080128A CN 110114888 B CN110114888 B CN 110114888B
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semiconductor device
thickness
layer
metal layer
semiconductor
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CN110114888A (zh
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松岛芳宏
曾田茂稔
安田英司
今井俊和
大河亮介
吉田一磨
加藤亮
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Nuvoton Technology Corp Japan
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Nuvoton Technology Corp Japan
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Abstract

半导体装置(1)具备：N型的半导体基板(32)，由硅构成；N型的低浓度杂质层(33)，与半导体基板(32)的上表面接触；金属层(31)，与半导体基板(32)的下表面整面接触，厚度为20μm以上；以及晶体管(10及20)，形成在低浓度杂质层内；半导体基板(32)作为晶体管(10及20)的漏极区域发挥功能；将在晶体管(10及20)的源极电极之间经由晶体管(10)侧的半导体基板(32)、金属层(31)、晶体管(20)侧的半导体基板(32)流动的双向路径作为主电流路径；金属层(31)的厚度相对于包括半导体基板(32)和低浓度杂质层(33)的半导体层的厚度的比例大于0.27；半导体装置(1)还在金属层(31)的下表面整面具有仅经由粘接层(39)粘接的由陶瓷材料构成的支承体(30)。

Description

半导体装置
技术领域
本发明涉及半导体装置，特别涉及能够进行倒装(face down)安装的芯片尺寸封装型的半导体装置。
背景技术
以往，提出了一种半导体装置，具备具有第1主面及第2主面的半导体基板、跨从该第1主面到该第2主面而设置的2个纵型MOS(Metal Oxide Semiconductor，金属氧化物半导体)晶体管和形成在该第2主面上的金属层。在该结构中，作为从第1晶体管向第2晶体管流动的电流路径，不仅使用半导体基板内部的水平方向路径，还能够使用导通电阻低的金属层中的水平方向路径，所以能够降低半导体装置的导通电阻。
在专利文献1中，提出了除了上述结构以外、还在金属层的与半导体基板相反侧形成有导电层的半导体装置。通过该导电层，在将芯片单片化的工序中能够抑制金属层的毛刺的发生。
此外，在专利文献2中，提出了除了上述结构以外、还在金属层的与半导体基板相反侧形成有绝缘覆膜的半导体装置。通过该绝缘覆膜，能够维持半导体装置的薄型化，并且能够防止伤痕或缺陷等破损。
现有技术文献
专利文献
专利文献1：日本特开2016－86006号公报
专利文献2：日本特开2012－182238号公报
发明内容
发明要解决的课题
但是，在专利文献1及专利文献2所公开的半导体装置中，金属层的热膨胀系数比半导体基板的热膨胀系数大，所以发生因温度变化带来的半导体装置的翘曲。
在专利文献1中，在金属层的与半导体基板相反侧形成有导电层，但导电层的主材料是与金属层相同种类的金属，所以形成足够减轻因温度变化带来的半导体装置的翘曲的厚度的导电层在制造方面并不容易。
在专利文献2中，在金属层的与半导体基板相反侧形成有用来实现半导体装置的薄型化及破损的防止的绝缘覆膜，但在金属层的厚度是为了确保低导通电阻而需要的厚度的情况下，在绝缘覆膜中不发生足够减轻半导体装置的翘曲的应力。
即，在专利文献1及2所公开的半导体装置中，不能兼顾导通电阻的降低和半导体装置的翘曲的抑制。
所以，本发明的目的是提供兼顾了导通电阻的降低和翘曲的抑制的芯片尺寸封装型的半导体装置。
用来解决课题的手段
为了解决上述课题，有关本发明的半导体装置的一技术方案，是能够进行倒装安装的芯片尺寸封装型的半导体装置，具备：半导体基板，由硅构成，包含第1导电型的杂质；低浓度杂质层，与上述半导体基板的上表面接触而形成，包含浓度比上述半导体基板的上述第1导电型的杂质的浓度低的上述第1导电型的杂质；金属层，与上述半导体基板的下表面整面接触而形成，仅由厚度为20μm以上的金属材料构成；第1纵型MOS晶体管，形成在上述低浓度杂质层内的第1区域中；以及第2纵型MOS晶体管，形成在上述低浓度杂质层内的第2区域中，该第2区域在沿着上述半导体基板的上表面的方向上与上述第1区域相邻；上述第1纵型MOS晶体管具有在上述低浓度杂质层的上表面形成的第1源极电极及第1栅极电极；上述第2纵型MOS晶体管具有在上述低浓度杂质层的上表面形成的第2源极电极及第2栅极电极；上述半导体基板作为使上述第1纵型MOS晶体管的第1漏极区域及上述第2纵型MOS晶体管的第2漏极区域共通化的漏极区域发挥功能；将在上述第1源极电极与上述第2源极电极之间经由上述第1漏极区域、上述金属层及上述第2漏极区域流动的双向路径作为主电流路径；上述金属层的厚度相对于包括上述半导体基板和上述低浓度杂质层的半导体层的厚度的比例大于0.27；上述半导体装置还具有由陶瓷材料构成的支承体，该支承体仅经由粘接层粘接于上述金属层的下表面整面。
根据该结构，取得在具有用来确保低导通电阻的厚度的金属层的上表面形成的半导体基板的热膨胀系数与在金属层的下表面形成的粘接层及支承体的热膨胀系数的平衡，因此能够降低导通电阻，并且能够抑制半导体装置的翘曲。
发明效果
根据有关本发明的半导体装置，能够提供兼顾了导通电阻的降低和翘曲的抑制的芯片尺寸封装型的半导体装置。
附图说明
图1A是有关实施方式1的半导体装置的剖视图。
图1B是表示有关实施方式1的半导体装置的电极结构的一例的俯视图。
图2A是表示有关实施方式1的半导体装置向充放电电路的第1应用例的电路图。
图2B是将向充放电电路的应用例仅用单向的晶体管构成的情况下的电路图。
图2C是表示有关实施方式1的半导体装置向充放电电路的第2应用例的电路图。
图3A是表示有关比较例1的半导体装置的相对于金属层的厚度的、导通电阻的曲线图。
图3B是表示有关比较例2的半导体装置的相对于金属层的厚度/半导体层的厚度的、导通电阻及翘曲量的曲线图。
图4A是表示用来导出在多层体中发生的翘曲的基本模型的图。
图4B是说明在多层体中发生的翘曲量δ的侧视概略图。
图5是表示相对于粘接层的厚度及支承体的厚度的、翘曲量的曲线图。
图6A是表示使用有效值计算式计算出的、将半导体层的厚度固定的情况下的用来使翘曲量成为20μm的金属层、粘接层及支承体的厚度的关系的曲线图。
图6B是表示使用有效值计算式计算出的、将半导体层的厚度固定的情况下的用来使翘曲量成为20μm的半导体层、粘接层及支承体的厚度的关系的曲线图。
图7是在有关实施方式1的半导体装置中、规定了用来使翘曲量成为目标值及容许值的相对于粘接层的厚度的、支承体的厚度的关系的曲线图。
图8A是有关实施方式1的变形例1的半导体装置的剖视图。
图8B是表示有关实施方式1的变形例1的半导体装置的电极结构的一例的俯视图。
图9是有关实施方式1的变形例2的半导体装置的剖视图。
图10A是表示有关实施方式1的半导体装置的制造方法的第1工序的剖视图。
图10B是表示有关实施方式1的半导体装置的制造方法的第2工序的剖视图。
图10C是表示有关实施方式1的半导体装置的制造方法的第3工序的剖视图。
图11A是表示有关实施方式1的半导体装置的制造方法的第4工序的剖视图。
图11B是表示有关实施方式1的半导体装置的制造方法的第5工序的剖视图。
图12A是表示有关实施方式1的半导体装置的制造方法的第6工序的剖视图。
图12B是表示有关实施方式1的半导体装置的制造方法的第7工序的剖视图。
图13是表示有关实施方式1的半导体装置的制造方法的第8工序的剖视图。
图14是表示有关实施方式1的半导体装置的制造方法的第9工序的剖视图。
具体实施方式
(作为本发明的基础的认识)
对在专利文献2中公开的具有2个纵型MOS晶体管的半导体装置的导通电阻的降低及翘曲的抑制进行讨论。
在专利文献2所公开的半导体装置中，流过金属层的导通电流沿与金属层的主面平行的方向流动。因此，从降低导通电阻的观点来看，优选的是使金属层较厚。但是，根据专利文献2，从降低半导体装置的翘曲的观点来看，金属层越厚，则金属层的热膨胀率越成为支配性的，所以金属层的厚度优选的是设为半导体基板的1/4以下。在此情况下，用来降低导通电阻的金属层的厚度被半导体基板的厚度限制，根据半导体基板的厚度，金属层变薄，不能得到充分的导通电阻。
此外，在金属层的与半导体基板相反侧，形成有以伤痕或缺陷的防止为目的的绝缘覆膜。从防止从金属层的剥离及半导体装置的薄型化的观点出发，该绝缘覆膜由涂敷型的有机材料、有机类的带或无机类氧化物薄膜构成。因此，绝缘覆膜虽然附属性地具有抑制由金属层引起的半导体装置的翘曲的功能，但在以导通电阻的降低为目的而使金属层变厚的情况下，不具有用来抑制由金属层引起的半导体装置的翘曲的足够的应力。
所以，本发明者专门研究的结果，关于将具有2个纵型MOS晶体管的半导体装置应用为充放电电路的情况下能得到实用性的低导通电阻的、具有厚度20μm以上的金属层的半导体装置，找到了使半导体基板及金属层的翘曲量成为规定值以下的半导体装置的结构。
以下说明的实施方式都表示本发明的一具体例。在以下的实施方式中表示的数值、形状、材料、构成要素、构成要素的配置及连接形态等是一例，不是限定本发明的意思。此外，以下的实施方式的构成要素中的、在表示最上位概念的独立权利要求中没有记载的构成要素，设为任意的构成要素而进行说明。
(实施方式1)
[1.半导体装置的基本构造]
以下，对有关本发明的半导体装置1的构造进行说明。有关本发明的半导体装置1，是在半导体基板形成有2个纵型MOS(Metal Oxide Semiconductor)晶体管的CSP(ChipSize Package：芯片尺寸封装)型的多晶体管芯片。上述2个纵型MOS晶体管是功率晶体管，是所谓的沟槽MOS型FET(Field EffectTransistor)。但是，有关本实施方式的半导体装置1并不适用于固体摄像装置等的被分类为光电子类的装置。
图1A是表示半导体装置1的构造的一例的剖视图。此外，图1B是表示有关实施方式1的半导体装置1的电极结构的一例的俯视图。图1A的剖视图是观察图1B的IA－IA的切断面的图。如图1A所示，半导体装置1具有半导体基板32、低浓度杂质层33、金属层31、粘接层39、支承体30、第1纵型MOS晶体管10(以下称作晶体管10)和第2纵型MOS晶体管20(以下称作晶体管20)。此外，如图1B所示，半导体装置1在将半导体基板32平面视的情况下具有2个第1源极电极11、2个第2源极电极21、1个第1栅极电极19及1个第2栅极电极29。在晶体管10的上表面，沿着与晶体管10和晶体管20对置的方向垂直的方向，依次形成有第1源极电极11、第1栅极电极19及第1源极电极11。此外，在晶体管20的上表面，沿着与晶体管10和晶体管20对置的方向垂直的方向，依次形成有第2源极电极21、第2栅极电极29及第2源极电极21。
另外，构成1个晶体管的源极电极及栅极电极的个数及配置关系并不限定于图1B所示。
半导体基板32包含第1导电型的杂质，由硅构成。半导体基板32例如是N型的硅基板。
低浓度杂质层33与半导体基板32的上表面(图1A中的上侧主面)接触而形成，包含比半导体基板32的第1导电型的杂质的浓度低的浓度的第1导电型的杂质。低浓度杂质层33例如也可以通过外延成长而形成在半导体基板32上。
如图1A所示，将半导体基板32及低浓度杂质层33的层叠体定义为半导体层40。
金属层31与半导体基板32的下表面(图1A中的下侧主面)整面接触而形成，仅由金属材料构成。金属层31作为不被限定的一例，也可以由包含银、铜、金、铝中的某1种以上的金属材料构成。
支承体30经由粘接层39粘接于金属层31的2个主面中的不与半导体基板32接触的下表面整面，由陶瓷材料构成。作为构成支承体30的陶瓷材料，特别例示硅，但除此以外也可以例示石英、蓝宝石、硼硅酸玻璃、钠钙玻璃等。
粘接层39是与金属层31及支承体30接触而配置，用来将金属层31与支承体30粘接的层。粘接层39通过例如将由丙烯酸树脂或环氧树脂构成的粘接剂或DAF(Die AttachFilm：芯片结合用薄膜粘接剂)等固化而形成。
晶体管10形成在低浓度杂质层33内的第1区域(图1A中的左侧半部区域)中，具有形成在低浓度杂质层33的上表面上的第1源极电极11及处于其他截面的第1栅极电极19(参照图1B)。
在低浓度杂质层33的第1区域中，形成有包含与第1导电型不同的第2导电型的杂质的第1主体区域18。在第1主体区域18中，形成有包含第1导电型的杂质的第1源极区域14、第1栅极导体15及第1栅极绝缘膜16。第1源极电极11由第1部分12和第2部分13构成，第1部分12经由第2部分13而与第1源极区域14及第1主体区域18连接。第1栅极电极19与第1栅极导体15连接。
第1源极电极11的第1部分12是在安装时与焊料等的导电性接合材料呈现良好的接合性的层，作为不被限定的一例，也可以由包含镍、钛、钨、钯中的某1种以上的金属材料构成。对于第1部分12的表面，也可以施以金等的镀层。
第1源极电极11的第2部分13是将第1部分12与半导体层40连接的层，作为不被限定的一例，也可以由包含铝、铜、金、银中的某1种以上的金属材料构成。
晶体管20形成于低浓度杂质层33内的在沿着半导体基板32的上表面的方向上相邻的第2区域(图1A中的右侧半部区域)中，具有在低浓度杂质层33的上表面形成的第2源极电极21及处于其他截面的第2栅极电极29。
在低浓度杂质层33的第2区域中，形成有包含与第1导电型不同的第2导电型的杂质的第2主体区域28。在第2主体区域28中，形成有包含第1导电型的杂质的第2源极区域24、第2栅极导体25及第2栅极绝缘膜26。第2源极电极21由第1部分22和第2部分23构成，第1部分22经由第2部分23而与第2源极区域24及第2主体区域28连接。第2栅极电极29与第2栅极导体25连接。
第2源极电极21的第1部分22是在安装时与焊料等的导电性接合材料呈现良好的接合性的层，作为不被限定的一例，也可以由包含镍、钛、钨、钯中的某1种以上的金属材料构成。对于第1部分22的表面，也可以施以金等的镀层。
第2源极电极21的第2部分23是将第1部分22与半导体层40连接的层，作为不被限定的一例，也可以由包含铝、铜、金、银中的某1种以上的金属材料构成。
第1主体区域18及第2主体区域28被具有开口的层间绝缘层34覆盖，设置有经过层间绝缘层34的开口而与第1源极区域14及第2源极区域24连接的源极电极的第2部分13及23。层间绝缘层34及源极电极的第2部分13及23被具有开口的钝化层35覆盖，设置有经过钝化层35的开口与第2部分13、23分别连接的源极电极的第1部分12及22。
在将半导体装置1向安装基板安装的情况下，第1源极电极11、第1栅极电极19、第2源极电极21及第2栅极电极29经由焊料等的导电性接合材料，通过倒装与设置在安装基板上的电极接合。在此情况下，半导体装置1的翘曲越大，则第1源极电极11、第1栅极电极19、第2源极电极21及第2栅极电极29与设置在安装基板上的电极的电连接越不稳定。即，为了使半导体装置1向安装基板的安装更稳定化，需要使半导体装置1的翘曲变得更小。
通过晶体管10及20的上述结构，半导体基板32作为将晶体管10的第1漏极区域及晶体管20的第2漏极区域共通化的共通漏极区域发挥作用。此外，半导体装置1将在第1源极电极11与第2源极电极21之间经由第1漏极区域、金属层31及第2漏极区域流动的双向路径作为主电流路径。
图2A是表示半导体装置1向充放电电路的第1应用例的电路图。如图2A所示，半导体装置1根据从控制IC2给出的控制信号，控制从电池3向负载4的放电及从负载4向电池3的充电。
图2B是将同样的应用例仅用单向的晶体管10构成的情况下的电路图。如图2B所示，放电电流可以通过将晶体管10设为截止状态而停止，但对充电电流而言，即使将晶体管10设为截止状态，也在形成在第1主体区域18与低浓度杂质层33之间的体二极管中以正向(从第1主体区域18向低浓度杂质层33的方向)流动，所以不能停止。所以，为了使得在放电及充电的哪个方向上都能够进行完全的电流切断，需要双向晶体管。
图2C是表示半导体装置1向充放电电路的第2应用例的电路图。如图2C所示，半导体装置1根据从控制IC2给出的控制信号，通过将晶体管10设为截止状态而将放电电流切断，通过将晶体管20设为截止状态而将充电电流切断。
另外，在图1A所示的半导体装置1中，例如也可以将第1导电型设为N型、将第2导电型设为P型，第1源极区域14、第2源极区域24、半导体基板32及低浓度杂质层33是N型半导体，并且第1主体区域18及第2主体区域28是P型半导体。
此外，例如也可以将第1导电型设为P型，将第2导电型设为N型，第1源极区域14、第2源极区域24、半导体基板32及低浓度杂质层33是P型半导体，并且第1主体区域18及第2主体区域28是N型半导体。
在以下的说明中，只要没有特别说明，在图1A所示的半导体装置1中，就设为将第1导电型设为N型、将第2导电型设为P型的所谓N沟道型晶体管的情况而进行说明。
首先，对半导体装置1的导通状态进行说明。
在图1A所示的半导体装置1中，如果对第1源极电极11施加高电压，对第2源极电极21施加低电压，以第2源极电极21为基准而对第1栅极电极19(第1栅极导体15)及第2栅极电极29(第2栅极导体25)施加阈值以上的电压，则在第1栅极绝缘膜16及第2栅极绝缘膜26的附近形成沟道，以第1源极电极11－第1主体区域18－第1漏极区域－金属层31－第2漏极区域－第2主体区域28－第2源极电极21的路径流过电流。
这是图2A中的充电电流的情况，是晶体管10、20导通而流过导通电流的半导体装置1的导通状态。
晶体管10及20间的导通电流流过金属层31。因此，通过使金属层31变厚，导通电流的路径的截面积扩大，半导体装置1的导通电阻下降。
接着，对半导体装置1的截止状态进行说明。
在图1A中，第1主体区域18与低浓度杂质层33之间、以及第2主体区域28与低浓度杂质层33之间的PN结分别构成体二极管。以下，将在第1主体区域18与低浓度杂质层33之间形成的体二极管记作第1体二极管，将在第2主体区域28与低浓度杂质层33之间形成的体二极管记作第2体二极管。
在图1A中，以第2源极电极21为基准，如果第2栅极电极29(第2栅极导体25)的电压小于阈值，则即使对第1源极电极11施加高电压、对第2源极电极21施加低电压，在晶体管20的栅极绝缘膜26的附近也不形成沟道，成为不流过导通电流的截止状态。此时，晶体管10的偏置状态是相对于第1体二极管为正向的偏置状态，所以与对第1栅极电极19(第1栅极导体15)施加的电压无关地，晶体管10成为导通状态。
另外，在向第1源极电极11和第2源极电极21的电压施加条件相反的对第2源极电极21施加高电压、对第1源极电极11施加低电压的情况下，也如果以第1源极电极11为基准而第1栅极电极19(第1栅极导体15)的电压小于阈值，则在晶体管10的栅极绝缘膜16的附近不形成沟道，半导体装置1成为不流过导通电流的截止状态。
[2.降低半导体装置的导通电阻的基本构造]
这里，对在有关本实施方式的半导体装置1中用来降低半导体装置1的导通电阻的基本结构进行说明。
图3A是表示有关比较例1的半导体装置的相对于金属层的厚度的、导通电阻的曲线图。有关比较例1的半导体装置相对于图1A及图1B所示的半导体装置1，具有没有形成粘接层39及支承体30的结构。作为有关比较例1的半导体装置，设想(1)半导体层40的厚度是43μm的结构、以及(2)半导体层40的厚度是78μm的结构，对于这2个类型的半导体装置，测量使金属层31的厚度在10～40μm的范围中变化的情况下的半导体装置的导通电阻。关于导通电阻，通过按每个试样而在将试样安装在评价基板上的状态下测量的第1方法、以及将探头抵接在裸芯片状态的试样上而进行的第2方法中的某一种来进行。关于因测量方法的不同而发生的测量值的差异，适当进行了修正。
在表1中表示有关比较例1的半导体装置的各参数。
[表1]
参数 数值范围
半导体层40厚度(μm) 43，78
金属层31厚度(Ag：μm) 10－40
低浓度杂质层33厚度(μm) 2.75
对角长L1(mm) 3.92
金属层31厚度/半导体层40厚度 0.13－0.93
如图3A所示，随着使金属层31变厚，导通电阻变低。
作为智能电话及平板电脑的充放电电路，在应用本发明的半导体装置的情况下，因为充电时间缩短及急速充电实现的制约，导通电阻作为20V耐压规格而被要求2.2～2.4mΩ以下。
根据图3A，导通电阻满足2.4mΩ以下的金属层31的厚度需要是20μm以上。
图3B是表示有关比较例2的半导体装置中的、金属层31的厚度相对于半导体层40的厚度的比例(以下，有记作金属层31厚度/半导体层40厚度的情况)、导通电阻及翘曲量的关系的曲线图。有关比较例2的半导体装置相对于图1A及图1B所示的半导体装置1，具有没有形成粘接层39及支承体30的结构。作为有关比较例2的半导体装置，测量使金属层31的厚度在10μm～40μm的范围中变化、并且使半导体层40的厚度在28～93μm的范围中变化的情况下的导通电阻、半导体基板32及金属层31的层叠体的翘曲量。关于上述翘曲量，将裸芯片状态的试样置于模拟回流工序的最高温度250℃的热负荷循环下，通过莫尔条纹法测量裸芯片的形状，记录所测量的翘曲量的最大值。
在表2中表示有关比较例2的半导体装置的各参数。
[表2]
参数 数值范围
半导体层40厚度(μm) 28－93
金属层31厚度(Ag：μm) 10－40
低浓度杂质层33厚度(μm) 2.75
对角长L1(mm) 3.92
金属层31厚度/半导体层40厚度 0.11－1.43
如图3B所示，随着使金属层31厚度/半导体层40厚度变大，导通电阻变低。另一方面，随着使金属层31厚度/半导体层40厚度变大，翘曲量增加。
根据图3B，导通电阻满足2.4mΩ以下的金属层31厚度/半导体层40厚度被要求大于0.27。但是，如果金属层31厚度/半导体层40厚度大于0.27，则翘曲量成为20μm以上。随着翘曲量变大，在向安装基板的倒装安装时，难以实现稳定的安装，发生不良状况。例如发生(1)半导体装置上的电极与安装基板上的电极之间的焊料接合变得不完全、(2)发生该焊料内的空隙、(3)发生因焊料从电极露出而造成的电极间短路等的不良状况。
即，在有关比较例1及2的半导体装置的情况下，为了使导通电阻满足作为充放电电路而需要的2.4mΩ以下，需要(1)金属层31的厚度为20μm以上、并且(2)金属层31厚度/半导体层40厚度大于0.27，但在满足上述(1)及(2)的情况下，发生翘曲量成为20μm以上的问题。
[3.兼顾半导体装置的导通电阻的降低及翘曲的降低的构造]
相对于上述的有关比较例1及2的半导体装置，有关本实施方式的半导体装置1中与金属层31的与半导体基板32相反侧的主面整面接触而形成粘接层39，与粘接层39的与金属层31相反侧的主面整面接触而形成由陶瓷材料构成的支承体30。
作为由陶瓷材料构成的支承体30的应力发生的主要原因的热膨胀系数及杨氏模量等物理常数与由金属材料构成的金属层31的上述物理常数相比，具有与半导体基板32的上述物理常数接近的值。即，通过支承体30与金属层31的接合，发生将通过半导体基板32与金属层31的接合而发生的热膨胀应力抵消的方向的热膨胀应力。由此，在与金属层31对置的主面中，取得热膨胀应力的平衡，所以能够抑制金属层31及半导体层40的层叠体的翘曲。
相对于此，在有关专利文献1的半导体装置中，与金属层的与半导体基板相反侧的主面接触而形成有导电层。导电层的上述物理常数具有比半导体基板的上述物理常数更接近于金属层的上述物理常数的值。因此，在有关专利文献1的半导体装置中，将通过半导体基板与金属层的接合而发生的应力抵消的方向的应力不会通过导电层与金属层的接合而发生。
此外，在有关本实施方式的半导体装置1中，作为用来抑制在厚度20μm以上、并且相对于半导体层40的厚度的比例大于0.27的金属层31上作用的热膨胀应力的支承体30，用在专利文献2中公开的绝缘覆膜(涂敷型的有机材料、有机类的带或无机类氧化物薄膜)那样的薄膜类的材料是不够的。相对于此，作为用来抑制在厚度20μm以上、并且相对于半导体层40的厚度的比例大于0.27的金属层31上作用的热膨胀应力的支承体30，将热膨胀系数及杨氏模量与半导体层40比较接近的陶瓷材料的支承体30直接向金属层31粘贴在现实中较困难。因此，在有关本实施方式的半导体装置1中，做成了使粘接层39介于金属层31与支承体30之间的结构。
由此，为了抑制在厚度20μm以上、并且相对于半导体层40的厚度的比例大于0.27的金属层31上作用的热膨胀应力，在金属层31的与半导体基板32相反侧形成粘接层39及由陶瓷材料构成的支承体30，由此能够提供兼顾了导通电阻的降低和半导体装置1的翘曲的抑制的芯片尺寸封装型的半导体装置1。
另外，支承体30的陶瓷材料例如是硅。由此，与氮化硅及氧化硅相比，提高将半导体装置通过切割(dicing)而单片化的情况下的切削加工性。此外，与氮化硅及氧化硅相比容易获得材料，并且成本低。
此外，金属层31的金属材料例如是银(Ag)。由此，与通常作为金属材料使用的铜(Cu)等相比，能够有效地降低导通电阻。
另外，有关本实施方式的半导体装置1中，金属层31也可以比半导体层40厚。由此，能够贡献于导通电阻的进一步降低。
此外，支承体30也可以比半导体层40薄。在有关本实施方式的半导体装置1的结构中，由于粘接层39介于金属层31与支承体30之间，所以即使在支承体30比半导体层40薄的情况下，也能够贡献于半导体基板32及金属层31的翘曲量降低。
此外，粘接层39也可以是导电性粘接剂，例如可以举出导电性DAF。此外，作为导电性粘接剂的材料，例如可以举出银膏。由此，能够贡献于导通电阻的进一步降低。
[4.构成半导体装置的各层的厚度的优化]
这里，说明将用来降低有关本实施方式的半导体装置1的导通电阻及翘曲的各层的厚度优化的过程。
首先，将贴合了物理常数不同的多层的情况下发生的翘曲量的理论式(由多层粘合理论导出的式子)适用于由半导体层40、金属层31、粘接层39及支承体30这4层构成的有关本实施方式的半导体装置1(步骤S10)。
接着，将上述理论式拟合，以使基于上述理论式导出的有关本实施方式的半导体装置1的翘曲量δ匹配于使用有限要素法构建的翘曲计算模拟器中的计算值(步骤S20)。
最后，根据由上述理论式及翘曲计算模拟器导出的有效的翘曲量δe的计算式，导出有关本实施方式的半导体装置1的翘曲量δe为20μm以下及40μm以下的情况下的粘接层39及支承体30的厚度(步骤S30)。
首先，对上述步骤S10进行说明。
图4A是表示用来导出在多层体中发生的翘曲量的基本模型的图。如图4A所示，将具有(热膨胀系数α1，杨氏模量E1)及厚度t1的第1层、具有(热膨胀系数α2，杨氏模量E2)及厚度t2的第2层、具有(热膨胀系数α3，杨氏模量E3)及厚度t3的第3层、以及具有(热膨胀系数α4，杨氏模量E4)及厚度t4的第4层朝向y轴负方向依次接合。另外，假定从y轴方向观察的各层的长度L及宽度(进深)b在4层中都相同。
图4B是说明在多层体中发生的翘曲量δ的侧视概略图。如该图所示，将通过在多层体中发生的应力而多层体的x轴正方向的端部从水平位置向y轴负方向移位的量定义为翘曲量δ。
这里，基于非专利文献1(尾田十八，“多層ばり理論によるプリント基板の応力·変形解析(基于多层粘合理论的印刷基板的应力·变形解析)”，机论A篇，pp.1777－1782，1993年)中记载的多层粘合理论，在图4A所示的多层体模型中发生的翘曲量δ由以下的式1表示。此外，式1的R由式2表示。
[数式1]
Figure GDA0003574913060000141
[数式2]
Figure GDA0003574913060000151
F＝4X0Y+K12X12+K13X13+K23X23+K14X14+K24X24+K34X34
G＝2ΔT((α1-α2)X12+(α1-α3)X13+(α2-α3)X23+(α1-α4)X14+(α2-α4)X24+(α3-α4)X34}
Y＝E1I1+E2I2+E3I3+E4I4
Figure GDA0003574913060000152
X0＝t1E1+t2E2+t3E3+t4E4
X12＝K12t1t2E1E2，X13＝K13t1t3E1E3，X23＝K23t2t3E2E3
X14＝K14t1t4E1E4，X24＝K24t2t4E2E4，X34＝K34t3t4E3E4
K12＝t1+t2，K13＝t1+t3+2t2，K23＝t2+t3
K14＝t1+t4+2(t2+t3)，K24＝t2+t4+2t3，K34＝t3+t4 (式2)
根据式1及式2，翘曲量δ可以表示为各层的厚度tn(n＝1～4)的函数，决定该函数的其他参数是各层的长度L、变化温度ΔT、各层的(αn，En)(n＝1～4)。
在表3中，表示使用上述式1及式2求出的翘曲量δ的一例。此外，在表4中，表示在求出表3的翘曲量δ时使用的其他参数。
[表3]
Figure GDA0003574913060000153
[表4]
Figure GDA0003574913060000161
另外，在表4中，将宽度b设为1mm，但是关于翘曲量δ的计算，宽度b在分母及分子双方中出现而被抵消，所以宽度可以是任意的值。
接着，对上述步骤S20进行说明。在步骤S20中，将上述式1及式2拟合，以使基于上述式1及式2导出的翘曲量δ匹配于翘曲计算模拟器中的计算值δs。另外，在该拟合中使用的翘曲计算模拟器是将使用有限要素法解析的构造解析软件(ANSYS公司制)使用所需量的翘曲实测数据进行定制而成的。
使用向上述翘曲计算模拟器代入表3所示的各层的厚度t1～t4、表4所示的各参数而得到的翘曲量的计算值δs，能够对由式1及式2计算出的理论上的翘曲量δ进行修正。具体而言，如果设翘曲量δ与翘曲量δs的比为β(＝δs/δ)，则能够将翘曲量δ向拟合为翘曲计算模拟器计算值的有效的翘曲量δe变换。即，使用拟合系数β，用以下的式3表示有效的翘曲量δe。
[数式3]
δe＝β·δ (式3)
在表3的各数据中，最优的拟合系数β是0.67。
接着，对上述步骤S30进行说明。通过式3所示的有效的翘曲量δe的计算式(以后，称作有效值计算式)，导出有关本实施方式的半导体装置1的翘曲量是(1)20μm以下及(2)40μm以下的情况下的粘接层39及支承体30的厚度。
图5是使用有效值计算式计算出的、表示相对于粘接层39的厚度及支承体30的厚度的、翘曲量δe的变化的曲线图。在该图中，表示将半导体层40的厚度固定为20μm、以及将金属层31的厚度固定为30μm、使粘接层39的厚度变化为0μm、30μm及50μm的情况下的支承体30的厚度与翘曲量δe的关系。另外，其他参数为表4所示的值。
根据图5的曲线图，首先，掌握使翘曲量δe成为20μm以下的粘接层39与支承体30的关系。根据图5可知以下。
(1)粘接层39较厚时，翘曲量δe为0的支承体30的厚度较小。即，因粘接层39的存在，支承体30的所需量变少。
(2)如果使支承体30变厚，则暂且成为反翘曲(翘曲量δe取负值)，但如果进一步变厚，则接近于0。反翘曲中的翘曲量δe的极小点是10μm左右，不是20μm以上。因此，在给出粘接层39及支承体30的厚度的条件的情况下，只要给出使正向翘曲成为20μm以下的条件就可以。
在上述的粘接层39及支承体30的厚度的条件给出中，有关本实施方式的半导体装置1具备具有不同的物理常数及不同的厚度的4个层，所以研究对象的参数较多。所以，通过以下的方针，计算粘接层39及支承体30的厚度。
(1)主要的参数是4个层的各厚度及翘曲量δe。将翘曲量δe的规格值设为第1规格值20μm及第2规格值40μm。
(2)有关本实施方式的半导体装置1的特征在于，为了抑制在半导体层40及金属层31中发生的翘曲，配置了粘接层39及支承体30，所以将满足翘曲量δe的规格值的支承体30的厚度以依赖于粘接层39的厚度的形式来规定。即，根据使用的粘接层39的厚度，导出能够决定支承体30的厚度的函数。
图6A是表示使用有效值计算式计算出的、将半导体层40的厚度固定的情况下((a)是半导体层40的厚度10μm，(b)是半导体层40的厚度80μm)的、用来使翘曲量δe成为20μm的金属层31、粘接层39及支承体30的厚度的关系的曲线图。此外，图6B是表示使用有效值计算式计算出的、将金属层31的厚度固定的情况下((a)是金属层31的厚度20μm，(b)是金属层31的厚度70μm)的、用来使翘曲量δe成为20μm的半导体层40、粘接层39及支承体30的厚度的关系的曲线图。
在半导体层40的厚度20μm、40μm、60μm的情况下也使用有效值计算式取得如图6A的(a)及(b)所示的曲线图，此外，在金属层31的厚度40μm、50μm、60μm的情况下也使用有效值计算式取得如图6B的(a)及(b)所示的曲线图。从这样取得的曲线图，提取使翘曲量δe成为20μm的每种粘接层39的厚度的支承体30的厚度。此时，根据半导体层40的厚度及金属层31的厚度的变化，使翘曲量δe成为20μm的每种粘接层39的厚度的支承体30的厚度变化，在半导体层40的厚度及金属层31的厚度变化过程中，提取每种粘接层39的厚度的支承体30的厚度的最大值。将同样的提取过程还适用于使翘曲量δe成为40μm的每种粘接层39的厚度的支承体30的厚度。
在表5中，表示通过该提取过程取得的每种粘接层39的厚度的支承体30的厚度的组合。此外，在表6中表示在求出了表5的翘曲量δe时使用的其他参数。
[表5]
Figure GDA0003574913060000181
[表6]
Figure GDA0003574913060000182
另外，在将作为翘曲量δe规格值的20μm及40μm设定为目标值，提取相对于粘接层39的厚度的、支承体30的厚度的关系的情况下，使用表6所示的参数中的目标值，将作为翘曲量δe规格值的20μm及40μm设定为容许值，在提取相对于粘接层39的厚度的、支承体30的厚度的关系的情况下，使用表6所示的参数中的最大值。
图7是在有关实施方式1的半导体装置1中、规定了用来成为翘曲量20μm及40μm的相对于粘接层39的厚度的、支承体30的厚度的关系的曲线图。在该图中标绘了表5所示的提取数据。根据该图所示的曲线图，可得到(1)表示使翘曲量δe成为20μm(目标值)的相对于粘接层39的厚度的、支承体30的厚度的关系的近似式、(2)表示使翘曲量δe成为20μm(容许值)的相对于粘接层39的厚度的、支承体30的厚度的关系的近似式、(3)表示使翘曲量δe成为40μm(目标值)的相对于粘接层39的厚度的、支承体30的厚度的关系的近似式、(4)表示使翘曲量δe成为40μm(容许值)的相对于粘接层39的厚度的、支承体30的厚度的关系的近似式。根据这些近似式，抑制半导体装置1的翘曲量的相对于粘接层39的厚度的、支承体30的厚度的关系由式4～式7表示。
(1)在设粘接层39的厚度为t3(μm)、支承体30的厚度为t4(μm)的情况下，使翘曲量δe成为20μm以下的相对于粘接层39的厚度的、支承体30的厚度由以下的式4表示。
[数式4]
t4≥1.10×10-3·t3 2-2.24×10-1·t3+1.88×101 (式4)
由此，在金属层31的厚度为20μm、并且金属层31厚度/半导体层40厚度大于0.27的半导体装置1中，在各层的长度L是3.4mm以下、粘接层39的热膨胀系数α3是50(ppm/℃)以下、粘接层39的杨氏模量E3是1.1(GPa)以下的条件下，能够使半导体装置1的翘曲量成为20μm以下。
(2)在设粘接层39的厚度为t3(μm)、支承体30的厚度为t4(μm)的情况下，使翘曲量δe成为20μm以下的相对于粘接层39的厚度的、支承体30的厚度由以下的式5表示。
[数式5]
t4≥4.00×10-4·t3 2-8.68×10-2·t3+2.60×101 (式5)
由此，在金属层31的厚度为20μm、并且金属层31厚度/半导体层40厚度大于0.27的半导体装置1中，在各层的长度L是4.0mm以下、粘接层39的热膨胀系数α3是100(ppm/℃)以下、粘接层39的杨氏模量E3是5.0(GPa)以下的条件下，能够使半导体装置1的翘曲量成为20μm以下。
(3)在设粘接层39的厚度为t3(μm)、支承体30的厚度为t4(μm)的情况下，使翘曲量δe成为40μm以下的相对于粘接层39的厚度的、支承体30的厚度由以下的式6表示。
[数式6]
t4≥9.00×10-4·t3 2-1.54×10-1·t3+9.12 (式6)
由此，在金属层31的厚度为20μm、并且金属层31厚度/半导体层40厚度大于0.27的半导体装置1中，在各层的长度L是3.4mm以下、粘接层39的热膨胀系数α3是50(ppm/℃)以下、粘接层39的杨氏模量E3是1.1(GPa)以下的条件下，能够使半导体装置1的翘曲量成为40μm以下。
(4)在设粘接层39的厚度为t3(μm)、支承体30的厚度为t4(μm)的情况下，使翘曲量δe成为40μm以下的相对于粘接层39的厚度的、支承体30的厚度由以下的式7表示。
[数式7]
t4≥2.00×10-4·t3 2-4.11×10-2·t3+1.30×101 (式7)
由此，在金属层31的厚度为20μm、并且金属层31厚度/半导体层40厚度大于0.27的半导体装置1中，在各层的长度L是4.0mm以下、粘接层39的热膨胀系数α3是100(ppm/℃)以下、粘接层39的杨氏模量E3是5.0(GPa)以下的条件下，能够使半导体装置1的翘曲量成为40μm以下。
[5.有关变形例的半导体装置的构造]
图8A是有关实施方式1的变形例1的半导体装置1A的剖视图。此外，图8B是表示有关实施方式1的变形例1的半导体装置1A的电极结构的一例的俯视图。图8A的剖视图是观察图8B的VIIIA-VIIIA的切断面的图。如图8A所示，半导体装置1A具有半导体基板32、低浓度杂质层33、金属层31、粘接层39、支承体30、晶体管10和晶体管20。如图8B所示，在将半导体基板32平面视的情况下，半导体装置1A具有2个第1源极电极11、2个第2源极电极21、1个第1栅极电极19及1个第2栅极电极29。在晶体管10的上表面，沿着与晶体管10和晶体管20对置的方向垂直的方向，依次形成有第1源极电极11、第1栅极电极19及第1源极电极11。此外，在晶体管20的上表面，沿着与晶体管10和晶体管20对置的方向垂直的方向，依次形成有第2源极电极21、第1栅极电极29及第1源极电极21。另外，构成1个晶体管的源极电极及栅极电极的个数及配置关系并不限定于图8B所示。
有关本变形例的半导体装置1A与有关实施方式1的半导体装置1相比，结构上只有在晶体管10及20的边界形成有切入部61这一点不同。以下，对于有关本变形例的半导体装置1A，关于与有关实施方式1的半导体装置1相同的结构省略说明，以不同的结构为中心进行说明。
如图8A及图8B所示，在有关本变形例的半导体装置1A中，在晶体管10的第1区域与晶体管20的第2区域之间的边界，从半导体装置1A的上表面侧朝向下表面侧形成有切入部61。此外，切入部61被形成到低浓度杂质层33。另外，有关本变形例的半导体装置1A的切入部61的最下端比半导体基板32的下表面更靠半导体装置1A的上表面侧。
由此，能够将半导体基板32与低浓度杂质层33之间的内部应力缓和，能够防止半导体基板32与低浓度杂质层33的剥离。此外，通过切入部61到达半导体基板32，能够将半导体基板32与金属层31之间的内部应力缓和，能够防止半导体基板32与金属层31的剥离。
图9是有关实施方式1的变形例2的半导体装置1B的剖视图。另外，关于表示有关实施方式1的变形例2的半导体装置1B的电极结构的一例的俯视图，与图8B所示的半导体装置1A的俯视图是同样的，所以省略。
如图9所示，半导体装置1B具有半导体基板32、低浓度杂质层33、金属层31、粘接层39、支承体30、晶体管10和晶体管20。半导体装置1B在将半导体基板32平面视的情况下，具有2个第1源极电极11、2个第2源极电极21、1个第1栅极电极19及1个第2栅极电极29。在晶体管10的上表面，沿着与晶体管10和晶体管20对置的方向垂直的方向，依次形成有第1源极电极11、第1栅极电极19及第1源极电极11。此外，在晶体管20的上表面，沿着与晶体管10和晶体管20对置的方向垂直的方向，依次形成有第2源极电极21、第1栅极电极29及第1源极电极21。另外，构成1个晶体管的源极电极及栅极电极的个数及配置关系并不限定于图8B所示。
有关本变形例的半导体装置1B与有关实施方式1的半导体装置1相比，结构上只有在晶体管10及20的边界形成有切入部62这一点不同。以下，对于有关本变形例的半导体装置1B，关于与有关实施方式1的半导体装置1相同的结构省略说明，以不同的结构为中心进行说明。
如图9所示，在有关本变形例的半导体装置1B中，在晶体管10的第1区域与晶体管20的第2区域之间的边界，从半导体装置1B的上表面侧朝向下表面侧形成有切入部62。此外，切入部62被形成到金属层31。另外，有关本变形例的半导体装置1B的切入部62的最下端位于金属层31的上表面与下表面之间。
由此，能够将半导体基板32与金属层31之间的内部应力缓和，能够防止半导体基板32与金属层31的剥离。进而，能够将金属层31与粘接层39及支承体30之间的内部应力缓和，能够防止金属层31与支承体30之间的剥离。
[6.半导体装置的制造方法]
参照图10A～图10C、图11A～图11B、图12A～图12B、图13及图14，对有关实施方式1的半导体装置1的制造方法进行说明。这里以“纵型”MOSFET为例进行说明，但除此以外，在二极管、“纵型”的双极晶体管等中也当然能够得到同样的效果。
图10A是表示有关实施方式1的半导体装置1的制造方法的第1工序的剖视图。图10B是表示有关实施方式1的半导体装置1的制造方法的第2工序的剖视图。图10C是表示有关实施方式1的半导体装置的制造方法的第3工序的剖视图。
首先，如图10A所示，在半导体基板32A的一主面上形成低浓度杂质层33，进而在低浓度杂质层33的表面区域中形成元件区域。接着，在元件区域上的规定部位形成以Al或Cu等金属为主材料的电极(第1源极电极、第2源极电极)。
接着，如图10B所示，在半导体基板32A的一主面侧涂敷临时粘接剂37。此时，优选的是使临时粘接剂37比电极及元件区域等的凹凸厚。进而，在临时粘接剂37之上载置玻璃基板36，通过推压而粘接。此时，为了使得气泡不进入到玻璃基板36与临时粘接剂37之间，优选的是在真空腔室内粘接。
接着，如图10C所示，为了能够实现被要求的电气特性(导通电阻)，对半导体基板32A的与一主面相反侧的背面进行背面研磨，直到半导体基板32A的厚度成为希望的厚度(优选的是50μm以下)，形成希望的厚度的半导体基板32。更优选的是进行CMP等的镜面处理。
图11A是表示有关实施方式1的半导体装置1的制造方法的第4工序的剖视图。图11B是表示有关实施方式1的半导体装置1的制造方法的第5工序的剖视图。
接着，如图11A所示，在半导体基板32的与一主面相反侧的背面形成金属层31。作为具体的方法，使用蒸镀法在半导体基板32的背面整体形成第1金属层31A，以使其与半导体基板32取欧姆接触。这里，作为第1金属层31A，例如从距半导体基板32的背面较近一侧起依次层叠Ti及Ni。
接着，在第1金属层31A上形成第2金属层31B。具体而言，使用电解镀层法形成。这里，作为第2金属层31B，可以主要使用Ag、Au、Cu等。在以后的说明中，将第1金属层31A和第2金属层31B一起称作金属层31。
接着，如图11B所示，在金属层31上涂敷粘接剂，形成粘接层39。此时，优选的是使粘接层39比金属层31的表面凹凸厚。进而，在粘接层39之上载置支承体30，通过推压而粘接。此时，为了使得气泡不进入到支承体30与粘接层39之间，优选的是在真空腔室内粘接。
作为形成粘接层39的粘接剂，使用环氧树脂、酚醛树脂等的热固化型树脂。此外，作为支承体30，除了硅等的材料以外，在使用石英、蓝宝石、硼硅酸玻璃、钠钙玻璃等对于紫外线透明的材料的情况下，作为粘接剂也可以使用环氧丙烯酸酯、丙烯酸丙烯酸酯、氨酯丙烯酸酯等的紫外线固化型树脂。
接着，对使上述粘接剂固化的工序进行说明。作为将热固化型树脂用作粘接剂的情况下的工序，将进行了贴合后的晶片例如投入到150℃左右的恒温炉中并加热1～2小时。通过加热，使上述粘接剂固化，使支承体30与金属层31之间较强地粘接。
此外，在上述粘接剂中使用紫外线固化型树脂的情况下，对使用高压水银灯等紫外线发生装置进行了贴合的晶片的支承体30侧的面照射紫外线。照射的光量例如设为300～2000mJ/cm2。
图12A是表示有关实施方式1的半导体装置1的制造方法的第6工序的剖视图。图12B是表示有关实施方式1的半导体装置1的制造方法的第7工序的剖视图。
接着，如图12A所示，在支承体30的表面及环形框架50上粘贴切割带38，进行向环形框架50的装配。
接着，将临时粘接剂37和玻璃基板36除去。具体而言，如图12A所示，通过向临时粘接剂37的与玻璃基板36的边界面附近照射激光70，使与玻璃基板36接触的部分的临时粘接剂37改性，从由半导体基板32构成的晶片除去玻璃基板36。然后，如图12B所示，将临时粘接剂37剥离除去。
图13是表示有关实施方式1的半导体装置1的制造方法的第8工序的剖视图。
最后，如图13所示，例如使用切割锯等的切割刀具80，将半导体基板32、低浓度杂质层33、金属层31、粘接层39及支承体30切割，向多个半导体基板1单片化。
在包括金属层31的半导体基板32的切割时，有切削掉的金属附着在刀具上、成为堵塞状态而不能维持切削能力的问题。进而可以想到，如果使由硅构成的半导体基板32变薄，则导致向刀具的切削负荷减小、刀具的磨损变慢、难以消除上述的堵塞这样的恶性循环，进而难以维持切削能力。相对于此，在有关本实施方式的半导体装置1中，作为支承体30而使用硅。硅是对刀具赋予适度的负荷而促进刀具的磨损的材质，所以能够改善上述的堵塞问题。
此外，在比较例1及2那样的以往的构造中，由于半导体装置的单侧最表面为金属层，所以当通过切割加工将金属层切削时，由刀具将金属层拉深，发生较大的毛刺。
相对于此，在有关本实施方式的半导体装置1的制造工序中，由于是金属层31被半导体基板32及支承体30夹着的构造，所以成为在最表面没有金属层31那样的延展性材料的状态，所以起到在切削端面不易发生毛刺的效果。
图14是表示有关实施方式1的半导体装置的制造方法的第9工序的剖视图。作为再另一例，如图14所示，在最后的切割工序时，使用切割刀具81在多个晶体管之间设置切入部64。由此，能够将由半导体基板32和形成在其上的元件区域及电极带来的内部应力缓和，能够防止半导体基板32与金属层31之间的剥离。图14的工序也可以在图10A～图10C、图11A～图11B、图12A～图12B所示的制造工序之后执行，在图14的工序之后，通过图13所示的切割工序向单个的半导体装置1分离。如图14所示，在形成在半导体装置1上的多个晶体管之间通过切割刀具81形成切入部64。
以上，基于实施方式对有关本发明的1个或多个技术方案的半导体装置进行了说明，但本发明并不限定于该实施方式。只要不脱离本发明的主旨，对本实施方式实施了本领域技术人员想到的各种变形后的形态、或将不同实施方式的一部分的构成要素组合而构建的形态也包含在本发明的1个或多个技术方案的范围内。
产业上的可利用性
有关本发明的半导体装置作为CSP型的半导体装置，能够广泛地用于双向晶体管、单向晶体管、二极管等各种半导体装置。
标号说明
1、1A、1B 半导体装置
2 控制IC
3 电池
4 负载
10 晶体管(第1纵型MOS晶体管)
11 第1源极电极
12、22 第1部分
13、23 第2部分
14 第1源极区域
15 第1栅极导体
16 第1栅极绝缘膜
18 第1主体区域
19 第1栅极电极
20 晶体管(第2纵型MOS晶体管)
21 第2源极电极
24 第2源极区域
25 第2栅极导体
26 第2栅极绝缘膜
28 第2主体区域
29 第2栅极电极
30 支承体
31 金属层
31A 第1金属层
31B 第2金属层
32、32A 半导体基板
33 低浓度杂质层
34 层间绝缘层
35 钝化层
36 玻璃基板
37 临时粘接剂
38 切割带
39 粘接层
40 半导体层
50 环形框架
61、62 切入部
63、64 切入部
70 激光
80、81 切割刀具

Claims (12)

1.一种半导体装置，其是能够进行倒装安装的芯片尺寸封装型的半导体装置，其中，具备：
半导体基板，由硅构成，包含第1导电型的杂质；
低浓度杂质层，与上述半导体基板的上表面接触而形成，包含浓度比上述半导体基板的上述第1导电型的杂质的浓度低的上述第1导电型的杂质；
金属层，与上述半导体基板的下表面整面接触而形成，仅由厚度为20μm以上的金属材料构成；
第1纵型MOS晶体管，形成在上述低浓度杂质层内的第1区域中；以及
第2纵型MOS晶体管，形成在上述低浓度杂质层内的第2区域中，该第2区域在沿着上述半导体基板的上表面的方向上与上述第1区域相邻；
上述第1纵型MOS晶体管具有在上述低浓度杂质层的上表面形成的第1源极电极及第1栅极电极；
上述第2纵型MOS晶体管具有在上述低浓度杂质层的上表面形成的第2源极电极及第2栅极电极；
上述半导体基板作为将上述第1纵型MOS晶体管的第1漏极区域及上述第2纵型MOS晶体管的第2漏极区域共通化的漏极区域发挥功能；
将在上述第1源极电极与上述第2源极电极之间经由上述第1漏极区域、上述金属层及上述第2漏极区域流动的双向路径作为主电流路径；
上述金属层的厚度相对于包括上述半导体基板和上述低浓度杂质层的半导体层的厚度的比例大于0.27；
上述半导体装置还具有由陶瓷材料构成的支承体，该支承体仅经由粘接层粘接在上述金属层的下表面整面。
2.如权利要求1所述的半导体装置，其中，
上述陶瓷材料是硅。
3.如权利要求1或2所述的半导体装置，其中，
上述金属材料是银。
4.如权利要求3所述的半导体装置，其中，
上述金属层的厚度比上述半导体层的厚度厚。
5.如权利要求3所述的半导体装置，其中，
上述支承体的厚度比上述半导体层的厚度薄。
6.如权利要求3所述的半导体装置，其中，
上述粘接层的构成材料是导电性材料。
7.如权利要求3所述的半导体装置，其中，
在设上述支承体的厚度为t4、上述粘接层的厚度为t3的情况下，满足
[数式1]
t4≥9.00×10-4·t3 2-1.54×10-1·t3+9.12。
8.如权利要求7所述的半导体装置，其中，
在设上述支承体的厚度为t4、上述粘接层的厚度为t3的情况下，满足
[数式2]
t4≥2.00×10-4·t3 2-4.11×10-2·t3+1.30×101。
9.如权利要求7所述的半导体装置，其中，
在设上述支承体的厚度为t4、上述粘接层的厚度为t3的情况下，满足
[数式3]
t4≥1.10×10-3·t3 2-2.24×10-1·t3+1.88×101。
10.如权利要求9所述的半导体装置，其中，
在设上述支承体的厚度为t4、上述粘接层的厚度为t3的情况下，满足
[数式4]
t4≥4.00×10-4·t3 2-8.68×10-2·t3+2.60×101。
11.如权利要求1所述的半导体装置，其中，
在上述第1区域与上述第2区域之间的边界，从上述半导体装置的上表面侧朝向下表面侧形成有切入部；
上述切入部的最下端比上述半导体基板的下表面更靠上述上表面侧。
12.如权利要求1所述的半导体装置，其中，
在上述第1区域与上述第2区域之间的边界，从上述半导体装置的上表面侧朝向下表面侧形成有切入部；
上述切入部的最下端位于上述金属层的上表面与下表面之间。
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