JP6281897B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6281897B2 JP6281897B2 JP2013225789A JP2013225789A JP6281897B2 JP 6281897 B2 JP6281897 B2 JP 6281897B2 JP 2013225789 A JP2013225789 A JP 2013225789A JP 2013225789 A JP2013225789 A JP 2013225789A JP 6281897 B2 JP6281897 B2 JP 6281897B2
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- Prior art keywords
- diffusion layer
- semiconductor device
- region
- type diffusion
- output power
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- 229910000679 solder Inorganic materials 0.000 description 6
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- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Description
第1の実施の形態に係る半導体装置の構成例について説明する。図1Bは、第1の実施の形態に係る半導体装置の構成例を模式的に示す断面図である。半導体装置1は、N+半導体基板11と、N−エピタキシャル層12と、出力パワーMOSFET100と、出力パワーMOSFET200と、P型拡散層領域13とを具備している。
ただし、図1Bの半導体装置1を、図4の車載用の4出力ハイサイドIPDに適用した場合の動作について説明する。ここでは、電気的ノイズが出力パワーMOSFETの出力端子に印加されたときの動作について説明する。
第2の実施の形態に係る半導体装置について説明する。本実施の形態では、出力パワーMOSFETの周囲にP型ウェルを設けている点、及び、出力パワーMOSFET間に設けられるP型拡散層領域の構成の点で、第1の実施の形態と相違している。以下では、その相違点に関して主に説明する。
加えて、寄生電流をより効率的にバッテリー電位VBATを有する電極へ流し込むことが可能となる。そのため、出力パワーMOSFETに流れ込む寄生電流をより低減することが可能となる。
第3の実施の形態に係る半導体装置について説明する。本実施の形態では、出力パワーMOSFET間に設けられるP型拡散層領域に関わる構成が、第1の実施の形態と相違している。以下では、その相違点に関して主に説明する。
加えて、P型拡散層領域13の近傍でN型拡散層領域72を介してバッテリー電位VBATに接続しているため、電極層71(例示:アルミ配線)の抵抗による電圧降下の影響が低減される。そのため、出力パワーMOSFETに流れ込む寄生電流をより効率的にバッテリー電位VBATに流し込むことが可能となる。
第4の実施の形態に係る半導体装置について説明する。本実施の形態では、出力パワーMOSFETと通常のMOSFETとの間にP型拡散層領域を設ける点で、第1の実施の形態と相違している。以下では、その相違点に関して主に説明する。
加えて、制御回路30のPchMOSFET600及びNchMOSFET500へ寄生電流が侵入することを防止でき、制御回路30の誤動作を防止することが可能となる。
2 :リードフレーム
3 :制御チップ
3a、3b、3d :パッド
3c :GND用配線
4、4a、4b、4c :ボンディングワイヤ
5 :マイクロコンピュータ
6 :基板
7 :モータ
8 :トランジスタMLL
9 :トランジスタMLR
11 :N+半導体基板
12 :N−エピタキシャル層
13 :P型拡散層領域
13a :P型拡散層領域
14 :電極層
15 :寄生PNPトランジスタ
16 :N+拡散層領域
16a :ビア
17 :層間絶縁層
18 :カバー膜
19、19a :パッド
21 :はんだ
23、23a、23b、23c :端子
30 :制御回路
42 :ワイヤーハーネス
61 :P型ウェル
62 :P型ウェル
63 :P型拡散層領域
63a :P型拡散層領域
71 :電極層
72 :N型拡散層領域
101 :P型ベース層
102 :ポリシリコン層
102a :絶縁層
103 :電極
103a :N型拡散層
104 :P型拡散層
201 :P型ベース層
202 :ポリシリコン層
202a :絶縁層
203 :電極
203a :N型拡散層
204 :P型拡散層
501 :Pウェル
502 :ゲート電極
502a :ゲート絶縁膜
503、504 :ソース/ドレイン
602 :ゲート電極
602a :ゲート絶縁膜
603、604 :ソース/ドレイン
1001 :半導体装置
1013 :P型拡散層
1014 :トレンチ酸化膜
IB :ベース電流
IC :コレクタ電流
100、200、300、400 :NchパワーMOFET:
500 :NchMOSFET
600 :PchMOSFET
OUT1 :出力端子
OUT2 :出力端子
R :負荷
VBAT :バッテリー電位
Claims (8)
- 高濃度で第1導電型を有する第1半導体層と、
前記第1半導体層上に接合され、低濃度で前記第1導電型を有する第2半導体層と、
前記第2半導体層の表面領域に形成された前記第1導電型チャネルの第1パワートランジスタと、
前記第2半導体層の表面領域に形成されたトランジスタと、
前記第2半導体層の表面領域に、前記第1パワートランジスタと前記トランジスタとの間に境界を設けるように形成された第2導電型の第1拡散層領域と、
前記第1拡散層領域に接続された電極と
を具備し、
前記第1半導体層は、前記第1パワートランジスタのドレインとして機能し、
前記第1拡散層領域に接続された前記電極は、前記ドレインと同電位に設定される
半導体装置。 - 請求項1に記載の半導体装置において、
前記第1導電型はN型であり、
前記第2導電型はP型であり、
前記第1拡散層領域は、相対的に高い電源電位に設定される
半導体装置。 - 請求項1に記載の半導体装置において、
前記トランジスタは、前記第2半導体層の表面領域に形成された前記第1導電型チャネルの第2パワートランジスタであり、
前記第1半導体層は、前記第2パワートランジスタのドレインとしても機能する
半導体装置。 - 請求項1に記載の半導体装置において、
前記トランジスタは、前記第2半導体層の表面領域に形成された、前記第1導電型チャネルのプレーナ型トランジスタ及び前記第2導電型チャネルのプレーナ型トランジスタの少なくとも一方である
半導体装置。 - 請求項3に記載の半導体装置において、
前記第1パワートランジスタ及び前記第2パワートランジスタを含む複数のパワートランジスタを更に具備し、
前記第1半導体層は、前記複数のパワートランジスタのドレインとしても機能し、
前記第1拡散層領域は、前記複数のパワートランジスタにおける隣り合う二つのパワートランジスタのソースの間に境界を設けるように形成される
半導体装置。 - 請求項1に記載の半導体装置において、
前記第1パワートランジスタは、チャネルとなる前記第2導電型のベース拡散層を備え、
前記第1拡散層領域の拡散深さは、前記ベース拡散層の拡散深さと同じである
半導体装置。 - 請求項1に記載の半導体装置において、
前記第1パワートランジスタは、チャネルとなる前記第2導電型のベース拡散層と、
前記ベース拡散層を周囲を囲むように設けられたウェル拡散層と
を備え、
前記第1拡散層領域の拡散深さは、前記ウェル拡散層の拡散深さと同じである
半導体装置。 - 請求項1に記載の半導体装置において、
前記第1パワートランジスタは、
チャネルとなる前記第2導電型のベース拡散層と、
前記ベース拡散層を表面側から内部側へ貫通するように形成されたゲートと、
前記ベース拡散層の表面領域における前記ゲートの側面に形成された前記第1導電型のソースと
を備える
半導体装置。
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JP6281897B2 (ja) * | 2013-10-30 | 2018-02-21 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9923051B1 (en) * | 2016-09-21 | 2018-03-20 | Xilinx, Inc. | Substrate noise isolation structures for semiconductor devices |
CN110114888B (zh) * | 2016-12-27 | 2022-06-21 | 新唐科技日本株式会社 | 半导体装置 |
JP6447946B1 (ja) | 2018-01-19 | 2019-01-09 | パナソニックIpマネジメント株式会社 | 半導体装置および半導体モジュール |
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JP2729062B2 (ja) * | 1987-10-27 | 1998-03-18 | 日本電気株式会社 | 集積回路装置 |
JPH06151740A (ja) * | 1992-11-12 | 1994-05-31 | Nippondenso Co Ltd | パワー半導体装置 |
EP0694960B1 (en) * | 1994-07-25 | 2002-07-03 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe | Process for the localized reduction of the lifetime of charge carriers |
JP3325736B2 (ja) * | 1995-02-09 | 2002-09-17 | 三菱電機株式会社 | 絶縁ゲート型半導体装置 |
DE69531783T2 (de) * | 1995-10-09 | 2004-07-15 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno - Corimme | Herstellungsverfahren für Leistungsanordnung mit Schutzring |
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US8159025B2 (en) * | 2010-01-06 | 2012-04-17 | Ptek Technology Co., Ltd. | Gate electrode in a trench for power MOS transistors |
JP2011171551A (ja) * | 2010-02-19 | 2011-09-01 | Toyota Motor Corp | 半導体装置の製造方法 |
JP5662108B2 (ja) * | 2010-11-05 | 2015-01-28 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置 |
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US9048118B2 (en) * | 2012-02-13 | 2015-06-02 | Maxpower Semiconductor Inc. | Lateral transistors with low-voltage-drop shunt to body diode |
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US9627527B2 (en) | 2017-04-18 |
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