WO2018123799A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2018123799A1
WO2018123799A1 PCT/JP2017/045908 JP2017045908W WO2018123799A1 WO 2018123799 A1 WO2018123799 A1 WO 2018123799A1 JP 2017045908 W JP2017045908 W JP 2017045908W WO 2018123799 A1 WO2018123799 A1 WO 2018123799A1
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Prior art keywords
semiconductor device
thickness
layer
metal layer
semiconductor
Prior art date
Application number
PCT/JP2017/045908
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English (en)
French (fr)
Inventor
芳宏 松島
茂稔 曽田
英司 安田
俊和 今井
亮介 大河
一磨 吉田
加藤　亮
Original Assignee
パナソニックＩｐマネジメント株式会社
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Application filed by パナソニックＩｐマネジメント株式会社 filed Critical パナソニックＩｐマネジメント株式会社
Priority to CN202210609454.3A priority Critical patent/CN114975302A/zh
Priority to JP2018559114A priority patent/JP7042217B2/ja
Priority to CN201780080128.5A priority patent/CN110114888B/zh
Publication of WO2018123799A1 publication Critical patent/WO2018123799A1/ja
Priority to US16/447,100 priority patent/US10854744B2/en
Priority to US17/070,211 priority patent/US11056589B2/en

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Definitions

  • the present disclosure relates to a semiconductor device, and more particularly to a chip size package type semiconductor device capable of face-down mounting.
  • a semiconductor substrate having a first main surface and a second main surface, two vertical MOS (Metal Oxide Semiconductor) transistors provided from the first main surface to the second main surface, and the second A semiconductor device including a metal layer formed on a main surface has been proposed.
  • the horizontal path inside the semiconductor substrate not only the horizontal path inside the semiconductor substrate but also the horizontal path in the metal layer having a low conduction resistance can be used as a current path flowing from the first transistor to the second transistor.
  • the on-resistance can be reduced.
  • Patent Document 1 proposes a semiconductor device in which a conductive layer is formed on the side opposite to the semiconductor substrate of the metal layer in addition to the above configuration. With this conductive layer, the generation of burrs in the metal layer can be suppressed in the step of chip separation.
  • Patent Document 2 proposes a semiconductor device in which an insulating film is formed on the opposite side of the metal layer from the semiconductor substrate in addition to the above configuration.
  • the insulating coating can prevent damage such as scratches and scratches while maintaining a thin semiconductor device.
  • Patent Document 1 a conductive layer is formed on the opposite side of the metal layer from the semiconductor substrate.
  • the main material of the conductive layer is the same kind of metal as the metal layer, warpage of the semiconductor device due to temperature change is reduced. Therefore, it is not easy to produce a conductive layer having a sufficient thickness.
  • Patent Documents 1 and 2 cannot achieve both reduction of on-resistance and suppression of warpage of the semiconductor device.
  • an object of the present disclosure is to provide a chip size package type semiconductor device that achieves both reduction of on-resistance and suppression of warpage.
  • one embodiment of a semiconductor device is a chip-size package type semiconductor device capable of face-down mounting, and includes a semiconductor substrate including a first conductivity type impurity and made of silicon.
  • a low-concentration impurity layer formed in contact with the upper surface of the semiconductor substrate and containing the first-conductivity-type impurity having a concentration lower than that of the first-conductivity-type impurity of the semiconductor substrate; and the entire lower surface of the semiconductor substrate
  • a metal layer made of only a metal material having a thickness of 20 ⁇ m or more, a first vertical MOS transistor formed in a first region in the low-concentration impurity layer, and the first And a second vertical MOS transistor formed in a second region in the low-concentration impurity layer adjacent to the region in the direction along the upper surface of the semiconductor substrate, and the first vertical MOS
  • the transistor has a first source electrode and a first gate electrode formed on the upper surface of the low concentration impurity layer, and the second vertical MOS transistor
  • a second source electrode and a second gate electrode wherein the semiconductor substrate includes a first drain region of the first vertical MOS transistor and a second drain region of the second vertical MOS transistor; Functions as a common drain region and flows between the first source electrode and the second source electrode via the first drain region, the metal layer, and the second drain region.
  • the bidirectional current path is a main current path, and the ratio of the thickness of the metal layer to the semiconductor layer including the semiconductor substrate and the low-concentration impurity layer is greater than 0.27.
  • a support made of a ceramic material which is bonded to the entire lower surface of the metal layer only through an adhesive layer.
  • the semiconductor device According to the semiconductor device according to the present disclosure, it is possible to provide a chip size package type semiconductor device capable of face-down mounting that achieves both reduction of on-resistance and suppression of warpage of the semiconductor device.
  • FIG. 1A is a cross-sectional view of the semiconductor device according to the first embodiment.
  • 1B is a top view showing an example of the electrode configuration of the semiconductor device according to Embodiment 1.
  • FIG. FIG. 2A is a circuit diagram showing a first application example to the charge / discharge circuit of the semiconductor device according to the first embodiment.
  • FIG. 2B is a circuit diagram in a case where an application example to the charge / discharge circuit is configured by only a unidirectional transistor.
  • FIG. 2C is a circuit diagram showing a second application example to the charge / discharge circuit of the semiconductor device according to the first embodiment.
  • FIG. 3A is a graph showing the on-resistance with respect to the thickness of the metal layer in the semiconductor device according to Comparative Example 1.
  • FIG. 3B is a graph showing the on-resistance and the amount of warpage with respect to the thickness of the metal layer / the thickness of the semiconductor layer in the semiconductor device according to Comparative Example 2.
  • FIG. 4A is a diagram illustrating a basic model for deriving warpage occurring in a multilayer body.
  • FIG. 4B is a schematic side view for explaining the amount of warpage ⁇ occurring in the multilayer body.
  • FIG. 5 is a graph showing the amount of warpage with respect to the thickness of the adhesive layer and the thickness of the support.
  • FIG. 6A is a graph showing the relationship among the thicknesses of the metal layer, the adhesive layer, and the support for setting the warping amount to 20 ⁇ m when the thickness of the semiconductor layer is fixed, calculated using the effective value calculation formula. It is.
  • FIG. 6B is a graph showing the relationship between the thicknesses of the semiconductor layer, the adhesive layer, and the support for setting the warping amount to 20 ⁇ m when the thickness of the metal layer is fixed, calculated using the effective value calculation formula. It is.
  • FIG. 7 is a graph defining the relationship between the thickness of the support and the thickness of the adhesive layer for setting the warpage amount to the target value and the allowable value in the semiconductor device according to the first embodiment.
  • FIG. 8A is a cross-sectional view of the semiconductor device according to Modification 1 of Embodiment 1.
  • 8B is a top view showing an example of the electrode configuration of the semiconductor device according to Modification 1 of Embodiment 1.
  • FIG. FIG. 9 is a cross-sectional view of the semiconductor device according to the second modification of the first embodiment.
  • FIG. 10A is a cross-sectional view showing a first step of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 10B is a cross-sectional view showing a second step of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 10C is a cross-sectional view showing a third step of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 11A is a cross-sectional view showing a fourth step of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 11B is a cross-sectional view showing a fifth step of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 12A is a cross-sectional view showing a sixth step of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 12B is a cross-sectional view showing a seventh step of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. FIG. 13 is a cross-sectional view showing an eighth step of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 14 is a cross-sectional view showing a ninth step of the method of manufacturing a semiconductor device according to the first embodiment.
  • the on-current flowing through the metal layer flows in a direction parallel to the main surface of the metal layer. Therefore, it is preferable to increase the thickness of the metal layer from the viewpoint of reducing the on-resistance.
  • the thermal expansion coefficient of the metal layer becomes dominant as the metal layer becomes thicker. Therefore, the thickness of the metal layer is 1 ⁇ 4 that of the semiconductor substrate. The following is preferred. In this case, the thickness of the metal layer for reducing the on-resistance is limited by the thickness of the semiconductor substrate. Depending on the thickness of the semiconductor substrate, the metal layer becomes thin and sufficient on-resistance cannot be obtained.
  • an insulating film is formed on the opposite side of the metal layer from the semiconductor substrate for the purpose of preventing scratches and scratches.
  • This insulating coating is composed of a coating-type organic material, an organic tape, or an inorganic oxide thin film from the viewpoint of preventing peeling from the metal layer and reducing the thickness of the semiconductor device. For this reason, the insulating coating has a function of suppressing the warpage of the semiconductor device caused by the metal layer, but when the metal layer is thickened for the purpose of reducing the on-resistance, the insulating coating is caused by the metal layer. It does not have sufficient stress to suppress warpage of the semiconductor device.
  • the present inventor has a metal layer having a thickness of 20 ⁇ m or more that can provide a practical low on-resistance when a semiconductor device having two vertical MOS transistors is applied as a charge / discharge circuit.
  • the semiconductor device the inventors have found a configuration of the semiconductor device in which the warpage amount of the semiconductor substrate and the metal layer is not more than a predetermined value.
  • the semiconductor device 1 according to the present disclosure is a CSP (Chip Size Package) type multi-transistor chip in which two vertical MOS (Metal Oxide Semiconductor) transistors are formed on a semiconductor substrate.
  • the two vertical MOS transistors are power transistors and are so-called trench MOS FETs (Field Effect Transistors).
  • the semiconductor device 1 according to the present embodiment is not applied to a device classified as optoelectronics such as a solid-state imaging device.
  • FIG. 1A is a cross-sectional view showing an example of the structure of the semiconductor device 1.
  • FIG. 1B is a top view showing an example of the electrode configuration of the semiconductor device 1 according to the first embodiment.
  • the cross-sectional view of FIG. 1A is a view of a cut surface taken along the line IA-IA of FIG. 1B.
  • the semiconductor device 1 includes a semiconductor substrate 32, a low-concentration impurity layer 33, a metal layer 31, an adhesive layer 39, a support 30, and a first vertical MOS transistor 10 (hereinafter referred to as “first vertical MOS transistor 10”). Transistor 10) and a second vertical MOS transistor 20 (hereinafter referred to as transistor 20).
  • the semiconductor device 1 when the semiconductor substrate 32 is viewed in plan, the semiconductor device 1 includes two first source electrodes 11, two second source electrodes 21, one first gate electrode 19, One second gate electrode 29 is provided.
  • a first source electrode 11, a first gate electrode 19, and a first source electrode 11 are formed in this order on the upper surface of the transistor 10 along a direction perpendicular to the direction in which the transistors 10 and 20 face each other.
  • a second source electrode 21, a second gate electrode 29, and a second source electrode 21 are provided on the upper surface of the transistor 20 along a direction perpendicular to the direction in which the transistors 10 and 20 face each other. It is formed in order.
  • the semiconductor substrate 32 contains a first conductivity type impurity and is made of silicon.
  • the semiconductor substrate 32 is, for example, an N-type silicon substrate.
  • the low-concentration impurity layer 33 is formed in contact with the upper surface of the semiconductor substrate 32 (upper main surface in FIG. 1A), and contains a first conductivity type impurity having a concentration lower than the concentration of the first conductivity type impurity of the semiconductor substrate 32. Including.
  • the low concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.
  • a stacked body of a semiconductor substrate 32 and a low concentration impurity layer 33 is defined as a semiconductor layer 40.
  • the metal layer 31 is formed in contact with the entire lower surface (lower main surface in FIG. 1A) of the semiconductor substrate 32, and is composed of only a metal material.
  • the metal layer 31 may be made of a metal material including any one or more of silver, copper, gold, and aluminum.
  • the support 30 is bonded to the entire lower surface of the two main surfaces of the metal layer 31 that is not in contact with the semiconductor substrate 32 via an adhesive layer 39, and is made of a ceramic material.
  • the ceramic material constituting the support 30 is particularly exemplified by silicon, but quartz, sapphire, borosilicate glass, soda-lime glass, etc. are also exemplified.
  • the adhesive layer 39 is disposed in contact with the metal layer 31 and the support 30 and is a layer for bonding the metal layer 31 and the support 30.
  • the adhesive layer 39 is formed by curing, for example, an adhesive made of an acrylic resin or an epoxy resin, or DAF (Die Attach Film).
  • the transistor 10 is formed in the first region (the left half region in FIG. 1A) in the low concentration impurity layer 33, and is in a different cross section from the first source electrode 11 formed on the upper surface of the low concentration impurity layer 33. It has the 1st gate electrode 19 (refer FIG. 1B).
  • a first body region 18 containing an impurity of a second conductivity type different from the first conductivity type is formed.
  • a first source region 14 including a first conductivity type impurity, a first gate conductor 15, and a first gate insulating film 16 are formed.
  • the first source electrode 11 includes a first portion 12 and a second portion 13, and the first portion 12 is connected to the first source region 14 and the first body region 18 via the second portion 13. It is connected to the.
  • the first gate electrode 19 is connected to the first gate conductor 15.
  • the first portion 12 of the first source electrode 11 is a layer that exhibits good bonding properties with a conductive bonding material such as solder at the time of mounting.
  • a conductive bonding material such as solder at the time of mounting.
  • any one of nickel, titanium, tungsten, and palladium is not limited. Or a metal material including one or more of them.
  • the surface of the first portion 12 may be plated with gold or the like.
  • the second portion 13 of the first source electrode 11 is a layer that connects the first portion 12 and the semiconductor layer 40, and as one non-limiting example, any one of aluminum, copper, gold, and silver is used. You may be comprised with the metal material containing the above.
  • the transistor 20 is formed in the second region adjacent to the upper surface of the semiconductor substrate 32 in the low concentration impurity layer 33 (the right half region in FIG. 1A) and formed on the upper surface of the low concentration impurity layer 33.
  • the second source electrode 21 and the second gate electrode 29 in another cross section are provided.
  • a second body region 28 containing an impurity of a second conductivity type different from the first conductivity type is formed.
  • a second source region 24 containing a first conductivity type impurity, a second gate conductor 25, and a second gate insulating film 26 are formed.
  • the second source electrode 21 includes a first portion 22 and a second portion 23, and the first portion 22 is connected to the second source region 24 and the second body region 28 via the second portion 23. It is connected to the.
  • the second gate electrode 29 is connected to the second gate conductor 25.
  • the first portion 22 of the second source electrode 21 is a layer that exhibits good bonding properties with a conductive bonding material such as solder at the time of mounting.
  • a conductive bonding material such as solder at the time of mounting.
  • any one of nickel, titanium, tungsten, and palladium is not limited. Or a metal material including one or more of them.
  • the surface of the first portion 22 may be plated with gold or the like.
  • the second portion 23 of the second source electrode 21 is a layer that connects the first portion 22 and the semiconductor layer 40.
  • any one of aluminum, copper, gold, and silver is used. You may be comprised with the metal material containing the above.
  • the first body region 18 and the second body region 28 are covered with an interlayer insulating layer 34 having an opening, and are connected to the first source region 14 and the second source region 24 through the opening of the interlayer insulating layer 34. Electrode second portions 13 and 23 are provided.
  • the interlayer insulating layer 34 and the second portions 13 and 23 of the source electrode are covered with a passivation layer 35 having an opening, and the first portions of the source electrode connected to the second portions 13 and 23 through the opening of the passivation layer 35, respectively.
  • Portions 12 and 22 are provided.
  • the first source electrode 11, the first gate electrode 19, the second source electrode 21, and the second gate electrode 29 are made of a conductive bonding material such as solder. Via, the electrode provided on the mounting substrate is bonded face down. In this case, as the warp of the semiconductor device 1 is larger, the first source electrode 11, the first gate electrode 19, the second source electrode 21, the second gate electrode 29, and the electrodes provided on the mounting substrate The electrical connection of becomes unstable. That is, in order to further stabilize the mounting of the semiconductor device 1 on the mounting substrate, it is necessary to reduce the warpage of the semiconductor device 1.
  • the semiconductor substrate 32 functions as a common drain region in which the first drain region of the transistor 10 and the second drain region of the transistor 20 are shared. Further, the semiconductor device 1 has a bidirectional path that flows between the first source electrode 11 and the second source electrode 21 via the first drain region, the metal layer 31, and the second drain region. The main current path.
  • FIG. 2A is a circuit diagram showing a first application example of the charge / discharge circuit of the semiconductor device 1. As shown in FIG. 2A, the semiconductor device 1 controls the discharge from the battery 3 to the load 4 and the charge from the load 4 to the battery 3 in accordance with a control signal given from the control IC 2.
  • FIG. 2B is a circuit diagram in a case where a similar application example is configured by only a unidirectional transistor 10.
  • the discharge current can be stopped by turning off the transistor 10, but the charging current can be stopped between the first body region 18 and the low-concentration impurity layer 33 even when the transistor 10 is turned off. Since the body diode formed in this manner flows in the forward direction (the direction from the first body region 18 to the low-concentration impurity layer 33), it cannot be stopped. Therefore, a bidirectional transistor is required to enable complete current interruption in both the discharging and charging directions.
  • FIG. 2C is a circuit diagram showing a second application example to the charge / discharge circuit of the semiconductor device 1.
  • the semiconductor device 1 cuts off the discharge current by turning off the transistor 10 and turns off the charging current by turning off the transistor 20 in accordance with a control signal given from the control IC 2. Cut off.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the first source region 14 the second source region 24, the semiconductor substrate 32, and the low conductivity type.
  • the concentration impurity layer 33 may be an N-type semiconductor
  • the first body region 18 and the second body region 28 may be P-type semiconductors.
  • the first conductivity type is P type
  • the second conductivity type is N type
  • the first source region 14, the second source region 24, the semiconductor substrate 32, and the low concentration impurity layer 33 are P type semiconductors
  • the first body region 18 and the second body region 28 may be N-type semiconductors.
  • the semiconductor device 1 shown in FIG. 1A will be described as a so-called N-channel transistor in which the first conductivity type is N-type and the second conductivity type is P-type.
  • a high voltage is applied to the first source electrode 11, a low voltage is applied to the second source electrode 21, and the first gate electrode 19 (first When a voltage higher than the threshold is applied to the gate conductor 15) and the second gate electrode 29 (second gate conductor 25), a channel is formed in the vicinity of the first gate insulating film 16 and the second gate insulating film 26.
  • the formed current flows through the path of the first source electrode 11 -the first body region 18 -the first drain region -the metal layer 31 -the second drain region -the second body region 28 -the second source electrode 21. Flows.
  • FIG. 2A is the on state of the semiconductor device 1 in which the transistors 10 and 20 are turned on and the on current flows.
  • the on-current between the transistors 10 and 20 flows through the metal layer 31. Therefore, by increasing the thickness of the metal layer 31, the cross-sectional area of the on-current path is enlarged, and the on-resistance of the semiconductor device 1 is reduced.
  • the PN junctions between the first body region 18 and the low concentration impurity layer 33 and between the second body region 28 and the low concentration impurity layer 33 constitute a body diode.
  • a body diode formed between the first body region 18 and the low-concentration impurity layer 33 is referred to as a first body diode, and is formed between the second body region 28 and the low-concentration impurity layer 33.
  • the body diode is referred to as a second body diode.
  • the voltage application conditions to the first source electrode 11 and the second source electrode 21 are opposite. If the voltage of the first gate electrode 19 (first gate conductor 15) is lower than the threshold with reference to one source electrode 11, a channel is not formed in the vicinity of the gate insulating film 16 of the transistor 10, and the semiconductor The device 1 enters an off state where no on-current flows.
  • FIG. 3A is a graph showing the on-resistance with respect to the thickness of the metal layer in the semiconductor device according to Comparative Example 1.
  • the semiconductor device according to Comparative Example 1 has a configuration in which the adhesive layer 39 and the support 30 are not formed with respect to the semiconductor device 1 illustrated in FIGS. 1A and 1B.
  • the semiconductor device according to Comparative Example 1 it is assumed that (1) the semiconductor layer 40 has a thickness of 43 ⁇ m and (2) the semiconductor layer 40 has a thickness of 78 ⁇ m.
  • the on-resistance of the semiconductor device when the thickness of the metal layer 31 was changed in the range of 10 to 40 ⁇ m was measured. For each sample, the on-resistance was measured by either the first method of measuring the sample mounted on the evaluation substrate or the second method of applying the probe to the bare chip sample. Differences in measured values caused by differences in measurement methods were corrected as appropriate.
  • Table 1 shows parameters of the semiconductor device according to Comparative Example 1.
  • the on-resistance decreases as the metal layer 31 is thickened.
  • the on-resistance is 2.2 to 2.4 m ⁇ or less as a 20 V withstand voltage specification due to restrictions on shortening the charging time and realizing rapid charging. Desired.
  • the thickness of the metal layer 31 that satisfies the on-resistance of 2.4 m ⁇ or less needs to be 20 ⁇ m or more.
  • FIG. 3B shows the ratio of the thickness of the metal layer 31 to the thickness of the semiconductor layer 40 in the semiconductor device according to Comparative Example 2 (hereinafter, sometimes referred to as metal layer 31 thickness / semiconductor layer 40 thickness). It is a graph which shows the relationship between on-resistance and curvature amount.
  • the semiconductor device according to Comparative Example 2 has a configuration in which the adhesive layer 39 and the support 30 are not formed with respect to the semiconductor device 1 illustrated in FIGS. 1A and 1B.
  • the on-resistance and the semiconductor substrate when the thickness of the metal layer 31 is changed in the range of 10 ⁇ m to 40 ⁇ m and the thickness of the semiconductor layer 40 is changed in the range of 28 to 93 ⁇ m The amount of warpage of the laminate of 32 and the metal layer 31 was measured. For the amount of warpage, place the bare chip sample under a heat load cycle with a maximum temperature of 250 ° C that simulates the reflow process, measure the shape of the bare chip by the moire method, and record the maximum value of the measured warpage amount. did.
  • Table 2 shows parameters of the semiconductor device according to Comparative Example 2.
  • the ON resistance decreases as the thickness of the metal layer 31 / the thickness of the semiconductor layer 40 increases.
  • the amount of warpage increases as the thickness of the metal layer 31 / the thickness of the semiconductor layer 40 increases.
  • the thickness of the metal layer 31 / the thickness of the semiconductor layer 40 satisfying an on-resistance of 2.4 m ⁇ or less is larger than 0.27.
  • the amount of warpage is 20 ⁇ m or more.
  • the amount of warpage increases, stable mounting becomes difficult and problems occur during face-down mounting on a mounting board. For example, (1) solder bonding between the electrode on the semiconductor device and the electrode on the mounting substrate is incomplete, (2) voids are generated in the solder, and (3) the solder protrudes from the electrode. Problems such as short-circuit between electrodes occur.
  • the thickness of the metal layer 31 is 20 ⁇ m or more and ( 2) It is necessary that the thickness of the metal layer 31 / the thickness of the semiconductor layer 40 is larger than 0.27.
  • the warpage amount is 20 ⁇ m or more.
  • the adhesive layer 39 is formed in contact with the entire main surface of the metal layer 31 opposite to the semiconductor substrate 32, A support 30 made of a ceramic material is formed in contact with the entire main surface of the adhesive layer 39 opposite to the metal layer 31.
  • the physical constants such as the thermal expansion coefficient and the Young's modulus, which are the main factors of stress generation of the support 30 made of the ceramic material, are closer to the physical constant of the semiconductor substrate 32 than the physical constant of the metal layer 31 made of the metal material. Has a value. That is, thermal expansion stress in a direction that cancels the thermal expansion stress generated by the bonding between the semiconductor substrate 32 and the metal layer 31 is generated by the bonding between the support 30 and the metal layer 31. Thereby, in the main surface which the metal layer 31 opposes, since the thermal expansion stress is balanced, the curvature of the laminated body of the metal layer 31 and the semiconductor layer 40 can be suppressed.
  • a conductive layer is formed in contact with the main surface of the metal layer opposite to the semiconductor substrate.
  • the physical constant of the conductive layer has a value closer to the physical constant of the metal layer than the physical constant of the semiconductor substrate. For this reason, in the semiconductor device according to Patent Document 1, no stress in a direction to cancel the stress generated by the bonding between the semiconductor substrate and the metal layer is generated by the bonding between the conductive layer and the metal layer.
  • a thin film material such as an insulating coating (a coating type organic material, an organic tape, or an inorganic oxide thin film) disclosed in Patent Document 2 is insufficient.
  • the semiconductor device 1 is configured such that the adhesive layer 39 is interposed between the metal layer 31 and the support 30.
  • the metal layer 31 is opposite to the semiconductor substrate 32 in order to suppress the thermal expansion stress applied to the metal layer 31 having a thickness of 20 ⁇ m or more and a ratio of the thickness to the semiconductor layer 40 being larger than 0.27.
  • the chip size package type semiconductor device 1 that achieves both reduction of on-resistance and suppression of warpage of the semiconductor device 1 by forming the adhesive layer 39 and the support 30 made of a ceramic material. It becomes.
  • the ceramic material of the support 30 is, for example, silicon. Therefore, even when compared with silicon nitride and silicon oxide, the machinability when the semiconductor device is separated into pieces by dicing is improved. Further, it is easier to obtain materials than silicon nitride and silicon oxide, and the cost is low.
  • the metal material of the metal layer 31 is, for example, silver (Ag). This makes it possible to effectively reduce the on-resistance as compared with copper (Cu) or the like that is generally used as a metal material.
  • the metal layer 31 may be thicker than the semiconductor layer 40. This can contribute to further reduction of on-resistance.
  • the support 30 may be thinner than the semiconductor layer 40.
  • the adhesive layer 39 between the metal layer 31 and the support 30 is interposed, the semiconductor substrate 32 is provided even when the support 30 is thinner than the semiconductor layer 40. In addition, it is possible to contribute to the reduction of the warpage amount of the metal layer 31.
  • the adhesive layer 39 may be a conductive adhesive, for example, conductive DAF.
  • conductive DAF conductive DAF
  • the material for the conductive adhesive include silver paste. This can contribute to further reduction of on-resistance.
  • the theoretical formula of the amount of warpage generated when a plurality of multilayers having different physical constants are bonded together is expressed as 4 of the semiconductor layer 40, the metal layer 31, the adhesive layer 39, and the support 30. This is applied to the semiconductor device 1 according to the present embodiment, which is composed of layers (step S10).
  • the theoretical formula is set so that the warpage amount ⁇ of the semiconductor device 1 according to the present embodiment derived based on the theoretical formula matches the calculated value in the warpage calculation simulator constructed using the finite element method. Fitting is performed (step S20).
  • the adhesion when the warpage amount ⁇ e of the semiconductor device 1 according to the present embodiment is 20 ⁇ m or less and 40 ⁇ m or less.
  • the thicknesses of the layer 39 and the support 30 are derived (step S30).
  • step S10 will be described.
  • FIG. 4A is a diagram illustrating a basic model for deriving the amount of warpage occurring in the multilayer body.
  • a first layer having (thermal expansion coefficient ⁇ 1 , Young's modulus E 1 ) and thickness t 1
  • a third layer having two layers, (thermal expansion coefficient ⁇ 3 , Young's modulus E 3 ) and thickness t 3
  • a fourth layer having (thermal expansion coefficient ⁇ 4 , Young's modulus E 4 ) and thickness t 4 Are joined in this order toward the negative y-axis direction. It is assumed that the length L and width (depth) b of each layer viewed from the y-axis direction are the same for all four layers.
  • FIG. 4B is a schematic side view for explaining the amount of warpage ⁇ occurring in the multilayer body. As shown in the figure, the amount by which the end of the multilayer body in the positive x-axis direction shifts from the horizontal position in the negative y-axis direction due to the stress generated in the multilayer body is defined as a warpage amount ⁇ .
  • Table 3 shows an example of the warpage amount ⁇ obtained using the above formulas 1 and 2.
  • Table 4 shows other parameters used when the warpage amount ⁇ of Table 3 was obtained.
  • the width b is set to 1 mm. This is because the width b appears in both the denominator and the numerator and is offset in calculating the warpage amount ⁇ . It is.
  • step S20 the above equations 1 and 2 are fitted so that the warpage amount ⁇ derived based on the above equations 1 and 2 matches the calculated value ⁇ s in the warpage calculation simulator.
  • the warpage calculation simulator used for the fitting is a customized structure analysis software (manufactured by ANSYS) using finite element method analysis using a necessary amount of warpage measurement data.
  • step S30 will be described.
  • the warpage amount of the semiconductor device 1 according to the present embodiment is (1) 20 ⁇ m or less, and (2 ) The thicknesses of the adhesive layer 39 and the support 30 when the thickness is 40 ⁇ m or less are derived.
  • FIG. 5 is a graph showing a change in the warpage amount ⁇ e with respect to the thickness of the adhesive layer 39 and the thickness of the support 30 calculated using the effective value calculation formula.
  • the relationship between the thickness of 30 and the warpage amount ⁇ e is shown.
  • the other parameters have the values shown in Table 4.
  • the warpage amount ⁇ e takes a negative value
  • the minimum point of the warpage amount ⁇ e in the reverse warp is about 10 ⁇ m and does not exceed 20 ⁇ m. Therefore, when the conditions for the thickness of the adhesive layer 39 and the support 30 are determined, the condition for making the forward warpage 20 ⁇ m or less may be set.
  • the semiconductor device 1 In determining the thickness of the adhesive layer 39 and the support 30 as described above, the semiconductor device 1 according to the present embodiment has four layers having different physical constants and different thicknesses. Many. Therefore, the thickness of the adhesive layer 39 and the support 30 is calculated according to the following policy.
  • the main parameters are the thicknesses of the four layers and the warpage amount ⁇ e.
  • the standard value of the warpage amount ⁇ e is set to a first standard value of 20 ⁇ m and a second standard value of 40 ⁇ m.
  • the feature of the semiconductor device 1 according to the present embodiment is that the adhesive layer 39 and the support 30 are arranged in order to suppress the warp that occurs in the semiconductor layer 40 and the metal layer 31, and thus the warp amount.
  • the thickness of the support 30 that satisfies the standard value of ⁇ e is defined in a format that depends on the thickness of the adhesive layer 39. That is, a function that can determine the thickness of the support 30 is derived according to the thickness of the adhesive layer 39 to be used.
  • FIG. 6A shows a case where the thickness of the semiconductor layer 40 calculated using the effective value calculation formula is fixed ((a) is the thickness of the semiconductor layer 40 10 ⁇ m, (b) is the thickness of the semiconductor layer 40 80 ⁇ m). 4 is a graph showing the relationship among the thicknesses of the metal layer 31, the adhesive layer 39, and the support 30 for setting the warpage amount ⁇ e to 20 ⁇ m.
  • FIG. 6B shows the case where the thickness of the metal layer 31 calculated using the effective value calculation formula is fixed ((a) is the thickness of the metal layer 31 and (b) is the thickness of the metal layer 31 is 70 ⁇ m. Is a graph showing the relationship among the thicknesses of the semiconductor layer 40, the adhesive layer 39, and the support 30 for setting the warpage amount ⁇ e to 20 ⁇ m.
  • the graphs as shown in (a) and (b) of FIG. 6A are obtained even when the thickness of the semiconductor layer 40 is 20 ⁇ m, 40 ⁇ m, and 60 ⁇ m, and also as shown in (a) and (b) of FIG. 6B. Is obtained using the effective value calculation formula even when the thickness of the metal layer 31 is 40 ⁇ m, 50 ⁇ m, and 60 ⁇ m. From the graph obtained in this way, the thickness of the support 30 is extracted for each thickness of the adhesive layer 39 that sets the warpage amount ⁇ e to 20 ⁇ m. At this time, the thickness of the support 30 for each thickness of the adhesive layer 39 that changes the thickness of the semiconductor layer 40 and the thickness of the metal layer 31 to change the warpage amount ⁇ e to 20 ⁇ m changes.
  • the maximum value of the thickness of the support 30 for each thickness of the adhesive layer 39 is extracted.
  • the same extraction process is also applied to the thickness of the support 30 for each thickness of the adhesive layer 39 in which the warpage amount ⁇ e is 40 ⁇ m.
  • Table 5 shows combinations of thicknesses of the support 30 for each thickness of the adhesive layer 39 obtained by this extraction process.
  • Table 6 shows other parameters used when the warpage amount ⁇ e in Table 5 was obtained.
  • FIG. 7 is a graph that defines the relationship of the thickness of the support 30 with respect to the thickness of the adhesive layer 39 for making the warpage amounts 20 ⁇ m and 40 ⁇ m in the semiconductor device 1 according to the first embodiment.
  • the extracted data shown in Table 5 are plotted. From the graph shown in the figure, (1) an approximate expression representing the relationship of the thickness of the support 30 to the thickness of the adhesive layer 39 for setting the warpage amount ⁇ e to 20 ⁇ m (target value), and (2) the warpage amount ⁇ e.
  • Approximate expression expressing the relationship of the thickness of the support 30 to the thickness of the adhesive layer 39 to 20 ⁇ m (allowable value), (3) Support to the thickness of the adhesive layer 39 to set the warping amount ⁇ e to 40 ⁇ m (target value)
  • An approximate expression representing the relationship between the thicknesses of 30
  • (4) an approximate expression representing the relationship between the thickness of the support 30 and the thickness of the adhesive layer 39 for setting the warpage amount ⁇ e to 40 ⁇ m (allowable value). From these approximate expressions, the relationship of the thickness of the support 30 to the thickness of the adhesive layer 39 that suppresses the warpage amount of the semiconductor device 1 is expressed by Expressions 4 to 7.
  • the thickness of the adhesive layer 39 is t 3 ( ⁇ m) and the thickness of the support 30 is t 4 ( ⁇ m)
  • the thickness of 30 is expressed by Equation 4 below.
  • the length L of each layer is 3.4 mm or less.
  • the thermal expansion coefficient ⁇ 3 of the adhesive layer 39 is 1.1 (ppm / ° C.) or less and the Young's modulus E 3 of the adhesive layer 39 is 50 (GPa) or less, the warpage amount of the semiconductor device 1 is 20 ⁇ m. It is possible to:
  • the length L of each layer is 4.0 mm or less.
  • the thermal expansion coefficient ⁇ 3 of the adhesive layer 39 is 5.0 (ppm / ° C.) or less and the Young's modulus E 3 of the adhesive layer 39 is 100 (GPa) or less, the warpage amount of the semiconductor device 1 is 20 ⁇ m. It is possible to:
  • the length L of each layer is 3.4 mm or less
  • the thermal expansion coefficient ⁇ 3 of the adhesive layer 39 is 1.1 (ppm / ° C.) or less and the Young's modulus E 3 of the adhesive layer 39 is 50 (GPa) or less
  • the warpage amount of the semiconductor device 1 is 40 ⁇ m. It is possible to:
  • the length L of each layer is 4.0 mm or less.
  • the thermal expansion coefficient ⁇ 3 of the adhesive layer 39 is 5.0 (ppm / ° C.) or less and the Young's modulus E 3 of the adhesive layer 39 is 100 (GPa) or less, the warpage amount of the semiconductor device 1 is 40 ⁇ m. It is possible to:
  • FIG. 8A is a cross-sectional view of a semiconductor device 1A according to Modification 1 of Embodiment 1.
  • FIG. 8B is a top view showing an example of the electrode configuration of the semiconductor device 1A according to the first modification of the first embodiment.
  • the cross-sectional view of FIG. 8A is a view of a cut surface taken along the line VIIIA-VIIIA of FIG. 8B.
  • the semiconductor device 1 ⁇ / b> A includes a semiconductor substrate 32, a low concentration impurity layer 33, a metal layer 31, an adhesive layer 39, a support 30, a transistor 10, and a transistor 20. As shown in FIG.
  • the semiconductor device 1A when the semiconductor substrate 1A is viewed in plan, the semiconductor device 1A includes two first source electrodes 11, two second source electrodes 21, one first gate electrode 19, and One second gate electrode 29 is provided.
  • a first source electrode 11, a first gate electrode 19, and a first source electrode 11 are formed in this order on the upper surface of the transistor 10 along a direction perpendicular to the direction in which the transistors 10 and 20 face each other.
  • a second source electrode 21, a first gate electrode 29, and a first source electrode 21 are provided on the upper surface of the transistor 20 along a direction perpendicular to the direction in which the transistors 10 and 20 face each other. It is formed in order. Note that the number and arrangement of source electrodes and gate electrodes included in one transistor are not limited to those illustrated in FIG. 8B.
  • the semiconductor device 1A according to the present modification differs from the semiconductor device 1 according to the first embodiment only in that the notch 61 is formed at the boundary between the transistors 10 and 20.
  • the description of the same configuration as that of the semiconductor device 1 according to the first embodiment will be omitted, and a description will be given focusing on different configurations.
  • the boundary between the first region of the transistor 10 and the second region of the transistor 20 is from the upper surface side of the semiconductor device 1A.
  • a cut portion 61 is formed toward the lower surface side. Further, the cut portion 61 is formed up to the low concentration impurity layer 33. Note that the lowermost end of the cut portion 61 of the semiconductor device 1 ⁇ / b> A according to this modification is located on the upper surface side of the semiconductor device 1 ⁇ / b> A with respect to the lower surface of the semiconductor substrate 32.
  • FIG. 9 is a cross-sectional view of the semiconductor device 1B according to the second modification of the first embodiment. Note that a top view showing an example of the electrode configuration of the semiconductor device 1B according to the second modification of the first embodiment is omitted because it is the same as the top view of the semiconductor device 1A shown in FIG. 8B.
  • the semiconductor device 1 ⁇ / b> B includes a semiconductor substrate 32, a low concentration impurity layer 33, a metal layer 31, an adhesive layer 39, a support 30, a transistor 10, and a transistor 20.
  • the semiconductor substrate 32 is viewed in plan, the semiconductor device 1B includes two first source electrodes 11, two second source electrodes 21, one first gate electrode 19, and one second gate electrode. 29.
  • a first source electrode 11, a first gate electrode 19, and a first source electrode 11 are formed in this order on the upper surface of the transistor 10 along a direction perpendicular to the direction in which the transistors 10 and 20 face each other. Has been.
  • a second source electrode 21, a first gate electrode 29, and a first source electrode 21 are provided on the upper surface of the transistor 20 along a direction perpendicular to the direction in which the transistors 10 and 20 face each other. It is formed in order. Note that the number and arrangement of source electrodes and gate electrodes included in one transistor are not limited to those illustrated in FIG. 8B.
  • the semiconductor device 1B according to the present modification differs from the semiconductor device 1 according to the first embodiment only in that the notch 62 is formed at the boundary between the transistors 10 and 20.
  • the description of the same configuration as that of the semiconductor device 1 according to the first embodiment will be omitted, and a description will be given focusing on different configurations.
  • FIG. 10A is a cross-sectional view showing a first step of the method of manufacturing semiconductor device 1 according to the first embodiment.
  • FIG. 10B is a cross-sectional view showing a second step of the method of manufacturing semiconductor device 1 according to the first embodiment.
  • FIG. 10C is a cross-sectional view showing a third step of the method of manufacturing a semiconductor device according to the first embodiment.
  • a low-concentration impurity layer 33 is formed on one main surface of a semiconductor substrate 32A, and an element region is formed in the surface region of the low-concentration impurity layer 33.
  • electrodes first source electrode, second source electrode mainly made of a metal such as Al or Cu are formed at predetermined positions on the element region.
  • a temporary adhesive 37 is applied to one main surface side of the semiconductor substrate 32A. At this time, it is desirable to make the temporary adhesive 37 thicker than the unevenness of the electrode and the element region. Further, the glass substrate 36 is placed on the temporary adhesive 37 and pressed to adhere. At this time, in order to prevent bubbles from entering between the glass substrate 36 and the temporary adhesive 37, it is desirable to bond in a vacuum chamber.
  • the thickness of the semiconductor substrate 32 ⁇ / b> A is set to a desired thickness (on the back side opposite to one main surface of the semiconductor substrate 32 ⁇ / b> A so that the required electrical characteristics (on-resistance) can be realized.
  • the semiconductor substrate 32 having a desired thickness is formed by back grinding to preferably 50 ⁇ m or less. Further, it is desirable to perform a mirror surface treatment such as CMP.
  • FIG. 11A is a cross-sectional view showing a fourth step of the method of manufacturing semiconductor device 1 according to the first embodiment.
  • FIG. 11B is a cross-sectional view showing a fifth step of the method of manufacturing semiconductor device 1 according to the first embodiment.
  • a metal layer 31 is formed on the back surface opposite to the one main surface of the semiconductor substrate 32.
  • the first metal layer 31 ⁇ / b> A is formed on the entire back surface of the semiconductor substrate 32 by vapor deposition so as to make ohmic contact with the semiconductor substrate 32.
  • the first metal layer 31 ⁇ / b> A for example, Ti and Ni are sequentially stacked from the side close to the back surface of the semiconductor substrate 32.
  • the second metal layer 31B is formed on the first metal layer 31A. Specifically, it is formed using an electrolytic plating method. Here, it is preferable to use mainly Ag, Au, Cu or the like as the second metal layer 31B. In the following description, the first metal layer 31A and the second metal layer 31B are collectively referred to as the metal layer 31.
  • an adhesive is applied on the metal layer 31 to form an adhesive layer 39.
  • thermosetting resin such as an epoxy resin or a phenol resin
  • the support 30 is made of an epoxy acrylate or acrylic acid as an adhesive when using a material transparent to ultraviolet rays, such as quartz, sapphire, borosilicate glass, and soda lime glass.
  • An ultraviolet curable resin such as acrylate or urethane acrylate can also be used.
  • the process for curing the adhesive will be described.
  • the bonded wafers are heated in a thermostat at about 150 ° C. for 1 to 2 hours, for example.
  • the adhesive is cured by heating, and the support 30 and the metal layer 31 are strongly bonded.
  • the surface of the wafer 30 that has been bonded using an ultraviolet generator such as a high-pressure mercury lamp is irradiated with ultraviolet rays.
  • the amount of light to be irradiated is, for example, 300 to 2000 mJ / cm 2 .
  • FIG. 12A is a cross-sectional view showing a sixth step of the method of manufacturing semiconductor device 1 according to the first embodiment.
  • FIG. 12B is a cross-sectional view showing a seventh step of the method of manufacturing semiconductor device 1 according to the first embodiment.
  • the dicing tape 38 is attached to the surface of the support 30 and the ring frame 50, and the ring frame 50 is mounted.
  • the temporary adhesive 37 and the glass substrate 36 are removed. Specifically, as shown in FIG. 12A, the portion of the temporary adhesive 37 in contact with the glass substrate 36 is modified by irradiating a laser beam 70 near the boundary surface between the temporary adhesive 37 and the glass substrate 36. The glass substrate 36 is removed from the wafer made of the semiconductor substrate 32. Thereafter, as shown in FIG. 12B, the temporary adhesive 37 is peeled and removed.
  • FIG. 13 is a cross-sectional view showing an eighth step of the method of manufacturing semiconductor device 1 according to the first embodiment.
  • the semiconductor substrate 32, the low-concentration impurity layer 33, the metal layer 31, the adhesive layer 39, and the support 30 are diced by using a dicing blade 80 such as a dicing saw, for example.
  • a dicing blade 80 such as a dicing saw
  • the metal layer 31 is sandwiched between the semiconductor substrate 32 and the support 30 in the manufacturing process of the semiconductor device 1 according to the present embodiment, the ductility like the metal layer 31 is formed on the outermost surface. Since there is no material, there is an effect that burrs are hardly generated on the cutting end face.
  • FIG. 14 is a cross-sectional view showing a ninth step of the method of manufacturing a semiconductor device according to the first embodiment.
  • notches 64 are made using a dicing blade 81 between a plurality of transistors.
  • the process of FIG. 14 may be performed after the manufacturing process shown in FIGS. 10A to 10C, FIGS. 11A to 11B, and FIGS. 12A to 12B.
  • individual processes are performed by the dicing process shown in FIG.
  • the semiconductor device 1 is separated.
  • a notch 64 is formed by a dicing blade 81 between a plurality of transistors formed in the semiconductor device 1.
  • the semiconductor device has been described based on the embodiment, but the present disclosure is not limited to the embodiment. Unless it deviates from the gist of the present disclosure, various modifications conceived by those skilled in the art have been made in the present embodiment, and forms constructed by combining components in different embodiments are also applicable to one or more of the present disclosure. It may be included within the scope of the embodiments.
  • the semiconductor device according to the present invention can be widely used as a CSP type semiconductor device in various semiconductor devices such as a bidirectional transistor, a unidirectional transistor, and a diode.

Abstract

半導体装置（１）は、シリコンからなるＮ型の半導体基板（３２）と、半導体基板（３２）の上面に接するＮ型の低濃度不純物層（３３）と、半導体基板（３２）の下面全面に接する２０μｍ以上の厚さの金属層（３１）と、低濃度不純物層内に形成されたトランジスタ（１０および２０）とを備え、半導体基板（３２）は、トランジスタ（１０および２０）のドレイン領域として機能し、トランジスタ（１０および２０）のソース電極の間を、トランジスタ（１０）側の半導体基板（３２）、金属層（３１）、トランジスタ（２０）側の半導体基板（３２）を経由して流れる双方向経路を主電流経路とし、半導体基板（３２）と低濃度不純物層（３３）とを含む半導体層に対する金属層（３１）の厚さの割合は０．２７より大きく、半導体装置（１）は、さらに、金属層（３１）の下面全面に、接着層（３９）のみを介して接着されたセラミック材料からなる支持体（３０）を有する。

Description

半導体装置
　本開示は、半導体装置に関し、特に、フェイスダウン実装が可能なチップサイズパッケージ型の半導体装置に関する。
　従来、第１主面および第２主面を有する半導体基板と、当該第１主面から当該第２主面に渡って設けられた２つの縦型ＭＯＳ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）トランジスタと、当該第２主面上に形成された金属層とを備える半導体装置が提案されている。この構成では、第１のトランジスタから第２のトランジスタへ流れる電流経路として、半導体基板内部を水平方向経路だけでなく、導通抵抗が低い金属層中の水平方向経路も用いることができるので、半導体装置のオン抵抗の低減が可能である。
　特許文献１では、上記構成に加え、金属層の半導体基板とは反対側に導電層が形成された半導体装置が提案されている。この導電層により、チップを個片化する工程において、金属層のバリの発生を抑制できるとしている。
　また、特許文献２では、上記構成に加え、金属層の半導体基板とは反対側に絶縁被膜が形成された半導体装置が提案されている。この絶縁被膜により、半導体装置の薄型化を維持しつつ、キズやかけなどの破損を防止できるとしている。
特開２０１６－８６００６号公報 特開２０１２－１８２２３８号公報
　しかしながら、特許文献１および特許文献２に開示された半導体装置では、半導体基板の熱膨張係数よりも金属層の熱膨張係数の方が大きいため、温度変化による半導体装置の反りが発生する。
　特許文献１では、金属層の半導体基板とは反対側に導電層が形成されているが、導電層の主材料が金属層と同種の金属であるため、温度変化による半導体装置の反りを軽減するのに十分な厚さの導電層形成は製造する上では容易でない。
　特許文献２では、金属層の半導体基板とは反対側には、半導体装置の薄型化および破損の防止を実現するための絶縁被膜が形成されているが、金属層の厚さが低オン抵抗を確保するために必要な厚さの場合は、半導体装置の反りを軽減する十分な応力は絶縁被膜に発生しない。
　つまり、特許文献１および２に開示された半導体装置では、オン抵抗の低減と半導体装置の反りの抑制とを両立できない。
　そこで、本開示は、オン抵抗の低減と反りの抑制とを両立させたチップサイズパッケージ型の半導体装置を提供することを目的とする。
　上記課題を解決するため、本開示に係る半導体装置の一態様は、フェイスダウン実装が可能なチップサイズパッケージ型の半導体装置であって、第１導電型の不純物を含み、シリコンからなる半導体基板と、前記半導体基板の上面に接して形成され、前記半導体基板の前記第１導電型の不純物の濃度より低い濃度の前記第１導電型の不純物を含む低濃度不純物層と、前記半導体基板の下面全面に接して形成され、厚さが２０μｍ以上の金属材料のみで構成された金属層と、前記低濃度不純物層内の第１の領域に形成された第１の縦型ＭＯＳトランジスタと、前記第１の領域と前記半導体基板の上面に沿った方向で隣接する、前記低濃度不純物層内の第２の領域に形成された第２の縦型ＭＯＳトランジスタと、を備え、前記第１の縦型ＭＯＳトランジスタは、前記低濃度不純物層の上面に形成された第１のソース電極および第１のゲート電極を有し、前記第２の縦型ＭＯＳトランジスタは、前記低濃度不純物層の上面に形成された第２のソース電極および第２のゲート電極を有し、前記半導体基板は、前記第１の縦型ＭＯＳトランジスタの第１のドレイン領域および前記第２の縦型ＭＯＳトランジスタの第２のドレイン領域を共通化したドレイン領域として機能し、前記第１のソース電極と前記第２のソース電極との間を、前記第１のドレイン領域、前記金属層、および前記第２のドレイン領域を経由して流れる双方向経路を主電流経路とし、前記半導体基板と前記低濃度不純物層とを含む半導体層に対する前記金属層の厚さの割合は０．２７より大きく、前記半導体装置は、さらに、前記金属層の下面全面に、接着層のみを介して接着された、セラミック材料からなる支持体を有する。
　この構成によれば、低オン抵抗を確保するための厚さを有する金属層の上面に形成された半導体基板の熱膨張係数と金属層の下面に形成された接着層および支持体の熱膨張係数とのバランスが取れるために、オン抵抗を低減しつつ半導体装置の反りを抑制できる。
　本開示に係る半導体装置によれば、オン抵抗の低減と半導体装置の反りの抑制とを両立させたフェイスダウン実装が可能なチップサイズパッケージ型の半導体装置を提供することが可能となる。
図１Ａは、実施の形態１に係る半導体装置の断面図である。 図１Ｂは、実施の形態１に係る半導体装置の電極構成の一例を示す上面図である。 図２Ａは、実施の形態１に係る半導体装置の充放電回路への第１の応用例を示す回路図である。 図２Ｂは、充放電回路への応用例を、単方向のトランジスタのみで構成した場合の回路図である。 図２Ｃは、実施の形態１に係る半導体装置の充放電回路への第２の応用例を示す回路図である。 図３Ａは、比較例１に係る半導体装置における、金属層の厚さに対するオン抵抗を示すグラフである。 図３Ｂは、比較例２に係る半導体装置における、金属層の厚さ／半導体層の厚さに対するオン抵抗および反り量を表すグラフである。 図４Ａは、多層体に発生する反りを導出するための基本モデルを表す図である。 図４Ｂは、多層体に発生する反り量δを説明する側面概略図である。 図５は、接着層の厚さおよび支持体の厚さに対する反り量を表すグラフである。 図６Ａは、実効値算出式を用いて算出した、半導体層の厚さを固定した場合の、反り量を２０μｍにするための、金属層、接着層および支持体の厚さの関係を表すグラフである。 図６Ｂは、実効値算出式を用いて算出した、金属層の厚さを固定した場合の、反り量を２０μｍにするための、半導体層、接着層および支持体の厚さの関係を表すグラフである。 図７は、実施の形態１に係る半導体装置において、反り量を目標値および許容値にするための接着層の厚さに対する支持体の厚さの関係を規定したグラフである。 図８Ａは、実施の形態１の変形例１に係る半導体装置の断面図である。 図８Ｂは、実施の形態１の変形例１に係る半導体装置の電極構成の一例を示す上面図である。 図９は、実施の形態１の変形例２に係る半導体装置の断面図である。 図１０Ａは、実施の形態１に係る半導体装置の製造方法の第１工程を示す断面図である。 図１０Ｂは、実施の形態１に係る半導体装置の製造方法の第２工程を示す断面図である。 図１０Ｃは、実施の形態１に係る半導体装置の製造方法の第３工程を示す断面図である。 図１１Ａは、実施の形態１に係る半導体装置の製造方法の第４工程を示す断面図である。 図１１Ｂは、実施の形態１に係る半導体装置の製造方法の第５工程を示す断面図である。 図１２Ａは、実施の形態１に係る半導体装置の製造方法の第６工程を示す断面図である。 図１２Ｂは、実施の形態１に係る半導体装置の製造方法の第７工程を示す断面図である。 図１３は、実施の形態１に係る半導体装置の製造方法の第８工程を示す断面図である。 図１４は、実施の形態１に係る半導体装置の製造方法の第９工程を示す断面図である。
　（本開示の基礎となった知見）
　特許文献２に開示された、２つの縦型ＭＯＳトランジスタを有する半導体装置におけるオン抵抗の低減および反りの抑制について検討する。
　特許文献２に開示された半導体装置では、金属層を流れるオン電流は金属層の主面に平行な方向に流れる。よって、オン抵抗を低減するという観点では、金属層を厚くするほうが好ましい。ただし、特許文献２によれば、半導体装置の反りを低減するという観点では、金属層が厚くなるほど金属層の熱膨張率が支配的となるため、金属層の厚さは半導体基板の１／４以下とすることが好ましいとされている。この場合、オン抵抗を低減するための金属層の厚さが、半導体基板の厚さで制限されてしまい、半導体基板の厚さによっては、金属層が薄くなり十分なオン抵抗が得られない。
　また、金属層の半導体基板と反対側には、キズやかけの防止を目的とした絶縁被膜が形成されている。この絶縁被膜は、金属層からの剥離防止、および、半導体装置の薄型化という観点から、塗布型の有機材料、有機系のテープ、または無機系酸化物薄膜で構成される。このため、絶縁被膜は、金属層に起因した半導体装置の反りを抑制する機能を副次的には有するものの、オン抵抗の低減を目的として金属層を厚くした場合には、金属層に起因した半導体装置の反りを抑制するための十分な応力を有さない。
　そこで、本発明者は、鋭意検討の結果、２つの縦型ＭＯＳトランジスタを有する半導体装置を充放電回路として適用した場合に実用的な低オン抵抗が得られる、厚さ２０μｍ以上の金属層を有する半導体装置について、半導体基板および金属層の反り量を所定値以下とする半導体装置の構成を見出すに至った。
　以下で説明する実施の形態は、いずれも本開示の一具体例を示すものである。以下の実施の形態で示される数値、形状、材料、構成要素、構成要素の配置位置および接続形態などは、一例であり、本開示を限定する主旨ではない。また、以下の実施の形態における構成要素のうち、最上位概念を示す独立請求項に記載されていない構成要素については、任意の構成要素として説明される。
　（実施の形態１）
　[１．半導体装置の基本構造]
　以下、本開示に係る半導体装置１の構造について説明する。本開示に係る半導体装置１は、半導体基板に２つの縦型ＭＯＳ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）トランジスタを形成した、ＣＳＰ（Ｃｈｉｐ　Ｓｉｚｅ　Ｐａｃｋａｇｅ：チップサイズパッケージ）型のマルチトランジスタチップである。上記２つの縦型ＭＯＳトランジスタは、パワートランジスタであり、いわゆる、トレンチＭＯＳ型ＦＥＴ（Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）である。ただし、本実施の形態に係る半導体装置１は、固体撮像装置等のオプトエレクトロニクスに分類されるものには適用されない。
　図１Ａは、半導体装置１の構造の一例を示す断面図である。また、図１Ｂは、実施の形態１に係る半導体装置１の電極構成の一例を示す上面図である。図１Ａの断面図は、図１ＢのＩＡ－ＩＡにおける切断面を見た図である。図１Ａに示すように、半導体装置１は、半導体基板３２と、低濃度不純物層３３と、金属層３１と、接着層３９と、支持体３０と、第１の縦型ＭＯＳトランジスタ１０（以下、トランジスタ１０）と、第２の縦型ＭＯＳトランジスタ２０（以下、トランジスタ２０）と、を有する。また、図１Ｂに示すように、半導体装置１は、半導体基板３２を平面視した場合、２つの第１のソース電極１１、２つの第２のソース電極２１、１つの第１のゲート電極１９、および、１つの第２のゲート電極２９を有している。トランジスタ１０の上面には、トランジスタ１０とトランジスタ２０とが対向する方向と垂直な方向に沿って、第１のソース電極１１、第１のゲート電極１９、および第１のソース電極１１がこの順に形成されている。また、トランジスタ２０の上面には、トランジスタ１０とトランジスタ２０とが対向する方向と垂直な方向に沿って、第２のソース電極２１、第２のゲート電極２９、および第２のソース電極２１がこの順に形成されている。
　なお、１つのトランジスタを構成するソース電極およびゲート電極の個数および配置関係は、図１Ｂに示されたものに限定されない。
　半導体基板３２は、第１導電型の不純物を含み、シリコンからなる。半導体基板３２は、例えば、Ｎ型のシリコン基板である。
　低濃度不純物層３３は、半導体基板３２の上面（図１Ａでの上側主面）に接して形成され、半導体基板３２の第１導電型の不純物の濃度より低い濃度の第１導電型の不純物を含む。低濃度不純物層３３は、例えば、エピタキシャル成長により半導体基板３２上に形成されてもよい。
　図１Ａに示すように、半導体基板３２および低濃度不純物層３３の積層体を半導体層４０と定義する。
　金属層３１は、半導体基板３２の下面（図１Ａでの下側主面）全面に接して形成され、金属材料のみで構成されている。金属層３１は、限定されない一例として、銀、銅、金、アルミニウムのうちのいずれか１つ以上を含む金属材料で構成されてもよい。
　支持体３０は、金属層３１の２つの主面のうち半導体基板３２と接していない下面全面に、接着層３９を介して接着され、セラミック材料からなる。支持体３０を構成するセラミック材料としては、特に、シリコンが例示されるが、その他、石英、サファイヤ、ほうけい酸ガラス、ソーダ石灰ガラスなどが例示される。
　接着層３９は、金属層３１および支持体３０に接して配置され、金属層３１と支持体３０とを接着するための層である。接着層３９は、例えば、アクリル樹脂もしくはエポキシ樹脂からなる接着剤、またはＤＡＦ（Ｄｉｅ　Ａｔｔａｃｈ　Ｆｉｌｍ：ダイボンド用フィルム接着剤）、などが硬化することで形成される。
　トランジスタ１０は、低濃度不純物層３３内の第１の領域（図１Ａでの左側半分領域）に形成され、低濃度不純物層３３の上面に形成された第１のソース電極１１および別断面にある第１のゲート電極１９（図１Ｂ参照）を有する。
　低濃度不純物層３３の第１の領域には、第１導電型と異なる第２導電型の不純物を含む第１のボディ領域１８が形成されている。第１のボディ領域１８には、第１導電型の不純物を含む第１のソース領域１４、第１のゲート導体１５、および第１のゲート絶縁膜１６が形成されている。第１のソース電極１１は第１の部分１２と第２の部分１３とからなり、第１の部分１２は、第２の部分１３を介して第１のソース領域１４および第１のボディ領域１８に接続されている。第１のゲート電極１９は、第１のゲート導体１５に接続される。
　第１のソース電極１１の第１の部分１２は、実装時にはんだなどの導電性接合材と良好な接合性を示す層であり、限定されない一例として、ニッケル、チタン、タングステン、パラジウムのうちのいずれか１つ以上を含む金属材料で構成されてもよい。第１の部分１２の表面には、金などのめっきが施されてもよい。
　第１のソース電極１１の第２の部分１３は、第１の部分１２と半導体層４０とを接続する層であり、限定されない一例として、アルミニウム、銅、金、銀のうちのいずれか１つ以上を含む金属材料で構成されてもよい。
　トランジスタ２０は、低濃度不純物層３３内の半導体基板３２の上面に沿った方向で隣接する第２の領域（図１Ａでの右側半分領域）に形成され、低濃度不純物層３３の上面に形成された第２のソース電極２１および別断面にある第２のゲート電極２９を有する。
　低濃度不純物層３３の第２の領域には、第１導電型と異なる第２導電型の不純物を含む第２のボディ領域２８が形成されている。第２のボディ領域２８には、第１導電型の不純物を含む第２のソース領域２４、第２のゲート導体２５、および第２のゲート絶縁膜２６が形成されている。第２のソース電極２１は第１の部分２２と第２の部分２３とからなり、第１の部分２２は、第２の部分２３を介して第２のソース領域２４および第２のボディ領域２８に接続されている。第２のゲート電極２９は、第２のゲート導体２５に接続される。
　第２のソース電極２１の第１の部分２２は、実装時にはんだなどの導電性接合材と良好な接合性を示す層であり、限定されない一例として、ニッケル、チタン、タングステン、パラジウムのうちのいずれか１つ以上を含む金属材料で構成されてもよい。第１の部分２２の表面には、金などのめっきが施されてもよい。
　第２のソース電極２１の第２の部分２３は、第１の部分２２と半導体層４０とを接続する層であり、限定されない一例として、アルミニウム、銅、金、銀のうちのいずれか１つ以上を含む金属材料で構成されてもよい。
　第１のボディ領域１８および第２のボディ領域２８は、開口を有する層間絶縁層３４で覆われ、層間絶縁層３４の開口を通して第１のソース領域１４および第２のソース領域２４に接続するソース電極の第２の部分１３および２３が設けられている。層間絶縁層３４およびソース電極の第２の部分１３および２３は、開口を有するパッシベーション層３５で覆われ、パッシベーション層３５の開口を通して第２の部分１３、２３にそれぞれ接続するソース電極の第１の部分１２および２２が設けられている。
　半導体装置１が実装基板に実装される場合には、第１のソース電極１１、第１のゲート電極１９、第２のソース電極２１および第２のゲート電極２９は、はんだなどの導電性接合材を介して、実装基板上に設けられた電極と、フェイスダウンにより接合される。この場合、半導体装置１の反りが大きいほど、第１のソース電極１１、第１のゲート電極１９、第２のソース電極２１および第２のゲート電極２９と、実装基板上に設けられた電極との電気的接続が不安定となる。つまり、半導体装置１の実装基板への実装をより安定化させるには、半導体装置１の反りを、より小さくする必要がある。
　トランジスタ１０および２０の上記構成により、半導体基板３２は、トランジスタ１０の第１のドレイン領域およびトランジスタ２０の第２のドレイン領域が共通化された、共通ドレイン領域として働く。また、半導体装置１は、第１のソース電極１１と第２のソース電極２１との間を、第１のドレイン領域、金属層３１、および第２のドレイン領域を経由して流れる双方向経路を主電流経路とする。
　図２Ａは、半導体装置１の充放電回路への第１の応用例を示す回路図である。図２Ａに示すように、半導体装置１は、制御ＩＣ２から与えられる制御信号に応じて、電池３から負荷４への放電および負荷４から電池３への充電を制御する。
　図２Ｂは、同様の応用例を、単方向のトランジスタ１０のみで構成した場合の回路図である。図２Ｂに示すように、放電電流はトランジスタ１０をオフ状態にすることで停止できるが、充電電流はトランジスタ１０をオフ状態にしても、第１のボディ領域１８と低濃度不純物層３３との間に形成されるボディダイオードを順方向（第１のボディ領域１８から低濃度不純物層３３への方向）に流れるために停止することができない。そこで、放電および充電の何れの方向にも完全な電流遮断を可能とするために、双方向トランジスタが必要となる。
　図２Ｃは、半導体装置１の充放電回路への第２の応用例を示す回路図である。図２Ｃに示すように、半導体装置１は、制御ＩＣ２から与えられる制御信号に応じて、トランジスタ１０をオフ状態にすることにより放電電流を遮断し、トランジスタ２０をオフ状態にすることにより充電電流を遮断する。
　なお、図１Ａに示す半導体装置１において、例えば、第１導電型をＮ型、第２導電型をＰ型として、第１のソース領域１４、第２のソース領域２４、半導体基板３２、および低濃度不純物層３３はＮ型半導体であり、かつ、第１のボディ領域１８および第２のボディ領域２８はＰ型半導体であってもよい。
　また、例えば、第１導電型をＰ型、第２導電型をＮ型として、第１のソース領域１４、第２のソース領域２４、半導体基板３２、および低濃度不純物層３３はＰ型半導体であり、かつ、第１のボディ領域１８および第２のボディ領域２８はＮ型半導体であってもよい。
　以下の説明では断りのない限り、図１Ａに示す半導体装置１において、第１導電型をＮ型、第２導電型をＰ型とした、いわゆるＮチャネル型トランジスタの場合として説明する。
　まず、半導体装置１のオン状態について説明する。
　図１Ａに示す半導体装置１において、第１のソース電極１１に高電圧、第２のソース電極２１に低電圧を印加し、第２のソース電極２１を基準として第１のゲート電極１９（第１のゲート導体１５）および第２のゲート電極２９（第２のゲート導体２５）にしきい値以上の電圧を印加すると、第１のゲート絶縁膜１６および第２のゲート絶縁膜２６の近傍にチャネルが形成され、第１のソース電極１１－第１のボディ領域１８－第１のドレイン領域－金属層３１－第２のドレイン領域－第２のボディ領域２８－第２のソース電極２１という経路で電流が流れる。
　これは図２Ａにおける充電電流の場合であり、トランジスタ１０、２０が導通してオン電流が流れる半導体装置１のオン状態である。
　トランジスタ１０および２０間でのオン電流は、金属層３１を流れる。そのため、金属層３１の厚くすることで、オン電流の経路の断面積は拡大し、半導体装置１のオン抵抗は低下する。
　次に、半導体装置１のオフ状態について説明する。
　図１Ａにおいて、第１のボディ領域１８と低濃度不純物層３３との間、および、第２のボディ領域２８と低濃度不純物層３３との間のＰＮジャンクションが、各々、ボディダイオードを構成する。以下、第１のボディ領域１８と低濃度不純物層３３との間に形成されたボディダイオードを第１のボディダイオードと記し、第２のボディ領域２８と低濃度不純物層３３との間に形成されたボディダイオードを第２のボディダイオードと記す。
　図１Ａにおいて、第２のソース電極２１を基準として第２のゲート電極２９（第２のゲート導体２５）の電圧がしきい値未満であれば、第１のソース電極１１に高電圧、第２のソース電極２１に低電圧を印加してもトランジスタ２０のゲート絶縁膜２６の近傍にチャネルは形成されず、オン電流が流れないオフ状態になる。このとき、トランジスタ１０におけるバイアス状態は、第１のボディダイオードに対して順方向のバイアス状態なので、第１のゲート電極１９（第１のゲート導体１５）に印加される電圧に依存せずトランジスタ１０は導通状態となる。
　なお、第１のソース電極１１と第２のソース電極２１への電圧印加条件が逆の、第２のソース電極２１に高電圧、第１のソース電極１１に低電圧を印加した場合も、第１のソース電極１１を基準として第１のゲート電極１９（第１のゲート導体１５）の電圧がしきい値未満であれば、トランジスタ１０のゲート絶縁膜１６の近傍にチャネルは形成されず、半導体装置１はオン電流が流れないオフ状態になる。
　[２．半導体装置のオン抵抗を低減する基本構造]
　ここで、本実施の形態に係る半導体装置１において、半導体装置１のオン抵抗を低減するための基本構成について説明する。
　図３Ａは、比較例１に係る半導体装置における、金属層の厚さに対するオン抵抗を表すグラフである。比較例１に係る半導体装置は、図１Ａおよび図１Ｂに示された半導体装置１に対して、接着層３９および支持体３０が形成されていない構成を有している。比較例１に係る半導体装置として、（１）半導体層４０の厚さが４３μｍであるもの、および、（２）半導体層４０の厚さが７８μｍであるものを想定し、これら２タイプの半導体装置について、金属層３１の厚さを１０～４０μｍの範囲で変化させた場合の半導体装置のオン抵抗を測定した。オン抵抗は、サンプルごとに、サンプルを評価基板に実装した状態で測定する第１の方法、およびベアチップの状態のサンプルにプローブを当てて行う第２の方法の何れかで行った。測定方法の違いで生じる測定値の差異は、適宜補正した。
　表１に、比較例１に係る半導体装置の各パラメータを示す。
Figure JPOXMLDOC01-appb-T000005
　図３Ａに示すように、金属層３１を厚くするにつれて、オン抵抗が低くなっていく。
　スマートホンやタブレットの充放電回路として、本開示の半導体装置が適用される場合、充電時間短縮や急速充電実現の制約から、オン抵抗は、２０Ｖ耐圧仕様として、２．２～２．４ｍΩ以下が求められる。
　図３Ａより、オン抵抗が２．４ｍΩ以下を満たす金属層３１の厚さは、２０μｍ以上であることが必要となる。
　図３Ｂは、比較例２に係る半導体装置における、半導体層４０の厚さに対する金属層３１の厚さの割合（以下、金属層３１厚さ／半導体層４０厚さ、と記す場合がある）、オン抵抗、および反り量の関係を示すグラフである。比較例２に係る半導体装置は、図１Ａおよび図１Ｂに示された半導体装置１に対して、接着層３９および支持体３０が形成されていない構成を有している。比較例２に係る半導体装置として、金属層３１の厚さを１０μｍ～４０μｍの範囲で変化させ、かつ、半導体層４０の厚さを２８～９３μｍの範囲で変化させた場合のオン抵抗および半導体基板３２および金属層３１の積層体の反り量を測定した。上記反り量については、ベアチップの状態のサンプルを、リフロー工程を模した最高温度２５０℃の熱負荷サイクル下に置き、モアレ法によりベアチップの形状を測定し、測定された反り量の最大値を記録した。
　表２に、比較例２に係る半導体装置の各パラメータを示す。
Figure JPOXMLDOC01-appb-T000006
　図３Ｂに示すように、金属層３１厚さ／半導体層４０厚さを大きくするにつれて、オン抵抗が低くなっていく。一方、金属層３１厚さ／半導体層４０厚さを大きくするにつれて、反り量が増加していく。
　図３Ｂより、オン抵抗が２．４ｍΩ以下を満たす金属層３１厚さ／半導体層４０厚さは、０．２７よりも大きいことが要求される。しかしながら、金属層３１厚さ／半導体層４０厚さは、０．２７よりも大きくなると、反り量が２０μｍ以上となる。反り量が大きくなるにつれ、実装基板へのフェイスダウン実装の際、安定した実装が困難となり、不具合が発生する。例えば、（１）半導体装置上の電極と実装基板上の電極との間の半田接合が不完全となる、（２）当該半田内でのボイドが発生する、（３）電極からの半田はみ出しによる電極間ショートが発生する、などの不具合が発生する。
　つまり、比較例１および２に係る半導体装置の場合、オン抵抗を、充放電回路として必要な２．４ｍΩ以下を満たすためには、（１）金属層３１の厚さは２０μｍ以上、かつ、（２）金属層３１厚さ／半導体層４０厚さが０．２７よりも大きいこと、が必要であるが、上記（１）および（２）を満たす場合、反り量が２０μｍ以上となるといった問題が発生する。
　[３．半導体装置のオン抵抗の低減および反りの低減を両立する構造]
　上述した比較例１および２に係る半導体装置に対して、本実施の形態に係る半導体装置１は、金属層３１の半導体基板３２と反対側の主面全面に接して接着層３９が形成され、接着層３９の金属層３１と反対側の主面全面に接して、セラミック材料からなる支持体３０が形成されている。
　セラミック材料からなる支持体３０の応力発生の主要因である熱膨張係数およびヤング率などの物理定数は、金属材料からなる金属層３１の上記物理定数よりも、半導体基板３２の上記物理定数に近い値を有する。つまり、半導体基板３２と金属層３１との接合により発生する熱膨張応力を打ち消す方向の熱膨張応力が、支持体３０と金属層３１との接合により発生する。これにより、金属層３１の対向する主面において、熱膨張応力のバランスがとれるため、金属層３１および半導体層４０の積層体の反りを抑制できる。
　これに対して、特許文献１に係る半導体装置では、金属層の半導体基板と反対側の主面に接して導電層が形成されている。導電層の上記物理定数は、半導体基板の上記物理定数よりも金属層の上記物理定数に近い値を有する。このため、特許文献１に係る半導体装置では、半導体基板と金属層との接合により発生する応力を打ち消す方向の応力は、導電層と金属層との接合により発生しない。
　また、本実施の形態に係る半導体装置１において、厚さ２０μｍ以上であって、かつ、半導体層４０に対する厚さの割合が０．２７より大きい金属層３１にかかる熱膨張応力を抑制するための支持体３０としては、特許文献２に開示された絶縁被膜（塗布型の有機材料、有機系のテープ、または無機系酸化物薄膜）のような薄膜系の材料では不十分である。これに対して、厚さ２０μｍ以上であって、かつ、半導体層４０に対する厚さの割合が０．２７より大きい金属層３１にかかる熱膨張応力を抑制するための支持体３０として、熱膨張係数およびヤング率が比較的半導体層４０のそれに近いセラミック材料の支持体３０を金属層３１に直接貼り付けることは、現実的に困難である。よって、本実施の形態に係る半導体装置１では、金属層３１と支持体３０との間に、接着層３９を介在させる構成としている。
　これにより、厚さ２０μｍ以上であって、かつ、半導体層４０に対する厚さの割合が０．２７より大きい金属層３１にかかる熱膨張応力を抑制すべく、金属層３１の半導体基板３２と反対側に、接着層３９およびセラミック材料からなる支持体３０を形成することにより、オン抵抗の低減と半導体装置１の反りの抑制とを両立させたチップサイズパッケージ型の半導体装置１を提供することが可能となる。
　なお、支持体３０のセラミック材料は、例えば、シリコンである。これにより、窒化シリコンおよび酸化シリコンと比較しても、半導体装置をダイシングにより個片化する場合の切削加工性が向上する。また、窒化シリコンおよび酸化シリコンよりも材料入手が容易であり、また、低コストである。
　また、金属層３１の金属材料は、例えば、銀（Ａｇ）である。これにより、金属材料として一般に用いられる銅（Ｃｕ）などと比較して、オン抵抗を効果的に低減することが可能となる。
　なお、本実施の形態に係る半導体装置１において、金属層３１は、半導体層４０より厚くてもよい。これにより、オン抵抗のさらなる低減に貢献できる。
　また、支持体３０は、半導体層４０より薄くてもよい。本実施の形態に係る半導体装置１の構成では、金属層３１と支持体３０との間の接着層３９が介在するため、支持体３０が半導体層４０より薄い場合であっても、半導体基板３２および金属層３１の反り量低減に貢献できる。
　また、接着層３９は、導電性接着剤であってもよく、例えば、導電性ＤＡＦが挙げられる。また、導電性接着剤の材料としては、例えば、銀ペーストが挙げられる。これにより、オン抵抗のさらなる低減に貢献できる。
　[４．半導体装置を構成する各層の厚さの最適化]
　ここで、本実施の形態に係る半導体装置１のオン抵抗および反りを低減するための各層の厚さを最適化するプロセスについて説明する。
　まず、物理定数の異なる多層を貼り合わせた場合に発生する反り量の理論式（多層ばり理論により導出された式）を、半導体層４０、金属層３１、接着層３９、および支持体３０の４層から構成される、本実施の形態に係る半導体装置１に適用する（ステップＳ１０）。
　次に、上記理論式に基づいて導出される本実施の形態に係る半導体装置１の反り量δが有限要素法を用いて構築された反り計算シミュレータでの計算値に合うように上記理論式をフィッティングする（ステップＳ２０）。
　最後に、上記理論式および反り計算シミュレータにより導出された実効的な反り量δｅの算出式より、本実施の形態に係る半導体装置１の反り量δｅが２０μｍ以下および４０μｍ以下となる場合の、接着層３９および支持体３０の厚さを導出する（ステップＳ３０）。
　まず、上記ステップＳ１０について説明する。
　図４Ａは、多層体に発生する反り量を導出するための基本モデルを表す図である。図４Ａに示すように、（熱膨張係数α１、ヤング率Ｅ１）および厚さｔ１を有する第１層、（熱膨張係数α２、ヤング率Ｅ２）および厚さｔ２を有する第２層、（熱膨張係数α３、ヤング率Ｅ３）および厚さｔ３を有する第３層、ならびに、（熱膨張係数α４、ヤング率Ｅ４）および厚さｔ４を有する第４層が、ｙ軸負方向に向けて、この順で接合されている。なお、ｙ軸方向からみた各層の長さＬおよび幅（奥行き）ｂは、４層とも同じと仮定する。
　図４Ｂは、多層体に発生する反り量δを説明する側面概略図である。同図に示すように、多層体に発生する応力により、多層体のｘ軸正方向の端部が、水平位置からｙ軸負方向にシフトする量を反り量δと定義する。
　ここで、非特許文献１（尾田十八、「多層ばり理論によるプリント基板の応力・変形解析」、機論Ａ編、ｐｐ．１７７７－１７８２、１９９３年）に記載された多層ばり理論に基づき、図４Ａに示された多層体モデルに発生する反り量δは、以下の式１で表される。また、式１のＲは、式２で表される。
Figure JPOXMLDOC01-appb-M000007
Figure JPOXMLDOC01-appb-M000008
　式１および式２より、反り量δは、各層の厚さｔｎ（ｎ＝１～４）の関数として表すことができ、当該関数を決定する他のパラメータが、各層の長さＬ、変化温度ΔＴ、各層の（αｎ、Ｅｎ）（ｎ＝１～４）である。
　表３に、上記式１および式２を用いて求めた反り量δの一例を示す。また、表４に、表３の反り量δを求めた際に使用した他のパラメータを示す。
Figure JPOXMLDOC01-appb-T000009
Figure JPOXMLDOC01-appb-T000010
　なお、表４において、幅ｂを１ｍｍとしているが、これは、反り量δの計算に関して、幅ｂは分母および分子の双方に現れて相殺されるため、任意の値でよいことに起因するものである。
　次に、上記ステップＳ２０について説明する。ステップＳ２０では、上記式１および式２に基づいて導出された反り量δが反り計算シミュレータでの計算値δｓに合うように上記式１および式２をフィッティングする。なお、このフィッティングに用いた反り計算シミュレータは、有限要素法解析を用いた構造解析ソフトウェア（ＡＮＳＹＳ社製）を、必要量の反り実測データを用いてカスタマイズしたものである。
　上記反り計算シミュレータに、表３に示された各層の厚さｔ１～ｔ４、表４に示された各パラメータを代入して得られた反り量の計算値δｓを用いて、式１および式２により算出した理論的な反り量δを補正することが可能となる。具体的には、反り量δと反り量δｓとの比をβ（＝δｓ／δ）とすると、反り量δを反り計算シミュレータ算出値にフィッティングされた実効的な反り量δｅへと変換できる。つまり、実効的な反り量δｅは、フィッティング係数βを用いて、以下の式３で表される。
Figure JPOXMLDOC01-appb-M000011
　表３の各データにおいて、最適なフィッティング係数βは、０．６７であった。
　次に、上記ステップＳ３０について説明する。式３に示された実効的な反り量δｅの算出式（以降、実効値算出式と呼ぶ）により、本実施の形態に係る半導体装置１の反り量が（１）２０μｍ以下、および、（２）４０μｍ以下となる場合の、接着層３９および支持体３０の厚さを導出する。
　図５は、実効値算出式を用いて算出した、接着層３９の厚さ、および、支持体３０の厚さに対する反り量δｅの変化を表すグラフである。同図には、半導体層４０の厚さを２０μｍ、および、金属層３１の厚さを３０μｍと固定し、接着層３９の厚さを０μｍ、３０μｍ、および５０μｍと変化させた場合の、支持体３０の厚さと反り量δｅとの関係が示されている。なお、その他のパラメータは、表４に示された値となっている。
　図５のグラフより、まず、反り量δｅを２０μｍ以下にする接着層３９と支持体３０との関係を把握する。図５より、以下のことが解る。
　（１）接着層３９が厚い方が、反り量δｅが０となる支持体３０の厚さが小さい。つまり、接着層３９の存在で支持体３０の必要量が少なくなる。
　（２）支持体３０を厚くすると、一旦逆反りになる（反り量δｅが負値をとる）が、さらに厚くすると０に近づく。逆反りにおける反り量δｅの極小点は１０μｍ程度であり、２０μｍ以上にはならない。よって、接着層３９および支持体３０の厚さの条件を出す場合には、順反りを２０μｍ以下にする条件を出せばよい。
　上述した、接着層３９および支持体３０の厚さの条件出しにおいて、本実施の形態に係る半導体装置１は、異なる物理定数および異なる厚さを有する４つの層を有するため、検討対象のパラメータが多い。そこで、以下の方針により、接着層３９および支持体３０の厚さを算出する。
　（１）主たるパラメータは、４つの層の各厚さ、および、反り量δｅである。反り量δｅの規格値を、第１規格値２０μｍ、および、第２規格値４０μｍとする。
　（２）本実施の形態に係る半導体装置１の特徴は、半導体層４０および金属層３１で発生する反りを抑制するために、接着層３９および支持体３０が配置されていることなので、反り量δｅの規格値を満足する支持体３０の厚さを、接着層３９の厚さに依存する形式で規定する。つまり、使用する接着層３９の厚さに応じて、支持体３０の厚さを決定できる関数を導出する。
　図６Ａは、実効値算出式を用いて算出した、半導体層４０の厚さを固定した場合（（ａ）は半導体層４０の厚さ１０μｍ、（ｂ）は半導体層４０の厚さ８０μｍ）の、反り量δｅを２０μｍにするための、金属層３１、接着層３９および支持体３０の厚さの関係を表すグラフである。また、図６Ｂは、実効値算出式を用いて算出した、金属層３１の厚さを固定した場合（（ａ）は金属層３１の厚さ２０μｍ、（ｂ）は金属層３１の厚さ７０μｍ）の、反り量δｅを２０μｍにするための、半導体層４０、接着層３９および支持体３０の厚さの関係を表すグラフである。
　図６Ａの（ａ）および（ｂ）に示すようなグラフを、半導体層４０の厚さ２０μｍ、４０μｍ、６０μｍの場合においても、また、図６Ｂの（ａ）および（ｂ）に示すようなグラフを、金属層３１の厚さ４０μｍ、５０μｍ、６０μｍの場合においても実効値算出式を用いて取得する。このようにして取得されたグラフより、反り量δｅを２０μｍにする接着層３９の厚さ毎の支持体３０の厚さを抽出する。このとき、半導体層４０の厚さおよび金属層３１の厚さの変化により、反り量δｅを２０μｍにする接着層３９の厚さ毎の支持体３０の厚さは変化するが、半導体層４０の厚さおよび金属層３１の厚さが変化するなかで、接着層３９の厚さ毎の支持体３０の厚さの最大値を抽出する。同様の抽出プロセスを、反り量δｅを４０μｍにする接着層３９の厚さ毎の支持体３０の厚さについても適用する。
　表５に、この抽出プロセスにより取得された接着層３９の厚さ毎の支持体３０の厚さの組み合わせを示す。また、表６に、表５の反り量δｅを求めた際に使用した他のパラメータを示す。
Figure JPOXMLDOC01-appb-T000012
Figure JPOXMLDOC01-appb-T000013
　なお、反り量δｅ規格値である２０μｍおよび４０μｍを目標値として設定して、接着層３９の厚さに対する支持体３０の厚さの関係を抽出する場合には、表６に示されたパラメータのうち目標値を用い、反り量δｅ規格値である２０μｍおよび４０μｍを許容値として設定して、接着層３９の厚さに対する支持体３０の厚さの関係を抽出する場合には、表６に示されたパラメータのうち最大値を用いた。
　図７は、実施の形態１に係る半導体装置１において、反り量２０μｍおよび４０μｍにするための接着層３９の厚さに対する支持体３０の厚さの関係を規定したグラフである。同図には、表５に示された抽出データがプロットされている。同図に示されたグラフより、（１）反り量δｅを２０μｍ（目標値）にする接着層３９の厚さに対する支持体３０の厚さの関係を表す近似式、（２）反り量δｅを２０μｍ（許容値）にする接着層３９の厚さに対する支持体３０の厚さの関係を表す近似式、（３）反り量δｅを４０μｍ（目標値）にする接着層３９の厚さに対する支持体３０の厚さの関係を表す近似式、（４）反り量δｅを４０μｍ（許容値）にする接着層３９の厚さに対する支持体３０の厚さの関係を表す近似式、が得られる。これらの近似式より、半導体装置１の反り量を抑制する接着層３９の厚さに対する支持体３０の厚さの関係は、式４～式７で表される。
　（１）接着層３９の厚さをｔ３（μｍ）とし、支持体３０の厚さをｔ４（μｍ）とした場合、反り量δｅを２０μｍ以下とする接着層３９の厚さに対する支持体３０の厚さは、以下の式４で表される。
Figure JPOXMLDOC01-appb-M000014
　これにより、金属層３１の厚さが２０μｍ、かつ、金属層３１厚さ／半導体層４０厚さが０．２７よりも大きい半導体装置１において、各層の長さＬが３．４ｍｍ以下であり、接着層３９の熱膨張係数α３が１．１（ｐｐｍ／℃）以下であり、接着層３９のヤング率Ｅ３が５０（ＧＰａ）以下であるという条件において、半導体装置１の反り量を２０μｍ以下とすることが可能となる。
　（２）接着層３９の厚さをｔ３（μｍ）とし、支持体３０の厚さをｔ４（μｍ）とした場合、反り量δｅを２０μｍ以下とする接着層３９の厚さに対する支持体３０の厚さは、以下の式５で表される。
Figure JPOXMLDOC01-appb-M000015
　これにより、金属層３１の厚さが２０μｍ、かつ、金属層３１厚さ／半導体層４０厚さが０．２７よりも大きい半導体装置１において、各層の長さＬが４．０ｍｍ以下であり、接着層３９の熱膨張係数α３が５．０（ｐｐｍ／℃）以下であり、接着層３９のヤング率Ｅ３が１００（ＧＰａ）以下であるという条件において、半導体装置１の反り量を２０μｍ以下とすることが可能となる。
　（３）接着層３９の厚さをｔ３（μｍ）とし、支持体３０の厚さをｔ４（μｍ）とした場合、反り量δｅを４０μｍ以下とする接着層３９の厚さに対する支持体３０の厚さは、以下の式６で表される。
Figure JPOXMLDOC01-appb-M000016
　これにより、金属層３１の厚さが２０μｍ、かつ、金属層３１厚さ／半導体層４０厚さが０．２７よりも大きい半導体装置１において、各層の長さＬが３．４ｍｍ以下であり、接着層３９の熱膨張係数α３が１．１（ｐｐｍ／℃）以下であり、接着層３９のヤング率Ｅ３が５０（ＧＰａ）以下であるという条件において、半導体装置１の反り量を４０μｍ以下とすることが可能となる。
　（４）接着層３９の厚さをｔ３（μｍ）とし、支持体３０の厚さをｔ４（μｍ）とした場合、反り量δｅを４０μｍ以下とする接着層３９の厚さに対する支持体３０の厚さは、以下の式７で表される。
Figure JPOXMLDOC01-appb-M000017
　これにより、金属層３１の厚さが２０μｍ、かつ、金属層３１厚さ／半導体層４０厚さが０．２７よりも大きい半導体装置１において、各層の長さＬが４．０ｍｍ以下であり、接着層３９の熱膨張係数α３が５．０（ｐｐｍ／℃）以下であり、接着層３９のヤング率Ｅ３が１００（ＧＰａ）以下であるという条件において、半導体装置１の反り量を４０μｍ以下とすることが可能となる。
　[５．変形例に係る半導体装置の構造]
　図８Ａは、実施の形態１の変形例１に係る半導体装置１Ａの断面図である。また、図８Ｂは、実施の形態１の変形例１に係る半導体装置１Ａの電極構成の一例を示す上面図である。図８Ａの断面図は、図８ＢのＶＩＩＩＡ－ＶＩＩＩＡにおける切断面を見た図である。図８Ａに示すように、半導体装置１Ａは、半導体基板３２と、低濃度不純物層３３と、金属層３１と、接着層３９と、支持体３０と、トランジスタ１０と、トランジスタ２０と、を有する。図８Ｂに示すように、半導体装置１Ａは、半導体基板３２を平面視した場合、２つの第１のソース電極１１、２つの第２のソース電極２１、１つの第１のゲート電極１９、および、１つの第２のゲート電極２９を有している。トランジスタ１０の上面には、トランジスタ１０とトランジスタ２０とが対向する方向と垂直な方向に沿って、第１のソース電極１１、第１のゲート電極１９、および第１のソース電極１１がこの順に形成されている。また、トランジスタ２０の上面には、トランジスタ１０とトランジスタ２０とが対向する方向と垂直な方向に沿って、第２のソース電極２１、第１のゲート電極２９、および第１のソース電極２１がこの順に形成されている。なお、１つのトランジスタを構成するソース電極およびゲート電極の個数および配置関係は、図８Ｂに示されたものに限定されない。
　本変形例に係る半導体装置１Ａは、実施の形態１に係る半導体装置１と比較して、トランジスタ１０および２０の境界に、切り込み部６１が形成されている点のみが構成として異なる。以下、本変形例に係る半導体装置１Ａについて、実施の形態１に係る半導体装置１と同じ構成については説明を省略し、異なる構成を中心に説明する。
　図８Ａおよび図８Ｂに示すように、本変形例に係る半導体装置１Ａでは、トランジスタ１０の第１の領域と、トランジスタ２０の第２の領域との間の境界に、半導体装置１Ａの上面側から下面側に向けて切り込み部６１が形成されている。また、切り込み部６１は、低濃度不純物層３３まで形成されている。なお、本変形例に係る半導体装置１Ａの切り込み部６１の最下端は、半導体基板３２の下面よりも半導体装置１Ａの上面側に位置している。
　これにより、半導体基板３２と低濃度不純物層３３との間の内部応力を緩和でき、半導体基板３２と低濃度不純物層３３との剥離を防止できる。また、切り込み部６１が半導体基板３２まで到達することにより、半導体基板３２と金属層３１との間の内部応力を緩和でき、半導体基板３２と金属層３１との剥離を防止できる。
　図９は、実施の形態１の変形例２に係る半導体装置１Ｂの断面図である。なお、実施の形態１の変形例２に係る半導体装置１Ｂの電極構成の一例を示す上面図については、図８Ｂに示された半導体装置１Ａの上面図と同様であるため省略する。
　図９に示すように、半導体装置１Ｂは、半導体基板３２と、低濃度不純物層３３と、金属層３１と、接着層３９と、支持体３０と、トランジスタ１０と、トランジスタ２０と、を有する。半導体装置１Ｂは、半導体基板３２を平面視した場合、２つの第１のソース電極１１、２つの第２のソース電極２１、１つの第１のゲート電極１９、および、１つの第２のゲート電極２９を有している。トランジスタ１０の上面には、トランジスタ１０とトランジスタ２０とが対向する方向と垂直な方向に沿って、第１のソース電極１１、第１のゲート電極１９、および第１のソース電極１１がこの順に形成されている。また、トランジスタ２０の上面には、トランジスタ１０とトランジスタ２０とが対向する方向と垂直な方向に沿って、第２のソース電極２１、第１のゲート電極２９、および第１のソース電極２１がこの順に形成されている。なお、１つのトランジスタを構成するソース電極およびゲート電極の個数および配置関係は、図８Ｂに示されたものに限定されない。
　本変形例に係る半導体装置１Ｂは、実施の形態１に係る半導体装置１と比較して、トランジスタ１０および２０の境界に切り込み部６２が形成されている点のみが構成として異なる。以下、本変形例に係る半導体装置１Ｂについて、実施の形態１に係る半導体装置１と同じ構成については説明を省略し、異なる構成を中心に説明する。
　図９に示すように、本変形例に係る半導体装置１Ｂでは、トランジスタ１０の第１の領域と、トランジスタ２０の第２の領域との間の境界に、半導体装置１Ｂの上面側から下面側に向けて切り込み部６２が形成されている。また、切り込み部６２は、金属層３１まで形成されている。なお、本変形例に係る半導体装置１Ｂの切り込み部６２の最下端は、金属層３１の上面と下面との間に位置している。
　これにより、半導体基板３２と金属層３１との間の内部応力を緩和でき、半導体基板３２と金属層３１との剥離を防止できる。さらに、金属層３１と接着層３９および支持体３０との間の内部応力を緩和でき、金属層３１と支持体３０との間における剥離を防止できる。
　[６．半導体装置の製造方法]
　実施の形態１に係る半導体装置１の製造方法について、図１０Ａ～１０Ｃ、図１１Ａ～１１Ｂ、図１２Ａ～１２Ｂ、図１３および図１４を参照しながら説明する。ここでは「縦型」ＭＯＳＦＥＴを例にとって説明するが、他に、ダイオード、「縦型」のバイポーラトランジスタ等においても同様の効果が得られることは言うまでもない。
　図１０Ａは、実施の形態１に係る半導体装置１の製造方法の第１工程を示す断面図である。図１０Ｂは、実施の形態１に係る半導体装置１の製造方法の第２工程を示す断面図である。図１０Ｃは、実施の形態１に係る半導体装置の製造方法の第３工程を示す断面図である。
　まず、図１０Ａに示すように、半導体基板３２Ａの一主面上に低濃度不純物層３３を形成し、さらに低濃度不純物層３３の表面領域に素子領域を形成する。次に、素子領域上の所定箇所にＡｌまたはＣｕ等の金属を主材料とする電極（第１のソース電極、第２のソース電極）を形成する。
　次に、図１０Ｂに示すように、半導体基板３２Ａの一主面側に仮接着剤３７を塗布する。このとき、電極や素子領域などの凹凸よりも仮接着剤３７を厚くすることが望ましい。さらに、仮接着剤３７の上にガラス基板３６をのせて押圧することで接着する。このとき、ガラス基板３６と仮接着剤３７との間に気泡が入らないようにするため、真空チャンバー内で接着することが望ましい。
　次に、図１０Ｃに示すように、求められる電気特性（オン抵抗）を実現できるように、半導体基板３２Ａの一主面と反対側の裏面を、半導体基板３２Ａの厚さが所望の厚さ（好ましくは５０μｍ以下）にまでバックグラインドし、所望の厚さの半導体基板３２を形成する。さらにＣＭＰ等の鏡面処理をしておくことが望ましい。
　図１１Ａは、実施の形態１に係る半導体装置１の製造方法の第４工程を示す断面図である。図１１Ｂは、実施の形態１に係る半導体装置１の製造方法の第５工程を示す断面図である。
　次に、図１１Ａに示すように、半導体基板３２の一主面と反対側の裏面上に、金属層３１を形成する。具体的な方法としては、半導体基板３２とオーミックコンタクトをとるように蒸着法を用いて半導体基板３２の裏面全体に第１金属層３１Ａを形成する。ここで、第１金属層３１Ａとして、例えば、半導体基板３２の裏面に近い側から順にＴｉおよびＮｉを積層する。
　次に、第１金属層３１Ａ上に、第２金属層３１Ｂを形成する。具体的には、電解めっき法を用いて形成する。ここで、第２金属層３１Ｂとしては、主にＡｇ、Ａｕ、Ｃｕなどを用いるのが良い。以降の説明では、第１金属層３１Ａと第２金属層３１Ｂとを合わせて金属層３１と呼ぶ。
　次に、図１１Ｂに示すように、金属層３１上に接着剤を塗布し、接着層３９を形成する。このとき、金属層３１の表面凹凸よりも接着層３９を厚くすることが望ましい。さらに、接着層３９の上に支持体３０をのせて押圧することで接着する。このとき、支持体３０と接着層３９との間に気泡が入らないようにするため、真空チャンバー内で接着することが望ましい。
　接着層３９を形成する接着剤としては、エポキシ樹脂、フェノール樹脂などの熱硬化型樹脂を用いる。また、支持体３０として、シリコンなどの材料のほかに、石英、サファイヤ、ほうけい酸ガラス、ソーダ石灰ガラスなど、紫外線に対して透明な材料を用いる場合は、接着剤として、エポキシアクリレート、アクリル酸アクリレート、ウレタンアクリレートなどの紫外線硬化型樹脂を用いることもできる。
　次に、上記接着剤を硬化させる工程について説明する。接着剤として熱硬化型樹脂を用いる場合の工程としては、貼り合わせを行ったウェハを、例えば、１５０℃程度の恒温炉に入れて１～２時間加熱する。加熱により上記接着剤を硬化させ、支持体３０と金属層３１との間を強く接着させる。
　また、上記接着剤に紫外線硬化型樹脂を用いる場合には、高圧水銀ランプなどの紫外線発生装置を用いて貼り合わせを行ったウェハの支持体３０側の面に対して、紫外線を照射する。照射する光量は例えば、３００～２０００ｍＪ／ｃｍ２とする。
　図１２Ａは、実施の形態１に係る半導体装置１の製造方法の第６工程を示す断面図である。図１２Ｂは、実施の形態１に係る半導体装置１の製造方法の第７工程を示す断面図である。
　次に、図１２Ａに示すように、支持体３０の表面、およびリングフレーム５０にダイシングテープ３８を貼付けて、リングフレーム５０へのマウントを行う。
　次に、仮接着剤３７とガラス基板３６とを除去する。具体的には、図１２Ａに示すように、仮接着剤３７のガラス基板３６との境界面付近にレーザー光７０を照射することで、ガラス基板３６に接している部分の仮接着剤３７を改質させて、半導体基板３２からなるウェハからガラス基板３６を除去する。その後、図１２Ｂに示すように、仮接着剤３７を剥離除去する。
　図１３は、実施の形態１に係る半導体装置１の製造方法の第８工程を示す断面図である。
　最後に、図１３に示すように、例えば、ダイシングソー等のダイシングブレード８０を用いて、半導体基板３２、低濃度不純物層３３、金属層３１、接着層３９、および支持体３０をダイシングして複数の半導体基板１へ個片化する。
　金属層３１を含む半導体基板３２のダイシングの際は、切削した金属がブレードに付着して目詰まり状態となり切削能力を維持できないという課題がある。さらに、シリコンからなる半導体基板３２を薄くしていくと、ブレードへの切削負荷が減少しブレードの磨耗が遅くなり前述の目詰まりを解消しにくくなるという悪循環に至り、さらに切削能力の維持が難しくなることが想定される。これに対して、本実施の形態に係る半導体装置１では、支持体３０としてシリコンを用いる。シリコンは、ブレードに適度な負荷を与えブレードの磨耗を促進する材質であるため、上記の目詰まり課題を改善できる。
　また、比較例１および２のような従来の構造では、半導体装置の片側最表面が金属層となっているため、ダイシング加工で金属層を切削する際にブレードで金属層が引き伸ばされ大きなバリが発生する。
　これに対して、本実施の形態に係る半導体装置１の製造工程では、金属層３１が半導体基板３２および支持体３０に挟まれている構造であるため、最表面に金属層３１のような延性材料がない状態となるため、切削端面にバリが発生しにくい、という効果を奏する。
　図１４は、実施の形態１に係る半導体装置の製造方法の第９工程を示す断面図である。さらに別の一例として、図１４に示すように、最後のダイシング工程の際に、複数のトランジスタ間にダイシングブレード８１を用いて切り込み６４を入れる。これにより、半導体基板３２とその上に形成された素子領域や電極による内部応力を緩和することができ、半導体基板３２と金属層３１との間の剥離を防止できる。図１４の工程は、図１０Ａ～１０Ｃ、図１１Ａ～１１Ｂ、図１２Ａ～１２Ｂに示した製造工程の後、実行されてもよく、図１４の工程の後に、図１３に示すダイシング工程により個別の半導体装置１へと分離される。図１４に示すように、半導体装置１に形成された複数のトランジスタ間にダイシングブレード８１によって切り込み６４が形成される。
　以上、本開示の１つまたは複数の態様に係る半導体装置について、実施の形態に基づいて説明したが、本開示は、この実施の形態に限定されるものではない。本開示の趣旨を逸脱しない限り、当業者が思いつく各種変形を本実施の形態に施したものや、異なる実施の形態における構成要素を組み合わせて構築される形態も、本開示の１つまたは複数の態様の範囲内に含まれてもよい。
　本願発明に係る半導体装置は、ＣＳＰ型の半導体装置として、双方向トランジスタ、単方向トランジスタ、ダイオードなどの各種の半導体装置に広く利用できる。
　１、１Ａ、１Ｂ　　半導体装置
　２　　制御ＩＣ
　３　　電池
　４　　負荷
　１０　　トランジスタ（第１の縦型ＭＯＳトランジスタ）
　１１　　第１のソース電極
　１２、２２　　第１の部分
　１３、２３　　第２の部分
　１４　　第１のソース領域
　１５　　第１のゲート導体
　１６　　第１のゲート絶縁膜
　１８　　第１のボディ領域
　１９　　第１のゲート電極
　２０　　トランジスタ（第２の縦型ＭＯＳトランジスタ）
　２１　　第２のソース電極
　２４　　第２のソース領域
　２５　　第２のゲート導体
　２６　　第２のゲート絶縁膜
　２８　　第２のボディ領域
　２９　　第２のゲート電極
　３０　　支持体
　３１　　金属層
　３１Ａ　　第１金属層
　３１Ｂ　　第２金属層
　３２、３２Ａ　　半導体基板
　３３　　低濃度不純物層
　３４　　層間絶縁層
　３５　　パッシベーション層
　３６　　ガラス基板
　３７　　仮接着剤
　３８　　ダイシングテープ
　３９　　接着層
　４０　　半導体層
　５０　　リングフレーム
　６１、６２　　切り込み部
　６３、６４　　切り込み
　７０　　レーザー光
　８０、８１　　ダイシングブレード

Claims (12)

  1. 　フェイスダウン実装が可能なチップサイズパッケージ型の半導体装置であって、
    　第１導電型の不純物を含み、シリコンからなる半導体基板と、
    　前記半導体基板の上面に接して形成され、前記半導体基板の前記第１導電型の不純物の濃度より低い濃度の前記第１導電型の不純物を含む低濃度不純物層と、
    　前記半導体基板の下面全面に接して形成され、厚さが２０μｍ以上の金属材料のみで構成された金属層と、
    　前記低濃度不純物層内の第１の領域に形成された第１の縦型ＭＯＳトランジスタと、
    　前記第１の領域と前記半導体基板の上面に沿った方向で隣接する、前記低濃度不純物層内の第２の領域に形成された第２の縦型ＭＯＳトランジスタと、を備え、
    　前記第１の縦型ＭＯＳトランジスタは、前記低濃度不純物層の上面に形成された第１のソース電極および第１のゲート電極を有し、
    　前記第２の縦型ＭＯＳトランジスタは、前記低濃度不純物層の上面に形成された第２のソース電極および第２のゲート電極を有し、
    　前記半導体基板は、前記第１の縦型ＭＯＳトランジスタの第１のドレイン領域および前記第２の縦型ＭＯＳトランジスタの第２のドレイン領域を共通化したドレイン領域として機能し、
    　前記第１のソース電極と前記第２のソース電極との間を、前記第１のドレイン領域、前記金属層、および前記第２のドレイン領域を経由して流れる双方向経路を主電流経路とし、
    　前記半導体基板と前記低濃度不純物層とを含む半導体層に対する前記金属層の厚さの割合は０．２７より大きく、
    　前記半導体装置は、さらに、
    　前記金属層の下面全面に、接着層のみを介して接着された、セラミック材料からなる支持体を有する
    　半導体装置。
  2. 　前記セラミック材料は、シリコンである
    　請求項１に記載の半導体装置。
  3. 　前記金属材料は、銀である
    　請求項１または２に記載の半導体装置。
  4. 　前記金属層の厚さは、前記半導体層の厚さより厚い
    　請求項３に記載の半導体装置。
  5. 　前記支持体の厚さは、前記半導体層の厚さより薄い
    　請求項３に記載の半導体装置。
  6. 　前記接着層の構成材料は、導電性材料である
    　請求項３に記載の半導体装置。
  7. 　前記支持体の厚さをｔ４、前記接着層の厚さをｔ３とした場合、
    Figure JPOXMLDOC01-appb-M000001
     　を満足する
    　請求項３に記載の半導体装置。
  8. 　前記支持体の厚さをｔ４、前記接着層の厚さをｔ３とした場合、
    Figure JPOXMLDOC01-appb-M000002
     　を満足する
    　請求項７に記載の半導体装置。
  9. 　前記支持体の厚さをｔ４、前記接着層の厚さをｔ３とした場合、
    Figure JPOXMLDOC01-appb-M000003
     　を満足する
    　請求項７に記載の半導体装置。
  10. 　前記支持体の厚さをｔ４、前記接着層の厚さをｔ３とした場合、
    Figure JPOXMLDOC01-appb-M000004
     　を満足する
    　請求項９に記載の半導体装置。
  11. 　前記第１の領域と前記第２の領域との間の境界に、前記半導体装置の上面側から下面側に向けて切り込み部が形成されており、
    　前記切り込み部の最下端は、前記半導体基板の下面よりも前記上面側に位置する
    　請求項１に記載の半導体装置。
  12. 　前記切り込み部の最下端は、前記金属層の上面と下面との間に位置する
    　請求項１１に記載の半導体装置。
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