CN110676165A - 半导体器件和制造半导体器件的方法 - Google Patents

半导体器件和制造半导体器件的方法 Download PDF

Info

Publication number
CN110676165A
CN110676165A CN201910594096.1A CN201910594096A CN110676165A CN 110676165 A CN110676165 A CN 110676165A CN 201910594096 A CN201910594096 A CN 201910594096A CN 110676165 A CN110676165 A CN 110676165A
Authority
CN
China
Prior art keywords
silicon carbide
carbide substrate
metal
auxiliary
backside
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910594096.1A
Other languages
English (en)
Inventor
C.舍费尔
A.布雷梅瑟
B.戈勒
R.克恩
M.皮辛
R.鲁普
F.J.桑托斯罗德里格斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN110676165A publication Critical patent/CN110676165A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68309—Auxiliary support including alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04034—Bonding areas specifically adapted for strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Dicing (AREA)

Abstract

本发明涉及半导体器件和制造半导体器件的方法。根据本文描述的方法的实施例，提供了碳化硅衬底(700)，其包括多个器件区域(650)。可以在碳化硅衬底(700)的前侧处提供前侧金属化(610)。该方法还可以包括在碳化硅衬底(700)的后侧处提供辅助结构(800)。辅助结构(800)包括多个横向分离的金属部分(810)。每个金属部分(810)与器件区域(650)之一接触。

Description

半导体器件和制造半导体器件的方法
技术领域
本公开涉及制造半导体器件的方法和半导体器件。
背景技术
半导体晶片通常以标准晶片尺寸和/或厚度可用。例如，标准晶片直径可以是2英寸(50mm)、4英寸(100mm)或6英寸(150mm)。对于碳化硅晶片，标准晶片厚度可以是例如350μm。已经尝试减小半导体材料的最终厚度以改善器件特性。例如，在具有在前侧和后侧之间的垂直负载电流流动的功率半导体器件中，较薄的半导体管芯（die）可能导致较低的导通状态电阻。晶片分割方法旨在将晶片水平地分割成多个薄晶片以节省成本，但脆性半导体材料可能使比标准晶片更薄的半导体晶片的处理复杂化。辅助载体可以可逆地接合到半导体晶片的前侧，以增加机械稳定性。通常在晶片切割之前去除辅助载体。
发明内容
本公开的实施例涉及一种制造半导体器件的方法。提供碳化硅衬底，其包括多个器件区域。此外，在碳化硅衬底的前侧处提供前侧金属化。在碳化硅衬底的后侧处提供辅助结构。辅助结构包括多个横向（laterally）分离的金属部分。每个金属部分与器件区域之一接触。
本公开的另一个实施例涉及制造半导体器件的另一种方法。提供碳化硅衬底。此外，在碳化硅衬底的前侧处提供前侧金属化，并且在碳化硅衬底的后侧处提供后侧金属化。提供金属盘，使得金属盘和后侧金属化在结构上被连接。
本公开的另一实施例涉及一种半导体器件。该半导体器件包括碳化硅主体、在碳化硅主体的前侧处的第一负载电极、在碳化硅主体的后侧处的第二负载电极和与第二负载电极接触的金属板。金属板的厚度为至少30μm且至多300μm。负载端子与金属板接触。
在阅读以下详细描述和查看附图之后，本领域技术人员将认识到附加的特征和优点。
附图说明
附图被包括以提供对实施例的进一步理解，并且被包含在本说明书中并构成本说明书的一部分。附图图示了半导体器件的实施例和制造半导体器件的方法，并且与说明书一起用于解释实施例的原理。在以下详细描述和权利要求中描述了进一步的实施例。
图1是图示根据实施例的制造半导体器件的方法的简化示意流程图；
图2A-2B示出根据实施例的具有碳化硅衬底的晶片组装件的示意性截面图，其中辅助结构的金属部分与碳化硅衬底的器件区域接触；
图3A-3C示出根据实施例的具有碳化硅衬底的晶片组装件和辅助结构的示意性截面图，其涉及基于具有栅格形沟槽的金属盘的辅助结构；
图4A-4C示出根据实施例的具有碳化硅衬底的晶片组装件和辅助结构的示意性截面图，其中辅助结构的金属部分形成在非金属辅助基部的沟槽中；
图5A-5C示出根据实施例的具有碳化硅衬底的晶片组装件的示意性垂直截面图，其中辅助结构的金属部分形成在具有碳化硅衬底的工件的后侧处的矩阵状分离结构的开口中；
图6A-6J示出根据另一实施例的具有碳化硅衬底的晶片组装件、辅助结构和辅助载体的示意性垂直截面图；
图7是图示根据另一实施例的制造半导体器件的方法的简化示意流程图；
图8A-8C示出根据实施例的具有碳化硅衬底的工件、辅助结构和晶片组装件的示意性截面图，其涉及包括扁平金属盘的辅助结构；
图9A-9D图示根据实施例的具有碳化硅衬底的晶片组装件的示意性截面图，其涉及施加辅助结构之前的切割过程；
图10图示根据实施例的晶片组装件的示意性截面图，其涉及包括环部分的辅助载体；
图11图示根据另一实施例的半导体管芯的示意性截面图；
图12图示根据另一实施例的碳化硅器件的示意性截面图。
具体实施方式
在下面的详细描述中，参考附图，附图形成其一部分，并且其中通过图示的方式示出了其中可以实施碳化硅器件和制造碳化硅器件的方法的具体实施例。应当理解，在不脱离本公开的范围的情况下，可以利用其他实施例并且可以进行结构或逻辑上的改变。例如，针对一个实施例图示或描述的特征可以在其他实施例上使用或与其他实施例结合使用，以产生又另一个实施例。本公开旨在包括这样的修改和变化。特别地，还针对半导体器件的实施例公开了结合方法的实施例所描述的所有特征，反之亦然。
示例使用具体语言描述，其不应被解释为限制所附权利要求的范围。附图未按比例绘制，并且仅用于说明目的。如果没有另外说明，对应的元件在不同的附图中由相同的附图标记表示。
术语“具有”、“含有”、“包括”、“包含”、“有”等是开放的，并且这些术语指示所述结构、元件或特征的存在，但不排除附加的元件或特征。除非上下文另有明确说明，否则冠词“一”、“一个”和“该”旨在包括复数以及单数。
此外，术语“在……上”不应被解释为仅意味着“直接在……上”。而是，如果一个元件位于另一个元件“上”（例如，层在另一个层“上”或在衬底“上”），则另一个组件（例如，另一个层）可以位于这两个元件之间（例如，另一层可以位于层和衬底之间，如果该层在所述衬底“上”的话）。
术语“电连接”描述了电连接元件之间的永久低电阻连接，例如相关元件之间的直接接触或经由金属和/或重掺杂半导体材料的低电阻连接。术语“电耦合”包括适于信号和/或功率传输的一个或多个中间元件可以在电耦合的元件（例如可控制以临时提供第一状态下的低电阻连接和第二状态下的高电阻电去耦合的元件）之间。
图通过在掺杂类型“n”或“p”旁边指示“-”或“+”来说明相对掺杂浓度。例如，“n-”意指比“n”掺杂区的掺杂浓度更低的掺杂浓度，而“n+”掺杂区具有比“n”掺杂区更高的掺杂浓度。相同相对掺杂浓度的掺杂区不一定具有相同的绝对掺杂浓度。例如，两个不同的“n”掺杂区可以具有相同或不同的绝对掺杂浓度。
针对参数给出的范围包括边界值。例如，从a到b的参数y的范围理解为a≤y≤b。具有至少为c的值的参数y理解为c≤y，而具有至多为d的值的参数y理解为y≤d。
来自化合物或合金的层或结构的主要成分是原子形成化合物或合金的这样的元素。例如，镍和硅是硅化镍层的主要成分，而铜和铝是铜铝合金的主要成分。
IGFET（绝缘栅场效应晶体管）是包括MOSFET（金属氧化物半导体FET）和其他FET的电压控制器件，其具有基于掺杂半导体材料的栅电极和/或具有不基于或不排他地基于氧化物的栅极电介质。
根据实施例，制造半导体器件（例如碳化硅器件）的方法可以包括提供半导体衬底，例如碳化硅衬底。
在下文中，结合作为半导体衬底的半导体材料的碳化硅来解释半导体器件的实施例和方法的实施例。然而，这里描述的方法可以适合于通过用不同的半导体衬底替换碳化硅衬底来提供具有任何其他半导体材料的半导体器件。例如，宽带隙半导体材料（例如，具有GaN、AlN或Ga2O3作为主要成分）可以用作半导体材料。
此外，即使结合仅包括一种类型的半导体材料（即：碳化硅）的半导体衬底描述了该方法，但半导体衬底也可以包括不同类型的半导体材料。例如，半导体衬底可以包括第一半导体材料（例如GaN）的外延层和第一半导体材料已经外延生长到其上的第二不同半导体材料（例如Si）的半导体晶片。另外或作为替代，半导体衬底可以包括不同半导体材料的层堆叠和/或半导体材料的不同组成。例如，在第二半导体材料的半导体晶片上的第一半导体材料的外延层的情况下，中间层堆叠（例如，用于匹配第一和第二半导体材料的晶格常数和/或热膨胀系数）可以位于外延层和晶片之间。
该方法特别适合于提供具有高价半导体材料的半导体衬底的半导体器件。遍及该应用，高价半导体材料是需要高价半导体晶片和/或高价生长衬底以提供半导体器件的半导体材料。在该上下文中，“高价”可能意味着半导体晶片和/或生长衬底比相同尺寸（例如具有相当的晶体质量）的碳化硅晶片更昂贵。另外或作为替代，“高价”可能意味着半导体器件的裸管芯部分（即，没有封装或电路）的最终成本的至少30％或至少40％可以由半导体晶片和/或生长衬底的价格来确定。
碳化硅衬底可以是作为外延材料可以生长到其上的生长衬底的碳化硅晶片。另外或作为替代，碳化硅衬底可以是外延层。例如，碳化硅衬底可以已经在作为生长衬底的碳化硅晶片上外延生长，在所述外延生长之后去除碳化硅晶片的至少部分。碳化硅衬底也可以对应于碳化硅晶片，其中掺杂区可以已经被引入到碳化硅晶片中。
利用本文描述的方法的实施例而制造的半导体器件可以是功率半导体器件。例如，半导体器件可以是场效应晶体管(FET；例如MOSFET或JFET)、IGBT或二极管（例如，合并引脚肖特基二极管或合并引脚异质结二极管）或其组合。
碳化硅衬底可以包括多个器件区域。例如，多个器件区域可以被空闲区域横向分离。换句话说，空闲区域可以布置在两个相邻的器件区域之间。空闲区域可以形成在碳化硅衬底中，也就是说，可以是碳化硅衬底的一部分。空闲区域可以是栅格形的，即，在到碳化硅衬底上的顶视图中可以具有栅格的形状。空闲区域可以作为相应的器件区域的框架（frame）。
可以在碳化硅衬底的前侧处提供前侧金属化。前侧金属化可以以单件形成或可以包括多个分离的部分。分离的部分可以以多部分和/或以多件方式形成。在此和在下文中，元件或所述元件的部分以“多部分方式”形成可以意味着元件的部分经由较小的桥连接。“多部分”元件的顶面可以是连贯的（coherent），但不是简单连贯。例如，“多部分”元件可以包括所述元件的部分之间的孔和/或间隙。此外，在此和下文中，元件或所述元件的部分以“多件方式”形成可以意味着部分没有互连，即，部分彼此分离。“多部分”元件的顶面可能不连贯。如果元件的部分同时形成为“多部分”和“多件”，则所述元件可以包括其中第一部分以多部分方式形成的第一部件和其中第二部分以多件方式形成的第二部件，其中第一部件和第二部件可以彼此以多件方式形成。
前侧金属化的每个部分可以以一对一的方式分配给器件区域。在一个实施例中，可以在后侧处提供辅助结构之前在前侧处提供前侧金属化。
碳化硅衬底和前侧金属化可以共同形成工件，即用于进一步处理的中间产品。
可以在碳化硅衬底的后侧处提供辅助结构。辅助结构可以包括多个横向分离的金属部分。金属部分可以以多部分或多件方式形成。辅助结构的每个金属部分可以与碳化硅衬底的器件区域之一接触。特别地，辅助结构的每个金属部分可以与器件区域的确切一个接触。金属部分和器件区域可以以一对一的方式分配到彼此。
每个器件区域可以包括多个不同掺杂区，其构成从器件区域获得的最终化半导体器件的电功能。每个器件区域可以包括相同的功能电路（即，功能电路可以沿器件区域复制）。每个器件区域可以连接到最终化半导体器件的前侧金属化和后侧金属化。例如，后侧金属化可以包括辅助结构的至少一部分。
从每个器件区域，切割过程产生单个半导体管芯（“芯片”），其中半导体管芯包括半导体材料块，在其中或在其上制造给定的功能电路。在切割之前，每个半导体管芯形成碳化硅衬底的一个器件区域。
器件区域可以以矩阵布置。空闲区域可以没有成为半导体器件的组成部分的这样的元件和结构。空闲区域可以包括在晶片级制造过程和器件表征期间临时使用的元件和结构，例如电测试电路和/或对准标记。在切割过程期间可以消耗一部分的空闲区域。例如，使用机械锯的切割过程可以在空闲区域内产生划线。
辅助结构可以形成用于碳化硅衬底的刚性的和/或坚固的和/或机械稳定化的载体，例如在晶片级处施加的过程期间。在下文中，“机械稳定化”意指可以利用适当的工具在随后的过程步骤中处理碳化硅衬底，而不需要另外的载体，例如，以防止碳化硅衬底的破裂或弯曲和/或使处理容易。在至少一个方法步骤中，辅助结构可以是用于碳化硅衬底的仅有机械稳定化结构。例如，辅助结构可以在从碳化硅衬底的前侧去除辅助载体期间和之后稳定化碳化硅衬底。特别地，辅助结构可以在器件表征期间稳定化碳化硅衬底。
器件表征（管芯分选（sort）和/或电分选）可以包括用于每个器件区域的电测试。对于器件表征，碳化硅衬底可以安装在卡盘上，卡盘可以将碳化硅衬底与电探针对准。电探针可以至少与前侧金属化接触。通常，只要安装在碳化硅衬底的前侧处的辅助载体覆盖前侧金属化，器件表征就不可能。器件表征可以导致从整个碳化硅衬底和/或碳化硅衬底的半导体器件中的至少一些中分选。
后侧处的辅助结构可以机械稳定化碳化硅衬底，而不会阻止电探针接近前侧金属化。另外，由于辅助结构的金属部分是导电的，所以即使后侧金属化也电可用于器件表征。
例如，在垂直功率半导体器件中，负载电流可以通过半导体管芯在第一负载电极和第二负载电极之间沿垂直方向流动，第一负载电极可以形成前侧金属化的一部分，第二负载电极可以形成后侧金属化的一部分。在器件表征期间，辅助结构在探测期间机械稳定化碳化硅衬底，并允许在晶片级上的每个半导体管芯的完整功能测试。
由于辅助结构可以机械稳定化碳化硅衬底到切割，所以碳化硅衬底的厚度可以减小到180μm以下，例如，110μm以下，90μm以下或者至多70μm。最终厚度可以取决于碳化硅衬底的直径。例如，如果碳化硅衬底具有6英寸的直径，则厚度可以减小到110μm以下。
由于辅助结构的金属部分可以彼此横向分离，所以可以使用辅助结构而不会显著影响将各个半导体管芯与碳化硅衬底分离的切割过程的复杂性。
金属部分具有比高掺杂半导体材料明显更低的欧姆电阻率，使得金属部分可以成为最终化半导体器件的组成部分，而不会显著影响器件参数，诸如导通状态电阻。在碳化硅衬底的机械处理期间，例如在切割期间和/或在拾取和放置过程期间，金属部分可以减少裂缝的发生和/或可以降低碳化硅材料的机械损坏的风险。例如，碳化硅衬底的机械损坏可能是由于在机械处理期间碳化硅衬底的至少部分（例如，碳化硅衬底的边缘）被切掉，例如由于碳化硅是脆性材料。
根据实施例，提供辅助结构可以包括提供辅助结构并且在结构上将辅助结构的顶表面与碳化硅衬底的后侧表面连接。也就是说，辅助结构可以是预制的。结构连接可以是机械连接。
预制辅助结构然后将完全预制的辅助结构与碳化硅衬底的后侧表面机械连接允许以成本有效的方式在单独的过程中形成辅助结构。由于器件区域的边缘长度通常在毫米或至少几百μm的范围内，所以预制辅助结构相对于碳化硅衬底的器件区域的对准可以相对简单。
根据实施例，辅助结构可以包括具有沟槽的金属盘，其中沟槽从顶表面延伸到金属盘中。金属部分可以由被沟槽横向分离的金属盘的部分形成。通常，被沟槽横向分离的部分可以相对于碳化硅衬底的器件区域对准。
使用词语“盘”并不将金属盘限制为任何特定形状。金属盘可以具有椭圆形（例如圆形）或多边形（例如六边形）截面。
沟槽可以是栅格形的。在这种情况下，器件区域可以被栅格形的空闲区域分离。沟槽可以与空闲区域对准，即，可以与空闲区域至少部分地重叠。
具有沟槽的金属盘可以以相对简单的方式制造，例如，通过模制、蚀刻、研磨和/或锯切。基于预制金属盘的辅助结构可能仅需要相对简单的凹陷过程作为附加的过程步骤。例如，除了将碳化硅衬底切割成多个单独的半导体管芯的切割过程之外，还可以添加研磨过程作为这样的附加过程步骤。这可以在器件表征之后发生，例如在电分选之后。
根据实施例，提供辅助结构可以包括提供辅助基部。辅助基部可以包括横向分离的沟槽，其中沟槽可以从辅助基部的顶表面延伸到辅助基部中。金属部分可以形成在分离的沟槽中。
辅助基部可以包括或由可以以高选择性针对金属部分可去除或可以容易地切断的材料组成。因此，实施例可以仅对切割过程的复杂性增加很少。例如，辅助基部可以包括玻璃材料、聚合物材料（例如抗蚀剂材料）和/或晶体硅。
根据实施例，在结构上将辅助结构的顶表面与碳化硅衬底的后侧表面连接可以包括烧结、扩散焊接、直接接合、反应接合中的至少一种。
在直接接合的情况下，辅助结构的顶表面和碳化硅衬底的后侧表面足够平坦、光滑和清洁。直接接合的辅助结构和碳化硅衬底之间的粘附可以基于碳化硅衬底和辅助结构之间的化学接合、氢接合、金属接合、离子接合和/或共价接合。
直接接合可以包括施加将碳化硅衬底和辅助结构彼此压靠的物理力、在中等温度下的对顶表面和后侧表面中的至少一个的热处理、或两者的组合（熔融接合、热压接合、通过原子重排的接合）。直接接合可以包括不存在任何附加的中间层。
扩散焊接可以包括在辅助结构的顶表面和碳化硅衬底的后侧表面中的至少一个上涂敷扩散焊料材料。扩散焊料可以包括锡和至少一种其他金属。例如，扩散焊料可以是无铅的，并且可以包括Sn以及Ni、In、Pd、Mo、Cu、Au和Ag中的至少一种。
烧结可以包括在辅助结构的顶表面和碳化硅衬底的后侧表面中的至少一个处涂敷烧结膏，其中烧结膏可以包括银和铜中的至少一种。
可以在相对较低的温度下执行直接接合、扩散焊接和烧结，使得可以提供辅助结构而不会对碳化硅衬底中的先前形成的结构具有显著影响。
根据实施例，在碳化硅衬底的后侧处提供辅助结构可以包括在碳化硅衬底的后侧处（例如在后侧表面处）形成分离结构。
分离结构可以具有矩阵状的形状。例如，分离结构包括开口。分离结构中的开口可以暴露器件区域。金属部分可以形成在分离结构的开口中。
每个器件区域可以由一个开口暴露，其中每个器件区域可以完全暴露，或者每个器件区域的至少90％可以暴露。
在碳化硅衬底的后侧处（例如直接在碳化硅衬底的后侧表面上）形成分离结构可以包括对准过程，该对准过程可以使用碳化硅衬底的对准标记或碳化硅衬底中的先前形成的使用结构来使分离结构中的开口以高精度与器件区域对准。
分离结构可以通过印刷过程或通过光刻过程由例如酰亚胺、树脂（例如环氧树脂）或BCB（苯并环丁烯，C8H8）的有机材料形成。相对简单的过程可以以高选择性针对金属部分去除分离结构，或者可以容易地切穿分离结构，使得辅助结构可能仅略微影响切割过程的复杂性。
根据实施例，方法可以进一步包括将碳化硅衬底和辅助结构分割（例如锯切和/或切割）成多个半导体管芯，其中每个半导体管芯可以包括器件区域之一和金属部分之一。另外，前侧金属化被分成多个前侧金属部分和/或可以包括多个单独的前侧金属部分，其中每个半导体管芯可以包括前侧金属部分之一。
辅助结构不会针对将碳化硅衬底分成分离的半导体管芯的过程增加显著的复杂性。辅助结构可以在对半导体材料有效的切割过程期间稳定化（例如机械稳定化）碳化硅衬底，并且可以降低形成从划线延伸到器件区域中的裂缝的风险。金属部分还可以降低沿着划线切掉碳化硅晶体的部分的风险。金属部分增加了超薄半导体器件的厚度，并且因此可以简化例如从切割带拾取单个化的半导体管芯并且将半导体管芯放置在例如引线框架上的拾取和放置过程。金属部分可以在拾取和放置过程期间针对削片保护半导体盘的半导体部分。
根据另一实施例，制造半导体器件的方法可以包括提供碳化硅衬底。此外，可以在碳化硅衬底的前侧处提供前侧金属化和/或可以在碳化硅衬底的后侧处提供后侧金属化。
在另一方法步骤中，提供金属盘。例如，金属盘可以在碳化硅衬底处提供了前侧金属化和/或后侧金属化之后提供。金属盘和后侧金属化可以在结构上连接。金属盘可以机械稳定化碳化硅衬底。例如，在至少一个方法步骤中，金属盘可以形成碳化硅衬底的仅有的机械稳定化载体。前侧金属化和后侧金属化都可以可用于电分选和/或管芯分选。
通常，在本文所述方法的至少一个实施例中，在碳化硅衬底处提供金属化（例如前侧金属化和/或后侧金属化）可以包括金属或金属合金的溅射、电镀和气相沉积中的至少一种。例如，金属化（例如前侧金属化和/或后侧金属化）可以包括多个金属层，每个金属层由金属或金属合金形成，其中直接邻接的金属层由不同的材料或者不同的材料成分组成。
根据实施例，辅助载体可以形成在碳化硅衬底的前侧处。辅助载体可以在结构上连接辅助结构之前和/或在提供后侧金属化之前形成。在前侧金属化提供在碳化硅衬底的前侧处之后，可以进一步形成辅助载体。
在形成辅助载体之后并且在结构上连接金属盘和后侧金属化之前，可以减小碳化硅衬底的厚度。减小碳化硅衬底的厚度可以包括去除部分的碳化硅衬底，例如，通过以下中的至少一种：分离方法和机械去除（例如研磨和/或抛光）。通过减小厚度，可以获得薄的碳化硅衬底。
碳化硅衬底、前侧金属化和后侧金属化可以共同形成工件，即用于进一步处理的中间产品。
金属盘可以形成辅助结构，其可以在厚度减小之后并且在器件表征之前去除可以在减薄过程期间稳定化碳化硅衬底的辅助载体之后机械稳定化薄碳化硅衬底。
根据实施例，辅助载体可以包括环部分。辅助载体特别是辅助载体的环部分可以在没有粘合剂层的情况下接合到碳化硅衬底（例如经由后侧金属化）。也就是说，碳化硅衬底和辅助载体和/或辅助载体的环部分之间的接合可以没有粘合剂层。例如，热接合可以用于无粘合剂层的接合。
根据实施例，在形成辅助载体之前，可以形成前侧分离沟槽。前侧分离沟槽可以从前侧延伸到碳化硅衬底中。至少半导体管芯的半导体部分可以彼此横向分离，其中半导体管芯保持在碳化硅衬底内的原始位置处，使得可以更好地控制切割过程，例如机械锯切。
根据实施例，减小碳化硅衬底的厚度可以包括分离碳化硅衬底的层部分。遍及本申请，分离碳化硅衬底的层部分也可以称为“分离方法”。层部分可以重复用于制造其他半导体器件。可以从单个标准碳化硅晶片获得多个薄碳化硅衬底。
在至少一个实施例中，分离碳化硅衬底的层部分包括将离子注入到碳化硅衬底中以在碳化硅衬底中形成分离区域的步骤。分离区域中的吸收系数是分离区域外的碳化硅衬底中的吸收系数的至少5倍、或至少20倍那么高，例如针对要施加到碳化硅衬底的激光辐射的波长。该方法还可以包括用激光辐射照射碳化硅衬底的步骤。
例如，分离方法可以是激光辅助分离方法。也就是说，分离方法可以包含将激光辐射施加到碳化硅衬底，即，用激光辐射照射碳化硅衬底。激光辐射可以例如沿着碳化硅衬底的分离区域施加，以便沿着分离区域创建热机械应力，这可以促进和/或简化碳化硅衬底的层部分的去除。
离子可以是碳化硅衬底中的层，其可以具有针对施加到碳化硅衬底的激光辐射的更高的吸收系数。另外或作为替代，可以通过将激光辐射聚焦到碳化硅衬底中的明确限定的区域来限定分离区域，该明确限定的区域可以构成分离区域。在该上下文中，“明确限定”可以意指所述区域具有比沿着垂直方向的碳化硅衬底的总厚度小的沿着碳化硅衬底的垂直方向的厚度。通常，分离区域可以具有比碳化硅衬底的厚度小的厚度。分离区域的横向范围可以是碳化硅衬底的横向范围的至少90％、或至少95％。换句话说，分离区域可以基本上沿整个碳化硅衬底横向延伸。
分离区域可以包括与碳化硅衬底的其余部分不同的材料和/或可以具有与碳化硅衬底的其余部分不同的晶体结构，例如不同的多型或不同的结晶度。“碳化硅衬底的其余部分”可以是碳化硅衬底的没有分离区域并且围绕分离区域的部分。例如，分离区域可以具有与碳化硅衬底的其余部分不同的带隙（例如较低的带隙）。
或者，分离区域可以由与碳化硅衬底的其余部分相同的材料制成。在后一种情况下，可以仅通过将激光辐射聚焦到碳化硅衬底内的明确限定的区域来限定分离区域。
在一个示例中，可以通过将离子注入到碳化硅衬底中来创建分离区域。离子可以直接导致更高的吸收，例如由于离子处的更高吸收率，和/或可以导致碳化硅衬底的晶体结构转换成不同的多型（例如，从4H-SiC到3C-SiC）和/或不同的结晶度，使得激光辐射的吸收系数在分离区域中增加。例如，分离区域中的吸收系数可以是碳化硅衬底的其余部分中的至少5倍例如至少20倍或至少100倍那么高。
激光辐射可以处于非谐振体制，使得分离区域中的单光子过程的概率基本上为零，并且可能只必须考虑多光子过程（例如多光子吸收）。例如，如果分离区域的带隙是激光辐射的光子能量的至少两倍（通常至少十倍），则可以实现非谐振体制。在非谐振体制中例如通过将激光辐射聚焦到明确限定的区域来施加激光辐射可以导致创建穿孔平面（其可以对应于分离区域）。在这种情况下，激光辅助分离方法也可以称为激光调节。在穿孔平面内，与碳化硅衬底的其余部分相比，可以增加热机械应力，因此，例如通过向碳化硅衬底施加机械力和/或热应力简化了碳化硅衬底的分离。
作为替代，激光辐射可以处于谐振体制，其中单光子过程（例如单光子吸收）占主导地位，即多光子过程的概率很小（例如，是单光子过程的概率的至少十分之一那么小）。在谐振体制中，分离区域的带隙可以例如是激光辐射的光子能量的至多十倍（通常至多两倍）。激光辐射可以在分离区域中被吸收并且可以导致分离区域的损坏，使得分离碳化硅衬底不需要或仅需要很小的机械力和/或热应力。在谐振体制中，激光辅助分离方法也可以称为激光剥离。
根据实施例，在结构上连接辅助结构和后侧金属化之前，可以形成后侧分离沟槽，其从后侧延伸到碳化硅衬底中。后侧分离沟槽可以进一步延伸穿过后侧金属化。半导体管芯的半导体部分的分离和辅助结构的切割可以彼此独立地执行，使得每个切割过程可以适于材料的要求。
根据实施例，金属盘可以包括从金属盘的顶表面延伸到金属盘中的沟槽。沟槽可以是栅格形的。金属盘的顶表面可以与后侧金属化连接。
切割过程可以避免切割穿过金属盘。作为代替，作为例如研磨或机械抛光的平面凹陷过程可以完成切割过程。
根据另一实施例，半导体器件可以包括碳化硅主体。半导体器件还包括碳化硅主体的前侧处的第一负载电极和碳化硅主体的后侧处的第二负载电极。金属板可以与第二负载电极接触。金属板的厚度可以是至少30μm，例如至少50μm或至少80μm，并且至多300μm，例如至多200μm或至多180μm。金属板的厚度可以是（已经变薄的）碳化硅衬底的厚度的至少20％并且至多200％。负载端子可以与金属板接触。
金属板可以对应于金属盘或辅助结构或者用本文所述方法的实施例描述的辅助结构的金属部分。
金属板包括金属或金属合金作为主要材料。例如，金属板由作为主要材料的金属或金属合金组成。在此和在下文中，“由”材料或材料成分“组成”的组件将被解释为使得在所述组件中可以存在其他材料的不期望的杂质（这例如由于制造条件导致）。
当半导体器件的半导体管芯是晶片组装件的一部分时并且在将半导体管芯连接到引线框架之前，金属板可以在制造阶段处稳定化碳化硅主体。金属板进一步有助于器件表征，并且可以用于向碳化硅主体中引起机械应变，以改善电器件特性。根据其他实施例，半导体器件可以包括来自另一种宽带隙材料的主体，诸如氮化镓(GaN)、氮化铝(AlN)或氧化镓(Ga2O3)。
根据实施例，碳化硅主体可以包括第一掺杂区和第二掺杂区，其中第一掺杂区和第二掺杂区可以形成pn结。第一负载电极可以与第一掺杂区接触。第二负载电极可以与第二掺杂区接触。
根据实施例，金属板的厚度可以大于第一负载电极和第二负载电极之间的碳化硅主体的厚度。厚金属板可以简化薄半导体器件（例如具有薄于180μm的碳化硅主体的半导体器件）的处理，并且降低在后端过程期间削片和形成裂缝的风险。
根据实施例，第二负载电极可以包括镍、钛、钽、钼和铝中的一种，并且金属板可以包括钼和铜中的至少一种，其中金属板和第二负载电极可以通过烧结、扩散焊接和直接接合以不会不利地影响先前形成的结构的方式连接。
根据实施例，半导体器件可以包括横向围绕金属板的非金属框架结构。非金属框架结构可以促进半导体器件与晶片组装件的简单、可靠和成本有效的分离。
在方法和/或半导体器件的至少一些实施例中，以下特征（如果适用）单独或组合地应用：
（i）器件区域由空闲区域（特别是栅格形的空闲区域）横向分离；
（ii）每个金属部分与器件区域中的确切一个接触；
（iii）辅助结构形成用于碳化硅衬底的机械稳定化载体；
（iv）金属盘形成用于碳化硅衬底的机械稳定化载体；
（v）碳化硅衬底由单件形成；
（vi）半导体器件是功率半导体器件；
（vii）碳化硅主体的厚度为至多180μm；
（viii）辅助结构的一个金属部分形成半导体器件的金属板；
（ix）金属盘的一部分形成半导体器件的金属板；
（x）辅助结构和/或辅助结构的金属部分和/或金属盘和/或金属板的厚度为至少30μm和/或至多300μm。
在下文中，结合附图详细解释在此描述的方法和半导体器件的其他实施例。
遍及附图的描述，术语“工件”表示具有前侧金属化的碳化硅衬底的混合物，其中工件可以包括其他组件，诸如例如后侧金属化。本领域技术人员应当理解，前侧金属化可以在任何其他结构（例如，后侧金属化、辅助结构和/或金属盘）提供在碳化硅衬底的后侧处之前或之后附接到碳化硅衬底。
图1示出了制造半导体器件的方法。提供(902)工件，其可以包括碳化硅衬底和碳化硅衬底的前侧处的前侧金属化。工件包括多个器件区域和横向分离器件区域的空闲区域。辅助结构提供在工件的后侧处(904)。辅助结构包括多个横向分离的金属部分。每个金属部分与器件区域之一接触。
图2A-2B涉及一种方法，该方法包括形成具有横向分离的金属部分810的辅助结构。
图2A示出了工件600，其中工件600包括碳化硅衬底700和碳化硅衬底700的前侧处的前侧金属化610。其他实施例可以涉及具有基于另一宽带隙半导体材料（例如GaN、AlN或Ga2O3）的衬底的工件600。
碳化硅衬底700可以是扁平盘，其具有与标准晶片尺寸的直径对应的直径，例如，2英寸(51mm)、3英寸(76mm)、4英寸(100mm)、125mm、或200mm。碳化硅衬底700可以基于包括硅和碳作为主要成分的碳化硅晶体。碳化硅晶体可以包括其他材料，例如，由于材料和过程缺陷的无意杂质和/或有意的添加物。无意的杂质可以包括碳和/或氧。有意的添加物可以包括氢和/或掺杂剂原子，例如氮(N)、磷(P)、铍（Be）、硼(B)、铝(Al)和/或镓(Ga)。在碳化硅衬底700的前侧处的主表面701上的表面法线704限定垂直方向。正交于表面法线704的方向是横向或水平方向。
在主表面701和碳化硅衬底700的后侧表面702之间的碳化硅衬底700的厚度th1可以等于或小于相同直径的标准晶片的厚度。例如，厚度th1可以小于180μm，小于110μm，小于90μm，或者至多70μm。
工件600可以包括另外的结构和/或元件，例如，与碳化硅衬底700的后侧表面702接触的后侧金属化620。可以在前侧金属化610的部分和碳化硅衬底700的部分之间形成层间电介质605。钝化结构可以覆盖前侧金属化610和/或层间电介质605的边缘部分。
辅助载体可以形成在工件600的前侧处。辅助载体可以包括主载体（诸如例如，玻璃载体或半导体晶片，诸如硅晶片）和将主载体接合到工件600的前侧的粘合剂层。
工件600包括多个器件区域650和栅格形空闲区域660。器件区域650可以布置成行和列的矩阵。空闲区域660横向分离器件区域650。每个器件区域650可以包括形成在碳化硅衬底700中的多个掺杂区。
例如，每个器件区域650可以包括第一掺杂区120（例如发射极区）以及第二掺杂区130（例如漂移结构）。第一掺杂区120和第二掺杂区130可以形成pn结pn。
第一掺杂区120和前侧金属化的一部分可以形成低电阻欧姆接触。然而，在其他实施例中，前侧金属化可以与碳化硅衬底的至少一个掺杂区形成肖特基接触。第一掺杂区120（例如体现为发射极区）可以包括功率半导体二极管的阳极区，或者可以包括IGFET（例如MOSFET）、MCD(MOS控制的二极管)或IGBT（绝缘栅双极晶体管）的体区。
漂移结构和后侧金属化620的一部分可以形成低电阻欧姆接触。漂移结构可以包括轻掺杂的漂移层，其中选择漂移层中的厚度和掺杂剂浓度以适应给定的阻断电压。
空闲区域660可以包括碳化硅衬底700的一部分和后侧金属化620的一部分。前侧金属化610可以是连续结构或者可以包括多个分离的金属化部分，其中每个金属化部分形成在器件区域650的一个中。
后侧金属化620可以包括包含一种或多种主要成分的一个层，或者可以包括两个或更多个子层，其中子层具有不同的主要成分。例如，后侧金属化620可以包括镍层、银层、硅化镍层、钛层和/或铝层。
后侧金属化620的厚度th2可以在200nm至5000nm的范围内。后侧金属化620可以通过溅射、电镀和/或气相沉积而沉积在碳化硅衬底700上。后侧金属化620可以包括具有多个层的层堆叠。每个层可以由金属或金属合金组成。后侧金属化620的最外层（即，形成后侧金属化620的外表面的层）可以由Cu或AuSn组成，或者可以包括这些材料。在沉积后侧金属化620之后，可以例如经由化学机械抛光(CMP)平坦化后侧金属化620。这可以导致关于到后侧金属化620的线接合（例如到最外层的线接合）的改善表面质量。
辅助结构800提供在工件600的后侧处。辅助结构800可以预制，然后与工件600结构上连接，例如通过接合、烧结和/或扩散焊接。或者，辅助结构800可以逐步地直接在工件600的后侧表面602上形成。
图2B示出了包括工件600和辅助结构800的晶片组装件。辅助结构800的顶表面801与工件600的后侧表面602直接接触，其中后侧表面602可以包括后侧金属化620的暴露表面。
辅助结构800包括多个金属部分810。金属部分810可以包括铜、银、钨和钼中的至少一种作为（一种或多种）主要成分。在典型的实施例中，可以使用铜或钼。沿着顶表面801的金属部分810的至少一部分可以包括烧结膏的原子和/或扩散焊料的原子。
相邻金属部分810之间的中心到中心距离p2可以等于相邻器件区域650之间的中心到中心距离p1。金属部分810的厚度th3可以在30μm至200μm的范围内，例如，在80μm至120μm的范围内。
栅格形分离结构820可以使金属部分810彼此横向分离。分离结构820可以包括空隙和/或可以包括导电或介电辅助材料。根据实施例，分离结构820可以包括例如玻璃、树脂和/或硅。
在图2B的晶片组装件中，辅助结构800可以机械稳定化超薄碳化硅衬底700，并且同时可以有助于使工件600的两侧上的导电结构与电探针电接触，例如以用于器件表征的电测试。
图3A至4C涉及具有预制辅助结构800的实施例。例如，辅助结构800可以形成有栅格形沟槽805，其从辅助结构800的顶表面801延伸到辅助结构800中。具有栅格形沟槽805的辅助结构800可以通过使用适当的模具模制而形成。或者，沟槽805可以例如通过蚀刻和/或锯切而形成在扁平金属盘的顶表面801中。
图3A示出了具有横向分离的金属部分810的预制辅助结构800。连续金属基部819可以连接金属部分810并且可以将金属部分810保持在它们相对于彼此的位置处。
包括直接接合、扩散焊接和烧结中的至少一种的过程将金属部分810的顶表面与工件600的后侧表面602（例如与后金属化620）机械连接。
图3B所示的晶片组装件包括参考前面的附图描述的工件600和图3A的预制辅助结构800。器件表征可以电探测碳化硅衬底700。
切割过程可以沿着空闲区域660中的分离线来分离器件区域650，其中与晶片组装件分离的每个器件区域650形成单个半导体器件的半导体管芯。切割过程可以包括用于垂直切穿碳化硅衬底700和后侧金属化620两者的切断或锯切过程。
或者，切割过程可以包括凹陷过程，其例如通过研磨、蚀刻和/或通过化学机械抛光来去除连续金属基部819，其中可以在切穿工件600之前或之后去除连续金属基部819。如果在切穿工件600之后去除连续金属基部819，则可以在去除连续金属基部819之前将可逆载体（例如，带，诸如研磨带）接合和/或粘附到工件600的前侧。或者，组合的锯切过程可以切穿工件600和辅助结构800的连续金属基部819两者。
在图4A-4C中，通过在辅助基部840的顶表面801中形成多个横向分离的沟槽845来预制辅助结构800。
图4A示出了辅助基部840，其具有从顶表面801延伸到辅助基部840中的分离的沟槽845。辅助基部840的材料可以示出针对金属部分810的高蚀刻选择性和/或可以在机械切割过程的过程中容易切穿。辅助基部840包括连续部分842和在顶表面801和连续部分之间的矩阵部分841。矩阵部分841形成栅格并横向分离沟槽845。
金属可以沉积在辅助基部840的前侧上。金属的沉积可以包括电流沉积或使用刮板（德国：Rakel）的涂覆。包括辅助基部840的辅助结构800通过直接接合、扩散焊接或烧结机械地连接800在工件600的后侧602上（例如在后侧金属化620上）。
图4B示出了晶片组装件，其包括如参考图2A和2B所述的工件600和辅助结构800。辅助结构800包括图4A中的辅助基部840和图4A的辅助基部840的分离的沟槽845中沉积的金属所形成的金属部分810。可以去除辅助基部840的连续部分842。
图4C示出了在去除连续部分842之后的晶片组装件。辅助结构800包括金属部分810和由图4B的矩阵部分841形成的分离结构820。晶片组装件允许器件表征和切割，其中辅助结构可以永久地稳定化碳化硅衬底700。
图5A至5C示出了在工件600的后侧表面602上逐步形成辅助结构800。
图5A示出了参照图2A描述的工件600。栅格形分离结构820可以形成在工件600的后侧表面602上。形成分离结构820可以包括印刷过程或光刻过程。例如，可以将酰亚胺、树脂（例如环氧树脂）或BCB印刷（例如模版印刷）到工件后侧表面602上。或者，可以在后侧表面602上沉积诸如抗蚀剂层或玻璃层的层，并且光刻过程可以图案化沉积的层以从沉积的层的部分形成分离结构820。
如图5B所示，分离结构820可以形成包括开口825的矩阵。每个开口825暴露至少大部分，例如一个器件区域650的至少90％。每个器件区域650可以由一个开口825暴露。每个器件区域650可以完全暴露。
金属部分810可以形成在分离结构820的开口825中。例如，金属膏可以用刮板涂覆，其中可以去除过量的金属膏。烘烤过程可以干燥金属膏以形成固体金属膏。替代地或另外地，形成金属部分810可以包括印刷过程或金属的电化学或无电沉积。
图5C示出了在形成辅助结构800之后的晶片组装件，其包括在图4B的开口825中的金属部分810和分离结构820。晶片组装件允许在工件600的前侧和后侧两者处电探测。相对简单的过程可以以高选择性针对金属部分810去除分离结构820，或者可以容易地切穿分离结构820，使得辅助结构800可能仅对切割过程的复杂性具有低影响。
图6A-6J图示了制造半导体器件的方法，其中该方法组合使用如参考图2A-5C所述的辅助结构800与晶片分割方法。
可以处理可以具有标准碳化硅晶片的直径和厚度的碳化硅衬底700，其中电子组件的掺杂区形成在碳化硅衬底700中。
根据实施例，分离区域750可以形成在碳化硅衬底700中。分离区域750可以是损坏层。例如，可以通过主表面701或通过碳化硅衬底700的后侧表面702将离子（例如，N、V、B、Ar、C、Ni、Si、Ti、Ta、Mo、W和/或Al）注入到碳化硅衬底700中。可以将离子注入在碳化硅衬底700的碳化硅晶片中。注入的离子可以损坏和/或导致注入的末端峰周围的薄层中的碳化硅衬底700的晶格的改变。例如，由于离子的注入，分离区域750中的碳化硅衬底700的多型的至少一部分可以例如从4H-SiC变为3C-SiC。分离区域750可以具有比碳化硅衬底700的周围其余部分更高的吸收系数。吸收系数可以是针对要施加到碳化硅衬底700的激光辐射的波长的吸收系数。分离区域750可以具有至少30nm通常至少100nm并且至多1.5μm通常至多500nm的厚度。
在去除分离区域750之前或之后，可以通过注入掺杂原子来形成第一掺杂区120。在一个示例中，可以在去除碳化硅衬底700的层部分之后形成第一掺杂区750。
图6A示出了到主表面701距离dp1处的分离区域750。距离dp1可以大于最终化半导体器件的半导体主体的厚度。在该示例中，多个第一掺杂区120形成在主表面701和分离区域750之间。然而，在未在图6A中示出的其他示例中，可以在去除分离区域750下方的碳化硅衬底700的层部分之后形成多个第一掺杂区120。
层间电介质605和前侧金属化610可以形成在碳化硅衬底700的前侧处的主表面701上。前侧金属化610可以与碳化硅衬底700中的第一掺杂区120接触。层间电介质605的部分可以形成在主表面701和前侧金属化610的部分之间。可以形成钝化结构615。钝化结构615可以覆盖前侧金属化610的边缘。
图6B示出了包括碳化硅衬底700和可以至少包括前侧金属化610、层间电介质605和钝化结构615的前侧构造的工件600。工件600可以包括多个器件区域650，其中每个器件区域650包括相同的掺杂区图案和相同的前侧构造。空闲区域660横向地分离器件区域650。在主表面701的平面图中，空闲区域660可以是栅格形的，并且器件区域650可以形成在栅格形空闲区域660的矩形网格中。
根据与研磨前切割方法相关的实施例，可以在空闲区域660中形成前侧分离沟槽705。前侧分离沟槽705的宽度可以等于或小于空闲区域660的宽度。前侧分离沟槽705的深度dp2可以等于或大于最终化半导体器件的半导体主体的厚度。作为示例，形成前侧分离沟槽705可以包括蚀刻过程、机械锯切过程或基于激光的锯切过程。
前侧分离沟槽705可以暴露分离区域750，或者可以形成为使得前侧分离沟槽705不暴露分离区域750。
图6C示出了从主表面701延伸到碳化硅衬底700中的前侧分离沟槽705。在所示实施例中，前侧分离沟槽705的深度dp2小于主表面701和分离区域750之间的距离dp1。
辅助载体680可以附接到工件600的前侧。例如，粘合剂层681可以在工件600的前侧处粘附接合主载体682。粘合剂层681可以由临时接合/剥离粘合剂形成。例如，液体胶可以施加到前侧上，其中胶可以填充前侧分离沟槽705。预烘烤可以干燥胶和/或去除溶剂。可以使主载体682与干燥的胶的暴露顶表面进行接触。干燥的胶可以例如通过用紫外线辐射照射来固化以形成粘合剂层681。根据另一个示例，粘合剂层681可以是粘合剂带，其粘附接合主载体682和工件600。
图6D示出了粘合剂层681和主载体682。主载体682可以是或可以包括透明或不透明的支撑物（例如玻璃载体或硅晶片）。粘合剂层681可以包括固化的粘合剂材料，其中粘合剂材料可以是在辐射下可固化的，例如，在紫外线辐射下。例如，粘合剂层可以包括丙烯酸酯聚合物、合成橡胶和/或硅氧烷。
例如，可以通过晶片分离方法（通常是使用分离区域750的激光辅助分离方法）来减小碳化硅衬底700的厚度。例如，可以将（例如具有至少300nm并且至多600nm的波长的）激光辐射施加到碳化硅衬底700。激光辐射可以在分离区域750中至少部分地被吸收，从而导致分离区域750的至少一部分的分解和/或破坏。然后，可以通过向碳化硅衬底700施加机械力和/或应力来分离碳化硅衬底700。
另外或作为替代，加热处理可以引起注入离子的重新分配，其中小孔可以在分离区域750中形成，并且适度的机械力可以沿着水平面通过分离区域750分离层部分。
根据另一实施例，可以对碳化硅衬底700进行研磨或化学机械抛光，其中可以省略形成分离区域750。
图6E示出了具有减薄的碳化硅衬底700的晶片组装件，其可以包括图6D的分离区域750的剩余部分751。可以继续碳化硅衬底700的后侧处理。后侧处理可以包括机械抛光，其去除分离区域750的剩余部分751并且可以暴露前侧分离沟槽705。
在前侧分离沟槽705的深度dp2足够小使得分离区域750的剩余部分751的去除不暴露前侧分离沟槽705的情况下，后侧处理可以不受前侧分离沟槽705中的粘合剂材料的影响。
后侧处理可以包括沿着碳化硅衬底700的后侧表面702形成重掺杂接触部分139，其中接触部分139中的掺杂剂浓度足够高以形成与金属的欧姆接触。例如，镍硅化物或镍和硅的混合物可以沉积在碳化硅衬底700的后侧表面702上，并且热处理可以将沉积的镍和硅原子转变为重掺杂接触部分139。根据另一实施例，注入过程可以沿着碳化硅衬底700的后侧表面702形成掺杂层，其中热处理可以通过在碳化硅晶体的晶格位置处融入注入的原子来激活注入的掺杂剂。
热处理可以包括碳化硅衬底700的后侧表面702的局部照射，使得先前形成在碳化硅衬底700的前侧处的结构可以保持不受影响。在热处理之前或之后，可以在碳化硅衬底700的后侧表面702上形成后侧金属化620，以形成接触部分139。
在图6F中所示的晶片组装件中，工件600包括通过后侧金属化620连接的多个半导体管芯950，其中每个半导体管芯950包括与完整的后侧结构结合的图6E的器件区域650的所有特征。完成的后侧结构可以包括重掺杂接触部分139和后侧金属化620的一部分。辅助载体680和连续后侧金属化620将半导体管芯950保持在图6E的器件区域650的位置处。
根据参考图2A至5C详细描述的任何实施例，辅助结构800提供在工件600的后侧表面602上。
例如，可以将包括银和/或铜的烧结膏施加到辅助结构800的顶表面801或工件600的后侧表面602中的至少一个。烧结膏可以被烘烤使得烧结膏失去其溶剂。可以使辅助结构800的顶表面801与工件600的后侧表面602接触。
预烧结可以充分地临时稳定化辅助结构800和工件600之间的机械连接，使得辅助载体680可以从前侧去除，而辅助结构800不会与工件600分离。
如图6G所示，辅助结构800与工件600的后侧表面602接触。辅助结构800可以包括横向分离多个金属部分810的分离结构820。每个金属部分810与器件区域650之一直接接触。
激光可以局部加热粘合剂层681以从工件600去除主载体682。可以将耐温直到至少270℃的温度的保护箔690施加到工件600的前侧。
图6H示出了工件600的前侧处的保护箔690。作为示例，保护箔690可以包括含有Kapton®和/或聚四氟乙烯(PTFE)的层。作为示例，烧结过程可以在200℃至270℃的范围内的温度处完成。在完成烧结之后，可以去除保护箔690。
图6I示出了在去除保护箔之后晶片组装件准备用于器件表征和切割。切割过程可以包括利用锯切刀片的锯切过程或通过分离结构820的激光辅助切断。
图6J示出了从图6I的晶片组装件获得的多个半导体管芯950。每个半导体管芯950可以包括由图6A的碳化硅衬底700的一部分形成的碳化硅主体100、由图6G的金属部分810获得的金属板、以及从图6G的分离结构820的剩余部分获得的框架结构350。框架结构350可以横向围绕金属板340。
图7示出了制造半导体器件的方法。提供工件(912)。工件可以包括碳化硅衬底、碳化硅衬底的前侧处的前侧金属化和碳化硅衬底的后侧处的后侧金属化。可以提供金属载体(914)。可以连接金属载体和后侧金属化(916)。
图8A-8C图示了制造半导体器件的方法，其中金属盘(809)可以在器件表征和切割期间稳定化碳化硅衬底。
图8A示出了工件600，其包括碳化硅衬底700、前侧处的前侧金属化和碳化硅衬底的后侧处的后侧金属化620。关于进一步的细节，参考对图2A的工件的描述。
图8B示出了辅助结构800，其至少包括金属盘809。金属盘809的直径可以与工件600的直径大致相同。金属盘809的厚度th4可以在30μm至300μm的范围内，例如，在80μm至120μm的范围内。金属盘809可以仅包括铜、银、钨或钼作为主要成分。根据其他实施例，金属盘809可以包括铜合金，例如其主要成分是铜和铝的铜合金，或者其主要成分是铜、铝和硅的铜合金。
图8B的金属盘809和图8A的工件600的后侧金属化620通过烧结、扩散焊接、反应接合和直接接合中的至少一种机械连接。
图8C示出了包括图8A的工件600和图8B的金属盘809的晶片组装件。直接邻接后侧金属化620的金属盘809的一部分和/或直接邻接金属盘809的后侧金属化620的一部分可以形成过渡层885。过渡层885可以包括扩散焊料的原子和/或烧结膏的原子。
图9A-9D图示了制造半导体器件的方法，其将金属盘809与来自后侧的半导体管芯的预切割结合。
可以提供具有工件600和接合在工件600的前侧上的辅助载体680的晶片组装件。例如，可以根据参考图6A-6F描述的过程形成晶片组装件，其中可以省略如图6C所示的前侧分离沟槽705的形成。
图9A示出了工件600的前侧处的辅助载体680。工件600包括碳化硅衬底700、前侧金属化610和后侧金属化620。关于进一步的细节，参考图6A-6F的描述。后侧分离沟槽706可以例如通过锯切形成在工件600的空闲区域660中。
图9B示出了从后侧表面602延伸到工件600中的后侧分离沟槽706。例如，后侧分离沟槽706可以延伸直到粘合剂层681。后侧分离沟槽706可以将器件区域650彼此完全分离。
辅助结构800和工件600被连接。辅助结构800可以包括金属盘809。金属盘809可以通过直接接合、扩散焊接和/或烧结与后侧金属化620连接。
图9C示出了包括辅助载体680、横向分离的器件区域650和金属盘809的晶片组装件。可以去除辅助载体680。
图9D示出了在去除辅助载体680之后的金属盘809和器件区域650。金属盘809将器件区域650保持在图9C的碳化硅衬底700中具有的器件区域650的位置处。横向分离的器件区域650可用于电探测和器件表征。
可以通过选择性地影响金属盘809的过程从晶片组装件切断半导体管芯，使得可以高度避免半导体管芯950的碳化硅主体100中的削片和裂缝的形成。
在图10中，辅助载体680包括来自刚性材料的环部分686，其可以沿着工件600的边缘热接合。环部分686可以在器件区域外与工件600接触。辅助载体680可以包括固定在环部分686的顶表面687上的盖部分688。环部分686和/或盖部分688可以包括玻璃。多孔材料可以至少部分地填充盖部分688和工件600之间的空间。辅助载体680可以在没有粘合剂层的情况下使用，并且可以通过例如局部热退火以简单和保守的方式从工件600剥离。
图11和12示出了半导体管芯和半导体器件的示例性实施例，其可以用结合图1、2A-2B、3A-3C、4A-4C、5A-5C、6A-6J、7、8A-8C、9A-9D和10的实施例描述的方法制造。反之，图1、2A-2B、3A-3C、4A-4C、5A-5C、6A-6J、7、8A-8C、9A-9D和10示出了制造半导体器件的方法的示例性实施例，其中半导体器件可以是如本文所述（特别是结合图11和12的实施例）的半导体器件。
图11的半导体管芯950可以是功率半导体器件的半导体管芯，其可以用作功率电子器件中的开关或整流器。例如，功率半导体器件可以是半导体二极管。根据实施例，半导体管芯950可以包括并联电布置的多个基本相同的晶体管单元。例如，半导体管芯可以是HEMT（高电子迁移率晶体管）；IGFET（绝缘栅场效应晶体管），例如MOSFET（金属氧化物半导体FET）；JFET（结FET）；合并引脚肖特基二极管(MPS二极管)；IGBT（绝缘栅双极晶体管）或MCD(MOS控制二极管)或它们的组合。
半导体管芯950可以包括基于4H-SiC(4H多型碳化硅)的碳化硅主体100。可以在碳化硅主体100中形成多个掺杂区。例如，碳化硅主体100可以包括第一掺杂区120和第二掺杂区130。第一掺杂区120可以包括发射极区，其中发射极区可以包括功率半导体二极管的阳极区，或者可以包括场效应晶体管单元的体区。第一掺杂区120和第二掺杂区130可以形成pn结pn。可以沿着碳化硅主体100的后侧处的第二表面102形成重掺杂接触部分139。
在碳化硅主体100的前侧处的第一表面101上，层间电介质605可以将前侧金属化610的部分与碳化硅主体分离。前侧金属化610的至少一部分可以与第一掺杂区120（例如发射极区）接触。前侧金属化610可以包括栅极焊盘330和可以包括源极焊盘的第一负载电极310。
钝化结构615可以包括覆盖前侧金属化610的垂直边缘的层。钝化结构615可以包括例如玻璃、聚酰亚胺、DLC（金刚石类碳）和/或氮化硅。后侧金属化620可以形成第二负载电极320的一部分，例如，漏电极。第二负载电极320和接触部分139可以形成欧姆接触。碳化硅主体100的厚度t1可以小于110μm，例如，至多90μm。金属板340与后侧金属化620接触。金属板340的厚度可以在30μm至300μm的范围内，例如从80μm至120μm。
与后侧金属化620直接接触的金属板340的一部分和/或与金属板340直接接触的后侧金属化620的一部分可以形成过渡区域385。过渡区域385可以包括如上所述的扩散焊料的原子和/或烧结膏的原子。非金属框架结构350可以横向围绕金属板340并且可以与后侧金属化620直接接触。框架结构350可以包括晶体硅、玻璃或树脂，或由晶体硅、玻璃或树脂组成。
图12示出了半导体器件500，其可以包括如图11所示的半导体管芯950。半导体管芯950的漏电极320可以与负载端子（例如，与漏极端子972）在结构上连接且电连接。例如，漏电极320可以焊接到漏极端子972上。漏极端子972的横向水平区域可以显著大于半导体管芯950的水平截面积。漏极端子972的厚度可以在200μm至2000μm的范围内。
第一负载电极310可以与另一个负载端子（例如源极端子971）电连接，例如通过接合线975或金属夹。另一接合线可以将栅极焊盘330与栅极端子电连接。漏极端子972、源极端子971和栅极端子可以共面布置，并且可以是引线框架的分离部分。模具主体974可以封装接合线975、半导体管芯950和部分的栅极端子、漏极端子972和源极端子971。
尽管这里已经说明和描述了特定实施例，但是本领域普通技术人员应当理解，在不脱离本公开的范围的情况下，可以用各种替换和/或等同的实现来代替所示出和描述的特定实施例。本申请旨在覆盖本文所讨论的具体实施例的任何改编或变化。因此，本公开旨在仅由权利要求及其等同物限制。

Claims (22)

1.一种制造半导体器件的方法，包括：
提供具有多个器件区域(650)的碳化硅衬底(700)；
在碳化硅衬底(700)的前侧处提供前侧金属化(610)；和
在碳化硅衬底(700)的后侧处提供辅助结构(800)，其中辅助结构(800)包括多个横向分离的金属部分(810)，并且其中每个金属部分(810)与器件区域(650)之一接触。
2.根据前一权利要求所述的方法，其中所述碳化硅衬底(700)包括横向分离所述器件区域(650)的栅格形的空闲区域。
3.根据前述权利要求中任一项所述的方法，其中，提供辅助结构(800)包括：
提供辅助结构(800)，和
结构上连接辅助结构(800)的顶表面(801)与碳化硅衬底(700)的后侧表面(602)。
4.根据前述权利要求中任一项所述的方法，其中，
辅助结构(800)包括具有栅格形沟槽(805)的金属盘(809)，并且其中栅格形沟槽(805)从辅助结构(800)的顶表面(801)延伸到金属盘(809)中，并且使金属部分(810)彼此横向分离。
5.根据前述权利要求中任一项所述的方法，其中，提供辅助结构(800)包括：
提供辅助基部(840)，其具有从辅助结构(800)的顶表面(801)延伸到辅助基部(840)中的横向分离的沟槽(845)，并且在分离的沟槽(845)中形成金属部分(810)。
6.根据权利要求3所述的方法，其中，结构上连接辅助结构(800)的顶表面(801)与碳化硅衬底(700)的后侧表面(602)包括以下中的至少一个：
烧结、扩散焊接和直接接合。
7.根据前述权利要求中任一项所述的方法，其中，在碳化硅衬底(700)的后侧处提供辅助结构(800)包括：
在碳化硅衬底(700)的后侧处形成分离结构(820)，其中分离结构(820)中的开口(825)暴露器件区域(650)；和
在开口(825)中形成金属部分(810)。
8.根据前述权利要求中任一项所述的方法，还包括：
将碳化硅衬底(700)和辅助结构(800)分成半导体管芯(950)，其中每个半导体管芯(950)包括器件区域(650)之一和金属部分(810)之一。
9.一种制造半导体器件的方法，包括：
提供碳化硅衬底(700)，
在碳化硅衬底(700)的前侧处提供前侧金属化(610)，并且在碳化硅衬底(700)的后侧处提供后侧金属化(620)；
提供金属盘(809)；和
结构上连接金属盘(809)和后侧金属化(620)。
10.根据前一权利要求所述的方法，还包括：
在结构上连接金属盘(809)之前，在碳化硅衬底(700)的前侧处形成辅助载体(680)，以及
在形成辅助载体(680)之后并且在结构上连接金属盘(809)和后侧金属化(620)之前，减小碳化硅衬底(700)的厚度。
11.根据前一权利要求所述的方法，其中
辅助载体(680)包括环部分(686)。
12.根据前两项权利要求中任一项所述的方法，还包括：
在形成辅助载体(680)之前，形成从前侧延伸到碳化硅衬底(700)中的前侧分离沟槽(705)。
13.根据前三项权利要求中任一项所述的方法，其中减小碳化硅衬底(700)的厚度包括：
分离碳化硅衬底(700)的层部分。
14.根据前一权利要求所述的方法，其中所述分离包括以下步骤：
将离子注入到碳化硅衬底(700)中以在碳化硅衬底(700)中形成分离区域(750)，其中分离区域(750)中的吸收系数是分离区域(750)之外的碳化硅衬底(700)中的吸收系数的至少5倍那么高；和
用激光辐射照射碳化硅衬底(700)。
15.根据前五项权利要求中任一项所述的方法，还包括：
在结构上连接之前，形成从后侧延伸到碳化硅衬底(700)中的后侧分离沟槽(706)。
16.根据前六项权利要求中任一项所述的方法，其中，
金属盘(809)包括从金属盘的顶表面(801)延伸到金属盘(809)中的栅格形沟槽(805)，并且其中顶表面(801)在结构上与后侧金属化(620)连接。
17.一种半导体器件，包括：
碳化硅主体(100)；
在碳化硅主体(100)的前侧处的第一负载电极(310)；
在碳化硅主体(100)的后侧处的第二负载电极(320)；
金属板(340)，与第二负载电极(320)接触，其中金属板(340)的厚度为至少30μm且至多300μm；和
负载端子(972)，与金属板(340)接触。
18.根据前一权利要求所述的半导体器件，其中
碳化硅主体(100)包括第一掺杂区(120)和第二掺杂区(130)，第一掺杂区(120)和第二掺杂区(130)形成pn结(pn)，
第一负载电极(310)与第一掺杂区(120)接触，并且
第二负载电极(320)与第二掺杂区(130)接触。
19.根据前两项权利要求中任一项所述的半导体器件，其中，
金属板(340)的厚度大于第一负载电极(310)和第二负载电极(320)之间的碳化硅主体(100)的厚度。
20.根据前三项权利要求中任一项所述的半导体器件，其中，
第二负载电极(320)包括镍、钛、钽和铝中的至少一种。
21.根据前四项权利要求中任一项所述的半导体器件，其中，
金属板(340)包括钼和铜中的至少一种。
22.根据前五项权利要求中任一项所述的半导体器件，还包括：
横向围绕金属板(340)的非金属框架结构(350)。
CN201910594096.1A 2018-07-03 2019-07-03 半导体器件和制造半导体器件的方法 Pending CN110676165A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102018116051.8 2018-07-03
DE102018116051.8A DE102018116051A1 (de) 2018-07-03 2018-07-03 Halbleitervorrichtung und verfahren zum herstellen einer halbleitervorrichtung

Publications (1)

Publication Number Publication Date
CN110676165A true CN110676165A (zh) 2020-01-10

Family

ID=68943474

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910594096.1A Pending CN110676165A (zh) 2018-07-03 2019-07-03 半导体器件和制造半导体器件的方法

Country Status (3)

Country Link
US (1) US11139375B2 (zh)
CN (1) CN110676165A (zh)
DE (1) DE102018116051A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102019111377A1 (de) * 2018-05-28 2019-11-28 Infineon Technologies Ag Verfahren zum Verarbeiten eines Siliziumkarbid-Wafers und ein Siliziumkarbid-Halbleiterbauelement
US11158520B2 (en) * 2019-03-11 2021-10-26 Hrl Laboratories, Llc Method to protect die during metal-embedded chip assembly (MECA) process
US11309201B2 (en) * 2020-05-14 2022-04-19 Vanguard International Semiconductor Corporation Method of forming dice and structure of die
DE102021204298A1 (de) * 2021-04-29 2022-11-03 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen eines vertikalen Leistungshalbleiterbauelements und vertikales Leistungshalbleiterbauelement
DE102021205375A1 (de) * 2021-05-27 2022-12-01 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum herstellen eines vertikalen halbleiterbauelements
DE102021205516A1 (de) 2021-05-31 2022-12-01 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum herstellen eines vertikalen halbleiterbauelements und vertikales halbleiterbauelement

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009224454A (ja) * 2008-03-14 2009-10-01 Disco Abrasive Syst Ltd 光デバイスの製造方法
US9029200B2 (en) * 2010-07-15 2015-05-12 Infineon Technologies Austria Ag Method for manufacturing semiconductor devices having a metallisation layer
CN103563075B (zh) * 2011-06-16 2016-05-18 富士电机株式会社 半导体单元及使用该单元的半导体器件
US9548332B2 (en) * 2012-04-27 2017-01-17 Apple Inc. Method of forming a micro LED device with self-aligned metallization stack
US9875935B2 (en) * 2013-03-08 2018-01-23 Infineon Technologies Austria Ag Semiconductor device and method for producing the same
US9293409B2 (en) * 2013-09-11 2016-03-22 Infineon Technologies Ag Method for manufacturing a semiconductor device, and semiconductor device
DE102015112649B4 (de) * 2015-07-31 2021-02-04 Infineon Technologies Ag Verfahren zum bilden eines halbleiterbauelements und halbleiterbauelement

Also Published As

Publication number Publication date
DE102018116051A1 (de) 2020-01-09
US20200013859A1 (en) 2020-01-09
US11139375B2 (en) 2021-10-05

Similar Documents

Publication Publication Date Title
US11139375B2 (en) Semiconductor device and method of manufacturing a semiconductor device
CN106449507B (zh) 用于形成半导体器件的方法以及半导体器件
US8803312B2 (en) Method for manufacturing semiconductor devices having a glass substrate
US10395967B2 (en) Method for manufacturing semiconductor device
US11990520B2 (en) Method of manufacturing a semiconductor device having frame structures laterally surrounding backside metal structures
US8294254B2 (en) Chip scale surface mounted semiconductor device package and process of manufacture
US9887152B2 (en) Method for manufacturing semiconductor devices having a metallisation layer
CN109585370B (zh) 包括自对准背侧导电层的半导体芯片及其制造方法
US9117801B2 (en) Semiconductor devices having a glass substrate, and method for manufacturing thereof
US10134636B2 (en) Methods for producing semiconductor devices
CN107068564B (zh) 形成半导体器件的方法
US8025783B2 (en) Method for producing a composite material, associated composite material and associated semiconductor circuit arrangements
CN114868231A (zh) 半导体元件及其制造方法、以及半导体装置及其制造方法
JP2005217012A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination