JP7042217B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7042217B2 JP7042217B2 JP2018559114A JP2018559114A JP7042217B2 JP 7042217 B2 JP7042217 B2 JP 7042217B2 JP 2018559114 A JP2018559114 A JP 2018559114A JP 2018559114 A JP2018559114 A JP 2018559114A JP 7042217 B2 JP7042217 B2 JP 7042217B2
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- semiconductor device
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- semiconductor
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Description
特許文献2に開示された、2つの縦型MOSトランジスタを有する半導体装置におけるオン抵抗の低減および反りの抑制について検討する。
[1.半導体装置の基本構造]
以下、本開示に係る半導体装置1の構造について説明する。本開示に係る半導体装置1は、半導体基板に2つの縦型MOS(Metal Oxide Semiconductor)トランジスタを形成した、CSP(Chip Size Package:チップサイズパッケージ)型のマルチトランジスタチップである。上記2つの縦型MOSトランジスタは、パワートランジスタであり、いわゆる、トレンチMOS型FET(Field Effect Transistor)である。ただし、本実施の形態に係る半導体装置1は、固体撮像装置等のオプトエレクトロニクスに分類されるものには適用されない。
ここで、本実施の形態に係る半導体装置1において、半導体装置1のオン抵抗を低減するための基本構成について説明する。
上述した比較例1および2に係る半導体装置に対して、本実施の形態に係る半導体装置1は、金属層31の半導体基板32と反対側の主面全面に接して接着層39が形成され、接着層39の金属層31と反対側の主面全面に接して、セラミック材料からなる支持体30が形成されている。
ここで、本実施の形態に係る半導体装置1のオン抵抗および反りを低減するための各層の厚さを最適化するプロセスについて説明する。
図8Aは、実施の形態1の変形例1に係る半導体装置1Aの断面図である。また、図8Bは、実施の形態1の変形例1に係る半導体装置1Aの電極構成の一例を示す上面図である。図8Aの断面図は、図8BのVIIIA-VIIIAにおける切断面を見た図である。図8Aに示すように、半導体装置1Aは、半導体基板32と、低濃度不純物層33と、金属層31と、接着層39と、支持体30と、トランジスタ10と、トランジスタ20と、を有する。図8Bに示すように、半導体装置1Aは、半導体基板32を平面視した場合、2つの第1のソース電極11、2つの第2のソース電極21、1つの第1のゲート電極19、および、1つの第2のゲート電極29を有している。トランジスタ10の上面には、トランジスタ10とトランジスタ20とが対向する方向と垂直な方向に沿って、第1のソース電極11、第1のゲート電極19、および第1のソース電極11がこの順に形成されている。また、トランジスタ20の上面には、トランジスタ10とトランジスタ20とが対向する方向と垂直な方向に沿って、第2のソース電極21、第1のゲート電極29、および第1のソース電極21がこの順に形成されている。なお、1つのトランジスタを構成するソース電極およびゲート電極の個数および配置関係は、図8Bに示されたものに限定されない。
実施の形態1に係る半導体装置1の製造方法について、図10A~10C、図11A~11B、図12A~12B、図13および図14を参照しながら説明する。ここでは「縦型」MOSFETを例にとって説明するが、他に、ダイオード、「縦型」のバイポーラトランジスタ等においても同様の効果が得られることは言うまでもない。
2 制御IC
3 電池
4 負荷
10 トランジスタ(第1の縦型MOSトランジスタ)
11 第1のソース電極
12、22 第1の部分
13、23 第2の部分
14 第1のソース領域
15 第1のゲート導体
16 第1のゲート絶縁膜
18 第1のボディ領域
19 第1のゲート電極
20 トランジスタ(第2の縦型MOSトランジスタ)
21 第2のソース電極
24 第2のソース領域
25 第2のゲート導体
26 第2のゲート絶縁膜
28 第2のボディ領域
29 第2のゲート電極
30 支持体
31 金属層
31A 第1金属層
31B 第2金属層
32、32A 半導体基板
33 低濃度不純物層
34 層間絶縁層
35 パッシベーション層
36 ガラス基板
37 仮接着剤
38 ダイシングテープ
39 接着層
40 半導体層
50 リングフレーム
61、62 切り込み部
63、64 切り込み
70 レーザー光
80、81 ダイシングブレード
Claims (14)
- フェイスダウン実装が可能なチップサイズパッケージ型の半導体装置であって、
第1導電型の不純物を含み、シリコンからなる半導体基板と、
前記半導体基板の上面に接して形成され、前記半導体基板の前記第1導電型の不純物の濃度より低い濃度の前記第1導電型の不純物を含む低濃度不純物層と、
前記半導体基板の下面に接して形成され、金属材料のみで構成された金属層と、
前記低濃度不純物層内の第1の領域に形成された第1の縦型MOSトランジスタと、
前記第1の領域と前記半導体基板の上面に沿った方向で隣接する、前記低濃度不純物層内の第2の領域に形成された第2の縦型MOSトランジスタと、を備え、
前記第1の縦型MOSトランジスタは、前記低濃度不純物層の上面に形成された第1のソース電極および第1のゲート電極を有し、
前記第2の縦型MOSトランジスタは、前記低濃度不純物層の上面に形成された第2のソース電極および第2のゲート電極を有し、
前記半導体基板は、前記第1の縦型MOSトランジスタの第1のドレイン領域および前記第2の縦型MOSトランジスタの第2のドレイン領域を共通化したドレイン領域として機能し、
前記第1のソース電極と前記第2のソース電極との間を、前記第1のドレイン領域、前記金属層、および前記第2のドレイン領域を経由して流れる双方向経路を主電流経路とし、
前記半導体基板と前記低濃度不純物層とを含む半導体層に対する前記金属層の厚さの割合は0.27より大きく、
前記半導体装置は、さらに、
前記金属層の下面に、接着層のみを介して接着された、セラミック材料からなる支持体を有し、
前記支持体の厚さをt 4 、前記接着層の厚さをt 3 とした場合、
半導体装置。 - 前記セラミック材料は、シリコンである
請求項1に記載の半導体装置。 - 前記金属材料は、銀である
請求項1または2に記載の半導体装置。 - 前記金属層の厚さは、前記半導体層の厚さより厚い
請求項3に記載の半導体装置。 - 前記支持体の厚さは、前記半導体層の厚さより薄い
請求項3に記載の半導体装置。 - 前記接着層の構成材料は、導電性材料である
請求項3に記載の半導体装置。 - 前記第1の領域と前記第2の領域との間の境界に、前記半導体装置の上面側から下面側に向けて切り込み部が形成されており、
前記切り込み部の最下端は、前記半導体基板の下面よりも前記上面側に位置する
請求項1に記載の半導体装置。 - 前記切り込み部の最下端は、前記金属層の上面と下面との間に位置する
請求項10に記載の半導体装置。 - 前記金属材料からなるバリは、前記支持体の下面から突出していない
請求項1に記載の半導体装置。 - 前記半導体層の側面と前記支持体の側面とは、同一平面に含まれる
請求項1に記載の半導体装置。 - 前記接着層の熱膨張係数は50ppm/℃以下、または、前記接着層のヤング率は5GPa以下である
請求項1に記載の半導体装置。
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