JP2009164458A - Phase change memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase change memory capable of applying a reset current to phase change film for making it amorphous without the need for making the whole device larger and the need for a complicated manufacturing process. <P>SOLUTION: The phase change memory 80 includes a phase change film 16, lower plugs 12, 13 and an insulating film 15 between the phase change film 16 and lower plugs 12, 13. At a portion where the phase change film 16 connects with lower plugs 12, 13, lower plugs 12, 13 include a first region and a second region. The thickness of the insulating film 15 on lower plugs 12, 13 in the first region is zero or thinner than that of the insulating film 15 on lower plugs 12, 13 in the second region, thereby the current can be concentrated at lower plugs in the first region. In other words, the current density increases. Due to the current density rise, the phase change film 16 can be amorphous even if the value of reset current is lowered. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory, and more particularly to a phase change memory that stores information in a nonvolatile manner by a change in resistance value caused by a phase change.

  The phase change memory uses a phase change film as a storage element. The phase change memory can store binary information depending on whether the phase change film is in a crystalline state or an amorphous state. Here, by changing the profile of heating applied to the phase change film, the phase change film becomes a crystalline state or an amorphous state. Note that a change in resistance accompanying a change in phase state is used for reading information. In addition, since the phase change state does not change at room temperature, the phase change memory can hold information in a nonvolatile manner.

  As described above, in the phase change memory, heating of the phase change film is an important factor. In particular, for amorphization, it is necessary to heat the phase change film to about 600 ° C., and the phase change film must be efficiently heated.

  Note that Non-Patent Document 1, for example, exists as conventional literature related to phase change memory.

Y. Matsui et al., 2006 IEEE, “Ta2O5 Interfacial Layer between GST and W Plug enabling Low power of phase change memories”

  However, in the phase change memory having such a configuration, a very large current is required for the amorphization. Here, the current for amorphization is referred to as a reset current. For example, although it depends on the size of the phase change film, the magnitude of the reset current needs to be several hundred μA or more, and the reset current value is compared with 20 to 30 μA required for the operation of the conventional memory. An order of magnitude larger.

  For example, when the driving semiconductor device is a MOS transistor, a large reset current can be supplied to the phase change film by increasing the gate width. However, in this case, the entire apparatus becomes large.

  Moreover, a large reset current can be supplied to the phase change film by reducing the diameter of the lower plug (which can also be grasped as the lower electrode) that electrically connects the phase change film and the lower layer structure. This is because the current density of the supplied reset current increases. However, in this case, it is necessary to make the diameter of the lower plug smaller than the process rule, and it is necessary to add complicated process steps. That is, the manufacturing process must be complicated.

  Therefore, the present invention does not require an increase in the size of the entire apparatus, and does not require a complicated manufacturing process, and can supply a reset current necessary for amorphization to the phase change film. The purpose is to provide memory.

  In one embodiment according to the present invention, the phase change memory includes a phase change film, a lower plug, and an insulating film existing between the phase change film and the lower plug. In the portion connected to the phase change film, the lower plug has a first region and a second region. The thickness of the insulating film formed on the lower plug in the first region is zero or smaller than the thickness of the insulating film formed on the lower plug in the second region.

  According to the above-described embodiment, current can be concentrated in the lower plug of the first region. That is, the current density increases. Even if the current value of the reset current is lowered due to the increase in the current density, the phase change film can be made amorphous. In other words, according to the above-described embodiment, the reset current necessary for the amorphization can be supplied to the phase change film without requiring an increase in the size of the entire semiconductor device and a complicated manufacturing process. it can.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a main configuration of a semiconductor device in which a phase conversion memory according to the present embodiment is formed. The semiconductor device 100 includes a phase change memory 80 and a memory driving MOS transistor 50 formed on the semiconductor substrate 1. In the present embodiment, the MOS transistor 50 is the NMOS transistor 50.

  As shown in FIG. 1, the phase change memory 80 includes lower plugs 12 and 13, a phase change film 16, and an upper electrode 17. Here, the lower plugs 12 and 13 function as “plugs” that electrically connect the components to each other, and also function as “lower electrodes” of the phase change memory 80. The upper surfaces of the lower plugs 12 and 13 are connected to the lower surface of the phase change film 16 via the insulating film 15. Furthermore, the phase change film 16 is electrically connected to the upper surface of the electrode region 7 (which can be grasped as a lower layer structure than the phase change film 16) constituting the NMOS transistor 50. That is, the insulating film 15 exists between the lower plugs 12 and 13 and the phase change film 16. However, it is possible to supply current to the phase change film 16 via the lower plugs 12 and 13.

  In the present invention, the lower plugs 12 and 13 have a metal two-layer structure. A barrier metal film 12 such as a titanium nitride (TiN) film, which can make ohmic contact with the electrode region 7 of the MOS transistor 50 and functions as a barrier metal, is formed on the outermost layer of the lower plugs 12 and 13. Further, a conductor 13 such as a tungsten film is formed in contact with the barrier metal film 12 at the center (inside) of the lower plugs 12 and 13.

  The phase change film 16 can change into a crystalline state and an amorphous state. The phase change memory 80 can store binary information depending on whether the phase change film 16 is in a crystalline state or an amorphous state. Here, by changing the heating profile applied to the phase change film 16, the phase change film 16 becomes a crystalline state or an amorphous state. Note that a change in resistance associated with a change in phase state of the phase change film 16 is used for reading information. Further, the phase change state of the phase change film 16 does not change at room temperature. Therefore, the phase change memory 80 can hold information in a nonvolatile manner.

As the phase change film 16, a GST film that is a chalcogenide compound phase change material can be employed. The GST film is composed of germanium (Ge), antimony (Sb), and tellurium (Te), and the crystallization temperature and the melting point differ depending on the composition ratio. For example, Ge ₂ Sb ₂ Te ₅ has a crystallization temperature of 160 ° C. and a melting point of 600 ° C. The phase change film 16 can be any chalcogenide compound, and a material obtained by adding oxygen, nitrogen, zinc, carbide or the like to the chalcogenide compound can also be used.

  As shown in a region surrounded by a dotted line in FIG. 1, in the present embodiment, the upper surfaces of the lower plugs 12 and 13 (more specifically, the conductor 13) are narrower toward the bottom. The hollow 14 (pointed hollow 14) is formed. A phase change film 16 is formed in the recess 14 and on the upper surfaces of the lower plugs 12 and 13 via an insulating film 15. That is, the insulating film 15 is formed between the lower plugs 12 and 13 and the phase change film 16. However, as will be described later, the insulating film 15 may not be formed in the recess 14. In this case, the phase change film 16 is formed directly on the surface of the recess 14. Here, in the configuration shown in FIG. 1, the insulating film 15 is also formed between the lower surface of the phase change film 16 and the upper surface of the interlayer insulating film 10.

  Here, in the present invention, the regions of the lower plugs 12 and 13 connected to the phase change film 16 can be divided into a first region and a second region due to the difference in film thickness of the insulating film 15. The film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is zero or thinner than the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region. . In the present embodiment, as shown in FIG. 1, the recess 14 portion of the lower plugs 12 and 13 is the first region. On the other hand, in the present embodiment, the upper region of the lower plugs 12 and 13 other than the recess 14 is the second region.

  In the following, the manufacturing method of the semiconductor device 100 having the phase change memory 80 according to the present embodiment will be described while referring to the other configuration shown in FIG.

  As shown in FIG. 2, a semiconductor substrate 1 made of silicon is prepared, and an element isolation film 2 is selectively formed on the semiconductor substrate 1. Adjacent semiconductor elements are electrically isolated from each other by the element isolation film 2. Thereafter, an ion implantation process is performed to form a well region (not shown). As described above, in the present embodiment, the memory driving transistor 50 is an NMOS transistor. Therefore, the well region formed by the ion implantation process is an impurity region having P-type conductivity. Note that the well region is formed by a plurality of ion implantation processes including ion implantation for threshold adjustment.

  An insulating film and an electrode layer are deposited on the semiconductor substrate 1 shown in FIG. Thereafter, a patterning process is performed on the insulating film and the electrode layer. As a result, as shown in FIG. 3, a gate structure in which the gate insulating film 3 and the gate electrode 4 are selectively formed in this order is formed on the semiconductor substrate 1. Thereafter, ion implantation is performed using the gate structure as a mask. As a result, as shown in FIG. 3, low concentration extension regions 5 having an N-type conductivity are formed in the upper surface of the semiconductor substrate 1 on both sides of the gate structure.

  Next, an oxide film is formed on the semiconductor substrate 1 so as to cover the gate structure. Thereafter, an anisotropic etching process is performed on the oxide film. Thereby, as shown in FIG. 4, sidewall films 6 are formed on both side surfaces of the gate structure. Thereafter, ion implantation is performed using the gate structure in which the sidewall film 6 is formed on the side surface as a mask. Thereby, as shown in FIG. 4, N-type high-concentration impurity regions 7 are formed in the upper surface of the semiconductor substrate 1 on both sides of the gate structure in which the sidewall film 6 is formed.

  The low concentration extension region 5 and the high concentration impurity region 7 form an electrode region to be a source / drain electrode.

  Next, silicidation is performed on the upper surface of the electrode region (specifically, the high-concentration impurity region 7) and the upper surface of the gate electrode 4. Thereby, as shown in FIG. 5, a silicide layer 8 is formed on the high-concentration impurity region 7, and a silicide layer 9 is formed on the gate electrode 4. By forming the silicide layer 8, it is possible to reduce contact resistance with contact plugs (including lower plugs 12 and 13) to be formed later. The formation of the silicide layers 8 and 9 for the purpose of reducing the contact resistance can be omitted depending on the process generation.

  Next, as shown in FIG. 6, an interlayer insulating film 10 made of an oxide film is formed on the semiconductor substrate 1 so as to cover the gate structure. Thereafter, the interlayer insulating film 10 is subjected to a combination of a photolithography technique and an etching process. Thereby, as shown in FIG. 6, a contact hole (which can be grasped as a through hole) 11 is formed in the upper surface of the interlayer insulating film 10. Here, the contact hole 11 is formed so as to penetrate from the upper surface to the lower surface of the interlayer insulating film 10. Further, the silicide layer 8 is exposed from the bottom surface of the contact hole 11 as shown in FIG.

  Next, a barrier metal film 12 such as TiN is formed on the bottom and side surfaces of the contact hole 11 (see FIG. 7). The barrier metal film 12 has a function of preventing the later-described conductor (tungsten) 13 from diffusing into the interlayer insulating film 10, and between the silicide layer 8 and later-described contact plugs (including lower plugs 12 and 13). It also has a function that enables ohmic connection. Here, in the steps so far, the barrier metal film 12 is also formed on the interlayer insulating film 10 (see FIG. 7).

  Next, as shown in FIG. 7, a conductor 13 such as tungsten (W) is formed so as to fill the contact hole 11 in which the barrier metal film 12 is formed. Here, in the steps so far, the conductor 13 is also formed on the barrier metal film 12 formed on the interlayer insulating film 10 (see FIG. 7).

  As will be described later, the formation of the conductor 13 forms a gap K1 in the conductor 13 constituting the contact plugs 12 and 13 on the right side of FIG. The gap K1 becomes a depression 14 after a subsequent CMP (Chemical Mechanical Polishing) process. Further, the gap K1 is formed in the vicinity of the opening of the contact hole 11.

  Thereafter, the conductor 13 and the barrier metal film 12 are subjected to a CMP process under predetermined polishing conditions. As a result, as shown in FIG. 8, the barrier metal film 12 and the conductor 13 are left only in each contact hole 11, and the barrier metal film 12 and the conductor 13 on the interlayer insulating film 10 are removed. That is, in each contact hole 11, contact plugs 12 and 13 composed of a laminate of a barrier metal film 12 and a conductor 13 are formed (FIG. 8).

  Note that the contact plugs 12 and 13 (the contact plugs on the right side in FIG. 8) connected to the phase change film 16 via an insulating film 15 described later are referred to as “lower plugs”. On the other hand, the contact plugs 12 and 13 other than the lower plugs 12 and 13 (left side contact plugs in FIG. 8) are referred to as “normal plugs”. The definitions of the contact plugs 12 and 13 are common to other embodiments.

  Here, in the above, the diameter of the contact hole 11, the film thickness of the material of the conductor 13, the film forming conditions, and the like are appropriately selected. As a result, as shown in FIG. 8, a recess 14 (or a gap K1 in the conductor 13 as shown in FIG. 7) can be formed in the upper surface portions of the lower plugs 12 and 13.

  For example, the conductor 13 is formed with a film thickness equal to or larger than the radius of the contact hole 11 (film thickness of the conductor 13 ≧ diameter of the contact hole 11) under the film formation conditions of the conductor 13 with poor embedding property. Thereby, in the vicinity of the opening of the contact hole 11 (in other words, the upper surface of the lower plugs 12 and 13), a recess 14 whose width decreases toward the bottom can be formed. Further, it is not desirable that the cross-sectional shape of the contact hole 11 is a taper shape that improves the embedding property of the conductor 13. That is, from the viewpoint of forming the depression 14 (or the gap K1), it is more preferable that both side surface portions of the contact hole 11 stand perpendicular to the bottom surface portion. Further, from the viewpoint of lowering the embedding property of the conductor 13, it is better that the diameter of the contact hole 11 is smaller. For example, when the conductor 13 is formed by a normal CVD method, the recess 14 (gap K1) can be formed if the diameter of the contact hole 11 is 0.16 μm or less. Furthermore, in order to lower the embedding property of the conductor 13, a normal CVD method should be employed instead of an ALD (Atomic Layer Deposition) -CVD method.

  As can be seen from these facts, if the embedding technique used in the previous generation is used, the depression 14 (gap K1) can be generated on the upper surfaces of the lower plugs 12 and 13. For example, if a 130 nm embedding technique is used with a design rule of 90 nm, the depression 14 can be generated on the upper surfaces of the lower plugs 12 and 13. In other words, the gap K <b> 1 can be formed near the opening of the contact hole 11.

  Next, a film formation process (for example, a sputtering process) is performed on the upper surfaces of the lower plugs 12 and 13, the upper surfaces of the normal plugs 12 and 13, and the upper surface of the interlayer insulating film 10 under conditions with poor coverage.

  For example, a sputtering process using a metal such as Ta as a target is performed on the upper surfaces of the lower plugs 12 and 13, the upper surfaces of the normal plugs 12 and 13, and the upper surface of the interlayer insulating film 10. Thereafter, an oxidation treatment is performed on the metal film, and the metal film is turned into an insulating film. With this process, as shown in FIG. 9, the insulating film 15 is formed on the upper surfaces of the lower plugs 12 and 13, the upper surfaces of the normal plugs 12 and 13, and the upper surface of the interlayer insulating film 10.

  Incidentally, it is known that the coverage of the insulating film 15 formed by the sputtering process is not good. Therefore, as shown in the enlarged view of the upper surfaces of the lower plugs 12 and 13 in FIG. 10, the film thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region is as follows. , 13 is thinner than the thickness of the insulating film 15 formed on the surface.

  Here, the film thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region may be zero. Further, the surfaces of the lower plugs 12 and 13 in the first region are the surfaces in the recess 14 formed in the conductor 13 and decreasing in width toward the bottom as described above (see FIG. 10). On the other hand, the surfaces of the lower plugs 12 and 13 in the second region are the upper surfaces of the lower plugs 12 and 13 other than the recess 14 as described above (see FIG. 10).

  It is assumed that the aspect ratio (b / a) represented by the ratio between the opening width a of the depression 14 and the depth b of the depression 14 is 1 or more. Then, the embedding of the insulating film 15 in the recess 14 having the aspect ratio is reduced. Therefore, in this embodiment, since it is necessary to reduce the embedding property of the insulating film in the recess 14, it is necessary to form the recess 14 having an aspect ratio of 1 or more in this embodiment.

  Further, the thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the second region is required to be at least a level at which a tunnel current does not flow. On the other hand, the thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region needs to be a thickness at which a tunnel current flows. For example, when the insulating film 15 is TaO or CrO which is an oxide of Ta or Cr, the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is 0 to 3 nm. Is less than. On the other hand, the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region is 3 nm or more.

  Next, a phase change film 15 such as GST is formed on the insulating film 15 so as to fill the recess 14. Thereafter, a conductive film such as W (tungsten) is formed on the phase change film 15. Then, the phase change film 15 and the conductive film are applied in combination with a photolithography technique and an etching process. As a result, as shown in FIG. 11, a laminated body including the insulating film 15, the phase change film 16 and the upper electrode 17 connected to the upper surfaces of the lower plugs 12 and 13 is formed by patterning. FIG. 12 shows an enlarged cross-sectional view of the vicinity of the upper surfaces of the lower plugs 12 and 13 in FIG.

  As described above, the thickness of the insulating film 15 formed in the recess 14 may be zero. In this case, the phase change film 16 is formed in direct contact with the conductor 13 so as to fill the recess 14.

  Thereafter, an insulating film 18 such as SiN and an interlayer insulating film 19 functioning as an etching stopper are formed. Then, if necessary, normal plugs 12u and 13u are formed in the insulating film 18 and the interlayer insulating film 19, and wirings 20 and the like connected to the plugs 12u and 13u are formed. Here, the normal plugs 12u and 13u have a laminated structure of an outermost barrier metal film 12u and an inner conductor 13u.

  Further, the bottoms of the normal plugs 12u and 13u on the right side of the drawing are connected to the upper surface of the upper electrode 17 (FIG. 1). On the other hand, the bottoms of the normal plugs 12u and 13u on the left side of the drawing are connected to the top surfaces of the normal plugs 12 and 13 disposed in the lower layer (FIG. 1).

  The configuration shown in FIG. 1 (that is, the semiconductor device 100 having the phase change memory 80 and the memory driving transistor 50) is completed through the above steps.

  As described above, in the phase change memory 80 according to the present embodiment, the regions of the lower plugs 12 and 13 connected to the phase change film 16 have the first region and the second region (FIG. 10). The film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is zero or the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region. Is also thin. Here, in the present embodiment, the first region is a recess 14 formed on the upper surface of the lower plugs 12 and 13 and having a width that decreases toward the bottom. The second region is a region other than the depression 14 of the lower electrodes 12 and 13.

  Therefore, current can be concentrated in the lower plugs 12 and 13 in the first region. That is, the current density of the current supplied to the phase change film 16 can be further improved. Thereby, even if the current value of the reset current is reduced, the phase change film 16 can be made amorphous. That is, in the semiconductor device 100 according to the present embodiment, a reset current necessary for amorphization can be supplied to the phase change film 16. Note that the semiconductor device 100 according to the above embodiment does not require an increase in size of the entire apparatus. In addition, when manufacturing the semiconductor device 100, no complicated process is required.

  When the insulating film 15 is TaO or CrO, the thickness of the insulating film 15 formed in the first region is set to 0 to less than 3 nm, and the film of the insulating film 15 formed in the second region The thickness is 3 nm or more. By setting the film thickness, a tunnel current can flow from the lower plugs 12 and 13 to the phase change film 16 only in the first region.

  When the thickness of the insulating film 15 in the first region varies, a constant current is passed through the memory cell unit 80 after the semiconductor device 100 is manufactured. Thereby, the insulating film 15 in the first region can be destroyed so that a desired current value flows. That is, it is possible to generate a pinhole in the insulating film 15 in the first region. Here, the current condition and the voltage condition for breaking the insulating film 15 depend on the film thickness of the insulating film 15 and the like, but are about several μm and about 2 to 3 V as an example. Further, the insulating film 15 formed in the second region is not affected by the pinhole generation process.

  Due to the breakdown of the insulating film 15 in the first region, variation in the current value of the current flowing from the lower plugs 12 and 13 to the phase change film 16 can be suppressed.

  In addition, when the contact plugs 12 and 13 are created under the same conditions and design, the recess 14 is formed also in the normal plugs 12 and 13, unlike FIG. However, even if the depression 14 is formed in the normal plugs 12 and 13, there is no particular problem in the operation of the semiconductor device 100. If the contact plugs 12 and 13 are formed in different processes and different conditions, the recess 14 can be formed only in the lower plugs 12 and 13 as shown in FIG. , 13 can be made not to form the recess 14.

  In the present embodiment, the MOS transistor 50 is used for driving the memory. However, instead of the MOS transistor 50, a bipolar transistor, a diode, and other driving semiconductor devices can be employed. Further, the conductivity type of the transistor may be N-type or P-type.

<Embodiment 2>
FIG. 13 is a cross-sectional view showing the configuration of the phase change memory according to the present embodiment. FIG. 14 is an enlarged view of a region C11 surrounded by a dotted line in FIG.

  As shown in FIGS. 13 and 14, the lower plugs 12 and 13 are laminated bodies of the barrier metal film 12 and the conductors 13 as in the first embodiment. The barrier metal film 12 is formed on at least the side surface of the contact hole 11 formed in the surface of the interlayer insulating film 10. The conductor 13 is formed in contact with the barrier metal film 12 so as to fill the contact hole 11.

  In the present embodiment, the upper surface U1 of the conductor 13 is located below the upper end U2 of the barrier metal film. That is, as shown in FIGS. 13 and 14, the upper surface U <b> 1 of the conductor 13 is recessed from the upper surface of the interlayer insulating film 10. The recess portion is referred to as a recess portion 11d. The insulating film 15 is formed on the barrier metal film 12 formed on the side surface of the recess 11d, the upper surface of the conductor 13 desired from the bottom of the recess 11d, and the upper surface of the interlayer insulating film 10.

  As described in the first embodiment, the regions of the lower plugs 12 and 13 connected to the phase change film 16 are divided into the first region and the second region due to the difference in film thickness of the insulating film 15. Can be classified. The film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is zero or thinner than the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region. . In the present embodiment, the barrier metal film 12 from the upper end portion U2 of the barrier metal film 12 to the upper surface U1 of the conductor 13 corresponds to the first region. The upper surface U1 of the conductor 13 and the upper end portion U2 of the barrier metal film 12 correspond to the second region.

  Other configurations are the same as those in the first embodiment. Therefore, description of other structures here is omitted.

  Hereinafter, a method for manufacturing a semiconductor device having the phase change memory according to the present embodiment will be described.

  First, similarly to the first embodiment, the steps shown in FIGS. Thereafter, a barrier metal film 12 such as TiN is formed on the bottom and side surfaces of the contact hole 11. The barrier metal film 12 has a function of preventing the later-described conductor (tungsten) 13 from diffusing into the interlayer insulating film 10, and between the silicide layer 8 and later-described contact plugs (including lower plugs 12 and 13). It also has a function that enables ohmic connection. Here, in the steps so far, the barrier metal film 12 is also formed on the interlayer insulating film 10.

  Next, a conductor 13 such as tungsten (W) is formed so as to fill the contact hole 11 in which the barrier metal film 12 is formed. Here, in the steps so far, the conductor 13 is also formed on the barrier metal film 12 formed on the interlayer insulating film 10.

  Thereafter, the conductor 13 and the barrier metal film 12 are subjected to a CMP process under predetermined polishing conditions. As a result, as shown in FIG. 15, the barrier metal film 12 and the conductor 13 are left only in each contact hole 11, and the barrier metal film 12 and the conductor 13 on the interlayer insulating film 10 are removed. That is, in each contact hole 11, contact plugs 12 and 13 composed of a laminate of a barrier metal film 12 and a conductor 13 are formed (FIG. 15).

  Here, in the present embodiment, by adjusting the CMP processing time, the upper surface of the conductor 13 is positioned below the upper surface of the interlayer insulating film 10 as shown in FIG. That is, the recess portion 11 d is formed on the upper surface of the conductor 13.

  For example, when the conductor 13 is tungsten (W), the time of the W-CMP process is adjusted as follows. In a normal W-CMP process, the upper surface of the interlayer insulating film 10 is detected, and tungsten is not left on the interlayer insulating film 10, so over-polishing is performed. By the over polishing, a part of tungsten in the contact hole 11 is scraped, and a recess portion 11d is formed. If the over-polishing time is lengthened, the depth of the recess 11d can be increased accordingly.

  Next, a film formation process (for example, a sputtering process) is performed on the upper surfaces of the lower plugs 12 and 13, the upper surfaces of the normal plugs 12 and 13, and the upper surface of the interlayer insulating film 10 under conditions with poor coverage.

  For example, a sputtering process using a metal such as Ta as a target is performed on the upper surfaces of the lower plugs 12 and 13, the upper surfaces of the normal plugs 12 and 13, the side surfaces of the recess portions 11 d, and the upper surface of the interlayer insulating film 10. . Thereafter, an oxidation treatment is performed on the metal film, and the metal film is turned into an insulating film. In this process, as shown in FIG. 16, the insulating film 15 is formed on the upper surfaces of the lower plugs 12 and 13, the upper surfaces of the normal plugs 12 and 13, the side surfaces of the recess portion 11 d, and the upper surface of the interlayer insulating film 10.

  Incidentally, it is known that the coverage of the insulating film 15 formed by the sputtering process is not good. Therefore, as described with reference to FIG. 14, the film thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region is formed on the surfaces of the lower plugs 12 and 13 in the second region. It becomes thinner than the film thickness of the insulating film 15. That is, the thickness of the insulating film 15 formed on the barrier metal film 12 formed on the side surface portion of the recess portion 11d is smaller than the thickness of the insulating film 15 formed on the upper surface U1 of the conductor 13. In addition, the thickness of the insulating film 15 formed on the barrier metal film 12 formed on the side surface portion of the recess portion 11d is smaller than the thickness of the insulating film 15 formed on the upper end portion U2 of the barrier metal film 12.

  Here, the film thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region may be zero.

  Further, the thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the second region is required to be at least a level at which a tunnel current does not flow. On the other hand, the thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region needs to be a thickness at which a tunnel current flows. For example, when the insulating film 15 is TaO or CrO which is an oxide of Ta or Cr, the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is 0 to 3 nm. Is less than. On the other hand, the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region is 3 nm or more.

  Next, a phase change film 16 such as GST is formed on the insulating film 15 so as to fill the recess 11d. Thereafter, a conductive film such as W (tungsten) is formed on the phase change film 16. Then, the insulating film 15, the phase change film 16 and the conductive film are applied in combination with a photolithography technique and an etching process. As a result, as shown in FIG. 17, a laminate including the insulating film 15, the phase change film 16 and the upper electrode 17 connected to the upper surfaces of the lower plugs 12 and 13 is formed by patterning.

  As described above, the thickness of the insulating film 15 formed in the recess 14 may be zero. In this case, the phase change film 16 is formed in direct contact with the conductor 13 so as to fill the recess 11d.

  Thereafter, an insulating film 18 such as SiN and an interlayer insulating film 19 functioning as an etching stopper are formed. Then, if necessary, normal plugs 12u and 13u are formed in the insulating film 18 and the interlayer insulating film 19, and wirings 20 and the like connected to the plugs 12u and 13u are formed. Here, the normal plugs 12u and 13u have a laminated structure of an outermost barrier metal film 12u and an inner conductor 13u.

  Further, the bottoms of the normal plugs 12u, 13u on the right side of the drawing are connected to the upper surface of the upper electrode 17 (FIG. 13). On the other hand, the bottoms of the normal plugs 12u and 13u on the left side of the drawing are connected to the upper surfaces of the normal plugs 12 and 13 disposed in the lower layer (FIG. 13).

  Through the above steps, the configuration shown in FIG. 13 (that is, a semiconductor device having a phase change memory and a memory driving transistor) is completed.

  As described above, in the phase change memory according to the present embodiment, the regions of the lower plugs 12 and 13 connected to the phase change film 16 have the first region and the second region (FIG. 14). reference). The film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is zero or the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region. Is also thin. Here, in the present embodiment, the first region is on the barrier metal film 12 from the upper end portion U2 of the barrier metal film 12 to the upper surface U1 of the conductor 13. In other words, the barrier metal film 12 formed on the side surface of the recess portion 11d is the first region. The second region is on the upper surface U1 of the conductor 13 and the upper end portion U2 of the barrier metal film 12.

  Therefore, current can be concentrated in the lower plugs 12 and 13 in the first region. That is, the current density of the current supplied to the phase change film 16 can be further improved. Thereby, even if the current value of the reset current is reduced, the phase change film 16 can be made amorphous. That is, in the semiconductor device according to the present embodiment, a reset current necessary for amorphization can be supplied to the phase change film 16. Note that the semiconductor device according to the above embodiment does not require an increase in size of the entire apparatus. Further, no complicated process is required for manufacturing the semiconductor device.

  When the insulating film 15 is TaO or CrO, the thickness of the insulating film 15 formed in the first region is set to 0 to less than 3 nm, and the film of the insulating film 15 formed in the second region The thickness is 3 nm or more. By setting the film thickness, a tunnel current can flow from the lower plugs 12 and 13 to the phase change film 16 only in the first region.

  When the thickness of the insulating film 15 in the first region varies, a constant current is passed through the memory cell portion after the semiconductor device is manufactured. Thereby, the insulating film 15 in the first region can be destroyed so that a desired current value flows. That is, it is possible to generate a pinhole in the insulating film 15 in the first region. Here, the current condition and the voltage condition for breaking the insulating film 15 depend on the film thickness of the insulating film 15 and the like, but are about several μm and about 2 to 3 V as an example. Further, the insulating film 15 formed in the second region is not affected by the pinhole generation process.

  Due to the breakdown of the insulating film 15 in the first region, variation in the current value of the current flowing from the lower plugs 12 and 13 to the phase change film 16 can be suppressed.

  As shown in FIG. 15, the recess 11 d is formed also in the normal plugs 12 and 13 by the CMP process on the conductor 13. However, even if the recess 11d is formed in the normal plugs 12 and 13, there is no particular problem in terms of electrical characteristics.

  In this embodiment, a MOS transistor is used for memory driving. However, bipolar transistors, diodes, and other driving semiconductor devices can be employed instead of the MOS transistors. Further, the conductivity type of the transistor may be N-type or P-type.

  Note that the recess portion 11d may be formed by dry etching. Further, the recess portion 11d may be formed by using both the CMP process and the dry etching process. That is, after the predetermined amount of the conductor 13 and the predetermined amount of the barrier metal film 12 are removed by the CMP process, the conductor 13 and the barrier metal film 12 are dry-etched. The recess portion 11d may be formed by this process.

  The depth of the recess 11d is preferably as small as possible from the viewpoint of improving the current density as described above. However, it is necessary to make a step with respect to the interface insulating film. Therefore, in consideration of these matters, the depth of the recess portion 11d is preferably about 10 nm to 100 nm.

<Embodiment 3>
FIG. 18 is a cross-sectional view showing the configuration of the phase change memory according to the present embodiment. FIG. 19 is an enlarged view of a region C21 surrounded by a dotted line in FIG.

  As shown in FIGS. 18 and 19, the lower plugs 12 and 13 are laminated bodies of the barrier metal film 12 and the conductor 13 as in the first embodiment. The lower plugs 12 and 13 are formed in the contact holes 11 formed in the surface of the interlayer insulating film 10. Here, in the present embodiment, the lower plugs 12 and 13 have a protruding portion L1 protruding from the upper surface U5 of the interlayer insulating film 10.

  As described in the first embodiment, the regions of the lower plugs 12 and 13 connected to the phase change film 16 are divided into the first region and the second region due to the difference in film thickness of the insulating film 15. Can be classified. The film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is zero or thinner than the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region. . In the present embodiment, the side surface portion of the protruding portion L1 of the lower plugs 12 and 13 corresponds to the first region. Further, the upper surfaces of the lower plugs 12 and 13 (the upper surfaces of the protruding portions L1) correspond to the second region.

  Other configurations are the same as those in the first embodiment. Therefore, description of other structures here is omitted.

  Hereinafter, a method for manufacturing a semiconductor device having the phase change memory according to the present embodiment will be described.

  First, similarly to the first embodiment, the steps shown in FIGS. Thereafter, a barrier metal film 12 such as TiN is formed on the bottom and side surfaces of the contact hole 11. The barrier metal film 12 has a function of preventing the later-described conductor (tungsten) 13 from diffusing into the interlayer insulating film 10, and between the silicide layer 8 and later-described contact plugs (including lower plugs 12 and 13). It also has a function that enables ohmic connection. Here, in the steps so far, the barrier metal film 12 is also formed on the interlayer insulating film 10.

  Next, a conductor 13 such as tungsten (W) is formed so as to fill the contact hole 11 in which the barrier metal film 12 is formed. Here, in the steps so far, the conductor 13 is also formed on the barrier metal film 12 formed on the interlayer insulating film 10.

  Thereafter, the conductor 13 and the barrier metal film 12 are subjected to a CMP process under predetermined polishing conditions. As a result, as shown in FIG. 20, the barrier metal film 12 and the conductor 13 are left only in each contact hole 11, and the barrier metal film 12 and the conductor 13 on the interlayer insulating film 10 are removed. That is, in each contact hole 11, contact plugs 12 and 13 composed of a laminate of a barrier metal film 12 and a conductor 13 are formed (FIG. 20).

  Next, wet etching or dry etching treatment is performed on the interlayer insulating film 10. As a result, as shown in FIG. 21, the upper surface of the interlayer insulating film 10 is etched back, and the lower plugs 12 and 13 are projected from the upper surface of the interlayer insulating film 10. In other words, as shown in FIG. 21, the protrusion L <b> 1 is formed in the lower plugs 12 and 13 and the normal plugs 12 and 13 by the etch back.

  Next, a film formation process (for example, a sputtering process) is performed on the upper surface and side surfaces of the lower plugs 12 and 13, the upper surfaces and side surfaces of the normal plugs 12 and 13, and the upper surface of the interlayer insulating film 10 under poor coverage conditions.

  For example, the upper and side surfaces of the lower plugs 12 and 13, the upper and side surfaces of the normal plugs 12 and 13, and the upper surface of the interlayer insulating film 10 are subjected to sputtering using a metal such as Ta. Thereafter, an oxidation treatment is performed on the metal film, and the metal film is turned into an insulating film. 22, the insulating film 15 is formed on the upper surfaces and side surfaces of the lower plugs 12 and 13, the upper surfaces and side surfaces of the normal plugs 12 and 13, and the upper surface of the interlayer insulating film 10.

  Incidentally, it is known that the coverage of the insulating film 15 formed by the sputtering process is not good. Accordingly, as described with reference to FIG. 19, the film thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region is formed on the surfaces of the lower plugs 12 and 13 in the second region. It becomes thinner than the film thickness of the insulating film 15. That is, the film thickness of the insulating film 15 formed on the side surface portion of the protruding portion L1 is thinner than the film thickness of the insulating film 15 formed on the upper surface of the protruding portion L1.

  Here, as can be seen from the configuration of FIG. 19, the insulating film 15 is in contact with the barrier metal 12 on the side surface of the protrusion L <b> 1. On the other hand, the insulating film 15 is in contact with the conductor 13 and the upper end portions of the barrier metal film 12 on the upper surface of the protrusion L1. Further, the film thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region may be zero.

  As a film thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the second region, a minimum thickness that does not allow a tunnel current to flow is required. On the other hand, the thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region needs to be a thickness at which a tunnel current flows. For example, when the insulating film 15 is TaO or CrO which is an oxide of Ta or Cr, the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is 0 to 3 nm. Is less than. On the other hand, the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region is 3 nm or more.

  Next, a phase change film 16 such as GST is formed on the insulating film 15 so as to cover the protrusion L1. Thereafter, a conductive film such as W (tungsten) is formed on the phase change film 16. Then, the insulating film 15, the phase change film 15 and the conductive film are applied in combination with a photolithography technique and an etching process. As a result, as shown in FIG. 23, a laminated body composed of the insulating film 15, the phase change film 16 and the upper electrode 17 connected to the upper surfaces of the lower plugs 12 and 13 is formed by patterning.

  As described above, the thickness of the insulating film 15 formed on the side surface of the protruding portion L1 may be zero. In this case, the phase change film 16 is formed in direct contact with the side surface of the protrusion L1.

  Thereafter, an insulating film 18 such as SiN and an interlayer insulating film 19 functioning as an etching stopper are formed. Then, if necessary, normal plugs 12u and 13u are formed in the insulating film 18 and the interlayer insulating film 19, and wirings 20 and the like connected to the plugs 12u and 13u are formed. Here, the normal plugs 12u and 13u have a laminated structure of an outermost barrier metal film 12u and an inner conductor 13u.

  Further, the bottoms of the normal plugs 12u and 13u on the right side of the drawing are connected to the upper surface of the upper electrode 17 (FIG. 18). On the other hand, the bottoms of the normal plugs 12u and 13u on the left side of the drawing are connected to the upper surfaces of the normal plugs 12 and 13 disposed in the lower layer (FIG. 18).

  Through the steps described above, the configuration shown in FIG. 18 (that is, a semiconductor device having a phase change memory and a memory driving transistor) is completed.

  As described above, in the phase change memory according to the present embodiment, the regions of the lower plugs 12 and 13 connected to the phase change film 16 have the first region and the second region (FIG. 19). reference). The film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is zero or the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region. Is also thin. Here, in the present embodiment, the first region is on the side surface of the portion of the lower plugs 12 and 13 that protrude from the upper surface of the interlayer insulating film 10 (the protruding portion L1). The second region is on the upper surface of the protrusion L1.

  Therefore, current can be concentrated in the lower plugs 12 and 13 in the first region. That is, the current density of the current supplied to the phase change film 16 can be further improved. Thereby, even if the current value of the reset current is reduced, the phase change film 16 can be made amorphous. That is, in the semiconductor device according to the present embodiment, a reset current necessary for amorphization can be supplied to the phase change film 16. Note that the semiconductor device according to the above embodiment does not require an increase in size of the entire apparatus. Further, no complicated process is required for manufacturing the semiconductor device.

  When the insulating film 15 is TaO or CrO, the thickness of the insulating film 15 formed in the first region is set to 0 to less than 3 nm, and the film of the insulating film 15 formed in the second region The thickness is 3 nm or more. By setting the film thickness, a tunnel current can flow from the lower plugs 12 and 13 to the phase change film 16 only in the first region.

  If the thickness of the insulating film 15 in the first region varies, a constant current is passed through the memory cell portion after the semiconductor device is formed. Thereby, the insulating film 15 in the first region can be destroyed so that a desired current value flows. That is, it is possible to generate a pinhole in the insulating film 15 in the first region. Here, the current condition and the voltage condition for breaking the insulating film 15 depend on the film thickness of the insulating film 15 and the like, but are about several μm and about 2 to 3 V as an example. Further, the insulating film 15 formed in the second region is not affected by the pinhole generation process.

  Due to the breakdown of the insulating film 15 in the first region, variation in the current value of the current flowing from the lower plugs 12 and 13 to the phase change film 16 can be suppressed.

  As shown in FIG. 21, the upper portions of the normal plugs 12 and 13 also protrude from the upper surface of the interlayer insulating film 10 (that is, the protruding portion L1 is formed) by the etch back process for the interlayer insulating film 10. However, even if the protrusions L1 are formed in the normal plugs 12 and 13, there is no particular problem in the operation of the semiconductor device.

  In this embodiment, a MOS transistor is used for memory driving. However, bipolar transistors, diodes, and other driving semiconductor devices can be employed instead of the MOS transistors. Further, the conductivity type of the transistor may be N-type or P-type.

  Further, the height of the protruding portion L1 is preferably as small as possible from the viewpoint of improving the current density as described above. However, it is necessary to make a step with respect to the interface insulating film. Therefore, in consideration of these points, it is desirable that the height of the protrusion L1 is about 10 nm to 100 nm.

<Embodiment 4>
When a plurality of semiconductor devices having the configuration shown in FIG. 18 are formed by the method described in the third embodiment, variation in the protruding dimension of the protruding portion L1 may occur in each semiconductor device. This is because it is difficult to accurately control the etch back amount of the interlayer insulating film 10. Further, the etchback amount changes depending on the density of the layout of the contact plugs 12 and 13 (that is, the protruding dimension of the protruding portion L1 changes). Therefore, a structure / method for accurately forming the protrusion dimension of the protrusion L1 (in other words, the controllability of the protrusion dimension can be achieved) is provided in the present embodiment.

  FIG. 24 is a cross-sectional view showing the configuration of the phase change memory according to the present embodiment.

  As can be seen from a comparison between FIG. 18 and FIG. 24, they are different in the following points. That is, in the configuration according to the third embodiment, the interlayer insulating film has a single-layer structure of an oxide film. On the other hand, in the configuration according to the present embodiment, the interlayer insulating film 10 has a laminated structure of the nitride film 10t and the oxide film 10s. Here, a nitride film 10t is formed on the upper surface side of the interlayer insulating film 10, and an oxide film 10s is formed immediately below the nitride film 10t. In other words, as shown in FIG. 24, the nitride film 10 t is exposed from the upper surface of the interlayer insulating film 10, and a layer made of the oxide film 10 s is formed inside the interlayer insulating film 10.

  Also in the present embodiment, the lower plugs 12 and 13 have the protruding portion L1 protruding from the upper surface of the interlayer insulating film 10 (more specifically, the nitride film 10t). Similarly to the third embodiment, also in the present embodiment, the side surface portion of the protruding portion L1 of the lower plugs 12 and 13 corresponds to the first region. Further, the upper surfaces of the lower plugs 12 and 13 (the upper surfaces of the protruding portions L1) correspond to the second region.

  Other configurations are the same as those in the third embodiment. Therefore, description of other structures here is omitted.

  Hereinafter, a method for manufacturing a semiconductor device having the phase change memory according to the present embodiment will be described.

  First, similarly to the first embodiment, the steps shown in FIGS. Thereafter, an oxide film 10s is formed on the semiconductor substrate 1 so as to cover the gate structure. Next, a nitride film 10t is formed on the oxide film 10s, and an oxide film 10w is formed on the nitride film 10t. Here, at this stage, the interlayer insulating film 10 has a laminated structure including the oxide film 10s, the nitride film 10t, and the oxide film 10w.

  Thereafter, the interlayer insulating film 10 having the laminated structure is subjected to a combination of a photolithography technique and an etching process. As a result, a contact hole 11 is formed in the upper surface of the interlayer insulating film 10 as shown in FIG. Here, the contact hole 11 is formed so as to penetrate from the upper surface to the lower surface of the interlayer insulating film 10. Further, the silicide layer 8 is exposed from the bottom surface of the contact hole 11 as shown in FIG.

  Next, a barrier metal film 12 such as TiN is formed on the bottom and side surfaces of the contact hole 11. The barrier metal film 12 has a function of preventing the later-described conductor (tungsten) 13 from diffusing into the interlayer insulating film 10, and between the silicide layer 8 and later-described contact plugs (including lower plugs 12 and 13). It also has a function that enables ohmic connection. Here, in the steps so far, the barrier metal film 12 is also formed on the oxide film 10w.

  Next, a conductor 13 such as tungsten (W) is formed so as to fill the contact hole 11 in which the barrier metal film 12 is formed. Here, in the steps so far, the conductor 13 is also formed on the barrier metal film 12 formed on the oxide film 10w.

  Thereafter, the conductor 13 and the barrier metal film 12 are subjected to a CMP process under predetermined polishing conditions. As a result, as shown in FIG. 26, the barrier metal film 12 and the conductor 13 are left only in each contact hole 11, and the barrier metal film 12 and the conductor on the interlayer insulating film 10 (more specifically, the oxide film 10w) are left. 13 is removed. That is, in each contact hole 11, contact plugs 12 and 13 composed of a laminate of a barrier metal film 12 and a conductor 13 are formed (FIG. 26).

  Next, wet etching or dry etching treatment is performed on the oxide film 10w. During the etching process, the nitride film 10t functions as an etching stopper. That is, the oxide film 10w can be etched away with good control. Thereby, as shown in FIG. 27, the lower plugs 12 and 13 are projected from the upper surface of the interlayer insulating film 10 (specifically, the nitride film 10t). In other words, by the etching process, as shown in FIG. 27, the protrusions L1 are formed in the lower plugs 12 and 13 and the normal plugs 12 and 13.

  Here, as can be seen from the above description, the protruding dimension of the protruding portion L1 is the same as the thickness of the oxide film 10w. That is, by making the interlayer insulating film 10 have the above-described laminated structure, the protruding dimension of the protruding portion L1 can be easily controlled only by controlling the film thickness of the oxide film 10w during film formation. Further, by removing the oxide film 10w, the interlayer insulating film 10 has a laminated structure in which the oxide film 10s and the nitride film 10t are formed in this order.

  Note that the steps after the formation of the insulating film 15 are the same as those described in the third embodiment. Therefore, description of the subsequent steps is omitted.

  The configuration shown in FIG. 24 (that is, the semiconductor device having the phase change memory and the memory driving transistor 50) is completed through the above steps. As described above, in the finished product, the interlayer insulating film 10 has a laminated structure in which the oxide film 10s (lower layer) and the nitride film 10t (upper layer) are formed in this order.

  As described above, in the present embodiment, the nitride film 10t serving as an etching stopper during the etching process is formed on the oxide film 10s. Therefore, by forming the oxide film 10w having a desired thickness on the nitride film 10t and etching the oxide film 10w, the projecting dimension of the projecting portion L1 can be easily controlled with high accuracy.

  Needless to say, this embodiment also has the same effect as that described in the third embodiment.

  In the above description, the nitride film 10t serving as an etching stopper is formed on the oxide film 10s when the oxide film 10w is etched.

  However, a nitride film may be formed on the oxide film, and the oxide film may function as an etching stopper for the nitride film. Also by this method, the projecting dimension of the projecting portion L1 can be easily controlled. In the case of this method, the interlayer insulating film 10 has a laminated structure in which an oxide film and a nitride film are laminated in this order during the manufacturing process. However, when completed, the interlayer insulating film 10 has a structure similar to that shown in FIG. That is, the interlayer insulating film 10 is composed of a single layer of oxide film.

<Embodiment 5>
FIG. 28 is a cross-sectional view showing the configuration of the phase change memory according to the present embodiment. FIG. 29 is an enlarged view of a region C31 surrounded by a dotted line in FIG.

  As shown in FIGS. 28 and 29, the lower plugs 12 and 13 are laminated bodies of the barrier metal film 12 serving as the outer layer and the conductor 13 serving as the inner layer, as in the first embodiment. In the present embodiment, as shown in FIGS. 28 and 29, the upper surfaces of the lower plugs 12 and 13 (more specifically, the conductor 13) are rough. That is, a plurality of convex portions and a plurality of concave portions are formed on the upper surface of the lower plugs 12 and 13 (specifically, the conductor 13). In FIGS. 28 and 29, a region where the plurality of concave and convex portions are formed is denoted by reference numeral G1.

  As described in the first embodiment, the regions of the lower plugs 12 and 13 connected to the phase change film 16 are divided into the first region and the second region due to the difference in film thickness of the insulating film 15. Can be classified. The film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is zero or thinner than the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region. . In the present embodiment, the apex of the convex portion formed on the upper surface of the conductor 13 and the vicinity of the apex of the convex portion correspond to the first region. The bottom surface of the recess formed on the top surface of the conductor 13 and the vicinity of the bottom surface of the recess correspond to the second region.

  Other configurations are the same as those in the first embodiment. Therefore, description of other structures here is omitted.

  Hereinafter, a method for manufacturing a semiconductor device having the phase change memory according to the present embodiment will be described.

  First, similarly to the first embodiment, the steps shown in FIGS. Thereafter, a barrier metal film 12 such as TiN is formed on the bottom and side surfaces of the contact hole 11. The barrier metal film 12 has a function of preventing the later-described conductor (tungsten) 13 from diffusing into the interlayer insulating film 10, and between the silicide layer 8 and later-described contact plugs (including lower plugs 12 and 13). It also has a function that enables ohmic connection. Here, in the steps so far, the barrier metal film 12 is also formed on the interlayer insulating film 10.

  Next, a conductor 13 such as tungsten (W) is formed so as to fill the contact hole 11 in which the barrier metal film 12 is formed. Here, in the steps so far, the conductor 13 is also formed on the barrier metal film 12 formed on the interlayer insulating film 10.

  Thereafter, the conductor 13 and the barrier metal film 12 are subjected to a CMP process under predetermined polishing conditions. Thereby, as shown in FIG. 30, the barrier metal film 12 and the conductor 13 are left only in each contact hole 11, and the barrier metal film 12 and the conductor 13 on the interlayer insulating film 10 are removed. That is, in each contact hole 11, contact plugs 12 and 13 composed of a laminate of a barrier metal film 12 and a conductor 13 are formed (FIG. 30).

  Here, in this Embodiment, the particle diameter of the particle | grains which comprise the conductor 13 is enlarged. Further, in the CMP process, a slurry that reduces flatness is used. Thereby, as shown in the enlarged views of FIG. 30 and FIG. 29, a concavo-convex region G1 having a plurality of concavo-convex shapes is formed on the upper surface of the conductor 13. The particle size of tungsten is generally large although it depends on the film forming conditions. When the conductor 13 is formed by a normal CVD method, the grain size of tungsten is about 50 nm. Moreover, when the conductor 13 is formed by ALD-CVD, the thickness is about 20 nm. However, these exemplified particle sizes vary somewhat depending on the deposition conditions, deposition gas, and post-treatment.

  For example, although depending on the film thickness and coverage of the insulating film, the flatness of the conductor 13 can be reduced by setting the particle diameter of tungsten or the like constituting the conductor 13 to about 10 nm or more. Further, by adopting fumed silica as a slurry used in the W-CMP process, the flatness of tungsten can be lowered. Further, by adopting polishing conditions in which the polishing rate is increased under high pressure, a chemical reaction is likely to occur, and as a result, the flatness of the conductor 13 is lowered.

  In addition, the uneven | corrugated shape formed in the above is not constant, and the height of the vertex of a convex part and the depth of the bottom part of a recessed part differ depending on a place.

  Next, a film formation process (for example, a sputtering process) is performed on the upper surfaces of the lower plugs 12 and 13, the upper surfaces of the normal plugs 12 and 13, and the upper surface of the interlayer insulating film 10 under conditions with poor coverage.

  For example, a sputtering process using a metal such as Ta as a target is performed on the upper surfaces of the lower plugs 12 and 13, the upper surfaces of the normal plugs 12 and 13, and the upper surface of the interlayer insulating film 10. Thereafter, an oxidation treatment is performed on the metal film, and the metal film is turned into an insulating film. With this process, as shown in FIG. 31, the insulating film 15 is formed on the upper surfaces of the lower plugs 12 and 13, the upper surfaces of the normal plugs 12 and 13, and the upper surface of the interlayer insulating film 10.

  Incidentally, it is known that the coverage of the insulating film 15 formed by the sputtering process is not good. Therefore, as described with reference to FIG. 29, the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region is formed on the surfaces of the lower plugs 12 and 13 in the second region. It becomes thinner than the film thickness of the insulating film 15. That is, the apex of the convex portion formed on the upper surface of the conductor 13 and the film thickness of the insulating film 15 formed in the vicinity of the apex are formed on the bottom portion of the concave portion formed on the upper surface of the conductor 13 and in the vicinity of the bottom portion. The thickness of the insulating film 15 becomes smaller.

  Here, the film thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region may be zero.

  When the aspect ratio (b / a) expressed by the ratio of the opening width a of the recess and the depth b of the recess is less than 1, the insulating film 15 can be uniformly embedded in the recess. . That is, in the case of the aspect ratio, the embedding property of the insulating film 15 in the recess is improved. Therefore, from the viewpoint of forming the second region described above, in this embodiment, it is necessary to uniformly embed the insulating film 15 in the recess, so that the aspect ratio of the recess formed in this embodiment is less than 1. It is necessary to.

  Further, the thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the second region is required to be at least a level at which a tunnel current does not flow. On the other hand, the thickness of the insulating film 15 formed on the surfaces of the lower plugs 12 and 13 in the first region needs to be a thickness at which a tunnel current flows. For example, when the insulating film 15 is TaO or CrO which is an oxide of Ta or Cr, the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is 0 to 3 nm. Is less than. On the other hand, the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region is 3 nm or more.

  Next, a phase change film 16 such as GST is formed on the insulating film 15. Thereafter, a conductive film such as W (tungsten) is formed on the phase change film 16. Then, the insulating film 15, the phase change film 16 and the conductive film are applied in combination with a photolithography technique and an etching process. As a result, as shown in FIG. 32, a laminated body including the insulating film 15, the phase change film 16 and the upper electrode 17 connected to the upper surfaces of the lower plugs 12 and 13 is formed by patterning.

  As described above, the thickness of the top of the convex portion formed on the conductor 13 and the thickness of the insulating film 15 formed near the top may be zero. In this case, the phase change film 16 is formed in direct contact with the apex of the convex portion and the conductor 13 near the apex.

  Thereafter, an insulating film 18 such as SiN and an interlayer insulating film 19 functioning as an etching stopper are formed. Then, if necessary, normal plugs 12u and 13u are formed in the insulating film 18 and the interlayer insulating film 19, and wirings 20 and the like connected to the plugs 12u and 13u are formed. Here, the normal plugs 12u and 13u have a laminated structure of an outermost barrier metal film 12u and an inner conductor 13u.

  The bottoms of the normal plugs 12u and 13u on the right side of the drawing are connected to the upper surface of the upper electrode 17 (FIG. 28). On the other hand, the bottoms of the normal plugs 12u and 13u on the left side of the drawing are connected to the upper surfaces of the normal plugs 12 and 13 disposed in the lower layer (FIG. 28).

  The configuration shown in FIG. 28 (that is, the semiconductor device having the phase change memory and the memory drive transistor 50) is completed through the above steps.

  As described above, in the phase change memory according to the present embodiment, the regions of the lower plugs 12 and 13 connected to the phase change film 16 have the first region and the second region (FIG. 29). reference). The film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the first region is zero or the film thickness of the insulating film 15 formed on the lower plugs 12 and 13 in the second region. Is also thin. Here, in the present embodiment, the first region is the apex of the convex portion formed on the upper surface of the conductor 13 and the vicinity of the apex. The second region is the bottom of the recess formed on the top surface of the conductor 13 and the vicinity of the bottom.

  Therefore, current can be concentrated in the lower plugs 12 and 13 in the first region. That is, the current density of the current supplied to the phase change film 16 can be further improved. Thereby, even if the current value of the reset current is reduced, the phase change film 16 can be made amorphous. That is, in the semiconductor device according to the present embodiment, a reset current necessary for amorphization can be supplied to the phase change film 16. Note that the semiconductor device according to the above embodiment does not require an increase in size of the entire apparatus. Further, no complicated process is required for manufacturing the semiconductor device.

  When the insulating film 15 is TaO or CrO, the thickness of the insulating film 15 formed in the first region is set to 0 to less than 3 nm, and the film of the insulating film 15 formed in the second region The thickness is 3 nm or more. By setting the film thickness, a tunnel current can flow from the lower plugs 12 and 13 to the phase change film 16 only in the first region.

  If the thickness of the insulating film 15 in the first region varies, a constant current is passed through the memory cell portion after the semiconductor device is formed. Thereby, the insulating film 15 in the first region can be destroyed so that a desired current value flows. That is, it is possible to generate a pinhole in the insulating film 15 in the first region. Here, the current condition and the voltage condition for breaking the insulating film 15 depend on the film thickness of the insulating film 15 and the like, but are about several μm and about 2 to 3 V as an example. Further, the insulating film 15 formed in the second region is not affected by the pinhole generation process.

  Due to the breakdown of the insulating film 15 in the first region, variation in the current value of the current flowing from the lower plugs 12 and 13 to the phase change film 16 can be suppressed.

  Note that the contact hole 11 on the left side of FIG. 6 and the contact hole 11 on the right side of FIG. 6 are filled with the conductor 13 having the same particle size and subjected to the CMP process described with reference to FIG. And normal plugs 12 and 13 are created. In this case, although different from FIG. 30, the uneven region G1 is also formed on the upper surfaces of the normal plugs 12 and 13. However, even if the uneven region G1 is formed in the normal plugs 12 and 13, there is no particular problem in terms of electrical characteristics.

  If the normal plugs 12 and 13 and the lower plugs 12 and 13 are made of different constituent materials, the normal plugs 12 and 13 and the lower plugs 12 and 13 are formed by CMP processing under different conditions. Thereby, as shown in FIG. 30, the uneven | corrugated | grooved area | region G1 can be formed also only in the upper surface of the lower plugs 12 and 13. FIG. For example, a material having a small particle diameter such as copper is used as the conductor 13 that normally fills the plugs 12 and 13. On the other hand, a material having a large particle diameter such as tungsten is used as the conductor 13 filling the lower plugs 12 and 13. Thereby, as shown in FIG. 30, the uneven | corrugated | grooved area | region G1 can be formed also only in the upper surface of the lower plugs 12 and 13. FIG.

  In this embodiment, a MOS transistor is used for memory driving. However, instead of the MOS transistor 50, a bipolar transistor, a diode, and other driving semiconductor devices can be employed. Further, the conductivity type of the transistor may be N-type or P-type.

  The grain size of polysilicon can be changed by the film forming conditions and the subsequent annealing treatment. That is, the grain size of polysilicon can be 10 nm or more when the manufacturing method is changed. Therefore, polysilicon may be adopted as the constituent material of the conductor 13.

  For example, when forming a TFT (Thin Film Transistor), it is known that the particle size of polysilicon particles is about 200 nm. Therefore, the uneven region G <b> 1 can be formed on the upper surface of the conductor 13 by adopting the polysilicon having a large particle size and performing CMP processing with reduced flatness.

1 is a cross-sectional view showing a configuration of a semiconductor device (phase change memory) according to a first embodiment. FIG. 6 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device (phase change memory) according to the first embodiment. FIG. 6 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device (phase change memory) according to the first embodiment. FIG. 6 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device (phase change memory) according to the first embodiment. FIG. 6 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device (phase change memory) according to the first embodiment. FIG. 6 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device (phase change memory) according to the first embodiment. FIG. 6 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device (phase change memory) according to the first embodiment. FIG. 6 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device (phase change memory) according to the first embodiment. FIG. 6 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device (phase change memory) according to the first embodiment. It is an expanded sectional view showing the composition near the upper surface of the lower plug. FIG. 6 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device (phase change memory) according to the first embodiment. It is an expanded sectional view showing the composition near the upper surface of the lower plug. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device (phase change memory) according to a second embodiment. It is an expanded sectional view showing the composition near the upper surface of the lower plug. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the second embodiment. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device (phase change memory) according to a third embodiment. It is an expanded sectional view showing the composition near the upper surface of the lower plug. FIG. 11 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the third embodiment. FIG. 11 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the third embodiment. FIG. 11 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the third embodiment. FIG. 11 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the third embodiment. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device (phase change memory) according to a fourth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the fourth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the fourth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the fourth embodiment. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device (phase change memory) according to a fifth embodiment. It is an expanded sectional view showing the composition near the upper surface of the lower plug. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device (phase change memory) according to the fifth embodiment.

Explanation of symbols

  1 semiconductor substrate, 2 element isolation film, 3 gate insulating film, 4 gate electrode, 5 low concentration extension region, 6 side wall film, 7 high concentration impurity region, 8, 9 silicide layer, 10 interlayer insulating film, 10s, 10w Oxide film, 10t nitride film, 11 contact hole, 11d recess, 12 barrier metal, 13 conductor, 12 + 13 lower plug, 14 depression, 15 insulating film, 16 phase change film, 17 upper electrode, 50 MOS transistor for memory drive, 80 phase change memory, 100 semiconductor device, K1 gap, L1 protrusion, G1 uneven region.

Claims (7)

A phase change film capable of changing into a crystalline state and an amorphous state;
A lower plug connecting the phase change film and a lower layer configuration than the phase change film;
An insulating film formed between the lower plug and the phase change film,
In the portion connected to the phase change film, the lower plug is
Having a first region and a second region;
The thickness of the insulating film formed on the lower plug in the first region is
Zero or thinner than the thickness of the insulating film formed on the lower plug in the second region,
Phase change memory characterized by that. The insulating film is
TaO or CrO,
The thickness of the insulating film formed on the lower plug in the first region is
0 to less than 3 nm,
The film thickness of the insulating film formed on the lower plug in the second region is
3 nm or more,
The phase change memory according to claim 1. On the upper surface of the lower plug,
A dent that narrows toward the bottom is formed,
The recess of the lower plug is
The first region,
The phase change memory according to claim 1. The lower plug is
A barrier metal film formed on at least the side surface of the through hole in the interlayer insulating film;
A conductor formed in contact with the barrier metal film so as to fill the inside of the through hole;
The upper surface of the conductor is
Located below the upper end of the barrier metal film,
The barrier metal film from the upper end of the barrier metal film to the upper surface of the conductor is
The first region,
The phase change memory according to claim 1. The lower plug is
It is formed in the interlayer insulation film,
The lower plug is
Having a protruding portion protruding from the upper surface of the interlayer insulating film;
A side surface of the protruding portion is
The first region,
The phase change memory according to claim 1. The interlayer insulating film is
In order from the top surface, it has a laminated structure in which a nitride film and an oxide film are formed in that order.
The phase change memory according to claim 5. On the upper surface of the lower plug,
A plurality of convex portions and a plurality of concave portions are formed,
The vertex of the convex part is
At least the first region,
The phase change memory according to claim 1.

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