US20050180083A1 - Drive circuit for el display panel - Google Patents

Drive circuit for el display panel Download PDF

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Publication number
US20050180083A1
US20050180083A1 US10/511,448 US51144804A US2005180083A1 US 20050180083 A1 US20050180083 A1 US 20050180083A1 US 51144804 A US51144804 A US 51144804A US 2005180083 A1 US2005180083 A1 US 2005180083A1
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United States
Prior art keywords
current
transistors
transistor
pixel
driver
Prior art date
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Abandoned
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US10/511,448
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English (en)
Inventor
Hiroshi Takahara
Hitoshi Tsuge
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Japan Display Central Inc
Original Assignee
Toshiba Matsushita Display Technology Co Ltd
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Assigned to TOSHIBA MATSUSHITA DISPLAY TECHNOLOGY CO., LTD. reassignment TOSHIBA MATSUSHITA DISPLAY TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TAKAHARA, HIROSHI, TSUGE, HITOSHI
Publication of US20050180083A1 publication Critical patent/US20050180083A1/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
    • G—PHYSICS
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H—ELECTRICITY
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K50/844—Encapsulations
    • H—ELECTRICITY
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    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/846—Passivation; Containers; Encapsulations comprising getter material or desiccants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K50/87—Arrangements for heating or cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/30—Devices specially adapted for multicolour light emission
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    • H—ELECTRICITY
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    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H—ELECTRICITY
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/80—Constructional details
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/80—Constructional details
    • H10K59/8794—Arrangements for heating and cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/861—Repairing

Definitions

  • the present invention relates to a self-luminous display panel such as an EL display panel which employs organic or inorganic electroluminescent (EL) elements as well as to a drive circuit (IC) for the display panel. Also, it relates to an information display apparatus and the like which employ the EL display panel, a drive method for the EL display panel, and the drive circuit for the EL display panel.
  • a self-luminous display panel such as an EL display panel which employs organic or inorganic electroluminescent (EL) elements as well as to a drive circuit (IC) for the display panel.
  • IC drive circuit
  • active-matrix display apparatus display images by arranging a large number of pixels in a matrix and controlling the light intensity of each pixel according to a video signal. For example, if liquid crystals are used as an electrochemical substance, the transmittance of each pixel changes according to a voltage written into the pixel. With active-matrix display apparatus which employ an organic electroluminescent (EL) material as an electrochemical substance, emission brightness changes according to current written into pixels.
  • EL organic electroluminescent
  • each pixel works as a shutter, and images are displayed as a backlight is blocked off and revealed by the pixels or shutters.
  • An organic EL display panel is of a self-luminous type in which each pixel has a light-emitting element. Consequently, organic EL display panels have the advantages of being more viewable than liquid crystal display panels, requiring no backlighting, having high response speed, etc.
  • Brightness of each light-emitting element (pixel) in an organic EL display panel is controlled by an amount of current. That is, organic EL display panels differ greatly from liquid crystal display panels in that light-emitting elements are driven or controlled by current.
  • a construction of organic EL display panels can be either a simple-matrix type or active-matrix type. It is difficult to implement a large high-resolution display panel of the former type although the former type is simple in structure and inexpensive. The latter type allows a large high-resolution display panel to be implemented, but involves a problem that it is a technically difficult control method and is relatively expensive.
  • active-matrix type display panels are developed intensively. In the active-matrix type display panel, current flowing through the light-emitting elements provided in each pixel is controlled by thin-film transistors (transistors) installed in the pixels.
  • a pixel 16 consists of an EL element 15 which is a light-emitting element, a first transistor 11 a, a second transistor 11 b, and a storage capacitance 19 .
  • the EL element 15 is an organic electroluminescent (EL) element.
  • the transistor 11 a which supplies (controls) current to the EL element 15 is referred to as a driver transistor 11 .
  • a transistor, such as the transistor 11 b shown in FIG. 62 which operates as a switch is referred to as a switching transistor 11 .
  • the organic EL element 15 in many cases, may be referred to as an OLED (organic light-emitting diode) because of its rectification.
  • OLED organic light-emitting diode
  • FIG. 62 or the like a diode symbol is used for the EL element 15 .
  • the EL element 15 is not limited to an OLED. It may be of any type as long as its brightness is controlled by the amount of current flowing through the element 15 . Examples include an inorganic EL element, a white light-emitting diode consisting of a semiconductor, atypical light-emitting diode, and a light-emitting transistor. Rectification is not necessarily required of the EL element 15 . Bidirectional diodes are also available.
  • the EL element 15 according to the present specification may be any of the above elements.
  • a source terminal (S) of the P-channel transistor 11 a is designated as Vdd (power supply potential) and a cathode of the EL element 15 is connected to ground potential (Vk).
  • Vdd power supply potential
  • a cathode of the EL element 15 is connected to ground potential (Vk).
  • an anode is connected to a drain terminal (D) of the transistor 11 b.
  • a gate terminal of the P-channel transistor 11 a is connected to a gate signal line 17 a
  • a source terminal is connected to a source signal line 18
  • a drain terminal is connected to the storage capacitance 19 and a gate terminal (G) of the P-channel transistor 11 a.
  • a video signal which represents brightness information is first applied to the source signal line 18 with the gate signal line 17 a selected. Then, the transistor 11 a conducts, the storage capacitance 19 is charged or discharged, and gate potential of the transistor 11 b matches the potential of the video signal.
  • the gate signal line 17 a is deselected, the transistor 11 a is turned off and the transistor 11 b is cut off electrically from the source signal line 18 .
  • the gate potential of the transistor 11 a is maintained stably by the storage capacitance (capacitor) 19 .
  • Current delivered to the EL element 15 via the transistor 11 a depends on gate-source voltage Vgs of the transistor 11 a and the EL element 15 continues to emit light at an intensity which corresponds to the amount of current supplied via the transistor 11 a.
  • liquid crystal display panels are not self-luminous devices, there is a problem that they cannot display images without backlighting. Also, there has been a problem that a certain thickness is required to provide a backlight, which makes the display panel thicker. Besides, to display colors on a liquid crystal display panel, color filters must be used. Therefore, there has been a problem of the lowered usability of light. Also, there has been the problem of narrow color reproduction range.
  • Organic EL display panels are made of low-temperature polysilicon transistor arrays.
  • organic EL elements use current to emit light, there has been a problem that variations in the characteristics of the transistors will cause display irregularities.
  • the display irregularities can be reduced using current programming of pixels.
  • a current-driven driver circuit is required for current programming.
  • variations will also occur in transistor elements which compose a current output stage. This in turn causes variations in gradation output currents from output terminals, making it impossible to display images properly.
  • a driver circuit for an EL display panel comprises a plurality of transistors which output unit currents and produces an output current by varying the number of transistors.
  • the driver circuit is characterized by comprising a multi-stage current mirror circuit.
  • a transistor group which delivers signals via voltages is formed densely.
  • signals are delivered between the transistor group and current mirror circuit group via currents.
  • reference currents are produced by a plurality of transistors.
  • a first invention of the present invention is a driver circuit for an EL display panel comprising:
  • a second invention of the present invention is a driver circuit for an EL display panel comprising:
  • a third invention of the present invention is the driver circuit for an EL display panel according to the second invention of the present invention, wherein:
  • a fourth invention of the present invention is the driver circuit for an EL display panel according to the second invention of the present invention, wherein:
  • power supply voltage used is between 2.5 V and 9 V both inclusive.
  • a fifth invention of the present invention is a driver circuit for an EL display panel comprising:
  • a sixth invention of the present invention is a driver circuit for an EL display panel comprising:
  • a seventh invention of the present invention is the driver circuit for an EL display panel according to the sixth invention of the present invention, comprising:
  • An eighth invention of the present invention is the driver circuit for an EL display panel according to the sixth or seventh invention of the present invention, wherein in a driver IC chip which includes the driver circuit, the third transistor is electrically connected, in an area in which the first reference current supply wirings are placed, to two outermost placed wirings of the reference current supply wiring group placed in the area.
  • a ninth invention of the present invention is an EL display apparatus comprising:
  • a tenth invention of the present invention is the EL display apparatus according to the ninth invention of the present invention, wherein the first wiring has a light shielding function.
  • An eleventh invention of the present invention is an EL display apparatus comprising:
  • a twelfth invention of the present invention is an EL display apparatus comprising:
  • a thirteenth invention of the present invention is an EL display apparatus comprising:
  • FIG. 1 is a block diagram of a pixel in a display panel according to the present invention.
  • FIG. 2 is a block diagram of a pixel in a display panel according to the present invention.
  • FIG. 3 is an explanatory diagram illustrating operation of a display panel according to the present invention.
  • FIG. 4 is an explanatory diagram illustrating operation of a display panel according to the present invention.
  • FIG. 5 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 6 is a block diagram of a display apparatus according to the present invention.
  • FIG. 7 is an explanatory diagram illustrating a manufacturing method of a display panel according to the present invention.
  • FIG. 8 is a block diagram of a display apparatus according to the present invention.
  • FIG. 9 is a block diagram of a display apparatus according to the present invention.
  • FIG. 10 is a sectional view of a display panel according to the present invention.
  • FIG. 11 is a sectional view of a display panel according to the present invention.
  • FIG. 12 is an explanatory diagram illustrating a display panel according to the present invention.
  • FIG. 13 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 14 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 15 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 16 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 17 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 18 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 19 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 20 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 21 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 22 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 23 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 24 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 25 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 26 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 27 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 28 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 29 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 30 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 31 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 32 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 33 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 34 is a block diagram of a display apparatus according to the present invention.
  • FIG. 35 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 36 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 37 is a block diagram of a display apparatus according to the present invention.
  • FIG. 38 is a block diagram of a display apparatus according to the present invention.
  • FIG. 39 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 40 is a block diagram of a display apparatus according to the present invention.
  • FIG. 41 is a block diagram of a display apparatus according to the present invention.
  • FIG. 42 is a block diagram of a pixel in a display panel according to the present invention.
  • FIG. 43 is a block diagram of a pixel in a display panel according to the present invention.
  • FIG. 44 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 45 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 46 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 47 is a block diagram of a pixel in a display panel according to the present invention.
  • FIG. 48 is a block diagram of a display apparatus according to the present invention.
  • FIG. 49 is an explanatory diagram illustrating a drive circuit according to the present invention.
  • FIG. 50 is a block diagram of a pixel in a display panel according to the present invention.
  • FIG. 51 is a diagram of a pixel in a display panel according to the present invention.
  • FIG. 52 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 53 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 54 is a block diagram of a pixel in a display panel according to the present invention.
  • FIG. 55 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 56 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention.
  • FIG. 57 is an explanatory diagram illustrating a cell phone according to the present invention.
  • FIG. 58 is an explanatory diagram illustrating a viewfinder according to the present invention.
  • FIG. 59 is an explanatory diagram illustrating a video camera according to the present invention.
  • FIG. 60 is an explanatory diagram illustrating a digital camera according to the present invention.
  • FIG. 61 is an explanatory diagram illustrating a TV (monitor) according to the present invention.
  • FIG. 62 is a block diagram of a pixel in a conventional display panel
  • FIG. 63 is a functional block diagram of a driver circuit according to the present invention.
  • FIG. 64 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 65 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 66 is an explanatory diagram illustrating a voltage-based delivery type multi-stage current mirror circuit
  • FIG. 67 is an explanatory diagram illustrating a current-based delivery type multi-stage current mirror circuit
  • FIG. 68 is an explanatory diagram illustrating a driver circuit according to another example of the present invention.
  • FIG. 69 is an explanatory diagram illustrating a driver circuit according to another example of the present invention.
  • FIG. 70 is an explanatory diagram illustrating a driver circuit according to another example of the present invention.
  • FIG. 71 is an explanatory diagram illustrating a driver circuit according to another example of the present invention.
  • FIG. 72 is an explanatory diagram illustrating a conventional driver circuit
  • FIG. 73 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 74 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 75 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 76 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 77 is an explanatory diagram illustrating a control method of a driver circuit according to the present invention.
  • FIG. 78 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 79 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 80 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 81 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 82 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 83 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 84 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 85 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 86 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 87 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 88 is an explanatory diagram illustrating a drive method according to the present invention.
  • FIG. 89 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 90 is an explanatory diagram illustrating a drive method according to the present invention.
  • FIG. 91 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 92 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 93 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 94 is an explanatory diagram illustrating a driver circuit according to the present invention.
  • FIG. 95 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 96 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 97 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 98 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 99 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 100 is a sectional view of an EL display apparatus according to the present invention.
  • FIG. 101 is a sectional view of an EL display apparatus according to the present invention.
  • FIG. 102 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 103 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 104 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 105 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 106 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 107 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 108 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 109 is a block diagram of an EL display apparatus according to the present invention.
  • FIG. 110 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 111 is a block diagram of a gate driver circuit according to the present invention.
  • FIG. 112 is a timing chart of the gate driver circuit shown in FIG. 111 ;
  • FIG. 113 is a block diagram of part of a gate driver circuit according to the present invention.
  • FIG. 114 is a timing chart of the gate driver circuit shown in FIG. 113 ;
  • FIG. 115 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 116 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 117 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 118 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 119 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 120 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 121 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 122 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 123 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 124 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 125 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 126 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 127 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 128 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 129 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 130 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 131 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 132 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 133 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 134 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 135 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 136 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 137 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 138 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 139 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 140 is an explanatory diagram illustrating a display panel according to the present invention.
  • FIG. 141 is an explanatory diagram illustrating a display panel according to the present invention.
  • FIG. 142 is an explanatory diagram illustrating a display panel according to the present invention.
  • FIG. 143 is an explanatory diagram illustrating a display panel according to the present invention.
  • FIG. 144 is a block diagram of a pixel in a display panel according to the present invention.
  • FIG. 145 is a block diagram of a pixel in a display panel according to the present invention.
  • FIG. 146 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 147 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 148 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 149 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 150 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 151 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 152 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 153 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 154 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 155 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 156 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 157 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 158 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 159 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 160 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 161 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 162 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 163 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 164 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 165 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 166 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 167 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 168 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 169 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 170 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 171 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 172 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 173 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 174 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 175 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 176 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 177 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 178 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 179 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 180 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 181 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 182 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 183 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 184 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 185 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 186 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 187 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 188 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 189 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 190 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 191 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 192 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 193 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 194 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 195 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 196 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 197 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 198 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 199 is an explanatory diagram illustrating a drive circuit of an EL display apparatus according to the present invention.
  • FIG. 200 is an explanatory diagram illustrating a drive method of an EL display apparatus according to the present invention.
  • FIG. 201 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 202 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 203 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 204 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 205 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 206 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 207 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 208 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 209 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 210 is an explanatory diagram illustrating an EL display apparatus according to the present invention.
  • FIG. 211 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 212 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 213 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 214 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 215 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 216 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 217 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 218 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 219 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 220 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 221 is an explanatory diagram illustrating a display apparatus according to the present invention.
  • FIG. 222 is an explanatory diagram illustrating a display apparatus according to the present invention.
  • FIG. 223 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 224 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 225 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 226 is an explanatory diagram illustrating a source driver IC according to the present invention.
  • FIG. 227 is an explanatory diagram illustrating a display apparatus according to the present invention.
  • FIG. 228 is an explanatory diagram illustrating a display apparatus according to the present invention.
  • FIG. 11 a thin encapsulation film 111 and the like are shown as being fairly thick.
  • FIG. 10 a sealing lid 85 is shown as being thin.
  • Some parts are omitted.
  • the display panel according to the present invention requires a phase film such as a circular polarizing plate to prevent reflection, the phase film is omitted in drawings herein. This also applies to the drawings below.
  • the same or similar forms, materials, functions, or operations are denoted by the same reference numbers or characters.
  • a touch panel or the like can be attached to a display panel in FIG. 8 to provide an information display apparatus shown in FIGS. 19 and 59 to 61 .
  • a magnifying lens 1582 can be mounted to configure a view finder (see FIG. 58 ) used for a video camera (see FIG. 159 , etc.) or the like.
  • drive methods described with reference to FIG. 4, 15 , 18 , 21 , 23 , etc. can be applied to any display apparatus or display panel according to the present invention.
  • thin-film transistors are cited herein as driver transistors 11 and switching transistors 11 , this is not restrictive. Thin-film diodes (TFDs) or ring diodes may be used instead. Also, the present invention is not limited to thin-film elements, and transistors formed on silicon wafers may also be used. In this case, a board 71 can be made of a silicon wafer. Needless to say, FETs, MOS-FETs, MOS transistors, or bipolar transistors may also be used. They are basically, thin-film transistors. It goes without saying that the present invention may also use varistors, thyristors, ring diodes, photodiodes, phototransistors, or PLZT elements. That is, the transistor 11 , gate driver circuit 12 , and source driver circuit 14 according to the present invention can use any of the above elements.
  • an organic EL display panel consists of a glass substrate (array board) 71 , transparent electrodes 105 formed as pixel electrodes, at least one organic functional layer (EL layer) 15 , and a metal electrode (reflective film) (cathode) 106 , which are stacked one on top of another, where the organic functional layer consists of an electron transport layer, light-emitting layer, positive hole transport layer, etc.
  • the organic functional layer (EL layer) 15 emits light when a positive voltage is applied to the anode or transparent electrodes (pixel electrodes) 105 and a negative voltage is applied to the cathode or metal electrode (reflective electrode) 106 , i.e., when a direct current is applied between the transparent electrodes 105 and metal electrode 106 .
  • the metal electrode 106 is made of metal with a small work function, such as lithium, silver, aluminum, magnesium, indium, copper, or an alloy thereof. In particular, it is preferable to use, for example, an Al—Li alloy.
  • the transparent electrodes 105 may be made of, conductive materials with a large work function such as ITO, or gold and the like. If gold is used as an electrode material, the electrodes become translucent. Incidentally, IZO or other material may be used instead of ITO. This also applies to other pixel electrodes 105 .
  • a desiccant 107 is placed in a space between the sealing lid 85 and array board 71 . This is because the organic EL film 15 is vulnerable to moisture. The desiccant 107 absorbs water penetrating a sealant and thereby prevents deterioration of the organic EL film 15 .
  • the film 111 (this may be a thin film, i.e., a thin encapsulation film) may be used for sealing as shown in FIG. 11 .
  • the encapsulation film (thin encapsulation film) 111 may be, for example, an electrolytic capacitor film on which DLC (diamond-like carbon) is vapor-deposited. This film features extremely low moisture penetration (high moisture resistance) It is used as the thin encapsulation film 111 . Also, it goes without saying that DLC diamond-like carbon) film may be vapor-deposited directly on a surface of the metal electrode 106 .
  • the thin encapsulation film may be formed by laminating thin resin films and metal films.
  • film thickness of the thin film is such that n ⁇ d is equal to or less than main emission wavelength ⁇ of the EL element 15 (where n is the refraction factor of the thin film, or the sum of refraction factors if two or more thin films are laminated (n ⁇ d of each thin film is calculated); d is the film thickness of the thin film, or the sum of refraction factors if two or more thin films are laminated).
  • n is the refraction factor of the thin film, or the sum of refraction factors if two or more thin films are laminated
  • d is the film thickness of the thin film, or the sum of refraction factors if two or more thin films are laminated.
  • thin film encapsulation A technique which uses a thin encapsulation film 111 for sealing instead of a sealing lid 85 as described above is called thin film encapsulation.
  • thin film encapsulation involves forming an EL film and then forming an aluminum electrode which will serve as a cathode on the EL film. Then, a resin layer is formed as a cushioning layer on the aluminum layer. An organic material such as acrylic or epoxy may be used for a cushioning layer. Suitable film thickness is from 1 ⁇ m to 10 ⁇ m (both inclusive).
  • the film thickness is from 2 ⁇ m to 6 ⁇ m (both inclusive).
  • the encapsulation film 74 is formed on the cushioning film. Without the cushioning film, structure of the EL film would be deformed by stress, resulting in streaky defects.
  • the thin encapsulation film 111 may be made, for example, of DLC (diamond-like carbon) or an electrolytic capacitor of a laminar structure (structure consisting of thin dielectric films and aluminum films vapor-deposited alternately).
  • thin film encapsulation involves forming the EL film 15 and then forming an Ag—Mg film 20 angstrom (inclusive) to 300 angstrom thick on the EL film 15 to serve as a cathode (anode).
  • a transparent electrode such as ITO is formed on the film to reduce resistance.
  • a resin layer is formed as a cushioning layer on the electrode film.
  • a thin encapsulation film 111 is formed on the cushioning film.
  • Half the light produced by the organic EL layer 15 is reflected by the metal electrode 106 and emitted through the array board 71 .
  • the metal electrode 106 reflects extraneous light, resulting in glare, which lowers display contrast.
  • a ⁇ /4 phase plate 108 and polarizing plate (polarizing film) 109 are placed on the array board 71 . These are generally called circular polarizing plates (circular polarizing sheets).
  • the pixels are reflective electrodes, the light produced by the organic EL layer 15 is emitted upward.
  • the phase plate 108 and polarizing plate 109 are placed on the side from which light is emitted.
  • Reflective pixels can be obtained by making pixel electrodes 105 from aluminum, chromium, silver, or the like. Also, by providing projections (or projections and depressions) on a surface of the pixel electrodes 105 , it is possible to increase an interface with the organic EL layer 15 , and thereby increase the light-emitting area, resulting in improved light-emission efficiency.
  • the reflective film which serves as the cathode 106 (anode 105 ) is made as a transparent electrode. If reflectance can be reduced to 30% or less, no circular polarizing plate is required. This is because glare is reduced greatly. Light interference is reduced as well.
  • LDD low doped drain
  • OEL organic EL elements
  • PEL PLED
  • OLED organic EL elements
  • An organic EL display panel of active-matrix type must satisfy two conditions: that it is capable of selecting a specific pixel and give necessary display information and that it is capable of passing current through the EL element throughout one frame period.
  • a switching transistor is used as a first transistor 11 b to select the pixel and a driver transistor is used as a second transistor 11 a to supply current to an EL element (EL film) 15 .
  • the turn-on current of a transistor is extremely uniform if the transistor is monocrystalline.
  • its threshold varies in a range of ⁇ 0.2 V to 0.5 V.
  • the turn-on current flowing through the driver transistor 11 a varies accordingly, causing display irregularities.
  • the irregularities are caused not only by variations in the threshold voltage, but also by mobility of the transistor and thickness of a gate insulating film. Characteristics also change due to degradation of the transistor 11 .
  • This phenomenon is not limited to low-temperature polysilicon technologies, and can occur in transistors formed on semiconductor films grown in solid-phase (CGS) by high-temperature polysilicon technology at a process temperature of 450 degrees (centigrade) or higher. Besides, the phenomenon can occur in organic transistors and amorphous silicon transistors.
  • the present invention provides a configuration or scheme which can accommodate the above technologies. Description will be given herein mainly of transistors produced by the low-temperature polysilicon technology.
  • Each pixel structure in an EL display panel according to the present invention comprises at least four transistors 11 and an EL element as shown concretely in FIG. 1 .
  • Pixel electrodes are configured to overlap with a source signal line.
  • the pixel electrodes 105 are formed on an insulating film or planarized acrylic film formed on the source signal line 18 for insulation.
  • a structure in which pixel electrodes overlap with at least part of the source signal line 18 is known as a high aperture (HA) structure. This reduces unnecessary light interference and allows proper light emission.
  • HA high aperture
  • the gate signal line (first scanning line) 17 a When the gate signal line (first scanning line) 17 a is activated (a turn-on voltage is applied), a current to be passed through the EL element 15 is delivered from the source driver circuit 14 via the driver transistor 11 a and switching transistor 11 c of the EL element 15 . Also, upon activation of (application of a turn-on voltage to) the gate signal line 17 a, the transistor 11 b opens to cause a short circuit between gate and drain of the transistor 11 a and gate voltage (or drain voltage) of the transistor 11 a is stored in a capacitor (storage capacitance, additional capacitance) 19 connected between the gate and drain of the transistor 11 a (see FIG. 3 ( a )).
  • the capacitor (storage capacitance) 19 should be from 0.2 pF to 2 pF both inclusive. More preferably, the capacitor (storage capacitance) 19 should be from 0.4 pF to 1.2 pF both inclusive.
  • the capacity of the capacitor 19 is determined taking pixel size into consideration. If the capacity needed for a single pixel is Cs (pF) and an area (rather than an aperture ratio) occupied by the pixel is Sp (square ⁇ m), a condition 500/Sp ⁇ Cs ⁇ 20000/Sp, and more preferably a condition 1000/Sp ⁇ Cs ⁇ 10000/Sp should be satisfied. Since gate capacity of the transistor is small, Q as referred to here is the capacity of the storage capacitance (capacitor) 19 alone.
  • the gate signal line 17 a is deactivated (a turn-off voltage is applied), a gate signal line 17 b is activated, and a current path is switched to a path which includes the first transistor 11 a, a transistor 11 d connected to the EL element 15 , and the EL element 15 to deliver the stored current to the EL element 15 (see FIG. 3 ( b )).
  • a single pixel contains four transistors 11 .
  • the gate of the transistor 11 a is connected to the source of the transistor 11 b.
  • the gates of the transistors 11 b and 11 c are connected to the gate signal line 17 a.
  • the drain of the transistor 11 b is connected to the source of the transistor 11 c and source of the transistor 11 d.
  • the drain of the transistor 11 c is connected to the source signal line 18 .
  • the gate of the transistor 11 d is connected to the gate signal line 17 b and the drain of the transistor 11 d is connected to the anode electrode of the EL element 15 .
  • all the transistors in FIG. 1 are P-channel transistors. Compared to N-channel transistors, P-channel transistors have more or less lower mobility, but they are preferable because they are more resistant to voltage and degradation.
  • the EL element according to the present invention is not limited to P-channel transistors and the present invention may employ N-channel transistors alone. Also, the present invention may employ both N-channel and P-channel transistors.
  • P-channel transistors should be used for all the transistors 11 composing pixels as well as for the built-in gate drivers 12 .
  • the EL element according to the present invention is controlled using two timings.
  • the first timing is the one when required current values are stored. Turning on the transistor 11 b and transistor 11 c with this timing provides an equivalent circuit shown in FIG. 3 ( a ).
  • a predetermined current Iw is applied from signal lines. This makes the gate and drain of the transistor 11 a connected, allowing the current Iw to flow through the transistor 11 a and transistor 11 c.
  • the gate-source voltage of the transistor 11 a is such that allows I1 to flow.
  • the second timing is the one when the transistor 11 a and transistor 11 c are closed and the transistor 11 d is opened.
  • the equivalent circuit available at this time is shown in FIG. 3 ( b ).
  • the source-gate voltage of the transistor 11 a is maintained. In this case, since the transistor 11 a always operates in a saturation region, the current Iw remains constant.
  • reference numeral 51 a in FIG. 5 ( a ) denotes a pixel (row) (write pixel row) programmed with current at a certain time point in a display screen 50 .
  • the pixel row 51 a is non-illuminated (non-display pixel (row)) as illustrated in FIG. 5 ( b ).
  • Other pixels (rows) are display pixels (rows) 53 (current flows through the EL elements 15 of the non-pixels 53 in the display area 53 , causing the EL elements 15 to emit light).
  • the programming current Iw flows through the source signal line 18 during current programming as shown in FIG. 3 ( a ).
  • the current Iw flows through the transistor 11 a and voltage is set (programmed) in the capacitor 19 in such a way as to maintain the current Iw.
  • the transistor 11 d is open (off).
  • the transistors 11 c and 11 b turn off and the transistor 11 d turns on as shown in FIG. 3 ( b ).
  • a turn-off voltage (Vgh) is applied to the gate signal line 17 a, turning off the transistors 11 b and 11 c.
  • a turn-on voltage (Vgl) is applied to the gate signal line 17 b, turning on the transistor 11 d.
  • a timing chart is shown in FIG. 4 .
  • the subscripts in brackets in FIG. 4 (e.g., ( 1 )) indicate pixel row numbers.
  • a gate signal line 17 a ( 1 ) denotes a gate signal line 17 a in a pixel row ( 1 ).
  • *H (where “*” is an arbitrary symbol or numeral and indicates a horizontal scanning line number) in the top row in FIG. 4 indicates a horizontal scanning period.
  • 1H is a first horizontal scanning period.
  • the items (1H number, 1-H cycle, order of pixel row numbers, etc.) described above are intended to facilitate explanation and are not intended to be restrictive.
  • the gate of the transistor 11 a and gate of the transistor 11 c are connected to the same gate signal line 11 a.
  • the gate of the transistor 11 a and gate of the transistor 11 c may be connected to different gate signal lines 11 (see FIG. 32 ). Then, one pixel will have three gate signal lines (two in the configuration in FIG. 1 ).
  • a write paths from signal lines are turned off according to operation timing of the present invention That is, when a predetermined current is stored, an accurate current value is not stored in a capacitance (capacitor) between the source (S) and gate (G) of the transistor 11 a if a current path is branched.
  • a capacitance capacitor between the source (S) and gate (G) of the transistor 11 a if a current path is branched.
  • the circuit described above can be implemented using four transistors at the minimum, but even if more than four transistors including a transistor 11 e are cascaded for more accurate timing control or for reduction of mirror effect (described later), the principle of operation is the same. By adding the transistor 11 e, it is possible to deliver programming current to the EL element 15 more precisely via the transistor 11 c.
  • the pixel configuration according to the present invention is not limited to those shown in FIGS. 1 and 2 .
  • pixels may be configured as shown in FIG. 140 .
  • FIG. 140 lacks the transistor 11 d unlike the configuration in FIG. 1 .
  • a changeover switch 1401 is formed or placed.
  • the switch 11 d in FIG. 1 functions to turn on and off (pass and shut off) the current delivered from the driver transistor 11 a to the EL element 15 .
  • the on/off control function of the transistor 11 d constitutes an important part of the present invention.
  • the configuration in FIG. 140 achieves the on/off function without using the transistor 11 d.
  • a terminal a of the changeover switch 1401 is connected to anode voltage Vdd.
  • the voltage applied to the terminal a is not limited to the anode voltage Vdd. It may be any voltage that can turn off the current flowing through the EL element 15 .
  • a terminal b of the changeover switch 1401 is connected to cathode voltage (indicated as ground in FIG. 140 ).
  • the voltage applied to the terminal b is not limited to the cathode voltage. It may be any voltage that can turn on the current flowing through the EL element 15 .
  • a terminal c of the changeover switch 1401 is connected with a cathode terminal of the EL element 15 .
  • the changeover switch 1401 may be of any type as long as it has a capability to turn on and off the current flowing through the EL element 15 .
  • its installation location is not limited to the one shown in FIG. 140 and the switch may be located anywhere on the path through which current is delivered to the EL element 15 .
  • the switch is not limited by its functionality as long as the switch can turn on and off the current flowing through the EL element 15 .
  • the present invention can have any pixel configuration as long as switching means capable of turning on and off the current flowing through the EL element 15 is installed on the current path for the EL element 15 .
  • the term “off” here does not mean a state in which no current flows, but it means a state in which the current flowing through the EL element 15 is reduced to below normal.
  • the changeover switch 1401 will require no explanation because it can be implemented easily by a combination of P-channel and N-channel transistors. For example, it can be implemented by two circuits of analog switches. Of course, the changeover switch 1401 can be constructed of only P-channel or N-channel transistors because it only turns off the current flowing through the EL element 15 .
  • the Vdd voltage is applied to the cathode terminal of the EL element 15 .
  • current does not flow through the EL element 15 regardless of the voltage state of voltage held by the gate terminal G of the driver transistor 11 a. Consequently, the EL element 15 is non-illuminated.
  • the changeover switch 1401 When the changeover switch 1401 is connected to the terminal b, the GND voltage is applied to the cathode terminal of the EL element 15 . Thus, current flows through the EL element 15 according to the state of voltage held by the gate terminal G of the driver transistor 11 a. Consequently, the EL element 15 is illuminated.
  • no switching transistor 11 d is formed between the driver transistor 11 a and the EL element 15 .
  • one pixel contains one driver transistor 11 a.
  • the present invention is not limited to this and one pixel may contain two or more driver transistors 11 a.
  • An example is shown in FIG. 144 , where one pixel contains two driver transistors 11 a 1 and 11 a 2 , whose gate terminals are connected to a common capacitor 19 .
  • By using a plurality of driver transistors 11 a it is possible to reduce variations in programming current.
  • the other part of the configuration is the same as those shown in FIG. 1 and the like, and thus description thereof will be omitted.
  • the current outputted by the driver transistor 11 a is passed through the EL element 15 and turned on and off by the switching transistor 11 d formed between the driver transistor 11 a and the EL element 15 .
  • the present invention is not limited to this.
  • another configuration is illustrated in FIG. 145 .
  • the current delivered to the EL element 15 is controlled by the driver transistor 11 a.
  • the current flowing through the EL element 15 is turned on and off by the transistor 11 d placed between the Vdd terminal and EL element 15 .
  • the transistor 11 d may be placed anywhere as long as it can control the current flowing through the EL element 15 .
  • the channel length of the first transistor 11 a is from 5 ⁇ m to 100 ⁇ m (both inclusive). More preferably, it is from 10 ⁇ m to 50 ⁇ m (both inclusive). This is probably because a long channel length L increases grain boundaries contained in the channel, reducing electric fields, and thereby suppressing kink effect.
  • circuit means which controls the current flowing through the EL element 15 is constructed, formed, or placed on the path along which current flows into the EL element 15 and the path along which current flows out of the EL element 15 (i.e., the current path for the EL element 15 ).
  • the configuration for use to control the path along which current flows into the EL element 15 is not limited to the pixel configuration in current-programming mode shown in FIG. 1, 140 , or the like.
  • the pixel configuration in voltage-programming mode shown in FIG. 141 can also be used.
  • placement of the transistor 11 d between the EL element 15 and driver transistor 11 a makes it possible to control the current flowing through the EL element 15 .
  • the switching circuit 1401 may be placed as shown in FIG. 140 .
  • a type of current programming by forming or placing a transistor 11 g as a switching element between the driver transistor 11 b and EL element 15 as shown in FIG. 142 , it is possible to turn on and off (control) the current flowing through the EL element 15 .
  • the transistor 11 g may be substituted with the changeover switch 1401 in FIG. 140 .
  • the switching transistors 11 d and 11 c in FIG. 142 are connected to a single gate signal line 17 a, the switching transistor 11 c may be controlled by a gate signal line 17 a 1 and the switching transistor 11 d may be controlled by a gate signal line 17 a 2 as shown in FIG. 143 .
  • the configuration in FIG. 143 makes pixel 16 control more versatile.
  • the transistors 11 b and 11 c may be N-channel transistors. Also, as shown in FIG. 42 ( b ), the transistors 11 c and 11 d may be P-channel transistors.
  • An object of the present invention is to propose a circuit configuration in which variations in transistor characteristics do not affect display. Four or more transistors are required for that. When determining circuit constants using transistor characteristics, it is difficult to determine appropriate circuit constants unless the characteristics of the four transistors are not consistent. Both thresholds of transistor characteristics and mobility of the transistors vary depending on whether the channel direction is horizontal or vertical with respect to the longitudinal axis of laser irradiation. Incidentally, variations are more of the same in both cases. However, the mobility and average threshold vary between the horizontal direction and vertical direction. Thus, it is desirable that all the transistors in a pixel have the same channel direction.
  • the capacitance value of the storage capacitance 19 is Cs and the turn-off current value of the second transistor 11 b is Ioff, preferably the following equation is satisfied. 3 ⁇ Cs/I off ⁇ 24 More preferably the following equation is satisfied. 6 ⁇ Cs/I off ⁇ 18
  • the turn-off current of the transistor 11 b By setting the turn-off current of the transistor 11 b to 5 pA or less, it is possible to reduce changes in the current flowing through the EL to 2% or less. This is because when leakage current increases, electric charges stored between the gate and source (across the capacitor) cannot be held for one field with no voltage applied. Thus, the larger the storage capacity of the capacitor 19 , the larger the permissible amount of the turn-off current. By satisfying the above equation, it is possible to reduce fluctuations in current values between adjacent pixels to 2% or less.
  • transistors composing an active matrix are p-channel polysilicon thin-film transistors and the transistor 11 b is a dual-gate or multi-gate transistor.
  • the transistor 11 b is a dual-gate or multi-gate transistor.
  • an ON/OFF ratio as possible is required of the transistor 11 b, which acts as a source-drain switch for the transistor 11 a.
  • By using a dual-gate or multi-gate structure for the transistor 11 b it is possible to achieve a high ON/OFF ratio.
  • the semiconductor films composing the transistors 11 in the pixel 16 are generally formed by laser annealing in low-temperature polysilicon technology. Variations in laser annealing conditions result in variations in transistor 11 characteristics. However, if the characteristics of the transistors 11 in the pixel 16 are consistent, it is possible to drive the pixel using current programming such as the one shown in FIG. 1 so that a predetermined current will flow through the EL element 15 . This is an advantage lacked by voltage programming.
  • the laser used is an excimer laser.
  • the semiconductor film formation according to the present invention is not limited to the laser annealing method.
  • the present invention may also use a heat annealing method and a method which involves solid-phase (CGS) growth.
  • CGS solid-phase
  • the present invention is not limited to the low-temperature polysilicon technology and may use high-temperature polysilicon technology.
  • the present invention moves a laser spot (laser irradiation range) 72 in parallel to the source signal line 18 as shown in FIG. 7 .
  • the laser spot 72 is moved in such a way as to align with one pixel row.
  • the number of pixel rows is not limited to one.
  • laser may be shot by treating RGB in FIG. 72 (three pixel columns in this case) as a single pixel 16 .
  • laser may be directed at two or more pixels at a time.
  • moving laser irradiation ranges may overlap (it is usual for moving laser irradiation ranges to overlap).
  • Pixels are constructed in such a way that three pixels of RGB will form a square shape.
  • each of the R, G, B pixels has oblong shape. Consequently, by performing annealing using an oblong laser spot 72 , it is possible to eliminate variations in the characteristics of the transistors 11 within each pixel. Also, the characteristics (mobility, Vt, S value, etc.) of the transistors 11 connected to the same source signal line 18 can be made uniform (i.e., although the transistors 11 connected to adjacent source signal lines 18 may differ in characteristics, the characteristics of the transistors 11 connected to the same source signal line can be made almost equal).
  • an annealing apparatus which emits the laser spot 72 recognizes positioning markers 73 a and 73 b on a glass substrate 74 (automatic positioning based on pattern recognition) and moves the laser spot 72 .
  • the positioning markers 73 are recognized by a pattern recognition apparatus.
  • the annealing apparatus (not shown) recognizes the positioning markers 73 and determines the location of the pixel column (makes the laser irradiation range 72 parallel to the source signal line 18 ). It emits the laser spot 72 in such a way as to overlap with the location of each pixel column for sequential annealing.
  • the laser annealing method (which involves emitting a linear laser spot in parallel to the source signal line 18 ) described with reference to FIG. 7 is used for current programming of an organic EL display panel, in particular.
  • the transistors 11 placed in the direction parallel to the source signal line have the same characteristics (the characteristics of the pixel transistors adjacent in the longitudinal direction are quite similar to each other). This reduces changes in the voltage level of the source signal lines when the pixels are driven by current, and thus reduces the chances of insufficient write current.
  • the current outputted from the source driver IC 14 does not have significant amplitude changes. If the transistors 11 a in FIG. 1 have the same characteristics and the currents used for current programming of pixels have the same value within the pixel column, the potential of the source signal line 18 during the current programming is constant. Thus, no potential fluctuation occurs in the source signal line 18 . If the transistors 11 a connected to the same source signal line 18 have almost the same characteristics, there should be no significant potential fluctuation in the source signal line 18 . This is also true to other current-programmable pixel configurations such as the one shown in FIG. 38 (thus, it is preferable to use the manufacturing method shown in FIG. 7 ).
  • a method which involves programming two or more pixel rows simultaneously and which are described with reference to FIGS. 27, 30 , etc. can achieve a uniform image display (because the method is not prone to display irregularities due mainly to variations in transistor characteristics)
  • FIG. 27 , etc. since a plurality of pixel rows are selected simultaneously, if the transistors in adjacent pixel rows are uniform, irregularities in the characteristics of the transistors placed in the lengthwise direction can be absorbed by the source driver circuit 14 .
  • the source driver circuit 14 may be formed in the same process as the pixel 16 .
  • the present invention ensures that a voltage threshold Vth 2 of the driver transistor 11 b will not fall below a voltage threshold Vth 1 of the corresponding driver transistor 11 a in the pixel.
  • gate length L 2 of the transistor 11 b is made longer than gate length L 1 of the transistor 11 a so that Vth 2 will not fall below Vth 1 even if process parameters of these thin-film transistors change. This makes it possible to suppress subtle current leakage.
  • the pixel in FIG. 38 consists of a driver transistor 11 a through which a signal current flows, a driver transistor 11 b which controls drive current flowing through a light-emitting element such as an EL element 15 , a transistor 11 c which connects or disconnects a pixel circuit and data line “data” by controlling a gate signal line 17 a 1 , a switching transistor 11 d which shorts the gate and drain of the transistor 11 a during a write period by controlling a gate signal line 17 a 2 , a capacitance C 19 which holds gate-source voltage of the transistor 11 a after application of voltage, the EL element 15 serving as a light-emitting element, etc.
  • the transistors 11 c and 11 d are N-channel transistors and other transistors are P-channel transistors, but this is only exemplary and are not restrictive.
  • a capacitance Cs has its one end connected to the gate of the transistor 11 a, and the other end to Vdd (power supply potential), but it may be connected to any fixed potential instead of Vdd.
  • the cathode (negative pole) of the EL element 15 is connected to the ground potential.
  • FIG. 6 is an explanatory diagram which mainly illustrates a circuit of the EL display apparatus.
  • Pixels 16 are arranged or formed in a matrix.
  • Each pixel 16 is connected with a source driver circuit 14 which outputs current for use in current programming of the pixel.
  • a source driver circuit 14 which outputs current for use in current programming of the pixel.
  • current mirror circuits (described later) corresponding to the bit count of a video signal. For example, if 64 gradations are used, 63 current mirror circuits are formed on respective source signal lines so as to apply desired current to the source signal lines 18 when an appropriate number of current mirror circuits is selected (see FIG. 64 ).
  • the minimum output current of one current mirror circuit is from 10 nA to 50 nA (both inclusive).
  • the minimum output current of the current mirror circuit should be from 15 nA to 35 nA (both inclusive) to secure accuracy of the transistors composing the current mirror circuit in the source driver IC 14 .
  • a precharge or discharge circuit is incorporated to charge or discharge the source signal line 18 forcibly.
  • voltage (current) output values of the precharge or discharge circuit which charges or discharges the source signal line 18 forcibly can be set separately for R, G, and B. This is because the thresholds of the EL element 15 differ among R, G, and B (regarding the precharge circuit refer to FIGS. 70 and 173 and its explanation).
  • Organic EL elements are known to have heavy temperature dependence (temperature characteristics).
  • reference current is adjusted (varied) in an analog fashion by adding nonlinear elements such as thermistors or posistors to the current mirror circuits to vary output current and adjusting the changes due to the temperature characteristics with the thermistors or the like.
  • the source driver 14 is made of a semiconductor silicon chip and connected with a terminal on the source signal line 18 of the board 71 by glass-on-chip (COG) technology.
  • the source driver 14 can be mounted not only by the COG technology. It is also possible to mount the source driver circuit 14 by chip-on-film (COF) technology and connect it to the signal lines of the display panel.
  • the driver IC it may be made of three chips by constructing a power supply IC 82 separately.
  • Panel is tested before the source driver IC 14 is mounted.
  • the test is conducted by applying a constant current to the source signal lines 18 .
  • the constant current is applied by attaching lead wires 2271 to the pads 1522 formed on the ends of the source signal lines 18 and forming test pads 2272 on their ends as illustrated in FIG. 227 .
  • test pads 2272 By forming the test pads 2272 , it is possible to conduct the test without using the pads 1522 .
  • the gate driver circuit 12 is formed by low-temperature polysilicon technology. That is, it is formed in the same process as the transistors in pixels. This is because the gate driver 12 has a simpler internal structure and lower operating frequency than the source driver circuit 14 . Thus, it can be formed easily even by low-temperature polysilicon technology and allows bezel width to be reduced.
  • the gate driver circuit 12 it is possible to construct the gate driver circuit 12 from a silicon chip and mount it on the board 71 using the COG technology.
  • switching elements such as pixel transistors as well as gate drivers may be formed by high-temperature polysilicon technology or may be formed of an organic material (organic transistors).
  • the gate driver 12 incorporates a shift register circuit 61 a for a gate signal line 17 a and a shift register circuit 61 b for a gate signal line 17 b.
  • the shift register circuits 61 are controlled by positive-phase and negative-phase clock signals (CLKxP and CLKxN) and a start pulse (STx) (see FIG. 6 ).
  • CLKxP and CLKxN positive-phase and negative-phase clock signals
  • STx start pulse
  • ENABL enable
  • UPDWN up-down
  • shift timings of the shift registers are controlled by a control signal from a control IC 81 (see FIGS. 8 and 208 ).
  • the gate driver circuit 12 incorporates a level shift circuit which level-shifts external data.
  • the shift register circuits 61 Since the shift register circuits 61 have small buffer capacity, they cannot drive the gate signal lines 17 directly. Therefore, at least two or more inverter circuits 62 are formed between each shift register circuit 61 and an output gate 63 which drives the gate signal line 17 (see FIG. 204 ).
  • the source driver 14 is formed on the board 71 by polysilicon technology such as low-temperature polysilicon technology.
  • a plurality of inverter circuits are formed between an analog switching gate such as a transfer gate which drives the source signal line 18 and the shift register of the source driver circuit 14 .
  • the following matters shift register output and output stages which drive signal lines (inverter circuits placed between output stages such as output gates or transfer gates) are common to the gate driver circuit and source driver circuit.
  • the output from the source driver 14 is shown in FIG. 6 as being connected directly to the source signal line 18 , actually the output from the shift register of the source driver is connected with multiple stages of inverter circuits, and the inverter outputs are connected to analog switching gates such as transfer gates.
  • the inverter circuit 62 consists of a P-channel MOS transistor and N-channel MOS transistor. As described earlier, the shift register circuit 61 of the gate driver circuit 12 has its output end connected with multiple stages of inverter circuits 62 and the final output is connected to the output gate 63 .
  • the inverter circuit 62 may be composed solely of P-channel MOS transistors. In that case, however, the circuit may be configured simply as a gate circuit rather than an inverter.
  • FIG. 8 is a block diagram of signal and voltage supplies on a display apparatus according to the present invention or a block diagram of the display apparatus.
  • Signals (power supply wiring, data wiring, etc.) are supplied from the control IC 81 to a source driver circuit 1 a via a flexible board 84 .
  • a control signal for the gate driver 12 is generated by the control IC, level-shifted by the source driver 14 , and applied to the gate driver 12 . Since drive voltage of the source driver 14 is 4 to 8 (V), the control signal with an amplitude of 3.3 (V) outputted from the control IC 81 can be converted into a signal with an amplitude of 5 (V) which can be received by the gate driver 12 .
  • reference numeral 14 has been described as a source driver, but instead of being a mere driver, it may incorporate a power circuit, buffer circuit (including a circuit such as a shift register), data conversion circuit, latch circuit, command decoder, shifting circuit, address conversion circuit, image memory, etc. Needless to say, a three-side free configuration or other configuration, drive system, etc. described with reference to FIG. 9 and the like are also applicable to the configuration described with reference to FIG. 8 and the like.
  • the display panel When the display panel is used for information display apparatus such as a cell phone, it is preferable to mount (form) the source driver IC (circuit) 14 and gate driver IC (circuit) 12 on one side of the display panel as shown in FIG. 9 (incidentally, a configuration in which driver ICs (circuits) are mounted (formed) on one side of a display panel is referred to as a three-side free configuration (structure).
  • the gate driver IC 12 is mounted on an X side of a display area and a source driver IC 14 is mounted on a Y side). This makes it easy in the design to center the center line of a display screen 50 on the display apparatus and mount the driver ICs.
  • the gate driver circuit may be produced by high-temperature polysilicon technology, low-temperature polysilicon technology or the like (i.e., at least one of the source driver circuit 14 and gate driver circuit 12 may be formed directly on the board 71 by polysilicon technology).
  • the three-side free configuration includes not only a configuration in which ICs are placed or formed directly on the board 71 , but also a configuration in which a film (TCP, TAB, or other technology) with a source driver IC (circuit) 14 and gate driver IC (circuit) 12 mounted are pasted on one side (or almost one side) of the board 71 . That is, the three-side free configuration includes configurations and arrangements in which two sides are left free of ICs and all similar configurations.
  • the gate driver circuit 12 If the gate driver circuit 12 is placed beside the source driver circuit 14 as shown in FIG. 9 , the gate signal line 17 must be formed along the side C.
  • the thick solid line in FIG. 9 , etc. indicates gate signal lines 17 formed in parallel.
  • gate signal lines 17 as there are scanning signal lines are formed in parallel in part b (bottom of the screen) while a single gate signal line 17 is formed in part a (top of the screen).
  • Spacing between the gate signal lines 17 formed on the side C is from 5 ⁇ m to 12 ⁇ m (both inclusive). If it is less than 5 ⁇ m, parasitic capacitance will cause noise on adjacent gate signal lines. It has been shown experimentally that parasitic capacitance has significant effects when the spacing is 7 ⁇ m or less. Furthermore, when the spacing is less than 5 ⁇ m, beating noise and other image noise appear intensely on the display screen. In particular, noise generation differs between the right and left sides of the screen and it is difficult to reduce the beating noise and other image noise. When the spacing exceeds 12 ⁇ m, bezel width D of the display panel becomes too large to be practical.
  • a ground pattern (conductive pattern which has been fixed at a constant voltage or set generally at a stable potential) can be placed under or above the gate signal lines 17 .
  • a separate shield plate shield foil: a conductive pattern which has been fixed at a constant voltage or set generally at a stable potential
  • shield foil a conductive pattern which has been fixed at a constant voltage or set generally at a stable potential
  • the gate signal lines 17 on the side C in FIG. 9 may be formed of ITO electrodes. However, to reduce resistance, preferably they are formed by laminating ITO and thin metal films. Also preferably they are formed of metal films. When using an ITO laminate, a titanium film is formed on the ITO, and a thin aluminum film or aluminum-molybdenum alloy film is formed on it. Alternatively, a chromium is formed on the ITO. For metal films, thin aluminum films or chromium films are used. This also applies to other examples of the present invention.
  • the gate signal lines 17 are placed on one side of the display area, this is not restrictive and they may be placed on both sides.
  • the gate signal line 17 a may be placed (formed) on the right side of the display screen 50 while the gate signal line 17 b may be placed (formed) on the left side of the display screen 50 . This also applies to other examples.
  • the source driver IC 14 and gate driver IC 12 may be integrated into a single chip. Then, it suffices to mount only one IC chip on the display panel. This also reduces implementation costs. Furthermore, this makes it possible to simultaneously generate various voltages for use in the single-chip driver IC.
  • the source driver IC 14 and gate driver IC 12 are made of silicon or other semiconductor wafers and mounted on the display panel, this is not restrictive. Needless to say, they may be formed directly on the display panel 82 using low-temperature polysilicon technology or high-temperature polysilicon technology.
  • pixels are of the three primary colors of R, G, and B, this is not restrictive. They may be of three colors of cyan, yellow, and magenta. They may be of two colors of B and yellow. Of course, they may be monochromatic. Alternatively, they may be of six colors of R, G, B, cyan, yellow, and magenta or of five colors of R, G, B, cyan, and magenta. These are natural colors which provide an expanded color reproduction range, enabling good display. Thus, the EL display apparatus according to the present invention is not limited to those which provide color display using the three primary colors of R, G, and B.
  • white light-emitting pixels may be formed.
  • the white light-emitting pixels can be created (formed or constructed) by laminating R, G, and B light-emitting structures.
  • a set of pixels consists of pixels for the three primary colors RGB and a white light-emitting pixel 16 W. Forming the white light-emitting pixels makes it easier to express peak brightness of white, and thus possible to implement bright image display.
  • pixel electrode areas for the different colors.
  • an equal area may be used if luminous efficiencies of the different colors as well as color purity are well balanced.
  • the pixel electrodes are adjusted.
  • the electrode area for each color can be determined based on current density. That is, when white balance is adjusted in a color temperature range of 7000 K (Kelvin) to 12000 K (both inclusive), difference between current densities of different colors should be within ⁇ 30%. More preferably, the difference should be within ⁇ 15%.
  • all the three primary colors should have a current density of 70 A/square meter to 130 A/square meter (both inclusive). More preferably, all the three primary colors should have a current density of 85 A/square meter to 115 A/square meter (both inclusive).
  • the EL element 15 is a self-luminous element. When light from this self-luminous element enters a transistor serving as a switching element, a photoconductive phenomenon occurs.
  • the photoconductive phenomenon is a phenomenon in which leakage (off-leakage) increases due to photoexcitation when a switching element such as a transistor is off.
  • the present invention forms a shading film under the gate driver 12 (source driver 14 in some cases) and under the pixel transistor 11 .
  • the shading film is formed of thin film of metal such as chromium and is from 50 nm to 150 nm thick (both inclusive). A thin film will provide a poor shading effect while a thick film will cause irregularities, making it difficult to pattern the transistor 11 A 1 in an upper layer.
  • the present invention also forms a cathode electrode on the surface of the driver 12 and the like and uses it as a shading film.
  • the present invention forms at least one layer of organic EL film, and preferably two or more layers, on the driver circuit 12 simultaneously with the formation of organic EL film on the pixel electrode.
  • the EL element 15 may become a bright spot which remains illuminated constantly.
  • the bright spot is visually conspicuous and must be turned into a black spot (turned off).
  • the pixel 16 which corresponds to the bright spot is detected and the capacitor 19 is irradiated with laser light to cause a short circuit across the capacitor.
  • the capacitor 19 can no longer hold electric charges, and thus the transistor 11 a can be stopped from passing current. It is desirable to remove that part of a cathode film which will be irradiated with laser light to prevent the laser irradiation from causing a short circuit between a terminal electrode of the capacitor 19 and the cathode film.
  • Flaws in a transistor 11 in the pixel 16 will affect the source driver IC 14 and the like. For example, if a source-drain (SD) short circuit 562 occurs in the driver transistor 11 a in FIG. 56 , a Vdd voltage of the panel is applied to the source driver IC 14 .
  • the power supply voltage of the source driver IC 14 is kept equal to or higher than the power supply voltage Vdd of the panel.
  • the reference voltage used by the source driver IC 14 can be adjusted with an electronic regulator 561 (See FIG. 148 ).
  • an SD short circuit 562 occurs in the transistor 11 a
  • an excessive current flows through the EL element 15 .
  • the EL element 15 remains illuminated constantly (becomes a bright spot).
  • the bright spot is conspicuous as a defect. For example, if a source-drain (SD) short circuit occurs in the transistor 11 a in FIG. 56 , current flows constantly from the Vdd voltage to the EL element 15 (when the transistor 11 d is on) regardless of the magnitude of gate (G) terminal voltage of the transistor 11 a. Thus, a bright spot results.
  • SD source-drain
  • the Vdd voltage is applied to the source signal line 18 and to the source driver 14 . If the power supply voltage of the source driver 14 is not higher than Vdd, voltage resistance may be exceeded, causing the source driver 14 to rupture. Thus, it is preferable that the power supply voltage of the source driver 14 is equal to or higher than the Vdd voltage (the higher voltage of the panel).
  • An SD short circuit of the transistor 11 a may go beyond a point defect and lead to rupture of the source driver circuit of the panel. Also, the bright spot is conspicuous, which makes the panel defective. Thus, it is necessary to turn the bright spot into a black spot by cutting the wiring which connects between the transistor 11 and EL element 15 . Preferably an optical means such as laser light is used to cut the wiring.
  • the gate signal line 17 a conducts when the row remains selected (since the transistor 11 in FIG. 1 is a P-channel transistor, the gate signal line 17 a conducts when it is in low state) and the gate signal line 17 b conducts when the row remains non-selected.
  • Parasitic capacitance (not shown) is present in the source signal line 18 .
  • the parasitic capacitance is caused by the capacitance at the junction of the source signal line 18 and gate signal line 17 , channel capacitance of the transistors 11 b and 11 c, etc.
  • C stray capacitance
  • V a voltage of the source signal line
  • I a current flowing through the source signal line.
  • the present invention is characterized in that the write current into a pixel is set at a value other than a predetermined value and that a current is passed through the EL element 15 intermittently.
  • N times larger current is written into the pixel transistor 11 and the conduction period of the EL element 15 is reduced to 1/N.
  • N1 times larger current may be written into the pixel transistor 11 and the conduction period of the EL element 15 maybe reduced to 1/N2 (N1 and N2 are different from each other)
  • average brightness over one field (frame) period of the display screen 50 is B 0 .
  • This drive method performs current (voltage) programming in such a way that the brightness B 1 of each pixel 16 is higher than the average brightness B 0 .
  • a non-display area 53 appears during at least one field (frame) period.
  • the average brightness over one field (frame) period is lower than B 1 .
  • non-display area 52 and display area 53 are not necessarily spaced equally. For example, they may appear at random (provided that the display period or non-display period makes up a predetermined value (constant ratio) as a whole). Also, display periods may vary among R, G, and B.
  • display periods of R, G, and B or non-display periods can be adjusted (set) to predetermined values (proportions) in such a way as to obtain an optimum white balance.
  • 1/N means reducing 1F (one field or one frame) to 1/N. Needless to say, however, it takes time to select one pixel row and to program current values (normally, one horizontal scanning period (1 H)) and error may result depending on scanning conditions.
  • the drive system turns off the current supplied to the EL element 15 , at least once during one frame (or one field) period. Also, the drive system at least achieves intermittent display by programming the pixel 16 with a current larger than a predetermined value.
  • a problem with an organic (inorganic) EL display is that it uses a display method basically different from that of an CRT or other display which presents an image as a set of displayed lines using an electron gun. That is, the EL display holds the current (voltage) written into a pixel for 1F (one field or one frame) period. Thus, a problem is that displaying moving pictures will result in blurred edges.
  • the drive method according to the present invention implements intermittent display.
  • the intermittent display can be achieved by simply turning on and off the transistor 11 d on a 1-H cycle. Consequently, a main clock of the circuit does not differ from conventional ones, and thus there is no increase in the power consumption of the circuit.
  • Liquid crystal display panels need an image memory in order to achieve intermittent display. According to the present invention, image data is held in each pixel 16 . Thus, the present invention requires no image memory for intermittent display.
  • the present invention controls the current passed through the EL element 15 by simply turning on and off the switching transistor 11 d, the transistor 11 e, and the like. That is, even if the current Iw flowing through the EL element 15 is turned off, the image data is held as it is in the capacitor 19 . Thus, when the transistor 11 d is turned on the next time, the current passed through the EL element 15 has the same value as the current flowing through the EL element 15 the previous time. Even to achieve black insertion (intermittent display such as black display), the present invention does not need to speed up the main clock of the circuit. Also, it does not need to elongate a time axis, and thus requires no image memory.
  • the EL element 15 responds quickly, requiring a short time from application of current to light emission.
  • the present invention is suitable for movie display, and by using intermittent display, it can solve a problem with conventional data-holding display panels (liquid crystal display panels, EL display panels, etc.) in displaying moving pictures.
  • the conduction period of the gate signal line 17 b (the transistor 11 d ) can be set to 1F/N. This makes it possible to apply the present invention to television sets, monitors, and other large display apparatus.
  • the output stage of the source driver circuit 14 is constituted of a constant-current circuit 704 (see FIG. 70 ).
  • the constant-current circuit eliminates the need to vary buffer size of the output stage according to the size of the display panel unlike the source driver circuits of liquid crystal display panels.
  • the parasitic capacitance of the source signal line 18 is generated by the coupling capacitance with adjacent source signal lines 18 , buffer output capacitance of the source driver IC (circuit) 14 , cross capacitance between the source signal line 18 and gate signal line 17 , etc.
  • This parasitic capacitance is normally 10 pF or larger.
  • voltage driving since voltage is applied to the source signal line 18 from the source driver IC 14 at low impedance, more or less large parasitic capacitance does not disturb driving.
  • the pixel capacitor 19 needs to be programmed with a minute current of 20 nA or less.
  • the parasitic capacitance cannot be charged and discharged during the time when one pixel row is programmed (normally within 1 H, but not limited to 1 H because two pixel rows may be programmed simultaneously). If the parasitic capacitance cannot be charged and discharged within a period of 1 H, sufficient current cannot be written into the pixel, resulting in inadequate resolution.
  • the programming current Iw flows through the source signal line 18 during current programming as shown in FIG. 3 ( a ).
  • the current Iw flows through the transistor 11 a and voltage is set (programmed) in the capacitor 19 in such a way as to maintain the current Iw.
  • the transistor 11 d is open (off).
  • the transistors 11 c and 11 b turn off and the transistor 11 d turns on as shown in FIG. 3 ( b ).
  • a turn-off voltage (Vgh) is applied to the gate signal line 17 a, turning off the transistors 11 b and 11 c.
  • a turn-on voltage (Vgl) is applied to the gate signal line 17 b, turning on the transistor 11 d.
  • a current I1 is N times the current which should normally flow (a predetermined value)
  • the current flowing through the EL element 15 in FIG. 3 ( b ) is also Iw.
  • the EL element 15 emits light 10 times more brightly that a predetermined value.
  • the magnification N the higher the display brightness B of the pixel 16 .
  • the magnification N and the brightness of the pixel 16 are proportional to each other.
  • the average brightness over the 1F equals predetermined brightness.
  • This display condition closely resembles the display condition under which a CRT is scanning a screen with an electronic gun. The difference is that 1/N of the entire screen illuminates (where the entire screen is taken as 1) (in a CRT, what illuminates is one pixel row—more precisely, one pixel).
  • 1F/N of the image display area 53 moves from top to bottom of the screen 50 as shown in FIG. 13 ( b ).
  • current flows through the EL element 15 only for the period of 1F/N, but current does not flow during the remaining period (1F(N ⁇ 1)/N).
  • the pixel is displayed intermittently.
  • the entire screen appears to be displayed uniformly to the human eye.
  • the write pixel row 51 a is non-illuminated 52 a.
  • the write pixel row 51 a may be illuminated.
  • a drive method which involves driving a pixel intermittently by programming it with a current larger than the predetermined drive current Iw shown in FIGS. 13, 16 , etc. is referred to as N-fold pulse driving.
  • image data display and black display are repeated every 1F. That is, image data is displayed at intervals (intermittently) in the temporal sense.
  • Liquid crystal display panels EL display panels other than that of the present invention
  • EL display panels other than that of the present invention cannot keep up with changes in image data during movie display, resulting is blurred moving pictures (edge blur of images). Since the present invention displays images intermittently, it can achieve a good display condition without edge blur of images. In short, movie display close to that of a CRT can be achieved.
  • the drive method according to the present invention cannot be implemented using a configuration in which logic (Vgh or Vgl) applied to the gate signal line 17 is applied to the transistor 11 b and the logic applied to the gate signal line 17 is converted (Vgh or Vgl) by an inverter and applied to the transistor 11 d.
  • the present invention requires a gate driver circuit 12 a which operates the gate signal line 17 a and gate driver circuit 12 b which operates the gate signal line 17 b.
  • the drive method according to the present invention provides a non-illuminated display even with the pixel configuration shown in FIG. 1 during periods other than the current programming period (1 H).
  • FIG. 14 A timing chart of the drive method shown in FIG. 13 is illustrated in FIG. 14 .
  • the pixel configuration referred to in the present invention and the like is the one shown in FIG. 1 unless otherwise stated.
  • the selection period is designated as 1 H
  • a turn-on voltage (Vgl) is applied to the gate signal line 17 a (see FIG. 14 ( a )
  • a turn-off voltage (Vgh) is applied to the gate signal line 17 b (see FIG. 14 ( b )).
  • current does not flow through the EL element 15 (non-illumination mode).
  • a turn-on voltage (Vgl) is applied to the gate signal line 17 b and a turn-off voltage (Vgh) is applied to the gate signal line 17 a.
  • Vgl turn-on voltage
  • Vgh turn-off voltage
  • the EL element 15 illuminates at a brightness (N ⁇ B) N times the predetermined brightness and the illumination period is 1F/N.
  • FIG. 15 shows an example in which operations shown in FIG. 14 are applied to each pixel row.
  • the figure shows voltage waveforms applied to the gate signal lines 17 .
  • Waveforms of the turn-off voltage are denoted by Vgh (high level) while waveforms of the turn-on voltage are denoted by Vgl (low level).
  • the subscripts such as ( 1 ) and ( 2 ) indicate selected pixel row numbers.
  • a gate signal line 17 a ( 1 ) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11 a in the selected pixel row to the source driver circuit 14 .
  • the capacitor 19 is programmed so that a 10 times larger current will flow through the transistor 11 a.
  • a gate signal line 17 a ( 2 ) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11 a in the selected pixel row to the source driver circuit 14 .
  • a turn-off voltage Vgh
  • Vgh a turn-off voltage
  • Vgl a turn-on voltage
  • a gate signal line 17 a ( 3 ) is selected, a turn-off voltage (Vgh) is applied to the gate signal line 17 b ( 3 ), and current does not flow through the EL element 15 in the pixel row ( 3 ).
  • Vgh turn-off voltage
  • Vgl turn-on voltage
  • the basic idea of the present invention is to use a large current for programming, insert a non-display area 52 , and thereby obtain a predetermined brightness.
  • the drive method according to the present invention causes a current larger than a predetermined current to flow through the EL element 15 , and thereby charges and discharges the parasitic capacitance of the source signal line 18 sufficiently. That is, there is no need to pass an N times larger current through the EL element 15 .
  • it is conceivable to form a current path in parallel with the EL element 15 form a dummy EL element and use a shield film to prevent the dummy EL element from emitting light
  • divide the flow of current between the EL element 15 and the dummy EL element are examples of the flow of current between the EL element 15 and the dummy EL element.
  • a programming current is set to 2.2 ⁇ A and the current of 2.2 ⁇ A is passed through the transistor 11 a. Then, the signal current of 0.2 ⁇ A may be passed through the EL element 15 and 2 ⁇ A may be passed through the dummy EL element, for example. That is, the dummy pixel row 281 in FIG. 27 remains selected constantly. Incidentally, the dummy pixel row is either kept from emitting light or hidden from view by a shield film or the like even if it emits light.
  • this method allows the entire display screen 50 to be used as the image display area 53 without a non-display area 52 .
  • FIG. 13 ( a ) shows writing into the display screen 50 .
  • reference numeral 51 a denotes a write pixel row.
  • a programming current is supplied to the source signal line 18 from the source driver IC 14 .
  • a programming current is written into the source signal line 18
  • the present invention is not limited to current programming.
  • the present invention may also use voltage programming ( FIG. 62 , etc.) which writes voltage into the source signal line 18 .
  • FIG. 13 ( a ) when the gate signal line 17 a is selected, the current to be passed through the source signal line 18 is programmed into the transistor 11 a. At this time, a turn-off voltage is applied to the gate signal line 17 b, and current does not flow through the EL element 15 . This is because when the transistor 11 d is on on the EL element 15 , a capacitance component of the EL element 15 is visible from the source signal line 18 and the capacitance prevents sufficient current from being programmed into the capacitor 19 .
  • the pixel row into which current is written is a non-illuminated area 52 as shown in FIG. 13 ( b ).
  • the screen becomes 10 times brighter.
  • 90% of the display screen 50 can be constituted of the non-illuminated area 52 .
  • S the number of horizontal scanning lines (number of pixel rows)
  • S/N of the entire area constitutes a display area 53 , which is illuminated N times more brightly. Then, the display area 53 is scanned in the vertical direction of the screen.
  • S(N ⁇ 1)/N of the entire area is a non-illuminated area 52 .
  • the non-illuminated area presents a black display (is non-luminous).
  • the non-luminous area 52 is produced by turning off the transistor 11 d.
  • the display area 53 is illuminated N times more brightly, naturally the value of N is adjusted by brightness adjustment and gamma adjustment.
  • the screen becomes 10 times brighter and 90% of the display screen 50 can be constituted of the non-illuminated area 52 .
  • R, G, and B pixels constitute the non-illuminated area 52 in the same proportion.
  • 1 ⁇ 8 of the R pixels, 1 ⁇ 6 of the G pixels, and 1/10 of the B pixels may constitute the non-illuminated area 52 with different colors making up different proportions.
  • the non-illuminated area 52 (or illuminated area 53 ) may be adjusted separately among R, G, and B.
  • allowing R, G, and B to be adjusted separately makes it possible to adjust white balance, making it easy to adjust color balance for each gradation (see FIG. 41 ).
  • pixel rows including the write pixel row 51 a compose a non-illuminated area 52 while an area of S/N (1F/N in the temporal sense) above the write pixel row 51 a compose a display area 53 (when write scans are performed from top to bottom of the screen. When the screen is scanned from bottom to top, the areas change places). Regarding the display condition of the screen, a strip of the display area 53 moves from top to bottom of the screen.
  • one display area 53 moves from top to bottom of the screen. At a low frame rate, the movement of the display area 53 is recognized visually. It tends to be recognized easily especially when a user closes his/her eyes or moves his/her head up and down.
  • the display area 53 can be divided into a plurality of parts as shown in FIG. 16 . If the total area of the divided display area is S (N ⁇ 1)/N, the brightness is equal to the brightness in FIG. 13 . Incidentally, there is no need to divide the display area 53 equally. Also, there is no need to divide the non-display area 52 equally.
  • Dividing the display area 53 reduces flickering of the screen. Thus, a flicker-free good image display can be achieved.
  • the display area 53 may be divided more finely. However, the more finely the display area 53 is divided, the poorer the movie display performance becomes.
  • FIG. 17 shows voltage waveforms of gate signal lines 17 and emission brightness of the EL element.
  • a period (1F/N) during which the gate signal line 17 b is set to Vgl is divided into a plurality of parts (K parts). That is, a period of 1F/(K ⁇ N) during which the gate signal line 17 b is set to Vgl repeats K times.
  • K parts a period of 1F/(K ⁇ N) during which the gate signal line 17 b is set to Vgl repeats K times.
  • the number of divisions is variable. For example, when the user presses a brightness adjustment switch or turns a brightness adjustment knob, the value of K may be changed in response. Also, the user may be allowed to adjust brightness. Alternatively, the value of K may be changed manually or automatically depending on images or data to be displayed.
  • a period (1F/N) during which the gate signal line 17 b is set to Vgl is divided into a plurality of parts (K parts) and that a period of 1F/(K ⁇ N) during which the gate signal line 17 b is set to Vgl repeats K times, this is not restrictive.
  • a period of 1F/(K ⁇ N) may be repeated L (L ⁇ K) times.
  • the present invention displays the display screen 50 by controlling the period (time) during which current is passed through the EL element 15 .
  • the idea of repeating the 1F/(K ⁇ N) period L (L ⁇ K) times is included in the technical idea of the present invention.
  • the display screen 50 is turned on and off (illuminated and non-illuminated) as the current delivered to the EL element 15 is switched on and off. That is, approximately equal current is passed through the transistor 11 a multiple times using electric charges held in the capacitor 19 .
  • the present invention is not limited to this.
  • the display screen 50 may be turned on and off (illuminated and non-illuminated) by charging and discharging the capacitor 19 .
  • FIG. 18 shows voltage waveforms applied to gate signal lines 17 to achieve the image display condition shown in FIG. 16 .
  • FIG. 18 differs from FIG. 15 in the operation of the gate signal line 17 b.
  • the gate signal line 17 b is turned on and off (Vgl and Vgh) as many times as there are screen divisions.
  • FIG. 18 is the same as FIG. 15 in other respects, and thus description thereof will be omitted.
  • intermittent display can be achieved by simply turning on and off the transistor 11 d.
  • FIGS. 38 , and 51 intermittent display can be achieved by simply turning on and off the transistor element 11 e. This is because image data is stored in the capacitor 19 (the number of gradations is infinite because analog values are used). That is, the image data is held in each pixel 16 for a period of 1F. Whether to deliver a current which corresponds to the stored image data to the EL element 15 is controlled by controlling the transistors 11 d and 11 e.
  • the drive method described above is not limited to a current-driven type and can be applied to a voltage-driven type as well. That is, in a configuration in which the current passed through the EL element 15 is stored in each pixel, intermittent driving is implemented by switching on and off the current path between the driver transistor 11 and EL element 15 .
  • the current passed through the EL element 15 by the transistor 11 a must be higher than 65%. More specifically, if the initial current written into the pixel 16 and passed through the EL element 15 is taken as 100%, the current passed through the EL element 15 just before it is written into the pixel 16 in the next frame (field) must not fall below 65%.
  • the operation clock of the gate driver circuit 12 is significantly slower than the operation clock of the source driver circuit 14 , there is no need to upgrade the main clock of the circuit. Besides, the value of N can be changed easily.
  • the image display direction (image writing direction) may be from top to bottom of the screen in the first field (frame), and from bottom to top of the screen in the second field (frame). That is, an upward direction and downward direction may be repeated alternately.
  • top-to-bottom and bottom-to-top writing directions on the screen are used in the drive method described above, this is not restrictive. It is also possible to fix the writing direction on the screen to a top-to-bottom direction or bottom-to-top direction and move the non-display area 52 from top to bottom in the first field, and from bottom to top in the second field. Alternatively, it is possible to divide a frame into three fields and assign the first field to R, the second field to G, and the third field to B so that three fields compose a single frame. It is also possible to display R, G, and B in turns by switching among them every horizontal scanning period (1 H) (see FIGS. 175 to 180 and their description). The items mentioned above also apply to other examples of the present invention.
  • the non-display area 52 need not be totally non-illuminated. Weak light emission or dim image display will not be a problem in practical use. It should be regarded to be an area which has a lower display brightness than the image display area 53 . Also, the non-display area 52 may be an area which does not display one or two colors out of R, G, and B. Also, it may be an area which displays one or two colors among R, G, and B at low brightness.
  • the brightness of the display area 53 is kept at a predetermined value, the larger the display area 53 , the brighter the display screen 50 .
  • the brightness of the image display area 53 is 100 (nt)
  • the percentage of the display screen 50 accounted for by the display area 53 changes from 10% to 20%, the brightness of the screen is doubled.
  • the display brightness of the screen 50 is proportional to the ratio of the display area 53 to the screen 50 .
  • the size of the display area 53 can be specified freely by controlling data pulses (ST 2 ) sent to the shift register circuit 61 . Also, by varying the input timing and period of the data pulses, it is possible to switch between the display condition shown in FIG. 16 and display condition shown in FIG. 13 . Increasing the number of data pulses in one IF period makes the screen 50 brighter and decreasing it makes the screen 50 dimmer. Also, continuous application of the data pulses brings on the display condition shown in FIG. 13 while intermittent application of the data pulses brings on the display condition shown in FIG. 16 .
  • FIG. 19 ( a ) shows a brightness adjustment scheme used when the display area 53 is continuous as in FIG. 13 .
  • the display brightness of the screen 50 in FIG. 19 ( a 1 ) is the brightest
  • the display brightness of the screen 50 in FIG. 19 ( a 2 ) is the second brightest
  • display brightness of the screen 50 in FIG. 19 ( a 3 ) is the dimmest.
  • FIG. 19 ( a ) is most suitable for movie display.
  • Changes from FIG. 19 ( a 1 ) to FIG. 19 ( a 3 ) can be achieved easily by controlling the shift register circuit 61 and the like of the gate driver circuit 12 as described above. In this case, there is no need to vary the Vdd voltage in FIG. 1 . That is, the brightness of the screen 50 can be varied without changing the power supply voltage. Also, in the process of change from FIG. 19 ( a 1 ) to FIG. 19 ( a 3 ), the gamma characteristics of the screen do not change at all. Thus, the contrast and gradation characteristics of the display screen are maintained regardless of the brightness of the screen 50 . This is an effective feature of the present invention.
  • the drive method according to the present invention does not depend on the display brightness of the screen and can display up to 64 gradations, which is the highest.
  • FIG. 19 ( b ) shows a brightness adjustment scheme used when the display areas 53 are scattered as in FIG. 16 .
  • the display brightness of the screen 50 in FIG. 19 ( b 1 ) is the brightest
  • the display brightness of the screen 50 in FIG. 19 ( b 2 ) is the second brightest
  • display brightness of the screen 50 in FIG. 19 ( b 3 ) is the dimmest.
  • Changes from FIG. 19 ( b 1 ) to FIG. 19 ( b 3 ) (or vice versa) can be achieved easily by controlling the shift register circuit 61 of the gate driver circuit 12 and the like as described above.
  • By scattering the display areas 53 as shown in FIG. 19 ( b ) it is possible to eliminate flickering even at a low frame rate.
  • the display areas 53 can be scattered more finely as shown in FIG. 19 ( c ).
  • the drive method in FIG. 19 ( a ) is suitable for moving pictures.
  • the drive method in FIG. 19 ( c ) is suitable when it is desired to reduce power consumption by displaying still pictures. Switching from FIG. 19 ( a ) to FIG. 19 ( c ) can be done easily by controlling the shift register circuit 61 .
  • a predetermined brightness can be achieved if a current Iw 5/4 a predetermined value is used for current programming and the EL element is illuminated for 4/5 of 1F.
  • a current Iw 10/4 a predetermined value may be used for current programming to illuminate the EL element for 4/5 of 1F. In this case, the EL element illuminates at twice a predetermined brightness.
  • a current Iw 5/4 a predetermined value may be used for current programming to illuminate the EL element for 2/5 of 1F. In this case, the EL element illuminates at 1/2 the predetermined brightness.
  • a current Iw 5/4 a predetermined value may be used for current programming to illuminate the EL element for 1/1 of 1F. In this case, the EL element illuminates at 5/4 the predetermined brightness.
  • the present invention controls the brightness of the display screen by controlling the magnitude of programming current and illumination period IF. Also, by illuminating the EL element for a period shorter than the period of 1F, the present invention can insert a non-display area 52 , and thereby improve movie display performance. By illuminating the EL element constantly for the period of 1F, the present invention can display a bright screen.
  • pixel size is A square mm and predetermined brightness of white raster display is B (nt), preferably programming current I ( ⁇ A) (programming current outputted from the source driver circuit 14 ) or the current written into the pixel satisfies: ( A ⁇ B )/20 ⁇ I ⁇ ( A ⁇ B )
  • the programming current I ( ⁇ A) falls within the range: ( A ⁇ B )/10 ⁇ I ⁇ ( A ⁇ B )
  • FIG. 20 is an explanatory diagram illustrating another example of increasing the current flowing through a source signal line 18 .
  • M pixel rows are selected simultaneously.
  • a current N times larger than a predetermined current is applied to the source signal line 18 from the source driver IC 14 .
  • a current N/M times larger than the current passed through the EL element 15 is programmed into each pixel.
  • current is passed through the EL element 15 for a duration of M/N the duration of one frame (one field) (M/N is used for ease of explanation and is not meant to be restrictive. As described earlier, it can be specified freely depending on the brightness of the screen 50 ). This makes it possible to charge and discharge parasitic capacitance of the source signal line 18 sufficiently, resulting in a sufficient resolution at the predetermined emission brightness.
  • FIG. 21 is an explanatory diagram illustrating drive waveforms used to implement the drive method shown in FIG. 20 .
  • Waveforms of the turn-off voltage are denoted by Vgh (H level) while waveforms of the turn-on voltage are denoted by (L level).
  • the subscripts (such as (1), (2), and (3)) indicate pixel row numbers. Incidentally, the number of rows is 220 in the case of a QCIF display panel, and 480 in the case of a VGA display panel.
  • a gate signal line 17 a ( 1 ) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11 a in the selected pixel row to the source driver circuit 14 .
  • Vgl voltage Vgl voltage
  • a programming current flows through the source signal line 18 in the direction from the transistor 11 a in the selected pixel row to the source driver circuit 14 .
  • the write pixel row 51 a is the (1)-th pixel row.
  • the predetermined value is a data current for use to display images, it is not a fixed value unless in the case of white raster display).
  • the gate signal lines 17 a ( 1 ), ( 2 ), ( 3 ), ( 4 ), and ( 5 ) are selected as shown in FIG. 21 . That is, the switching transistors 11 b and the transistors 11 c in the pixel rows ( 1 ), ( 2 ), ( 3 ), ( 4 ), and ( 5 ) are on. Also, the gate signal lines 17 b are 180 degrees out of phase with the gate signal lines 17 a. Thus, the switching transistors 11 d in the pixel rows ( 1 ), ( 2 ), ( 3 ), ( 4 ), and ( 5 ) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52 .
  • the capacitor 19 of each pixel 16 is programmed with a twice larger current.
  • the transistors 11 a have equal characteristics (Vt and S value)
  • the total programming current of the five transistors 11 a flows through the source signal line 18 .
  • a current conventionally written into the write pixel row 51 a is Iw
  • a current of Iw ⁇ 10 is passed through the source signal line 18 .
  • the write pixel rows 51 b into which image data is written later than the write pixel row ( 1 ) are auxiliary pixel rows used to increase the amount of current delivered to the source signal line 18 .
  • regular image data is written into the write pixel rows 51 b later.
  • the four pixel rows 51 b provide the same display as the pixel row 51 a during a period of 1 H. Consequently, at least the write pixel row 51 a and the pixel rows 51 b selected to increase current are in non-display mode 52 .
  • the pixel rows may be in display mode.
  • the gate signal line 17 a ( 1 ) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17 b.
  • the gate signal line 17 a ( 6 ) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11 a in the selected pixel row ( 6 ) to the source driver circuit 14 .
  • regular image data is held in the pixel row ( 1 ).
  • the gate signal line 17 a ( 2 ) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17 b.
  • the gate signal line 17 a ( 7 ) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11 a in the selected pixel row ( 7 ) to the source driver circuit 14 .
  • regular image data is held in the pixel row ( 2 ).
  • the entire screen is redrawn as it is scanned by shifting pixel rows one by one through the above operations.
  • each pixel is programmed with a twice larger current, ideally the emission brightness of the EL element 15 of each pixel is two times higher.
  • the brightness of the display screen is twice higher than a predetermined value.
  • an area which includes the write pixel rows 51 and which is half as large as the display screen 50 can be turned into a non-display area 52 as illustrated in FIG. 16 .
  • the display area 53 can be divided into a plurality of parts as illustrated in FIG. 22 . If the total area of the divided non-display area 52 is S (N ⁇ 1)/N, the brightness is equal to the brightness of the undivided display area.
  • FIG. 23 shows voltage waveforms applied to gate signal lines 17 .
  • FIG. 21 differs from FIG. 23 basically in the operation of the gate signal line 17 b.
  • the gate signal line 17 b is turned on and off (Vgl and Vgh) as many times as there are screen divisions.
  • FIG. 23 is the same as FIG. 21 in other respects, and thus description thereof will be omitted.
  • the display area 53 reduces flickering of the screen. Thus, a flicker-free good image display can be achieved. Incidentally, the display area 53 may be divided more finely. The more finely the display area 53 is divided, the less flickering occurs. Since the EL element 15 is highly responsive, even if it is turned on and off at intervals shorter than 5 ⁇ sec, there is no lowering of the display brightness.
  • the EL element 15 can be turned on and off by turning on and off a signal applied to the gate signal line 17 b.
  • the drive method according to the present invention can perform control using a low frequency on the order of KHz. Also, it does not need an image memory or the like in order to insert a black screen (insert anon-display area 52 ).
  • the drive circuit or method according to the present invention can be implemented at low costs.
  • FIG. 24 shows a case in which two pixel rows are selected simultaneously. It was found that on a display panel formed by low-temperature polysilicon technology, a method in which two pixel rows were selected simultaneously provided uniform display on a practical level. Probably this is because driver transistors 11 a in adjacent pixels had very similar characteristics. In laser annealing, good results were obtained when laser stripes were irradiated in parallel with the source signal line 18 .
  • the characteristics of the pixel transistors 11 a arranged vertically become almost uniform, making it possible to do proper current programming (even if the characteristics of the pixel transistors 11 a arranged horizontally are not uniform).
  • the above operation is performed in sync with 1 H (one horizontal scanning period) by shifting selected pixel rows one by one or by shifting two or more selected pixel rows at once.
  • the direction of the laser shot does not always need to be parallel with the direction of the source signal line 18 .
  • pixel transistors 11 a placed along one source signal line 18 can be made to take on almost equal characteristics.
  • directing a laser shot in parallel with the source signal line 18 means bringing a pixel vertically adjacent to an arbitrary pixel along the source signal line 18 into a laser irradiation range.
  • a source signal line 18 generally constitutes wiring which transmits programming current or voltage used as a video signal.
  • a write pixel row is shifted every 1 H, but this is not restrictive. Pixel rows may be shifted every 2 Hs (two pixel rows at a time). Also, more than two pixel rows may be shifted at a time. Also, pixel rows may be shifted at desired time intervals or every second pixel may be shifted.
  • the shifting interval may be varied according to locations on the screen.
  • the shifting interval may be decreased in the middle of the screen, and increased at the top and bottom of the screen.
  • a pixel row may be shifted at intervals of 200 ⁇ sec. in the middle of the screen 50 , and at intervals of 100 ⁇ sec. at the top and bottom of the screen 50 . This increases emission brightness in the middle of the screen 50 and decreases it around the perimeters (at the top and bottom of the screen 50 )).
  • the shifting interval is varied smoothly among the top, middle, and bottom of the screen 50 to avoid brightness contours.
  • the reference voltage of the source driver circuit 14 may be varied with the scanning location on the screen 50 (see FIG. 146 , etc.).
  • a reference current of 10 ⁇ A is used in the middle of the screen 50 and a reference current of 5 ⁇ A is used at the top of the screen 50 .
  • Varying a reference current in this way corresponding to a location in the screen 50 increases emission brightness in the middle of the screen 50 and decreases it around the perimeters (at the top and bottom of the screen 50 )).
  • the reference current is varied smoothly among the top, middle, and bottom of the screen 50 to avoid brightness contours.
  • images may be displayed by combining a drive method which varies the pixel-row shifting interval with the location on the screen and a drive method which varies the reference voltage with the location on the screen 50 .
  • the shifting interval may be varied on a frame-by-frame basis. Also, it is not strictly necessary to select consecutive pixel rows. For example, every second pixel row may be selected.
  • a possible drive method involves selecting the first and third pixel rows in the first horizontal scanning period, the second and fourth pixel rows in the second horizontal scanning period, the third and fifth pixel rows in the third horizontal scanning period, and the fourth and sixth pixel rows in the fourth horizontal scanning period.
  • a drive method which involves selecting the first, third, and fifth pixel rows in the first horizontal scanning period also belongs to the technical category of the present invention. Also, one in every few pixel rows maybe selected.
  • the combination of the direction of a laser shot and selection of multiple pixel rows is not limited to the pixel configurations in FIGS. 1, 2 , and 32 , but it is also applicable to other current-driven pixel configurations such as the current-mirror pixel configurations in FIGS. 38, 42 , 50 , etc. Also, it can be applied to voltage-driven pixel configurations in FIGS. 43, 51 , 54 , 62 , etc. This is because as long as transistors in upper and lower parts of the pixel have equal characteristics, current programming can be performed properly using the voltage value applied to the same source signal line 18 .
  • the gate signal lines 17 a ( 1 ) and ( 2 ) are selected (see FIG. 25 ). That is, the switching transistors 11 b and the transistors 11 c in the pixel rows ( 1 ) and ( 2 ) are on. Thus, at least the switching transistors 11 d in the pixel rows ( 1 ) and ( 2 ) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52 .
  • the display area 53 is divided into five parts to reduce flickering.
  • the current written into the write pixel row 51 a is Id
  • a current of Iw ⁇ 10 is passed through the source signal line 18 .
  • the pixel row 51 b provides the same display as the pixel row 51 a during a period of 1 H. Consequently, at least the write pixel row 51 a and the pixel row 51 b selected to increase current are in non-display mode 52 .
  • the gate signal line 17 a ( 1 ) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17 b.
  • the gate signal line 17 a ( 3 ) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11 a in the selected pixel row ( 3 ) to the source driver circuit 14 .
  • regular image data is held in the pixel row ( 1 ).
  • the gate signal line 17 a ( 2 ) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17 b.
  • the gate signal line 17 a ( 4 ) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11 a in the selected pixel row ( 4 ) to the source driver circuit 14 .
  • regular image data is held in the pixel row ( 2 ).
  • the entire screen is redrawn as it is scanned by shifting pixel rows one by one through the above operations (of course, two or more pixel rows may be shifted simultaneously. For example, in the case of pseudo-interlaced driving, two pixel rows will be shifted at a time. Also, from the viewpoint of image display, the same image may be written into two or more pixel rows).
  • each pixel is programmed with a five times larger current (voltage), ideally the emission brightness of the EL element 15 is five times higher.
  • the brightness of the display area 53 is five times higher than a predetermined value.
  • an area which includes the write pixel rows 51 and which is 1/5 the display screen 50 can be turned into a non-display area 52 .
  • two write pixel rows 51 are selected in sequence from the upper side to the lower side of the screen 50 (see also FIG. 26 . Pixels 16 a and 16 b are selected in FIG. 26 ). However, at the bottom of the screen, there does not exist 51 b although the write pixel row 51 a exists as shown in FIG. 27 ( b ). That is, there is only one pixel row to be selected. Thus, the current applied to the source signal line 18 is all written into the write pixel row 51 a. Consequently, twice as large a current as usual is written into the write pixel row 51 a.
  • the present invention forms (places) a dummy pixel row 281 at the bottom of the screen 50 , as shown in FIG. 27 ( b ).
  • the final pixel row of the screen 50 and the dummy pixel row 281 are selected. Consequently, a prescribed current is written into the write pixel row in FIG. 27 ( b ).
  • the dummy pixel row 281 is illustrated as being adjacent to the top end or bottom end of the display screen 50 , this is not restrictive. It may be formed at a location away from the display screen 50 . Besides, the dummy pixel row 281 does not need to contain a switching transistor 11 d or EL element 15 such as those shown in FIG. 1 . This reduces the size of the dummy pixel row 281 .
  • FIG. 28 shows a mechanism of how the state shown in FIG. 27 ( b ) takes place.
  • the final pixel row (dummy pixel row) 281 of the screen 50 is selected.
  • the dummy pixel row 281 is placed outside the screen 50 . That is, the dummy pixel row (dummy pixel) 281 does not illuminate, is not illuminated, or is hidden even if illuminated. For example, contact holes between the pixel electrode 105 and transistor 11 are eliminated, no EL film is formed on the dummy pixel row 281 , or the like. Also, an insulating film may be formed on the pixel electrode 105 of the dummy pixel row 271 .
  • the dummy pixel (row) 281 is provided (formed or placed) at the bottom of the screen 50 , this is not restrictive.
  • a dummy pixel row 281 should also be formed at the top of the screen 50 as shown in FIG. 29 ( b ). That is, dummy pixel rows 281 are formed (placed) both at the top and bottom of the screen 50 .
  • This configuration accommodates inverse scanning of the screen as well. Two pixel rows are selected simultaneously in the example described above.
  • the present invention is not limited to this.
  • five pixel rows may be selected simultaneously (see FIG. 23 ).
  • four dummy pixel rows 281 should be formed. That is, the number of dummy pixel rows 281 equals the number of pixel rows selected simultaneously minus one. However, this is true only when the selected pixel rows are shifted one by one.
  • (M ⁇ 1) ⁇ L dummy pixel rows should be formed, where M is the number of pixels selected and L is the number of pixel rows shifted at a time.
  • the dummy pixel row configuration or dummy pixel row driving according to the present invention uses one or more dummy pixel rows.
  • the larger the number of pixel rows selected simultaneously the more difficult it becomes to absorb variations in the characteristics of the transistors 11 a.
  • the current programmed into one pixel increases with decreases in the number M of pixel rows selected simultaneously, resulting in a large current flowing through the EL element 15 , which in turn makes the EL element 15 prone to degradation.
  • FIG. 30 shows how to solve this problem.
  • the basic concept behind FIG. 30 is to use a method of selecting a plurality of pixel rows simultaneously during 1 ⁇ 2 H (1 ⁇ 2 of a horizontal scanning period) as described with reference to FIGS. 22 and 29 and to use a method of selecting one pixel row in the latter 1 ⁇ 2 H (1 ⁇ 2 of the horizontal scanning period) as described with reference to FIGS. 5 and 13 .
  • This combination makes it possible to absorb variations in the characteristics of the transistors 11 a and achieve high speed and uniform surfaces.
  • the period of 1 ⁇ 2H is used for ease of understanding, this is not restrictive.
  • the first period may be 1 ⁇ 4 H and the second period may be 3 ⁇ 4 H.
  • the parasitic capacitance generated in the source signal line 18 and the like is charged and discharged in an extremely short period. Consequently, the potential of the source signal line 18 reaches a target potential in a short period of time and the terminal voltage of the capacitor 19 of each pixel 16 is programmed to pass a 25 times larger current.
  • the 25 times larger current is applied in the first 1 ⁇ 2 H (1 ⁇ 2 of the horizontal scanning period).
  • the transistors 11 d in the five write pixel rows are turned off in order not to display the image.
  • the display condition is as shown in FIG. 30 ( a 2 ).
  • one pixel is selected for current (voltage) programming.
  • the condition is as shown in FIG. 30 ( b 1 ).
  • Current (voltage) programming is performed so as to pass a five times larger current through the write pixel row 51 a as in the first period.
  • Equal current is passed in FIG. 30 ( a 1 ) and FIG. 30 ( b 1 ) to reach a target current more quickly by decreasing the changes in the terminal voltage of the programmed capacitor 19 .
  • FIG. 30 ( a 1 ) current is passed through a plurality of pixels, approaching an approximate target value quickly.
  • this first stage since a plurality of transistors 11 a are programmed, variations in the transistors cause error with respect to the target value.
  • the second stage only a pixel row where data will be written and held is selected and complete programming is performed by changing the value of current from the approximate target value to a predetermined target value.
  • FIG. 31 shows drive waveforms used to implement the drive method shown in FIG. 30 .
  • 1 H one horizontal scanning period
  • An ISEL signal is used to switch between the two phases.
  • the ISEL signal is illustrated in FIG. 31 .
  • the driver circuit 14 which performs operations shown in FIG. 30 comprises a current output circuit A and current output circuit B.
  • Each of the current output circuits consists of a D/A circuit which converts 8-bit gradation data from digital to analog, an operation amplifier, etc.
  • the current output circuit A is configured to output 25 times larger current.
  • the current output circuit B is configured to output 5 times larger current.
  • Outputs from the current output circuit A and current output circuit B are controlled by a switch circuit formed (placed) in a current output section through the ISEL signals and are applied to the source signal line 18 .
  • Such current output circuits are placed on each source signal line 18 .
  • the current output circuit A which outputs 25 times larger current is selected and current from the source signal line 18 is absorbed by the source driver IC 14 (more precisely, the current is absorbed by the current output circuit A formed in the source driver IC 14 ).
  • the magnification (such as ⁇ 25 or ⁇ 5) of the current from the current output circuits can be adjusted easily using a plurality of resisters and an analog switch.
  • the gate signal lines 17 a ( 1 ), ( 2 ), ( 3 ), ( 4 ), and ( 5 ) are selected (in the case of configuration shown in FIG. 1 ). That is, the switching transistors 11 b and the transistors 11 c in the pixel rows ( 1 ), ( 2 ), ( 3 ), ( 4 ), and ( 5 ) are on. Besides, since ISEL is low, the current output circuit A which outputs 25 times larger current is selected and connected to the source signal line 18 . Also, a turn-off voltage (Vgh) is applied to the gate signal line 17 b.
  • Vgh turn-off voltage
  • the switching transistors 11 d in the pixel rows ( 1 ), ( 2 ), ( 3 ), ( 4 ), and ( 5 ) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52 .
  • the transistors 11 a in the five pixels deliver a current of Iw ⁇ 2 each to the source signal line 18 .
  • the capacitor 19 of each pixel 16 is programmed with a five times larger current.
  • the transistors have equal characteristics (Vt and S value).
  • the total programming current of the five transistors 11 a flows through the source signal line 18 .
  • the current written into the write pixel row 51 a by a conventional drive method is Iw
  • a current of Iw ⁇ 25 is passed through the source signal line 18 .
  • the write pixel rows 51 b into which image data is written later than the write pixel row ( 1 ) are auxiliary pixel rows used to increase the amount of current delivered to the source signal line 18 .
  • regular image data is written into the write pixel rows 51 b later.
  • the pixel rows 51 b provide the same display as the pixel row 51 a during a period of 1 H. Consequently, at least the write pixel row 51 a and the pixel rows 51 b selected to increase current are in non-display mode 52 .
  • the write pixel row 51 a is selected. That is, only the (1)-th pixel row is selected.
  • a turn-on voltage (Vgl) is applied only to the gate signal line 17 a ( 1 ) and a turn-off voltage (Vgh) is applied to the gate signal lines 17 a ( 2 ), ( 3 ), ( 4 ), and ( 5 ).
  • Vgl turn-on voltage
  • Vgh turn-off voltage
  • the transistor 11 a in the pixel row ( 1 ) is in operation (supplying current to the source signal line 18 ), but the switching transistors 11 b and the transistors 11 c in the pixel rows ( 2 ), ( 3 ), ( 4 ), and ( 5 ) are off. That is, they are non-selected.
  • the current output circuit B which outputs 5 times larger current is selected and connected to the source signal line 18 .
  • a turn-off voltage (Vgh) is applied to the gate signal line 17 b, which is in the same state as during the first 1 ⁇ 2 H.
  • the switching transistors 11 d in the pixel rows ( 1 ), ( 2 ), ( 3 ), ( 4 ), and ( 5 ) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52 .
  • each transistor 11 a in the pixel row ( 1 ) deliver a current of Iw ⁇ 5 to the source signal line 18 .
  • the capacitor 19 in each pixel row ( 1 ) is programmed with a 5 times larger current.
  • the write pixel row shifts by one. That is, the pixel row ( 2 ) becomes the current write pixel row.
  • the gate signal lines 17 a ( 2 ), ( 3 ), ( 4 ), and ( 5 ) and ( 6 ) are selected. That is, the switching transistors 11 b and the transistors 11 c in the pixel rows ( 2 ), ( 3 ), ( 4 ), ( 5 ), and ( 6 ) are on.
  • ISEL since ISEL is low, the current output circuit A which outputs 25 times larger current is selected and connected to the source signal line 18 . Also, a turn-off voltage (Vgh) is applied to the gate signal line 17 b.
  • the switching transistors 11 d in the pixel rows ( 2 ), ( 3 ), ( 4 ), ( 5 ), and ( 6 ) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52 .
  • Vgl voltage is applied to the gate signal line 17 b ( 1 ) of the pixel row ( 1 )
  • the transistor 11 d is on and the EL element 15 in the pixel row ( 1 ) illuminates.
  • a turn-on voltage (Vgl) is applied only to the gate signal line 17 a ( 2 ) and a turn-off voltage (Vgh) is applied to the gate signal lines 17 a ( 3 ), ( 4 ), ( 5 ), and ( 6 ).
  • the transistors 11 a in the pixel rows ( 1 ) and ( 2 ) are in operation (the pixel row ( 1 ) supplies current to the EL element 15 and the pixel row ( 2 ) supplies current to the source signal line 18 ), but the switching transistors 11 b and the transistors 11 c in the pixel rows ( 3 ), ( 4 ), ( 5 ), and ( 6 ) are off. That is, they are non-selected.
  • the current output circuit B which outputs 5 times larger current is selected and the current output circuit 1222 b is connected to the source signal line 18 .
  • a turn-off voltage (Vgh) is applied to the gate signal line 17 b, which is in the same state as during the first 1 ⁇ 2 H.
  • the switching transistors 11 d in the pixel rows ( 2 ), ( 3 ), ( 4 ), ( 5 ), and ( 6 ) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52 .
  • each transistor 11 a in the pixel row ( 1 ) deliver a current of Iw ⁇ 5 to the source signal line 18 .
  • the capacitor 19 in each pixel row ( 1 ) is programmed with a 5 times larger current.
  • the entire screen is drawn as the above operations are performed in sequence.
  • the drive method described with reference to FIG. 30 selects G pixel rows (G is 2 or larger) in the first period and does programming in such a way as to pass N times larger current through each pixel row.
  • the drive method selects B pixel rows (B is smaller than G, but not smaller than 1) and does programming in such a way as to pass an N times larger current through the pixels.
  • Another scheme is also available. It selects G pixel rows (G is 2 or larger) in the first period and does programming in such a way that the total current in all the pixel rows will be an N times larger current.
  • a plurality of pixel rows are selected simultaneously in a period of 1 ⁇ 2 H and a single pixel row is selected in a period of 1 ⁇ 2 H in FIG. 31 , this is not restrictive.
  • a plurality of pixel rows may be selected simultaneously in a period of 1 ⁇ 4 H and a single pixel row may be selected in a period of 3 ⁇ 4 H.
  • the sum of the period in which a plurality of pixel rows are selected simultaneously and the period in which a single pixel row is selected is not limited to 1 H.
  • the total period may be 2 Hs or 1.5 Hs.
  • FIG. 30 it is also possible to select two pixel rows simultaneously in the second period after selecting five pixel rows simultaneously in the first 1 ⁇ 2 H. This can also achieve a practically acceptable image display.
  • pixel rows are selected in two stages—five pixel rows are selected simultaneously in the first 1 ⁇ 2 H period and a single pixel row is selected in the second 1 ⁇ 2 H period, but this is not restrictive. For example, it is also possible to select five pixel rows simultaneously in the first stage, select two of the five pixel rows in the second stage, and finally select one pixel row in the third stage. In short, image data may be written into pixel rows in two or more stages.
  • pixel rows are selected one by one and programmed with current, or two or more pixel rows are selected at a time and programmed with current.
  • the present invention is not limited to this. It is also possible to use a combination of the two methods according to image data: the method of selecting pixel rows one by one and programming them with current and the method of selecting two or more pixel rows at a time and programming them with current.
  • FIG. 186 combines a drive system which selects pixel rows one by one and a drive method which selects multiple pixel rows one by one.
  • one dummy pixel row 281 each is formed at the top and bottom of the screen.
  • the drive system which selects pixel rows one by one does not need to use dummy pixel rows.
  • the drive system which selects two pixel rows at a time as shown in FIG. 186 ( a 2 ) provides half the screen brightness compared to the drive system which selects pixel rows one by one as shown in FIG. 186 ( a 1 ).
  • the magnitude of the reference current inputted in the source driver IC 14 can be varied twice as much.
  • the programming current can be doubled.
  • FIG. 186 ( a 1 ) shows a typical drive method according to the present invention.
  • the drive method in FIG. 186 ( a 1 ) and drive method in FIG. 186 ( a 2 ) can be switched easily by controlling the start pulse supplied to the gate driver circuit 12 .
  • a problem is that the drive system which selects two pixel rows at a time as shown in FIG. 186 ( a 2 ) provides half the screen brightness compared to the drive system which selects pixel rows one by one ( FIG. 186 ( a 1 )).
  • the proportions of the non-display area 52 and display area 53 in FIG. 186 ( b ) can be varied easily by controlling the start pulse supplied to the gate driver circuit 12 . That is, the drive mode in FIG. 186 ( b ) can be varied according the display mode in FIGS. 186 ( a 1 ) and 186 ( a 2 ).
  • FIG. 187 shows a configuration of the display panel according to the present invention which performs the interlaced driving.
  • the gate signal lines 17 a of odd-numbered pixel rows are connected to a gate driver circuit 12 a 1 .
  • the gate signal lines 17 a of even-numbered pixel rows are connected to a gate driver circuit 12 a 2 .
  • the gate signal lines 17 b of the odd-numbered pixel rows are connected to a gate driver circuit 12 b 1 .
  • the gate signal lines 17 b of the even-numbered pixel rows are connected to a gate driver circuit 12 b 2 .
  • FIG. 188 ( a ) shows operating state in the first field of the display panel.
  • FIG. 188 ( b ) shows operating state in the second field of the display panel.
  • the oblique hatching which marks the gate driver circuits 12 indicates that the gate driver circuits 12 are not taking part in data scanning operation.
  • the gate driver circuit 12 a 1 is operating for write control of programming current and the gate driver circuit 12 b 2 is operating for illumination control of the EL element 15 .
  • the gate driver circuit 12 a 2 is operating for write control of programming current and the gate driver circuit 12 b 1 is operating for illumination control of the EL element 15 .
  • the above operations are repeated within the frame.
  • FIG. 189 shows image display status in the first field.
  • FIG. 189 ( a ) illustrates write pixel rows (locations of odd-numbered pixel rows programmed with current (voltage). The location of the write pixel row is shifted in sequence: FIG. 189 ( a 1 ) ⁇ ( a 2 ) ⁇ ( a 3 ). In the first field, odd-numbered pixel rows are rewritten in sequence (image data in the even-numbered pixel rows are maintained).
  • FIG. 189 ( b ) illustrates display status of odd-numbered pixel rows. Incidentally, FIG. 189 ( b ) illustrates only odd-numbered pixel rows. Even-numbered pixel rows are illustrated in FIG. 189 ( c ). As can be seen from FIG.
  • the EL elements 15 of the pixels in the odd-numbered pixel rows are non-illuminated.
  • the even-numbered pixel rows are scanned in both display area 53 and non-display area 52 as shown in FIG. 189 ( c ) (N-fold pulse driving).
  • FIG. 190 shows image display status in the second field.
  • FIG. 190 ( a ) illustrates write pixel rows (locations of odd-numbered pixel rows programmed with current (voltage). The location of the write pixel row is shifted in sequence: FIG. 190 ( a 1 ) ⁇ ( a 2 ) ⁇ ( a 3 ). In the second field, even-numbered pixel rows are rewritten in sequence (image data in the odd-numbered pixel rows are maintained).
  • FIG. 190 ( b ) illustrates display status of odd-numbered pixel rows. Incidentally, FIG. 190 ( b ) illustrates only odd-numbered pixel rows. Even-numbered pixel rows are illustrated in FIG. 190 ( c ). As can be seen from FIG.
  • the EL elements 15 of the pixels in the even-numbered pixel rows are non-illuminated.
  • the odd-numbered pixel rows are scanned in both display area 53 and non-display area 52 as shown in FIG. 190 ( c ) (N-fold pulse driving).
  • interlaced driving can be implemented easily on an EL display panel.
  • N-fold pulse driving eliminates shortages of write current and blurred moving pictures.
  • current (voltage) programming and illumination of EL elements 15 can be controlled easily and circuits can be implemented easily.
  • the drive method according to the present invention is not limited to those shown in FIGS. 189 and 190 .
  • a drive method shown in FIG. 191 is also available.
  • the example in FIG. 191 involves synchronizing the gate driver circuits 12 b 1 and 12 b 2 which control illumination of the EL elements 15 .
  • the write pixel row 51 being programmed with current (voltage) belongs to a non-display area (there is no need for this in the case of the current-mirror pixel configuration in FIG. 38 ).
  • FIG. 191 uses illumination control for both odd-numbered pixel rows and even-numbered pixel rows.
  • FIG. 192 shows an example in which illumination control varies between odd-numbered pixel rows and even-numbered pixel rows.
  • the illumination mode (display area 53 and non-display area 52 ) of odd-numbered pixel rows and illumination mode of even-numbered pixel rows have opposite patterns.
  • display area 53 and non-display area 52 have the same size.
  • this is not restrictive.
  • the drive method programs pixel rows with current (voltage) one at a time.
  • the drive method according to the present invention is not limited to this. Needless to say, two pixel rows (a plurality of pixel rows) maybe programmed with current (voltage) simultaneously as shown in FIG. 193 .
  • FIGS. 190 and 189 it is not strictly necessary to put all the odd-numbered pixel rows or even-numbered pixel rows in non-illumination mode.
  • the N-fold pulse driving method according to the present invention uses the same waveform for the gate signal lines 17 b of different pixel rows and applies current by shifting the pixel rows at 1 H intervals.
  • the use of such scanning makes it possible to shift illuminating pixel rows in sequence with the illumination duration of the EL elements 15 fixed to 1F/N. It is easy to shift pixel rows in this way while using the same waveform for the gate signal lines 17 b of the pixel rows. It can be done by simply controlling data ST 1 and ST 2 applied to the shift register circuits 61 a and 61 b in FIG. 6 .
  • ST 2 applied to the shift register circuit 17 b can be set low for a period of 1F/N and set high for the remaining period. Then, inputted ST 2 can be shifted using a clock CLK 2 synchronized with 1 H.
  • the EL elements 15 must be turned on and off at intervals of 0.5 msec or longer. Short intervals will lead to insufficient black display due to persistence of vision, resulting in blurred images and making it look as if the resolution has lowered. This also represents a display state of a data holding display. However, increasing the on/off intervals to 100 msec will cause flickering. Thus, the on/off intervals of the EL elements must be not shorter than 0.5 ⁇ sec and not longer than 100 msec. More preferably, the on/off intervals should be from 2 msec to 30 msec (both inclusive). Even more preferably, the on/off intervals should be from 3 msec to 20 msec (both inclusive).
  • an undivided black screen 152 achieves good movie display, but makes flickering of the screen more noticeable.
  • the number of divisions should be from 1 to 8 (both inclusive). More preferably, it should be from 1 to 5 (both inclusive).
  • the number of divisions of a black screen can be varied between still pictures and moving pictures.
  • the number of divisions is 1, a strip of black display which makes up 75% is scanned vertically.
  • the number of divisions is 3, three blocks are scanned, where each block consists of a black screen which makes up 25% and a display. screen which makes up 25/3 percent.
  • the number of divisions is increased for still pictures and decreased for moving pictures.
  • the switching can be done either automatically according to input images (detection of moving pictures) or manually by the user. Alternatively, the switching can be done according to input outlet such as video on the display apparatus.
  • the number of divisions should be 10 or more (in extreme cases, the display may be turned on and off every 1 H).
  • the number of divisions should be from 1 to 5 (both inclusive).
  • the number of divisions can be switched in three or more steps; for example, 0, 2, 4, 8 divisions, and so on
  • the ratio of the black screen to the entire display screen should be from 0.2 to 0.9 (from 1.2 to 9 in terms of N) both inclusive when the area of the entire screen is taken as 1. More preferably, the ratio should be from 0.25 to 0.6 (from 1.25 to 6 in terms of N) both inclusive. If the ratio is 0.20 or less, movie display is not improved much. When the ratio is 0.9 or more, the display part becomes bright and its vertical movements become liable to be recognized visually.
  • the number of frames per second is from 10 to 100 (10 Hz to 100 Hz) both inclusive. More preferably, it is from 12 to 65 (12 Hz to 65 Hz) both inclusive.
  • the number of frames is small, flickering of the screen becomes conspicuous while too large a number of frames makes writing from the source driver circuit 14 and the like difficult, resulting in deterioration of resolution.
  • the present invention allows the brightness of images to be varied by controlling the gate signal lines 17 .
  • the brightness of images may be varied by varying the current (voltage) applied to the source signal lines 18 .
  • the two methods described above FIGS. 33 and 35 and the like may be used in combination: the method of controlling the gate signal lines 17 and the method of varying the current (voltage) applied to the source signal lines 18 .
  • the above items also apply to the pixel configurations for current programming in FIG. 38 and the like as well as to the pixel configurations for voltage programming in FIGS. 43, 51 , 54 , and the like.
  • This can be accomplished through on/off control of the transistor 11 d in FIG. 38 , transistor 11 d in FIG. 43 , and transistor 11 e in FIG. 51 .
  • the N-fold pulse driving according to the present invention can be implemented easily.
  • the gate signal line 17 b may be set to Vgl for a period of 1F/N anytime during the period of 1F (not limited to 1F. Any unit time will do). This is because a predetermined brightness is obtained by turning off the EL element 15 for a predetermined period out of a unit time. However, it is preferable to set the gate signal line 17 b to Vgl and illuminate the EL element 15 immediately after the current programming period (1 H). This will reduce the effect of retention characteristics of the capacitor 19 in FIG. 1 .
  • the number of screen divisions is configured to be variable. For example, when the user presses a brightness adjustment switch or turns a brightness adjustment knob, the value of K may be changed in response. Alternatively, the value of K may be changed manually or automatically depending on images or data to be displayed.
  • the mechanism for changing the value of K (the number of divisions of the image display part 53 ) can be implemented easily. This can be achieved by simply making the time to change ST (when to set ST low during 1F) adjustable or variable.
  • a period (1F/N) during which the gate signal line 17 b is set to Vgl is divided into a plurality of parts (K parts) and that a period of 1F/(K ⁇ N) during which the gate signal line 17 b is set to Vgl repeats K times, this is not restrictive.
  • a period of 1F/(K ⁇ N) may be repeated L (L ⁇ K) times.
  • the present invention displays the display screen 50 by controlling the period (time) during which current is passed through the EL element 15 .
  • the idea of repeating the 1F/(K ⁇ N) period L (L ⁇ K) times is included in the technical idea of the present invention.
  • the control described here is also applicable to other examples of the present invention (of course, it is applicable to what is described later herein). These are also included in the N-fold pulse driving according to the present invention.
  • the above examples involve placing (forming) the transistor 11 d serving as a switching element between the EL element 15 and driver transistor 11 a and turning on and off the screen 50 by controlling the transistor 11 d.
  • This drive method eliminates shortages of write current in black display condition during current programming and thereby achieves proper resolution or black display. That is, in current programming, it is important to achieve proper black display.
  • the pixel configuration in FIG. 32 is basically the same as the one shown in FIG. 1 .
  • a programmed Iw current flows through the EL element 15 , illuminating the EL element 15 .
  • the driver transistor 11 a retains a capability to pass current.
  • the drive system shown in FIG. 32 resets (turns off) the transistor 11 a using this capability to pass current.
  • this drive system will be referred to as reset driving.
  • the transistors 11 b and 11 c must be able to be switched on and off independently of each other. Specifically, as illustrated in FIG. 32 , it is necessary to be able to independently control the gate signal line 17 a (gate signal line WR) used for on/off control of the transistor 11 b and the gate signal line 17 c (gate signal line EL) used for on/off control of the transistor 11 c.
  • the gate signal lines 17 a and 17 c can be controlled using two independent shift registers 61 as illustrated in FIG. 6 .
  • the drive voltage should be varied between the gate signal line 17 a which drives the transistor 11 b and the gate signal line 17 b which drives the transistor 11 d (when the pixel configuration in FIG. 1 is used).
  • the amplitude value (difference between turn-on voltage and turn-off voltage) of the gate signal line 17 a should be smaller than the amplitude value of the gate signal line 17 b.
  • Too large an amplitude value of the gate signal line 17 will increase penetration voltage between the gate signal line 17 and pixel 16 , resulting in an insufficient black level.
  • the amplitude of the gate signal line 17 a can be controlled by controlling the time when the potential of the source signal line 18 is not applied (or is applied (during selection)) to the pixel 16 . Since changes in the potential of the source signal line 18 are small, the amplitude value of the gate signal line 17 a can be made small.
  • the gate signal line 17 b is used for on/off control of EL.
  • its amplitude value becomes large.
  • output voltage is varied between the shift register circuits 61 a and 61 b. If the pixel is constructed of P-channel transistors, approximately equal Vgh (turn-off voltage) is used for the shift register circuits 61 a and 61 b while Vgl (turn-on voltage) of the shift register circuit 61 a is made lower than Vgl (turn-on voltage) of the shift register circuit 61 b.
  • FIG. 33 is a diagram illustrating a principle of reset driving.
  • the transistors 11 c and 11 d are turned off and the transistor 11 b is turned on.
  • the drain (D) terminal and gate (G) terminal of the driver transistor 11 a are short-circuited, allowing a current Ib to flow.
  • the transistor 11 a has been programmed with current in the previous field (frame) In this state, as the transistor 11 d is turned off and the transistor 11 b is turned on, the drive current Ib flows through the gate (G) terminal of the transistor 11 a. Consequently, the gate (G) terminal and drain (D) terminal of the transistor 11 a have the same potential, resetting the transistor 11 a (to a state in which no current flows).
  • the reset mode (in which no current flows) of the transistor 11 a is equivalent to a state in which an offset voltage is held in voltage offset canceling mode described with reference to FIG. 51 and the like.
  • the offset voltage is held between the terminals of the capacitor 19 .
  • the offset voltage varies with the characteristics of the transistor 11 a.
  • a state in which the transistor 11 a does not pass current is maintained in the capacitor 19 in each pixel (i.e., the transistor 11 a passes a black display current close to zero).
  • the operating time is from 0.1% to 10% of 1 H (one horizontal scanning period) both inclusive. More preferably, it is from 0.2% to 2% or from 0.2 ⁇ sec to 5 ⁇ sec (both inclusive). Also, this operation (the operation to be performed before the operation in FIG.
  • the operation time of FIG. 33 ( a ) As the operation time of FIG. 33 ( a ) becomes longer, a larger Ib current tends to flow, reducing the terminal voltage of the capacitor 19 . Thus, the operation time of FIG. 33 ( a ) should be fixed. It has been shown experimentally and analytically that preferably the operation time in FIG. 33 ( a ) is from 1 H to 5 Hs (both inclusive).
  • this period should be varied among R, G, and B pixels. This is because EL material varies among different colors and rising voltage varies among different EL materials. Optimum periods suitable for EL materials should be specified separately for the R, G, and B pixels. Although it has been stated that the period should be from 1 H to 5 Hs (both inclusive) in this example, it goes without saying that the period may be 5 Hs or longer in the case of a drive system which mainly concerns black insertion (writing of a black screen). Incidentally, the longer the period, the better the black display condition of pixels.
  • FIG. 33 ( b ) shows a state in which the transistors 11 c and 11 b are on and the transistor 11 d is off. This is a state in which current programming is being performed, as described earlier. Specifically, a programming current Iw is output (or absorbed) from the source driver circuit 14 and passed through the driver transistor 11 a. The potential of the gate (G) terminal of the driver transistor 11 a is set so that the programming current Iw flows (the set potential is held in the capacitor 19 ).
  • the transistor 11 a is held in the state in FIG. 33 ( a ) in which it does not pass current, and thus a proper black display is achieved. Also, when performing current programming for white display in FIG. 33 ( b ), the current programming is started from offset voltage of completely black display even if there are variations in the characteristics of driver transistors in pixels. Thus, the time required to reach a target current value becomes uniform according to gradations. This eliminates gradation errors due to variations in the characteristics of the transistors 11 a, making it possible to achieve proper image display.
  • Iw programming current
  • FIG. 33 ( c ) What is shown in FIG. 33 ( c ) has already been described with reference to FIG. 1 and the like, and thus detailed description thereof will be omitted.
  • the drive system (reset driving) described with reference to FIG. 33 consists of a first operation of disconnecting the driver transistor 11 a from the EL element 15 (so that no current flows) and shorting between the drain (D) terminal and gate (G) terminal of the driver transistor (or between the source (S) terminal and gate (G) terminal, or generally speaking, between two terminals including the gate (G) terminal of the driver transistor) and a second operation of programming the driver transistor with current (voltage) after the first operation. At least the second operation is performed after the first operation.
  • the transistors 11 b and 11 c must be able to be controlled independently as shown in FIG. 32 .
  • the pixel row to be programmed with current is reset (black display mode) and is programmed with current after 1 H (also in black display mode because the transistor 11 d is off).
  • current is supplied to the EL element 15 and the pixel row illuminates at a predetermined brightness (at the programmed current). That is, the pixel row of black display moves from top to bottom of the screen and it should look as if the image were rewritten at the location where the pixel row passed by.
  • this period may be approximately 5 Hs or shorter. This is because it takes a relatively long time for the reset in FIG. 33 ( a ) to be completed. If this period is 5 Hs, five pixel rows will be displayed in black (six pixel rows including the pixel row going through current programming).
  • the number of pixel rows which are reset at a time is not limited to one, and two or more pixel rows may be reset at a time. It is also possible to reset and scan two or more pixel rows at a time by overlapping some of them. For example, if four pixel rows are reset at a time, pixel rows ( 1 ), ( 2 ), ( 3 ), and ( 4 ) are reset in the first horizontal scanning period ( 1 unit), pixel rows ( 3 ), ( 4 ), ( 5 ), and ( 6 ) are reset in the second horizontal scanning period, pixel rows ( 5 ), ( 6 ), ( 7 ), and ( 8 ) are reset in the third horizontal scanning period, and pixel rows ( 7 ), ( 8 ), ( 9 ), and ( 10 ) are reset in the fourth horizontal scanning period.
  • the drive operations in FIGS. 33 ( b ) and 33 ( c ) are naturally carried out in sync with the drive operation in FIG. 33 ( a ).
  • FIGS. 33 ( b ) and 33 ( c ) may be performed after resetting all the pixels in the screen simultaneously or during scanning.
  • pixel rows may be reset (at intervals of one or more pixel rows) in interlaced driving mode (scanning at intervals of one or more pixel rows).
  • pixel rows may be reset at random.
  • the reset driving according to the present invention involves operating pixel rows (i.e., controlling the vertical direction of the screen).
  • the concept of reset driving does not limit control directions to the pixel row direction.
  • reset driving may be performed in the direction of pixel columns.
  • the reset driving in FIG. 33 can achieve better image display if combined with the N-fold pulse driving according to the present invention or with interlaced driving.
  • the configuration in FIG. 22 can easily implement intermittent N/K-fold pulse driving (this driving method provides two or more illuminated areas in a screen and can be implemented easily by turning on and off the transistor 11 d by controlling the gate signal line 17 b: this has been described earlier), and thus can achieve proper image display without flickering.
  • FIG. 34 is a block diagram of a display apparatus which implement reset driving.
  • the gate driver circuit 12 a controls the gate signal line 17 a and gate signal line 17 b in FIG. 32 .
  • the transistor 11 b is turned on and off.
  • the transistor 11 d is turned on and off.
  • the gate driver circuit 12 b controls the gate signal line 17 c in FIG. 32 .
  • the transistor 11 c is turned on and off.
  • the gate signal line 17 a is controlled by the gate driver circuit 12 a while the gate signal line 17 c is controlled by the gate driver circuit 12 b.
  • Other parts of the configuration are the same as or similar to those described earlier, and thus description thereof will be omitted.
  • FIG. 35 is a timing chart of reset driving. While a turn-on voltage is applied to the gate signal line 17 a to turn on the transistor 11 b and reset the driver transistor 11 a, a turn-off voltage is applied to the gate signal line 17 b to keep the transistor 11 d off. This creates the state shown in FIG. 32 ( a ). A current Ib flows during this period.
  • the reset time is 2 Hs (when a turn-on voltage is applied to the gate signal line 17 a and the transistor 11 b is turned on), this is not restrictive.
  • the reset time may be longer than 2 Hs. If a reset can be performed very quickly, the reset time may be less than 1 H.
  • the duration of the reset period can be changed easily using a DATA (ST) pulse period inputted in the gate driver circuit 12 .
  • a DATA (ST) pulse period inputted in the gate driver circuit 12 .
  • the reset period outputted for each gate signal line 17 a is 2 Hs.
  • the reset period outputted for each gate signal line 17 a is 5 Hs.
  • a turn-on voltage is applied to the gate signal line 17 c ( 1 ) of the pixel row ( 1 ).
  • the programming current Iw applied to the source signal line 18 is written into the driver transistor 11 a via the transistor 11 c.
  • a turn-off voltage is applied to the gate signal line 17 c of the pixel row ( 1 ), the transistor 11 c is turned off, and the pixel disconnected from the source signal line.
  • a turn-off voltage is also applied to the gate signal line 17 a and the driver transistor 11 a exits the reset mode (incidentally, the use of the term “current-programming mode” is more appropriate than the term “reset mode” to refer to this period).
  • a turn-on voltage is applied to the gate signal line 17 b, the transistor 11 d is turned on, and the current programmed into the driver transistor 11 a flows through the EL element 15 .
  • What has been said about the pixel row ( 1 ) similarly applies to the pixel row ( 2 ) and subsequent pixel rows. Also, their operation is obvious from FIG. 35 . Thus, description of ( 2 ) and subsequent pixel rows will be omitted.
  • FIG. 35 the reset period has been 1 H.
  • FIG. 36 shows an example in which the reset period is 5 Hs. The duration of the reset period can be changed easily using the DATA (ST) pulse period inputted in the gate driver circuit 12 .
  • FIG. 36 shows an example in which DATA inputted in the ST 1 terminal of the gate driver circuit 12 a is set high for a period of 5 Hs and the reset period outputted for each gate signal line 17 a is 5 Hs. The longer the reset period, the more completely the reset is performed, resulting in a proper black display. However, display brightness is decreased accordingly.
  • the reset period has been 5 Hs.
  • the reset mode is continuous.
  • the reset mode need not necessarily be continuous.
  • the signal outputted from each gate signal line 17 a may be turned on and off every 1 H. Such on/off operation can be achieved easily by operating an enable circuit (not shown) formed in the output stage of the shift register or controlling the DATA (ST) pulses inputted in the gate driver circuit 12 .
  • the gate driver circuit 12 a requires at least two shift register circuits (one for the gate signal line 17 a, the other for the gate signal line 17 b ). This presents a problem of an increased circuit scale of the gate driver circuit 12 a.
  • FIG. 37 shows an example in which the gate driver circuit 12 a has only one shift register. A timing chart of output signals resulting from operation of the circuit in FIG. 37 is shown in FIG. 35 . Note that the gate signal lines 17 coming out of the gate driver circuits 12 a and 12 b are denoted by different symbols between FIGS. 35 and 37 .
  • each gate signal line 17 a is ORed with the output from the preceding stage to the shift register circuit 61 a. That is, the gate signal line 17 a outputs a turn-on voltage for a period of 2 Hs.
  • the gate signal line 17 c outputs the output of the shift register circuit 61 a as it is. Thus, a turn-on voltage is applied for a period of 1 H.
  • a turn-on voltage is output to the gate signal lines 17 c of the pixel 16 ( 1 ), which now is in a state of being programmed with current (voltage).
  • a turn-on voltage is also output to the gate signal lines 17 a of the pixel 16 ( 2 ), turning on the transistor 11 b of the pixel 16 ( 2 ) and resetting the driver transistor 11 a of the pixel 16 ( 2 ).
  • a turn-on voltage is output to the gate signal lines 17 c of the pixel 16 ( 2 ), which now is in a state of being programmed with current (voltage).
  • a turn-on voltage is also output to the gate signal lines 17 a of the pixel 16 ( 3 , turning on the transistor 11 b of the pixel 16 ( 3 ) and resetting the driver transistor 11 a of the pixel 16 ( 3 ).
  • the gate signal lines 17 a outputs turn-on voltages for a period of 2 Hs
  • the gate signal lines 17 c receive a turn-on voltage for a period of 1 H.
  • FIG. 32 (basically, in FIG. 1 ).
  • the present invention is not limited to this.
  • it is also applicable to current-mirror pixel configurations such as the one shown in FIG. 38 .
  • FIG. 38 by turning on and off the transistor 11 e, N-fold pulse driving illustrated in FIGS. 13, 15 , etc. can be implemented.
  • FIG. 39 is an explanatory diagram illustrating an example employing the current-mirror pixel configuration shown in FIG. 38 . Reset driving in the current-mirror pixel configuration will be described below with reference to FIG. 39 .
  • the transistors 11 c and 11 e are turned off and the transistor 11 d is turned on. Then, the drain (D) terminal and gate (G) terminal of the current-programming transistor 11 b are short-circuited and a current Ib flows between them as shown in the figure.
  • the transistor 11 b has been programmed with current in the previous field (frame) and is capable of passing current (this is natural because the gate potential is held in the capacitor 19 for a period of 1F and image is displayed. However, current does not flow during a completely black display).
  • the drive current Ib flows through the gate (G) terminal of the transistor 11 a (gate (G) terminal and the drain (D) terminal are short-circuited). Consequently, the gate (G) terminal and drain (D) terminal of the transistor 11 a have the same potential, resetting the transistor 11 a (to a state in which no current flows). Since the driver transistor 11 b shares a common gate (G) terminal with the current-programming transistor 11 a, the driver transistor 11 b is also reset.
  • the reset mode (in which no current flows) of the transistors 11 a and 11 b is equivalent to a state in which a offset voltage is held in voltage offset canceling mode described with reference to FIG. 51 and the like. That is, in the state in FIG. 39 ( a ), the offset voltage is held between the terminals of the capacitor 19 (the offset voltage is a starting voltage at which a current starts to flow: when a voltage equal to or larger than the starting voltage is applied, a current flows through the transistor 11 ).
  • the offset voltage varies with the characteristics of the transistors 11 a and 11 b.
  • the operation time in FIG. 39 ( a ) should be fixed. It has been shown experimentally and analytically that preferably the operation time in FIG. 39 ( a ) is from 1 H to 10 Hs (ten horizontal scanning periods) both inclusive. More preferably, it should be from 1 H to 5 Hs or from 20 ⁇ sec to 2 msec (both inclusive). This also applies to the drive system in FIG. 33 .
  • the period from the reset mode in FIG. 39 ( a ) to the current-programming mode in FIG. 39 ( b ) is fixed (constant). That is, preferably the period from the reset mode in FIG. 33 ( a ) or FIG. 39 ( a ) to the current-programming mode in FIG. 33 ( b ) or FIG. 39 ( b ) should be from 1 H to 10 Hs (ten horizontal scanning periods) both inclusive. More preferably, it should be from 1 H to 5 Hs or from 20 ⁇ sec to 2 msec (both inclusive). If this period is short, the driver transistors 11 are not reset completely. If it is too long, the driver transistor 11 is turned off completely, which means that much time is required for current programming. Also, the brightness of the screen 50 is decreased.
  • FIG. 39 ( b ) shows a state in which the transistors 11 c and 11 d are turned on and the transistor 11 e is turned off. This is a state in which current programming is being performed. Specifically, a programming current Iw is output (absorbed) from the source driver circuit 14 and passed through the current programming transistor 11 a. The potential of the gate (G) terminal of the driver transistor 11 a is set in the capacitor 19 so that the programming current Iw will flow.
  • the transistor 11 b is held in the state in FIG. 33 ( a ) in which it does not pass current, and thus proper black display is achieved. Also, when performing current programming for white display in FIG. 39 ( b ), the current programming is started from offset voltage of completely black display even if there are variations in the characteristics of driver transistors in pixels (the offset voltage is a starting voltage at which a current specified according to the characteristics of each driver transistor starts to flow). Thus, the time required to reach a target current value becomes uniform according to gradations. This eliminates gradation errors due to variations in the characteristics of the transistor 11 a or 11 b, making it possible to achieve proper image display.
  • Iw programming current
  • the drive system (reset driving) described with reference to FIGS. 33 and 39 consists of a first operation of disconnecting the driver transistor 11 a or 11 b from the EL element 15 (using the transistor 11 e or 11 d so that no current flows) and shorting between the drain (D) terminal and gate (G) terminal of the driver transistor (or between the source (S) terminal and gate (G) terminal, or generally speaking, between two terminals including the gate (G) terminal of the driver transistor) and a second operation of programming the driver transistor with current (voltage) after the first operation.
  • At least the second operation is performed after the first operation.
  • the operation of disconnecting the driver transistor 11 a or 11 b from the EL element 15 in the first operation is not absolutely necessary.
  • the drain (D) terminal and gate (G) terminal of the driver transistor are short-circuited in the first operation without disconnecting the driver transistor 11 a or 11 b from the EL element 15 , nothing more than some variations in reset mode may result. Whether to omit disconnection should be determined by considering the characteristics of the transistors in the constructed array.
  • the current-mirror pixel configuration in FIG. 39 provides a drive method which resets the current-programming transistor 11 a, and consequently resets the driver transistor 11 b.
  • the pixel row to be programmed with current is reset (black display mode) and is programmed with current after a predetermined H.
  • the pixel row of black display moves from top to bottom of the screen and it should look as if the image were rewritten at the location where the pixel row passed by.
  • FIG. 43 is an explanatory diagram illustrating a pixel configuration (panel configuration) according to the present invention used to perform reset driving in a pixel configuration for voltage programming.
  • a transistor 11 e which resets a driver transistor 11 a has been formed.
  • the transistor 11 e turns on, causing a short circuit between the gate (G) terminal and drain (D) terminal of the driver transistor 11 a.
  • a transistor 11 d which cuts off a current path between the EL element 15 and driver transistor 11 a has been formed.
  • the transistors 11 b and 11 d are turned off and the transistor 11 e is turned on.
  • the drain (D) terminal and gate (G) terminal of the driver transistor 11 a are short-circuited and a current Ib flows as shown in the figure. Consequently, the gate (G) terminal and drain (D) terminal of the transistor 11 a have the same potential, resetting the transistor 11 a (to a state in which no current flows).
  • the transistor 11 d is turned on, the transistor 11 e is turned off, and current is passed through the transistor 11 a in sync with an HD synchronization signal as described with reference to FIG. 33 or 39 . Then the operation shown in FIG. 44 ( a ) is performed.
  • the reset mode (in which no current flows) of the transistors 11 a and 11 b is equivalent to a state in which an offset voltage is held in voltage offset canceling mode described with reference to FIG. 41 and the like. That is, in the state in FIG. 44 ( a ), the offset voltage (reset voltage) is held between the terminals of the capacitor 19 . The reset voltage varies with the characteristics of the driver transistor 11 a. Thus, in FIG. 44 ( a ), a state in which the driver transistors 11 a do not pass current is maintained in the capacitor 19 in each pixel (the transistor 11 a passes a black display current close to zero, i.e., it has been reset to the starting voltage at which a current starts to flow).
  • the operation time in FIG. 44 ( a ) should be fixed.
  • the operation time should be from 0.2 H to 5 Hs (five horizontal scanning periods) both inclusive. More preferably, it should be from 0.5 H to 4 Hs or from 2 ⁇ sec to 400 ⁇ sec (both inclusive).
  • the gate signal line 17 e should be shared with the gate signal line 17 a in a preceding stage. That is the gate signal line 17 e should be shorted to the gate signal line 17 a in the pixel row in the preceding stage.
  • This configuration is referred to as a preceding-stage gate control system.
  • the stage-stage gate control system uses waveforms of gate signal lines of a pixel row selected one or more Hs before the pixel row of interest.
  • this system is not limited to the previous pixel row.
  • the driver transistor 11 a of the pixel row of interest maybe reset using the waveforms of gate signal lines two pixel rows ahead.
  • the stage-stage gate control system will be described more concretely.
  • the pixel row of interest is the (N)-th pixel row whose gate signal lines are 17 e (N) and 17 a (N).
  • the preceding pixel row selected 1 H before is assumed to be the (N ⁇ 1)-th pixel row whose gate signal lines are 17 e (N ⁇ 1) and 17 a (N ⁇ 1).
  • the pixel row selected 1 H after the pixel row of interest is assumed to be the (N+1)-th pixel row whose gate signal lines are 17 e (N+1) and 17 a (N+1).
  • the pixel transistor 11 e (N) in the (N)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11 a (N) are shorted, and the driver transistor 11 a (N) is reset.
  • the pixel transistor 11 e (N+1) in the (N+1)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11 a (N+1) are shorted, and the driver transistor 11 a (N+1) is reset.
  • the pixel transistor 11 e (N+2) in the (N+2)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11 a (N+2) are shorted, and the driver transistor 11 a (N+2) is reset.
  • the driver transistor 11 a is reset for a period of 1 H, and then voltage (current) programming is performed.
  • FIG. 44 ( b ) shows a state in which the transistor 11 b is turned on and the transistors 11 e and 11 d are turned off.
  • This state in FIG. 44 ( b ) is a state in which voltage programming is being performed. Specifically, a programming voltage is output from the source driver circuit 14 and written into the gate (G) terminal of the driver transistor 11 a (the potential of the gate (G) terminal of the driver transistor 11 a is set in the capacitor 19 ). Incidentally, in the case of voltage programming, it is not always necessary to turn off the transistor 11 d during voltage programming.
  • the transistor 11 e is not necessary if there is no need to combine with the N-fold driving shown in FIG. 13, 15 , or the like or perform intermittent N/K-fold pulse driving (this driving method provides two or more illuminated areas in a screen and can be implemented easily by turning on and off the transistor 11 e ). Since this has been described earlier, description thereof will be omitted.
  • the voltage programming is started from offset voltage of completely black display even if there are variations in the characteristics of driver transistors in pixels (the offset voltage is a starting voltage at which a current specified according to the characteristics of each driver transistor starts to flow).
  • the time required to reach a target current value becomes uniform according to gradations. This eliminates gradation errors due to variations in the characteristics of the transistor 11 a, making it possible to achieve proper image display.
  • the transistor 11 d is turned off and the transistor 11 d is turned on to deliver the programming current to the EL element 15 from the driver transistor 11 a, and thereby illuminate the EL element 15 , as shown in FIG. 44 ( c ).
  • the reset driving according to the present invention using the voltage programming shown in FIG. 43 consists of a first operation of turning on the transistor 11 d, turning off the transistor 11 e, and passing current through the transistor 11 a in sync with the HD synchronization signal; a second operation of disconnecting the transistor 11 a from the EL element 15 and shorting between the drain (D) terminal and gate (G) terminal of the driver transistor 11 a (or between the source (S) terminal and gate (G) terminal, or generally speaking, between two terminals including the gate (G) terminal of the driver transistor); and a third operation of programming the driver transistor 11 a with voltage after the above operations.
  • the transistor 11 d is turned on and off to control the current delivered from the driver transistor element 11 a (in the case of configuration shown in FIG. 1 ) to the EL element 15 .
  • the gate signal line 17 b needs to be scanned, for which the shift register circuit 61 (the gate driver circuit 12 ) is required.
  • shift register circuits 61 are large in scale and the use of a shift register circuit 61 for the gate signal line 17 b makes it impossible to reduce bezel width. A system described with reference to FIG. 40 solves this problem.
  • the present invention is not limited to this and it goes without saying that the present invention can also be applied to other configuration for current programming (current-mirror pixel configuration) described with reference to FIG. 38 and the like. Also, the technical concept of turning on and off elements as a block can also be applied to the pixel configuration for voltage programming in FIG. 41 and the like.
  • this method since this method passes current through the EL elements 15 intermittently, it can be used in combination with a method (described with reference to FIG. 50 , etc.) which applies a reverse bias voltage.
  • reset driving can be performed in combination with other examples according to the present invention.
  • FIG. 40 shows an example of a block driving system.
  • a gate driver circuit 12 is formed directly on a board 71 or that a silicon chip, gate driver IC 12 , is mounted on a board 71 .
  • Source driver circuits 14 and source signal lines 18 are omitted to avoid complicating the drawing.
  • gate signal lines 17 a are connected to the gate driver circuit 12 .
  • gate signal lines 17 b are connected to illumination control lines 401 .
  • four gate signal lines 17 b are connected to one illumination control line 401 .
  • gate signal lines 17 b are grouped into a block here, this is not restrictive and it goes without saying that more than four gate signal lines 17 b may be grouped into a block.
  • a QCIF display panel which has 220 vertical scanning lines
  • odd-numbered rows and even-numbered rows are grouped into two different blocks, there is not much flickering even at a low frame rate, and thus the two blocks are sufficient.
  • the current flowing through the EL elements 15 are turned on and off on a block-by-block basis by the application of either a turn-on voltage (Vgl) or turn-off voltage (Vgh) to illumination control lines 401 a, 401 b, 401 c, 401 d, . . . , 401 n in sequence.
  • Vgl turn-on voltage
  • Vgh turn-off voltage
  • the gate signal lines 17 b do not intersect the illumination control lines 401 .
  • addition of capacitance is very small when the gate signal lines 17 b are viewed from the illumination control lines 401 . This makes it easy to drive the illumination control lines 401 .
  • the gate driver circuit 12 is connected with the gate signal lines 17 a.
  • a turn-on voltage is applied to gate signal lines 17 a
  • the appropriate pixel rows are selected and the transistors 11 b and 11 c in the selected pixel rows are turned on.
  • currents (voltage) applied to the source signal lines 18 are programmed into the capacitors 19 in the pixels.
  • the gate signal lines 17 b are connected with the gate (G) terminals of the transistors 11 d in the pixels.
  • Vgl turn-on voltage
  • Vgh turn-off voltage
  • control timing of turn-on/turn-off voltages applied to the illumination control lines 401 and a pixel row selection voltage (Vgl) outputted to the gate signal lines 17 a by the gate driver circuit 12 are synchronized with one horizontal scanning clock (1H).
  • this is not restrictive.
  • the signals applied to the illumination control lines 401 simply turn on and off the current delivered to the EL elements 15 . They do not need to be synchronized with image data outputted from the source driver circuits 14 . This is because the signals applied to the illumination control lines 401 are intended to control the current programmed into the capacitors 19 in the pixels 16 . Thus, they do not always need to be synchronized with the pixel row selection signal. Even when they are synchronized, the clock is not limited to a 1-H signal and may be a 1 ⁇ 2-H or 1 ⁇ 4-H signal.
  • the transistors 11 e can be turned on and off if the gate signal lines 17 b are connected to the illumination control lines 401 .
  • block driving can be implemented.
  • the block driving according to the present invention is a drive method which puts a plurality of pixel rows in non-illumination (black display) mode simultaneously using one control line.
  • one selection pixel row is placed (formed) per pixel row.
  • the present invention is not limited to this and a selection gate signal line may be placed (formed) for two or more pixel rows.
  • FIG. 41 shows such an example.
  • the gate signal line 17 a for pixel row selection selects three pixels ( 16 R, 16 G, and 16 B) simultaneously.
  • Reference character R is intended to indicate something related to a red pixel
  • reference character G indicates something related to a green pixel
  • reference character B indicates something related to a blue pixel.
  • the pixels 16 R, 16 G, and 16 B are selected and get ready to write data.
  • the pixel 16 R writes data into a capacitor 19 R via a source signal line 18 R
  • the pixel 16 G writes data into a capacitor 19 G via a source signal line 18 G
  • the pixel 16 B writes data into a capacitor 19 B via a source signal line 18 B.
  • the transistor 11 d of the pixel 16 R is connected to a gate signal line 17 b R
  • the transistor 11 d of the pixel 16 G is connected to a gate signal line 17 b G
  • the transistor 11 d of the pixel 16 B is connected to a gate signal line 17 b B.
  • an EL element 15 R of the pixel 16 R, EL element 15 G of the pixel 16 G, and EL element 15 B of the pixel 16 B can be turned on and off separately. Illumination times and illumination periods of the EL element 15 R, EL element 15 G, and EL element 15 B can be controlled separately by controlling the gate signal line 17 b R, gate signal line 17 b G, and gate signal line 17 b B.
  • shift register circuit 61 which scans the gate signal line 17 a
  • shift register circuit 61 which scans the gate signal line 17 b R
  • shift register circuit 61 which scans the gate signal line 17 b G
  • shift register circuit 61 which scans the gate signal line 17 b B.
  • this method sets an N times larger current value to pass a current proportional or corresponding to the N-fold value through the EL element 15 .
  • this drive method applies a current larger than a desired value to the EL element 15 in a pulsed manner.
  • This method performs current (voltage) programming so as to obtain desired emission brightness of the EL element by passing a current larger than a desired value intermittently through the driver transistor 11 a (in the case of FIG. 1 ) (i.e., a current which will give brightness higher than the desired brightness if passed through the EL element 15 continuously).
  • a compensation circuit which employs the penetration to the capacitor 19 is installed in the source driver circuit 14 . This will be described later.
  • N-channel transistors are used as the switching transistors 11 b and 11 c, etc. in FIG. 1 and the like. This will reduce penetration voltage reaching the capacitor 19 . Also, since off-leakage of the capacitor 19 is reduced, this method can be applied to a 10-Hz or lower frame rate.
  • P-channel transistors as the switching transistors 11 b and 11 c in FIG. 1 to cause penetration, and thereby obtain a proper black display.
  • the P-channel transistor 11 b turns off, the voltage goes high (Vgh), shifting the terminal voltage of the capacitor 19 slightly to the Vdd side. Consequently, the voltage at the gate (G) terminal of the transistor 11 a rises, resulting in more intense black display.
  • the current used for first gradation display can be increased (a certain base current can be delivered up until gradation 1 ), and thus shortages of write current can be eased during current programming.
  • FIG. 174 is an explanatory diagram illustrating a display panel which performs sequential driving according to the present invention.
  • a source driver circuit 14 outputs R, G, and B data to connection terminals 761 by switching among them.
  • the source driver circuit 14 only needs 1 ⁇ 3 as many output terminals as in FIG. 48 .
  • Signals outputted from the source driver circuit 14 to the connection terminals 761 are allocated to 18 R, 18 G, and 18 B by an output switching circuit 1741 .
  • the output switching circuit 1741 is formed directly on a board 71 by polysilicon technology. Alternatively, the output switching circuit 1741 may be formed with silicon chips and mounted on the board 71 by COG technology. Also, the output switching circuit 1741 may be incorporated into the source driver circuit 14 as a sub-circuit of the source driver circuit 14 .
  • a changeover switch 1742 is connected to an R terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18 R. If the changeover switch 1742 is connected to a G terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18 G. If the changeover switch 1742 is connected to a B terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18 B.
  • the changeover switch 1742 When the changeover switch 1742 is connected to the G terminal, the R terminal and B terminal of the changeover switch are open. Thus, the current entering the source signal lines 18 R and 18 B is 0 A. Consequently, the pixels 16 connected to the source signal lines 18 R and 18 B provide a black display.
  • R image data is written in sequence into the pixels 16 in the screen 50 in the first field.
  • G image data is written in sequence into the pixels 16 in the screen 50 .
  • B image data is written in sequence into the pixels 16 in the screen 50 .
  • R data ⁇ G data ⁇ B data ⁇ R data ⁇ . . . are rewritten in sequence in the appropriate fields to implement sequential driving.
  • Description of how N-fold pulse driving is performed by turning on and off the switching transistor 11 d as shown in FIG. 1 has been given with reference to FIGS. 5, 13 , 16 , etc. Needless to say, such a drive method can be combined with sequential driving. Of course, it goes without saying that other drive methods according to the present invention can be combined with sequential driving.
  • the G pixel and B pixel may retain the image data rewritten in the previous field. This can make the screen 50 brighter.
  • the R pixel and B pixel may retain the image data rewritten in the previous field.
  • the G pixel and R pixel may retain the image data rewritten in the previous field.
  • the gate signal line 17 a can be controlled separately for the R, G, and B pixels.
  • a gate signal line 17 a R can be designated as a signal line which turns on and off the transistors 11 b and 11 c of the R pixel
  • a gate signal line 17 a G can be designated as a signal line which turns on and off the transistors 11 b and 11 c of the G pixel
  • a gate signal line 17 a B can be designated as a signal line which turns on and off the transistors 11 b and 11 c of the B pixel.
  • the gate signal line 17 b can be designated as a signal line which commonly turns on and off the transistors 11 d of the R, G, and B pixels.
  • the source driver circuit 14 when the source driver circuit 14 outputs R image data and the changeover switch 1742 is set to an R contact, a turn-on voltage can be applied to the gate signal line 17 a R and a turn-off voltage can be applied to the gate signal lines aG and aB.
  • the R image data can be written into the R pixel 16 and the G pixel 16 and R pixel 16 can retain the image data of the previous field.
  • the changeover switch 1742 When the source driver circuit 14 outputs G image data in the second field and the changeover switch 1742 is set to aG contact, a turn-on voltage can be applied to the gate signal line 17 a G and a turn-off voltage can be applied to the gate signal lines aR and aB.
  • the G image data can be written into the G pixel 16 and the R pixel 16 and B pixel 16 can retain the image data of the previous field.
  • the changeover switch 1742 When the source driver circuit 14 outputs B image data in the third field and the changeover switch 1742 is set to aB contact, a turn-on voltage can be applied to the gate signal line 17 a B and a turn-off voltage can be applied to the gate signal line aR and aG.
  • the B image data can be written into the B pixel 16 and the R pixel 16 and G pixel 16 can retain the image data of the previous field.
  • the gate signal lines 17 a are placed (formed) in such a way as to turns on and off the transistors 11 b of the R, G, and B pixels 16 separately.
  • the present invention is not limited to this.
  • a gate signal line 17 a common to the R, G, and B pixels 16 may be formed of placed as illustrated in FIG. 175 .
  • the open state is an electrically floating state and is not desirable.
  • FIG. 175 shows a configuration in which measures are taken to eliminate such floating state.
  • a terminal a of a changeover switch 1742 of an output switching circuit 1741 is connected to a Vaa voltage (voltage for black display)
  • a terminal b is connected to an output terminal of the source driver circuit 14 .
  • the changeover switch 1742 is installed for each of the R, G, and B pixels.
  • a changeover switch 1742 R is connected to a Vaa terminal.
  • the Vaa voltage (voltage for black display) is applied to the source signal line 18 R.
  • a changeover switch 1742 G is connected to a Vaa terminal.
  • the Vaa voltage (voltage for black display) is applied to the source signal line 18 G.
  • a changeover switch 1742 B is connected to the output terminal of the source driver circuit 14 .
  • a B image signal is applied to the source signal line 18 B.
  • the R pixel 16 is rewritten in the first field
  • the G pixel 16 is rewritten in the second field
  • the B pixel 16 is rewritten in the third field. That is, the color of the pixel rewritten changes every field.
  • the present invention is not limited to this.
  • the color of the pixel rewritten may be changed every horizontal scanning period (1 H).
  • a possible drive method involves rewriting the R pixel in the first H, the G pixel in the second H, the B pixel in the third H, the R pixel in the fourth H, and so on.
  • the color of the pixel rewritten may be changed every two horizontal scanning periods or every 1 ⁇ 3 field.
  • FIG. 176 shows an example, in which the color of the pixel rewritten changes every 1 H.
  • the oblique hatching indicates that the pixels 16 either retain image data from the previous field instead of being rewritten or are displayed in black.
  • the black display of the pixels and retention of image data from the previous field may be repeated alternately.
  • FIGS. 174 to 178 show writing of pixels 16 .
  • illumination control of the EL elements 15 is not described, it goes without saying that this example can be used in combination with examples described earlier or later.
  • One frame need not necessarily consist of three fields and may consist of two fields or four or more fields.
  • one frame consists of two fields and the R and G pixels out of the three primary RGB colors are rewritten in the first field and the B pixel is rewritten in the second field.
  • one frame consists of four fields and the R pixel out of the three primary RGB colors is rewritten in the first field, the G pixel is rewritten in the second field, and the B pixel is rewritten in the third and fourth field.
  • white balance can be achieved more efficiently if the luminous efficiencies of the R, G, and B EL elements 15 are taken into consideration.
  • the R pixel 16 is rewritten in the first field
  • the G pixel 16 is rewritten in the second field
  • the B pixel 16 is rewritten in the third field. That is, the color of the pixel rewritten changes every field.
  • an R pixel is rewritten in the first H
  • a G pixel is rewritten in the second H
  • a B pixel is rewritten in the third H
  • an R pixel is rewritten in the fourth H
  • the color of the pixel rewritten may be changed every two or more horizontal scanning periods or every 1 ⁇ 3 field.
  • an R pixel is rewritten in the first H
  • a G pixel is rewritten in the second H
  • a B pixel is rewritten in the third H
  • an R pixel is rewritten in the fourth H.
  • a G pixel is rewritten in the first H
  • a B pixel is rewritten in the second H
  • an R pixel is rewritten in the third H
  • a G pixel is rewritten in the fourth H.
  • a B pixel is rewritten in the first H
  • an R pixel is rewritten in the second H
  • a G pixel is rewritten in the third H
  • a B pixel is rewritten in the fourth H.
  • a plurality of pixel 16 colors are rewritten every 1 H.
  • the pixel 16 rewritten in the first H is an R pixel
  • the pixel 16 rewritten in the second H is a G pixel
  • the pixel 16 rewritten in the third H is a B pixel
  • the pixel 16 rewritten in the fourth H is an R pixel.
  • positions of the different-colored pixels rewritten are changed every 1 H.
  • the R, G, and B pixels should have the same illumination time or luminous intensity in each picture element, which is a set of R, G, and B pixels. Needless to say, this is also done in the examples in FIGS. 175, 176 , and the like to avoid color irregularities.
  • the source driver circuit 14 can be configured to output image signals of arbitrary colors (or colors determined with some regularity) to the terminals and the changeover switches 1742 can be configured to connect to the R, G, and B contacts arbitrarily (or with some regularity).
  • the panel in an example in FIG. 178 has W (white) pixels 16 W in addition to the three primary colors RGB.
  • W white pixels 16 W
  • FIG. 178 ( a ) shows an example in which R, G, B, and W pixels 16 are formed in each pixel row.
  • FIG. 178 ( b ) shows an example in which R, G, B, and W pixels are placed in turns in different pixel rows.
  • the drive method in FIG. 178 can incorporate the drive methods in FIGS. 176, 177 , etc. Also, it goes without saying that N-fold pulse driving, simultaneous M-row driving, etc. can be incorporated. These matters can easily be implemented by those skilled in the art based on this specification, and thus description thereof will be omitted.
  • the display panel according to the present invention has the three primary colors RGB, but this is not restrictive.
  • the display panel may have cyan, yellow, and magenta in addition to R, G, and B, or it may have any one of R, G, and B or any two of R, G, and B.
  • FIGS. 174 to 178 illustrate how image data is written into pixels 16 . They do not illustrate (although, of course, they are related to) a method of displaying images by operating the transistors 11 d and passing current through the EL elements 15 unlike in FIG. 1 . In the configuration shown in FIG. 1 , current is passed through the EL elements 15 by controlling the transistors 11 d.
  • the drive methods in FIGS. 176, 177 , etc. can display RGB images in sequence by controlling the transistors 11 d (in the case of FIG. 1 ).
  • FIG. 179 ( a ) an R display area 53 R, G display area 53 G, and B display area 53 B are scanned from top to bottom (or from bottom to top) of the screen during one frame (one field) period. The remaining area becomes a non-display area 52 . That is, intermittent driving is performed.
  • FIG. 179 ( b ) shows an example in which a plurality of RGB display areas 53 are generated during one field (one frame) period.
  • This drive method is analogous to the one shown in FIG. 16 . Thus, it will require no explanation.
  • FIG. 179 ( b ) by dividing the display area 53 , it is possible to eliminate flickering even at a lower frame rate.
  • FIG. 180 ( a ) shows a case in which R, G, and B display areas 53 have different sizes (needless to say, the size of a display area 53 is proportional to its illumination period).
  • the R display area 53 R and G display area 53 G have the same size.
  • the B display area 53 B has a larger size than the G display area 53 G.
  • B With organic EL display panels, B often has a low luminous efficiency.
  • B display area 53 B By making the B display area 53 B larger than the display areas 53 of other colors as shown in FIG. 180 ( a ), it is possible to achieve a white balance efficiently.
  • FIG. 180 ( b ) shows an example in which there are a plurality of B display periods 53 B ( 53 B 1 and 53 B 2 ) during one field (one frame) period.
  • FIG. 180 ( a ) shows a method of varying the size of one B display area 53 B to allow the white balance to be adjusted properly
  • FIG. 180 ( b ) shows a method of displaying multiple B display areas 53 B having the same surface area to achieve a proper white balance.
  • the drive system according to the present invention is not limited to either FIG. 180 ( a ) or FIG. 180 ( b ). It is intended to generate R, G, and B display areas 53 and create an intermittent display, and thereby correct blurred moving pictures and insufficient writing into the pixels 16 . With the drive method in FIG. 16 , independent display areas 53 for R, G, and B are not generated. R, G, and B are displayed simultaneously (it should be stated that a W display area 53 is presented). Incidentally, it goes without saying that FIG. 180 ( a ) and FIG. 180 ( b ) may be combined. For example, it is possible to combine the drive method of using display areas 53 of different sizes for R, G, and B in FIG. 180 ( a ) with the drive method of generating multiple display areas 53 for R, G, or B in FIG. 180 ( b ).
  • the drive method in FIGS. 179 and 180 is not limited to the drive methods in FIGS. 174 to 178 according to the present invention. Needless to say, with a configuration in which the currents flowing through the EL elements 15 (EL elements 15 R, EL elements 15 G, and EL elements 15 B) are controlled separately for R, G, and B as shown in FIG. 41 , the drive method in FIGS. 179 and 180 can be implemented easily.
  • the gate signal line 17 b R By applying turn-on/turn-off voltages to the gate signal line 17 b R, it is possible to turn on and off the R pixel 16 R.
  • turn-on/turn-off voltages to the gate signal line 17 b G it is possible to turn on and off the G pixel 16 G.
  • turn-on/turn-off voltages to the gate signal line 17 b B it is possible to turn on and off the B pixel 16 B.
  • the above driving can be implemented by forming or placing a gate driver circuit 12 b R which controls the gate signal line 17 b R, a gate driver circuit 12 b G which controls the gate signal line 17 b G, and a gate driver circuit 12 b B which controls the gate signal line 17 b B, as illustrated in FIG. 181 .
  • a gate driver circuit 12 b R which controls the gate signal line 17 b R
  • a gate driver circuit 12 b G which controls the gate signal line 17 b G
  • a gate driver circuit 12 b B which controls the gate signal line 17 b B
  • the drive method in FIGS. 179 and 180 can be implemented using a gate signal line 17 b common to the R, G, and B pixels without using a gate signal line 17 b R which controls the EL elements 15 R, a gate signal line 17 b G which controls the EL elements 15 G, and a gate signal line 17 b B which controls the EL elements 15 B as long as black image data can be written into pixels 16 other than the pixels 16 whose image data is rewritten.
  • the gate signal line 17 b (EL-side selection signal line) applies a turn-on voltage (Vgl) and turn-off voltage (Vgh) every horizontal scanning period (1 H).
  • Vgl turn-on voltage
  • Vgh turn-off voltage
  • light emission quantity of the EL elements 15 is proportional to the duration of the current.
  • the duration is not limited to 1 H.
  • FIG. 194 shows 1 ⁇ 4-duty ratio driving.
  • a turn-on voltage is applied to the gate signal line 17 b (EL-side selection signal line) for 1 H every 4 Hs and the locations to which the turn-on voltage is applied are scanned in sync with a horizontal synchronization signal (HD).
  • HD horizontal synchronization signal
  • the unit length of a conduction period is 1 H.
  • the duration of the conduction period may be less than 1 H (1 ⁇ 2 H in FIG. 197 ) as shown in FIG. 197 or it may be equal to or less than 1 H.
  • the unit length of the conduction period is not limited to 1 H and a unit length other than 1 H can be generated easily.
  • the OEV 2 circuit formed or placed in the output stage of the gate driver circuit 12 b (circuit which controls the gate signal line 17 b ) can be used for that.
  • the pixel rows to be programmed with current are selected by the gate signal line 17 a (in the case of FIG. 1 ).
  • the output from the gate driver circuit 12 a which controls the gate signal line 17 a is referred to as a WR-side selection signal line.
  • EL elements 15 are selected by the gate signal line 17 b (in the case of FIG. 1 ).
  • the output from the gate driver circuit 12 b which controls the gate signal line 17 b is referred to as an EL-side selection signal line.
  • the gate driver circuits 12 are fed a start pulse, which is shifted as holding data in sequence within a shift register. Based on the holding data in the shift register of the gate driver circuit 12 a, it is determined whether to output a turn-on voltage (Vgl) or turn-off voltage (Vgh) to the WR-side selection signal line.
  • An OEV 1 circuit (not shown) which turns off output forcibly is formed or placed in an output stage of the gate driver circuit 12 a. When the OEV 1 circuit is low, a WR-side selection signal which is an output of the gate driver circuit 12 a is output as it is to the gate signal line 17 a.
  • FIG. 224 ( a ) OR circuit. Incidentally, the turn-on voltage is set at logic level L (0) and the turn-off voltage is set at logic voltage H (1).
  • the gate driver circuit 12 a when the gate driver circuit 12 a outputs a turn-off voltage, the turn-off voltage is applied to the gate signal line 17 a.
  • the gate driver circuit 12 a When the gate driver circuit 12 a outputs a turn-on voltage (logic low), it is ORed with the output of the OEV 1 circuit by the OR circuit and the result is output to the gate signal line 17 a. That is, when the OEV 1 circuit is high, the turn-off voltage (Vgh) is output to the gate driver signal line 17 a (see an exemplary timing chart in FIG. 224 ).
  • a turn-on voltage (Vgl) or turn-off voltage (Vgh) is determined whether to output a turn-on voltage (Vgl) or turn-off voltage (Vgh) to the gate signal line 17 b (EL-side selection signal line).
  • An OEV 2 circuit (not shown) which turns off output forcibly is formed or placed in an output stage of the gate driver circuit 12 b. When the OEV 2 circuit is low, an output of the gate driver circuit 12 b is output as it is to the gate signal line 17 b.
  • the gate driver circuit 12 b when the gate driver circuit 12 b outputs a turn-off voltage (an EL-side selection signal is a turn-off voltage), the turn-off voltage is applied to the gate signal line 17 b.
  • the gate driver circuit 12 b When the gate driver circuit 12 b outputs a turn-on voltage (logic low), it is ORed with the output of the OEV 2 circuit by the OR circuit and the result is output to the gate signal line 17 b. That is, when an input signal is high, the OEV 2 circuit outputs the turn-off voltage (Vgh) to the gate driver signal line 17 b.
  • the turn-off voltage (Vgh) is output forcibly to the gate signal line 17 b.
  • the EL-side selection signal if an input to the OEV 2 circuit is low, the EL-side selection signal is output directly to the gate signal line 17 b (see the exemplary timing chart in FIG. 176 ).
  • screen brightness is adjusted under the control of OEV 2 .
  • FIG. 223 illustrates relationship between permissible changes (%) and screen brightness (nt) As can be seen from FIG. 223 , relatively dark images have small permissible changes.
  • Permissible changes should be shorter when the screen is dark than when it is bright.
  • the conduction period of the gate signal line 17 b does not have a unit length of 1 H.
  • a turn-on voltage little shorter than 1 H is applied to the gate signal lines 17 b (EL-side selection signal lines) in odd-numbered pixel rows.
  • a turn-on voltage is applied to the gate signal lines 17 b (EL-side selection signal lines) in even-numbered pixel rows for a very short period.
  • the duration T 1 of the turn-on voltage applied to the gate signal lines 17 b (EL-side selection signal lines) in odd-numbered pixel rows plus the duration T 2 of the turn-on voltage applied to the gate signal lines 17 b (EL-side selection signal lines) in even-numbered pixel rows is designed to be 1 H.
  • FIG. 195 shows a state of the first field.
  • a turn-on voltage little shorter than 1 H is applied to the gate signal lines 17 b (EL-side selection signal lines) in even-numbered pixel rows.
  • a turn-on voltage is applied to the gate signal lines 17 b (EL-side selection signal lines) in odd-numbered pixel rows for a very short period.
  • the duration T 1 of the turn-on voltage applied to the gate signal lines 17 b (EL-side selection signal lines) in even-numbered pixel rows plus the duration T 2 of the turn-on voltage applied to the gate signal lines 17 b (EL-side selection signal lines) in odd-numbered pixel rows is designed to be 1 H.
  • the sum duration of turn-on voltage applications to gate signal lines 17 b in a plurality of pixel rows may be designed to be constant.
  • the illumination time of each EL element 15 in each pixel row in each field may be designed to be constant.
  • FIG. 196 shows a case in which the conduction period of the gate signal line 17 b (EL-side selection signal line) is 1.5 Hs.
  • the rise and fall of the gate signal line 17 b at point A are designed to overlap.
  • the gate signal line 17 b (EL-side selection signal line) and source signal line 18 are coupled.
  • any change in a waveform of the gate signal line 17 b (EL-side selection signal line) penetrates to the source signal line 18 . Consequently, any potential fluctuation in the source signal line 18 lowers accuracy of current (voltage) programming, causing irregularities in the characteristics of the driver transistors 11 a to appear in the display.
  • the voltage applied to the gate signal line 17 B (EL-side selection signal line) (1) changes from turn-on voltage (Vgl) to turn-off voltage (Vgh).
  • the voltage applied to the gate signal line 17 B (EL-side selection signal line) (2) changes from turn-off voltage (Vgh) to turn-on voltage (Vgl).
  • the signal waveform of the gate signal line 17 B (EL-side selection signal line) (1) and the signal waveform of the gate signal line 17 B (EL-side selection signal line) (2) cancel out each other.
  • the conduction period is 1.5 Hs.
  • the present invention is not limited to this. Needless to say, the duration of application of the turn-on voltage may be 1 H or less as illustrated in FIG. 198 .
  • display brightness in FIG. 199 ( b ) is lower than in FIG. 199 ( a ).
  • display brightness in FIG. 199 ( c ) is lower than in FIG. 199 ( b ).
  • FIG. 200 multiple sets of turn-on voltage and turn-off voltage may be applied in a period of 1 H.
  • FIG. 200 ( a ) shows an example in which six sets are applied.
  • FIG. 200 ( b ) shows an example in which three sets are applied.
  • FIG. 200 ( c ) shows an example in which one set is applied.
  • display brightness is lower in FIG. 200 ( b ) than in FIG. 200 ( a ). It is lower in FIG. 200 ( c ) than in FIG. 200 ( b ).
  • display brightness can be adjusted (controlled) easily.
  • One of the problems with the N-fold pulse driving according to the present invention is that a current N times larger than in the case of the conventional is applied to the EL element 15 although instantaneously. A large current may lower the life of the EL element. To solve this problem, it maybe useful to apply a reverse bias voltage Vm to the EL element.
  • Application of a reverse bias voltage means application of a reverse current, and thus injected electrons and positive holes are drawn to the negative and positive poles, respectively. This makes it possible to cancel formation of space charge in the organic layer and reduce electro-chemical degradation, thereby prolonging the life.
  • FIG. 45 shows reverse bias voltage Vm versus changes in terminal voltage of the EL element 15 .
  • the terminal voltage results when a rated current is applied to the EL element 15 .
  • the current density of the current passed through the EL element 15 is 100 A per square meter.
  • the trend in FIG. 45 shows little difference from the trend observed when the current density is 50 to 100 A per square meter. Thus, it is presumed that this method can be applied to a wide range of current density.
  • the vertical axis represents the ratio of the terminal voltage after 2500 hours to the initial terminal voltage of the EL element 15 .
  • the horizontal axis represents the ratio of the product of the reverse bias voltage Vm and its application duration t 1 in a period to a rated terminal voltage V 0 .
  • t 1 0.5.
  • the terminal voltage (rated terminal voltage) is 8 V when a current with a current density of 100 A per square meter is applied at time 0 (zero) and if the reverse bias voltage Vm is 8 V, then
  • reverse bias voltage ⁇ t 1 /(rated terminal voltage ⁇ t 2 )
  • /(8 (V) ⁇ 0.5) 1.0.
  • the terminal voltage ratio stops to change when
  • the reverse bias voltage Vm and the application duration rate t 1 should be determined in such a way as to make
  • the reverse bias voltage Vm and the application duration rate t 1 should be determined in such a way as to make
  • the reverse bias Vm and rated current should be applied alternately.
  • the reverse bias voltage Vm it is necessary to pass a larger current instantaneously than when no reverse bias voltage is applied. Consequently, the application of the reverse bias voltage Vm (sample A in FIG. 46 ) also increases the terminal voltage of the EL element 15 .
  • the rated terminal voltage V 0 should satisfy the average brightness (i.e., illuminate the EL element 15 ).
  • the average brightness i.e., illuminate the EL element 15 .
  • such a terminal voltage is obtained when a current with a current density of 200 A per square meter is applied.
  • the duty ratio is 1/2 the average brightness over one cycle is equal to the brightness at a current density of 200 A per square meter.
  • each EL element 15 is approximately 0.2 of a white peak current (a current which flows at a rated terminal voltage, or a current with a current density of 100 A per square meter according to examples cited herein).
  • the value of the horizontal axis should be multiplied by 0.2.
  • the reverse bias voltage Vm and the application duration rate t 1 (or t 2 or the ratio between t 1 and t 2 ) should be determined in such a way as to make
  • the reverse bias voltage Vm and the application duration rate t 1 should be determined in such a way as to make
  • /(rated terminal voltage ⁇ t 2 ) equal to 0.35 ( 1.75 ⁇ 0.2) or smaller.
  • the value of 1.0 should be changed to 0.2.
  • the reverse bias voltage Vm should be applied for a predetermined time t 1 in such a way as to make
  • an upper limit should be set to make
  • an N-channel transistor 11 g is used as shown in FIG. 47 .
  • this may be a P-channel transistor.
  • the gate potential control line 473 may be operated constantly at a fixed potential.
  • Vk is 0 (V)
  • the potential of the gate potential control line 473 is set to 0 (V) or higher (preferably, 2 V or higher).
  • this potential is denoted by Vsg.
  • the transistor 11 g (N) turns on and the reverse bias voltage Vm is applied to the anode electrode of the EL element 15 .
  • the reverse bias line 471 As the voltage of the reverse bias line 471 is set higher than the voltage applied to the gate potential control line 473 (i.e., the gate (G) terminal voltage of the transistor 11 g ), the transistor 11 g stays off and the reverse bias voltage Vm is not applied to the anode electrode of the EL element 15 .
  • the reverse bias line 471 may be put into a high-impedance state (such as an open state).
  • a gate driver circuit 12 c may be formed or placed separately to control the reverse bias line 471 as illustrated in FIG. 48 .
  • the gated river circuit 12 coperates by shifting in sequence as in the case of the gate driver circuit 12 a and the location of application of the reverse bias voltage is shifted in sync with the shift operation.
  • the drive method described above makes it possible to apply the reverse bias voltage Vm to the EL element 15 by varying only the potential of the reverse bias line 471 with the gate (G) terminal of the transistor 11 g set at a fixed potential. This makes it easy to control the application of the reverse bias voltage Vm.
  • the reverse bias voltage Vm is applied when current is not passed through the EL element 15 . This can be done by turning on the transistor 11 g when the transistor 11 d is off. That is, the reverse of on/off logic of the transistor 11 d can be applied to the gate potential control line 473 .
  • the gate (G) terminal of the transistors 11 d and 11 g can be connected to the gate signal line 17 b. Since the transistor 11 d is a P-channel transistor and the transistor 11 g is an N-channel transistor, they turn on and off in the opposite manner.
  • FIG. 49 is a timing chart of reverse bias driving.
  • the subscripts such as (1) and (2) indicate pixel row numbers. It is assumed for ease of explanation that (1) indicates the first pixel row while (2) indicates the second pixel row, but this is not restrictive. It is also possible to consider that (1) indicates the N-th pixel row while (2) indicates the (N+1)-th pixel row. The same applies to other examples except for some special cases.
  • examples in FIG. 49 and the like are described by citing the pixel configuration in FIG. 1 and the like, this is not restrictive. They are also applicable, for example, to the pixel configurations in FIGS. 41, 38 , etc.
  • Vgl When a turn-on voltage (Vgl) is applied to the gate signal line 17 a ( 1 ) in the first pixel row, a turn-off voltage (Vgh) is applied to the gate signal line 17 b ( 1 ) in the first pixel row.
  • Vgh When a turn-on voltage (Vgl) is applied to the gate signal line 17 a ( 1 ) in the first pixel row, a turn-off voltage (Vgh) is applied to the gate signal line 17 b ( 1 ) in the first pixel row.
  • Vgh turn-off voltage
  • a voltage Vsl (which turns on the transistor 11 g ) is applied to a reverse bias line 471 ( 1 ).
  • the transistor 11 d is on and a reverse bias voltage is applied to the EL element 15 .
  • the reverse bias voltage is applied a predetermined period (1/200 of 1 H or longer; or 0.5 ⁇ sec) after the turn-off voltage (Vgh) is applied to the gate signal line 17 b.
  • the reverse bias voltage is turned off a predetermined period (1/200 of 1 H or longer; or 0.5 ⁇ sec) before the turn-on voltage (Vgl) is applied to the gate signal line 17 b. This is done in order to prevent the transistors 11 d and 11 g from turning on simultaneously.
  • a turn-off voltage (Vgh) is applied to the gate signal line 17 a, and the second pixel row is selected. That is, a turn-on voltage is applied to a gate signal line 17 b ( 2 ).
  • a turn-on voltage (Vgl) is applied to the gate signal line 17 b, the transistor 11 d is turned on, and a current from the transistor 11 a flows through the EL element 15 , causing the EL element 15 to emit light.
  • a turn-off voltage (Vsh) is applied to the reverse bias line 471 ( 1 ) stopping the reverse bias voltage from being applied to the EL elements 15 in the first pixel row ( 1 ).
  • the voltage Vsl reverse bias voltage
  • a reverse bias voltage is applied while the pixels are being programmed.
  • the circuit configuration in FIG. 48 is not limited to this. It is obvious that a reverse bias voltage may be applied to a plurality of pixel rows continuously. It is also obvious that the reverse bias driving may be used in combination with block driving (see FIG. 40 ), N-fold pulse driving, reset driving, or dummy pixel driving.
  • Reverse bias voltage can be applied not only during image display.
  • the reverse bias voltage may be applied for a predetermined period after the EL display apparatus is turned off.
  • FIG. 50 shows a pixel configuration for current programming.
  • FIG. 50 shows a pixel configuration of a current mirror.
  • the transistor 11 d turns on 1 H (horizontal scanning period, i.e., one pixel row) or more before the given pixel is selected. Preferably, it turns on at least 3 Hs before. In that case, the transistor 11 d turns on 3 Hs before selection of the pixel, short-circuiting the gate (G) terminal and drain (D) terminal of the transistor 11 a. Consequently, the transistor 11 a is turned off. Thus, the current stops flowing through the transistor 11 b and the EL element 15 is turned off.
  • the transistor 11 g When the EL element 15 is not illuminated, the transistor 11 g turns on, applying a reverse bias voltage to the EL element 15 . Thus, the reverse bias voltage is applied while the transistor 11 d is on. Consequently, the transistor 11 d and transistor 11 g turn on simultaneously in logical terms.
  • the voltage Vsg is applied continuously to the gate (G) terminal of the transistor 11 g.
  • the transistor 11 g turns on when a reverse bias voltage sufficiently smaller than the voltage Vsg is applied to the reverse bias line 471 .
  • the transistor 11 d When the transistor 11 d is turned on, the pixel is put into black display mode.
  • the brightness during a display period needs to be increased to obtain a desired average brightness over one field (one frame) in spite of the black display period. That is, the current to be passed through the EL element 15 during the display period needs to be increased.
  • This operation is based on the N-fold pulse driving according to the present invention.
  • an operation characteristic of the present invention is implemented by a combination of the N-fold pulse driving and driving which involves creating a black display by turning on the transistor 11 d.
  • a configuration (method) characteristic of the present invention involves applying a reverse bias voltage to the EL element 15 when the EL element 15 is not illuminated.
  • the N-fold pulse driving allows a predetermined current (programmed current (at a voltage held in the capacitor 19 )) to be passed through the EL element 15 again during one field (one frame) period even after a black display is created once.
  • a predetermined current programmeed current (at a voltage held in the capacitor 19 )
  • the transistor 11 d turns on, since the capacitor 19 is discharged (or its charge is reduced), it is not possible to pass a predetermined current (programmed current) through the EL element 15 .
  • this configuration features ease of circuit operation.
  • the present invention is not limited to this and is applicable to other current-based pixel configurations such as those shown in FIGS. 38 and 50 . It is also applicable to a pixel configuration for voltage programming such as the one shown in FIGS. 51, 54 , and 62 .
  • FIG. 51 shows typically one of the simplest pixel configurations for voltage programming.
  • the transistor 11 b acts as a selection switching element while the transistor 11 a acts as a driver transistor which applies current to the EL element 15 .
  • This configuration contains a transistor (switching element) 11 g which applies a reverse bias voltage to the anode of the EL element 15 .
  • the current to be passed through the EL element 15 is applied to the source signal line 18 . Then, it is applied to the gate (G) terminal of the transistor 11 a as the transistor 11 b is selected.
  • the pixel configuration in FIG. 51 is of a voltage offset canceling type and operates in four stages: initialization operation, reset operation, programming operation, and light-emitting operation.
  • the initialization operation is performed after a horizontal synchronization signal (HD) is provided.
  • a turn-on voltage is applied to the gate signal line 17 b, turning on the transistor 11 g.
  • a turn-on voltage is also applied to the gate signal line 17 a, turning on the transistor 11 c.
  • a voltage Vdd is applied to the source signal line 18 .
  • the driver transistor 11 a turns on and a small current flows through the EL element 15 . This current makes the voltage on the drain (D) terminal of the driver transistor 11 a larger in absolute value than at least the voltage at an operating point of the driver transistor 11 a.
  • a turn-off voltage is applied to the gate signal line 17 b, turning off the transistor 11 e.
  • a turn-on voltage is applied to the gate signal line 17 c for a period of T 1 , turning on the transistor 11 b.
  • the period T 1 corresponds to a reset period.
  • a turn-on voltage is applied to the gate signal line 17 a continuously for a period of 1 H.
  • the period T 1 is between 20% and 90% (both inclusive) of 1 H or between 20 ⁇ sec and 160 ⁇ sec (both inclusive).
  • a capacitance ratio Ca/Cb between a capacitor 19 b (Cb) and capacitor 19 a (Ca) is between 1/6 and 2/1 (both inclusive)
  • the transistor 11 b turns on, short-circuiting the gate (G) terminal and drain (D) terminal of the driver transistor 11 a.
  • the voltages at the gate (G) terminal and drain (D) terminal of the transistor 11 a become equal, putting the transistor 11 a in an offset mode (reset mode: a state in which no current flows).
  • the voltage at the gate (G) terminal of the transistor 11 a approaches a starting voltage at which a current starts to flow.
  • a gate voltage which maintains the reset mode is held at a terminal b of the capacitor 19 b.
  • the capacitor 19 holds an offset voltage (reset voltage).
  • a turn-off voltage is applied to the gate signal line 17 c, turning off the transistor 11 b.
  • DATA voltage is applied to the source signal line 18 for a period of Td.
  • the sum of the DATA voltage and offset voltage (reset voltage) is applied to the gate (G) terminal of the driver transistor 11 a. This allows the driver transistor 11 a to pass a programmed current.
  • a turn-off voltage is applied to the gate signal line 17 a, turning off the transistor 11 c and cutting off the driver transistor 11 a from the source signal line 18 .
  • a turn-off voltage is also applied to the gate signal line 17 c, turning off the transistor 11 b, which remains off for a period of 1F.
  • a turn-on voltage and turn-off voltage are applied to the gate signal line 17 b periodically, as required.
  • the capacitor 19 holds a starting current voltage (offset voltage, reset voltage) of the transistor 11 a.
  • the darkest black display is created when the reset voltage is being applied to the gate (G) terminal of the driver transistor 11 a.
  • coupling between the source signal line 18 and pixel 16 , penetration voltage to the capacitor 19 , or punch-through of a transistor causes excessive brightness (reduced contrast) resulting in a whitish screen. Therefore, the drive method described with reference to FIG. 53 cannot achieve high display contrast.
  • Vdd voltage or a voltage which turns off the transistor 11 a to the source signal line 18 , turn on the transistor 11 b, and apply the voltage to the gate (G) terminal of the transistor 11 a.
  • This voltage turns off the transistor 11 a (or makes it pass almost no current (almost off: the transistor 11 a is in a high-impedance state)).
  • the transistor 11 g is turned on and a reverse bias voltage is applied to the EL element 15 .
  • FIG. 53 shows an example.
  • the gate signal line 17 a connected to the gate (G) terminal of the transistor 11 c in a pixel 16 a is also connected to the gate (G) terminal of the reset transistor 11 b in a pixel 16 b in the next stage.
  • the gate signal line 17 a connected to the gate (G) terminal of the transistor 11 c in the pixel 16 b is also connected to the gate (G) terminal of the reset transistor 11 b in a pixel 16 c in the next stage.
  • a turn-on voltage is applied to the gate signal line 17 a of the pixel 16 a and a turn-off voltage is applied to the gate signal lines 17 a of other pixels 16 .
  • a turn-off voltage is applied to the gate signal lines 17 b of the pixels 16 a and 16 b while a turn-on voltage is applied to the gate signal lines 17 b of the pixels 16 c and 16 d.
  • the pixel 16 a is in voltage programming mode and is not illuminated
  • the pixel 16 b is in reset mode and not illuminated
  • the pixel 16 c is pending current programming and is illuminated
  • the pixel 16 d is pending current programming and is illuminated.
  • FIG. 53 ( b ) After 1 H, data in a shift register 61 circuit of the controlling gate driver circuit 12 is shifted one bit to enter a state shown in FIG. 53 ( b ).
  • the pixel 16 a is pending current programming and is illuminated
  • the pixel 16 b is current programming mode and is not illuminated
  • the pixel 16 c is in reset mode and is not illuminated
  • the pixel 16 d is pending programming and is illuminated.
  • the pixel configuration for voltage programming in FIG. 43 can also implement preceding-stage gate control.
  • FIG. 54 shows an example in which a connection method of a preceding-stage gate control system is used for the pixel configuration in FIG. 43 .
  • the gate signal line 17 a connected to the gate (G) terminal of the transistor 11 b in the pixel 16 a is connected to the gate (G) terminal of the reset transistor 11 e in the pixel 16 b in the next stage.
  • the gate signal line 17 a connected to the gate (G) terminal of the transistor 11 b in the pixel 16 b is connected to the gate (G) terminal of the reset transistor 11 e in the pixel 16 c in the next stage.
  • the pixel 16 a is in voltage programming mode
  • the pixel 16 b is in reset mode
  • the pixel 16 c is pending current programming
  • the pixel 16 d is pending current programming.
  • FIG. 55 ( b ) After 1 H, data in the shift register 61 circuit of the controlling gate driver circuit 12 is shifted one bit to enter a state shown in FIG. 55 ( b ).
  • the pixel 16 a is pending current programming
  • the pixel 16 b is in current programming mode
  • the pixel 16 c is in reset mode
  • the pixel 16 d is pending programming.
  • the driver transistors 11 of the pixels are programmed with 0 current. That is, the source driver circuit 14 delivers no current. When no current is delivered, parasitic capacitance caused in the source signal line 18 cannot be discharged and the potential of the source signal line 18 cannot be varied. Consequently, the gate potential of the driver transistors also remains unchanged and the potential in the previous frame (field) (1 F) remains accumulated in the capacitor 19 . For example, if the previous frame contains white display, the white display is retained even if the current frame contains completely black display.
  • a black level voltage is written into the source signal line 18 at the beginning of one horizontal scanning period (1 H) before the current to be programmed is output to the source signal line 18 .
  • image data consists of the 0th to 7th gradations close to black level
  • a black level voltage is written only during a certain period at the beginning of one horizontal scanning period to reduce the load of current programming and make up for insufficient writing.
  • completely black display corresponds to the 0th gradation and white display corresponds to the 63rd gradation (in the case of 64-gradation display). Precharging will be described in detail later.
  • the current-driven source driver IC (circuit) 14 according to the present invention will be described below.
  • the source driver IC according to the present invention is used to implement the drive methods and drive circuits according to the present invention described earlier. It is used in combination with drive methods, drive circuits, and display apparatus according to the present invention.
  • the source driver circuit will be described as an IC chip, this is not restrictive and the source driver circuit may be built on the display panel using low-temperature polysilicon technology, or the like.
  • FIG. 72 an example of a conventional current-driven source driver circuit is shown in FIG. 72 , which provides a principle needed to describe current-driven source driver IC (source driver circuit)-according to the present invention.
  • reference numeral 721 denotes a D/A converter.
  • the D/A converter 721 is fed an n-bit data signal and outputs an analog signal based on the inputted data.
  • the analog signal enters an operational amplifier 722 , which feeds into an N-channel transistor 631 a. Current flowing through the N-channel transistor 631 a flows to a resister 691 .
  • a terminal voltage of the register R provides a negative input to the operational amplifier 722 .
  • the voltage at the negative terminal equals the voltage at the positive terminal of the operational amplifier 722 .
  • the output voltage of the D/A converter 721 equals the terminal voltage of the resister 691 .
  • the D/A converter circuit 721 has a large circuit scale. So does the operational amplifier 722 . Formation of the D/A converter circuit 721 and operational amplifier 722 in a single output circuit results in a huge source driver IC 14 , which is practically impossible to build.
  • the present invention has been made in view of the above point.
  • the source driver circuit 14 according to the present invention has a circuit configuration and layout configuration which reduces the scale of a current output circuit and minimizes variations in output current among current output terminals.
  • FIG. 63 is a block diagram showing a current-driven source driver IC (circuit) 14 according to the present invention.
  • FIG. 63 shows a multi-stage current mirror circuit comprising three-stage current sources ( 631 , 632 , 633 ).
  • the current value of the current source 631 in the first stage is copied by the current mirror circuit to N current sources 632 in the second stage (where N is an arbitrary integer).
  • the current values of the second-stage current sources 632 are copied by the current mirror circuit to M current sources 633 in the third stage (where M is an arbitrary integer). Consequently, this configuration causes the current value of the first-stage current source 631 to be copied to N ⁇ M third-stage current sources 633 .
  • the current-driven source driver IC (circuit) 14 employing the multi-stage current mirror circuit according to the present invention can absorb variations in transistor characteristics because it has the second-stage current sources 632 in between instead of copying the current value of the first-stage current source 631 directly to N ⁇ M third-stage current sources 633 using the current mirror circuit.
  • the present invention is characterized in that a first-stage current mirror circuit (current source 631 ) and second-stage current mirror circuits (current sources 632 ) are placed close to each other. If a first-stage current source 631 are connected with third-stage current sources 633 (i.e., in the case of two-stage current mirror circuit), the second-stage current sources 633 connected to the first-stage current source are large in number, making it impossible to place the first-stage current source 631 and third-stage current sources 633 close to each other.
  • the source driver circuit 14 copies the current value of the first-stage current mirror circuit (current source 631 ) to the second-stage current mirror circuits (current sources 632 ), and the current values of the second-stage current mirror circuits (current sources 632 ) to the third-stage current mirror circuits (current sources 632 ).
  • the second-stage current mirror circuits (current sources 632 ) connected to the first-stage current mirror circuit (current source 631 ) are small in number.
  • the first-stage current mirror circuit (current source 631 ) and second-stage current mirror circuits (current sources 632 ) can be placed close to each other.
  • transistors composing the current mirror circuits can be placed close to each other, naturally variations in the transistors are reduced, and so are variations in current values.
  • the number of the third-stage current mirror circuits (current sources 633 ) connected to the second-stage current mirror circuits (current sources 632 ) are reduced as well. Consequently, the second-stage current mirror circuits (current sources 632 ) and third-stage current mirror circuits (current sources 633 ) can be placed close to each other.
  • transistors in current receiving parts of the first-stage current mirror circuit can be placed close to each other on the whole.
  • transistors composing the current mirror circuits can be placed close to each other, reducing variations in the transistors and greatly reducing variations in current signals from output terminals.
  • a multi-stage current mirror circuit consisting of three stages has been cited in the above example for the sake of simplicity. Needless to say, the larger the number of stages, the smaller the current variations in the source driver IC 14 of the current-driven display panel. Thus, the number of stages of a current mirror circuit is not limited to three and may be more than three.
  • current sources 631 , 632 , and 633 are used interchangeably. That is, current sources are a basic construct of the present invention and the current sources are embodied into current mirror circuits.
  • a current source is not limited to a current mirror circuit and may be a current circuit consisting of a combination of a operational amplifier 722 , transistor 631 , and register R as shown in FIG. 72 .
  • FIG. 64 is a structural drawing of a more concrete source driver IC (circuit) 14 . It illustrates part of third current sources 633 . This is an output part connected to one source signal line 18 . It is composed of multiple current mirror circuits (current sources 634 (1 unit)) of the same size as a current mirror configuration in the final stage. Their number is bit-weighted according to the data size of image data.
  • the transistors composing the source driver IC (circuit) 14 are not limited to a MOS type and may be a bipolar type. Also, they are not limited to silicon semiconductors and may be gallium arsenide semiconductors. Also, they may be germanium semiconductors. Alternatively, they may be formed directly on a substrate using low-temperature polysilicon technology, other polysilicon technology, or amorphous silicon technology.
  • FIG. 48 illustrates an example of the present invention which handles 6-bit digital input.
  • Six bits are the sixth power of two, and thus provide a 64-gradation display.
  • Sixty-four (64) gradations require one D0-bit unit transistor 634 , two D1-bit unit transistors 634 , four D2-bit unit transistors 634 , eight D3-bit unit transistors 634 , sixteen D4-bit unit transistors 634 , and thirty-two D5-bit unit transistors 634 for a total of sixty-three unit transistors 634 .
  • the present invention produces one output using as many unit transistors 634 as the number of gradations (64 gradations in this example) minus 1.
  • D 0 represents LSB input and D 5 represents MSB input.
  • a switch 641 a is closed (the switch 481 a is an on/off means and may be constructed of a single transistor or may be an analog switch consisting of a P-channel transistor and N-channel transistor.
  • current flows to a current source (single-unit) 634 composing a current mirror.
  • the current flows through internal wiring 643 in the IC 14 . Since the internal wiring 643 is connected to the source signal line 18 via a terminal electrode of the IC 14 , the current flowing through internal wiring 643 provides a programming current for the pixels 16 .
  • a switch 641 b is closed. Then, current flows to two current sources (single-unit) 634 composing a current mirror. The current flows through the internal wiring 643 in the IC 14 . Since the internal wiring 643 is connected to the source signal line 18 via a terminal electrode of the IC 14 , the current flowing through internal wiring 643 provides a programming current for the pixels 16 .
  • switches 641 When a D 2 input terminal is high (positive logic), a switch 641 c is closed. Then, current flows to four current sources (single-unit) 634 composing a current mirror. When a D 5 input terminal is high (positive logic), a switch 641 f is closed. Then, current flows to 32 (thirty-two) current sources (single-unit) 634 composing a current mirror.
  • each current source 634 need to pass equal current.
  • individual current sources 634 may be weighted.
  • a current output circuit may be constructed using a mixture of single-unit current sources 634 , double-sized current sources 634 , quadruple-sized current sources 634 , etc.
  • the weighted current sources may not provide the right proportions, resulting in variations.
  • the unit transistor 634 should be equal to or larger than a certain size. The smaller the transistor size, the larger the variations in output current.
  • FIG. 117 Relationship between size of transistors and variations in output current is shown in FIG. 117 .
  • the horizontal axis of the graph in FIG. 117 represents transistor size (square ⁇ m).
  • the vertical axis represents variations in output current in percentage terms.
  • the variations (%) in output current here were determined using groups of 63 unit current sources (unit transistors) 634 formed on a wafer.
  • the horizontal axis of the graph represents the size of a transistor constituting one current source, since there are actually 63 transistors connected in parallel, the total area of the transistors is 63 times larger.
  • the present invention is based on the size of a unit transistor 634 .
  • FIG. 117 shows that variations in the output current of 63 unit transistors 634 with an area of 30 square ⁇ m each is 0.5%.
  • the sizes of the unit transistor must be equal to or larger than 2 square ⁇ m (in the case of 64 gradations, sixty-three 2-square ⁇ m unit transistors operate).
  • the upper limit to the size of the unit transistor 634 is 300 square ⁇ m.
  • the size of the unit transistor 634 must be from 2 square ⁇ m to 300 square ⁇ m (both inclusive).
  • the variations in the output current must be within 1%. From FIG. 117 , it can been seen that in order for the variations to be within 1%, the size of the unit transistor must be equal to or larger than 8 square ⁇ m. Thus, in the case of 128 gradations, the size of the unit transistor 634 must be from 8 square ⁇ m to 300 square ⁇ m (both inclusive).
  • 64 gradations are represented by 63 transistors.
  • the unit-transistor 634 size is the total size of two unit transistors 634 .
  • a kink is a phenomenon in which current flowing through a unit transistor 634 changes when the voltage between the source (S) and drain (D) of the unit transistor 634 is varied with the gate voltage of the unit transistor 634 kept constant. In the absence of kink effect (in ideal state), the current flowing through the unit transistor 634 does not change even if the voltage applied between the source (S) and drain (D) of the unit transistor 484 is varied.
  • Kink effect occurs when the source signal lines 18 vary due to variations in Vt of driver transistors 11 a shown in FIG. 1 and the like.
  • the driver circuit 14 passes programming current through the source signal line 18 so that the programming current will flow through the driver transistor 11 a of the pixel.
  • the programming current causes changes in the gate terminal voltage of the driver transistor 11 a, and consequently the programming current flows through the driver transistor 11 a.
  • the gate terminal voltage of the driver transistor 11 a equals the potential of the source signal line 18 .
  • the potentials of the source signal lines 18 vary due to variations in Vt of the driver transistors 11 a in pixels 16 .
  • the potential of a source signal line 18 equals the source-drain voltage of the unit transistor 634 of the driver circuit 14 . That is, variations in Vt of the driver transistors 11 a in the pixels 16 cause the source-drain voltage applied to the unit transistors 634 to vary. Then, the source-drain voltage causes variations in the output voltage of the unit transistor 634 due to kinks.
  • FIG. 118 is a graph which represents this phenomenon.
  • the vertical axis represents the output current of the unit transistor 634 obtained when a predetermined voltage is applied to the gate terminal.
  • the horizontal axis represents the voltage between source (S) and drain (D).
  • L in L/W represents the channel length and W represents the channel width of the unit transistor 634 .
  • L, W represents the size of the unit transistor 634 which outputs current for one gradation.
  • Wand L should be calculated by substituting the sub-unit transistors with an equivalent unit transistor 634 . Basically, the calculation should be performed by taking into consideration the transistor size and output current.
  • FIG. 172 is a graph showing deviation (variation) in L/W of unit transistors from a target value.
  • L/W of a unit transistor is two or more.
  • a large L/W means a long L, and thus a large transistor size.
  • L/W is 40 or less.
  • L/W also depends on the number of gradations. If the number of gradations is small, there is no problem even if there are variations in the output current of the unit transistor 634 due to kink effect because there are large differences between gradations. However, in the case of a display panel with a large number of gradations, since there are small differences between gradations, even small variations in the output current of the unit transistor 634 due to kink effect will decrease the number of gradations.
  • the driver circuit 14 is configured to satisfy the following relationship: ( ⁇ square root ⁇ square root over ( ) ⁇ ( K/ 16)) ⁇ L/W ⁇ and ( ⁇ square root ⁇ square root over ( ) ⁇ ( K/ 16)) ⁇ 20 where K is the number of gradations, L is the channel length of the unit transistor 634 , and W is the channel width of the unit transistor.
  • K is the number of gradations
  • L is the channel length of the unit transistor 634
  • W is the channel width of the unit transistor.
  • a first current source 631 and second current sources 632 are formed separately and are placed densely (close to each other).
  • the transistors 633 a in the current mirror circuits composing the second current sources 632 and third current sources are also placed densely (close to each other).
  • the variations in the output current of the unit transistor 634 also depend on the voltage resistance of the source driver IC 14 .
  • the voltage resistance of the source driver IC generally means the power supply voltage of the IC.
  • voltage resistance of 5 V means the use of the power supply voltage at a standard voltage of 5 V.
  • IC voltage resistance can translate into maximum working voltage.
  • Semiconductor IC makers have standardized voltage-resistance processes such as a 5-V voltage-resistance process and 10-V voltage-resistance process.
  • film properties and film thickness of a gate insulating film of the unit transistor 634 have something to do with the fact that IC voltage resistance affects variations in the output current of the unit transistor 634 .
  • the transistors 634 produced in a process with high IC voltage resistance have a thick gate insulating film. This is intended to avoid dielectric breakdown even under application of a high voltage.
  • a thick gate insulating film makes its control difficult and increases variations in its film properties. This increases variations in the transistors.
  • the transistors produced in a high voltage-resistance process have low mobility. With low mobility, even slight changes in electrons injected into transistor gates cause changes in characteristics. This increases variations in the transistors.
  • FIG. 170 illustrates relationship between IC voltage resistance and output variations of unit transistors.
  • the variation rate on the vertical axis is based on the variation of unit transistors 634 produced in a 1.8-V voltage resistance process, which variation is taken to be 1 .
  • a plurality of unit transistors 634 were produced in each IC voltage resistance process and variations in their output current were determined.
  • the voltage resistance processes were composed discretely of 1.8-V voltage resistance, 2.5-V voltage resistance, 3.3-V voltage resistance, 5-V voltage resistance, 8-V voltage resistance, and 10-V voltage resistance, 15-V voltage resistance processes.
  • variations in the transistors formed in the different voltage resistance processes are plotted on the graph and connected with straight lines.
  • the variation rate (variations in the output current of the unit transistors 634 ) increases gradually up until an IC voltage resistance of 9 V.
  • the slope of the variation rate with respect to the IC voltage resistance becomes large.
  • the permissible limit to the variation rate is 3 for 64- to 256-gradation display.
  • the variation rate varies with the area, L/W, etc. of the unit transistor 634 .
  • the variation rate with respect to the IC voltage resistance is hardly affected by the shape of the unit transistor 634 .
  • the variation rate tends to increase above an IC voltage resistance of 9 to 10 V.
  • the potential at an output terminal 64 in FIG. 64 varies with the programming current in the driver transistor 11 a of the pixel 16 .
  • the driver transistor 11 a of the pixel 16 passes white raster (maximum white display) current, its gate terminal voltage is designated as Vw.
  • Vw white raster
  • Vb black raster (completely black display) current
  • Vw-Vb The absolute value of Vw-Vb must be 2 V or larger.
  • a voltage resistance process in the range of 2.5-V to 10-V (both inclusive) for the source driver IC 14 . More preferably, a voltage resistance process in the range of 3-V to 9-V (both inclusive) is used for the source driver IC 14 .
  • a voltage resistance process in the range of 2.5-V to 10-V (both inclusive) is used for the source driver IC 12 .
  • This voltage resistance is also applied to examples (e.g., a low-temperature polysilicon process) in which the source driver circuit 14 is formed directly on an array board 71 .
  • Working voltage resistance of a source driver circuit 14 formed directly on an array board 71 can be high and exceeds 15 V in some cases. In such cases, the power supply voltage used for the source driver circuit 14 may be substituted with the IC voltage resistance illustrated in FIG. 170 . Also, the source driver IC 14 may have the IC voltage resistance substituted with the power supply voltage used.
  • FIG. 171 is a graph obtained by varying the transistor width W of a unit transistor 634 with the area of the unit transistor 634 kept constant.
  • the variation of the unit transistor 634 with a channel width W of 2 ⁇ m is taken as 1.
  • the variation rate increases gradually when W of the unit transistor is from 2 ⁇ m to 9 or 10 ⁇ m.
  • the increase in the variation rate tends to become large when W is 10 ⁇ m or more.
  • the permissible limit to the variation rate is 3 for 64- to 256-gradation display.
  • the variation rate varies with the area of the unit transistor 634 .
  • the variation rate with respect to the IC voltage resistance is hardly affected by the area of the unit transistor 634 .
  • the channel width W of the unit transistor 634 is from 2 ⁇ m to 10 ⁇ m (both inclusive). More preferably, the channel width W of the unit transistor 634 is from 2 ⁇ m to 9 ⁇ m (both inclusive).
  • D 0 which is provided by one unit transistor 634 , provides the value of the current flowing through the unit transistor 633 of the final-stage current source.
  • D 1 which is provided by two unit transistors 634 , provides a two times larger current value than the final-stage current source.
  • D 2 which is provided by four unit transistors 634 , provides a four times larger current value than the final-stage current source;
  • D 5 which is provided by 32 unit transistors 484 , provides a 32 times larger current value than the final-stage current source.
  • programming current Iw is output (drawn) to the source signal line via switches controlled by 6-bit image data consisting of D 0 , D 1 , D 2 , . . . , and D 5 .
  • 6-bit image data consisting of D 0 , D 1 , D 2 , . . . , and D 5 .
  • currents 1 time, 2 times, 4 times, . . . and/or 32 times as large as the final-stage current source 633 are added and outputted to the output line. That is, according to activation and deactivation of the 6-bit image data consisting of D 0 , D 1 , D 2 , . . . , and D 5 , 0 to 63 times as large a current as the final-stage current source 633 is output from the output line (the current is drawn from the source signal line 18 ).
  • reference currents (IaR, IaG, and IaB) for R, G, and B, respectively, can be adjusted by variable resistors 651 ( 651 R, 651 G, and 651 B).
  • the white balance can be adjusted easily.
  • this configuration is available only when the driver transistors 11 a of pixels 16 are P-channel transistors and the current sources (single-unit transistors) 634 of the source driver IC 14 are N-channel transistors.
  • the present invention can use a configuration in which the programming current Iw is a discharge current.
  • FIG. 144 shows an example.
  • a variable resistor 651 is used to generate reference current.
  • the variable resistor 651 in FIG. 68 is replaced by the transistor 631 a and current flowing through a transistor 1444 which forms a current mirror circuit in conjunction with the transistor 631 a is controlled by an operational amplifier 722 or the like.
  • the transistor 1444 and transistor 631 a forms the current mirror circuit. If the current mirror factor is 1 , the current flowing through the transistor 1444 provides a reference current.
  • Output voltage of the operational amplifier 722 is fed to an N-channel transistor 1443 and the current flowing through the N-channel transistor 1443 flows through an external resistor 691 .
  • a resistor 691 a is a fixed-chip resister. Basically, the resistor 691 a is enough.
  • a resistor 691 b is a resistive element such as a posistor or thermistor whose value changes with temperature.
  • the resistor 691 a is used to compensate for temperature characteristics of the EL element 15 .
  • the resistor 691 a is inserted or placed in parallel or series with the resistor 691 b according to (to compensate for) the temperature characteristics of the EL element 15 .
  • the resistor 691 a and resistor 691 b will be treated below as one resistor 691 .
  • a resistor 691 with an accuracy of 1% or better is easily available.
  • the resistor 691 may be built into the source driver IC 14 using diffused resistor technology or a polysilicon pattern.
  • the chip resistor 691 is mounted on an input terminal 761 a.
  • the temperature characteristics of EL elements 15 differ among R, G, and B.
  • three external resistors 691 are required for R, G, and B.
  • Terminal voltage of the resistor 691 provides a negative input to the operational amplifier 722 and the voltage at the negative terminal has the same magnitude as the voltage at a positive terminal of the operational amplifier 722 .
  • V 1 the current obtained by dividing with this voltage by the resistance 691 flows through the transistor 1444 .
  • This current serves as the reference current.
  • the reference current is set between 2 ⁇ A and 30 ⁇ A (both inclusive).
  • a small reference current flowing through the parent transistor 63 lowers the accuracy of the unit current source 634 . Too large a reference current increases the current mirror factor converted (in the downward direction in this case) within the IC, increasing variations in the current mirror circuit, and thus lowering the accuracy of the unit current source 634 again.
  • a reference voltage Vref received from a reference voltage circuit 1441 is applied to the positive terminal of the operational amplifier 722 .
  • the reference voltage Vref may be generated within the source driver circuit 14 (internally generated reference voltage Vref).
  • the reference voltage Vref ranges between 2 (V) and the anode voltage Vdd (V) (both inclusive).
  • the reference voltage is fed through a connection terminal 761 a.
  • the voltage Vref can be fed into the positive terminal of the operational amplifier 722 .
  • An electronic regulator circuit 561 is placed between the connection terminal 761 a and positive terminal because the luminous efficiency of the EL elements 15 varies among R, G, and B.
  • the electronic regulator circuit 561 is intended to adjust the current passed through each of the EL elements 15 for R, G, and B, and thereby achieve a white balance.
  • a variable resistor may be used as the resistor 691 .
  • One of the uses of the electronic regulator circuit 561 is to readjust white balance when the degradation rate of the EL elements 15 varies among R, G, and B.
  • the EL elements 15 for B are especially prone to degradation.
  • the EL elements 15 for B become darker with years of use of a EL display panel, turning the screen yellowish.
  • the white balance is adjusted using the electronic regulator circuit 561 for B.
  • brightness correction or white balance correction of the EL elements may be performed by linking the electronic regulator circuit 561 to a temperature sensor 781 (see FIG. 78 and its description).
  • the electronic regulator circuit 561 is built into the IC (circuit) 14 . Alternatively, it is formed directly on an array board 71 using the low-temperature poly-silicon technology.
  • a plurality of unit resistors (R 1 , R 2 , R 3 , R 4 , . . . Rn) formed through polysilicon patterning are connected in series.
  • Analog switches (S 1 , S 2 , S 2 , . . . Sn+1) are placed among the unit resistors, the reference voltage Vref is divided, and the resulting voltages are output.
  • the transistor 1443 is illustrated as a bipolar transistor, but this is not restrictive. It may be a FET or MOS transistor. Needless to say, there is no need to built the transistor 1443 into the IC 14 , and may be placed outside the IC. Also, power generator and other generator circuits as well as the transistor 1443 may be built into the gate driver circuit 12 .
  • the white balance can be adjusted by controlling the ratios of the RGB reference currents.
  • the value of current passed by the unit current source 634 is determined based on one reference current.
  • the current passed by the unit current source 634 can be determined by determining the magnitude of the reference current. Consequently, the white balance in every gradation can be achieved by setting a reference current for each of R, G, and B.
  • the above matters work because the source driver circuit 14 produces current outputs varied in steps (is current-driven). Thus, the point is how the magnitude of the reference current can be set for each of R, G, and B.
  • the light emission efficiency of an EL element is determined by, or depends heavily on, the thickness of a film vapor-deposited or applied to the EL element.
  • the film thickness is almost constant within each lot.
  • lot control of the film thickness of the EL element 15 it is possible to determine relationship between the current passed through the EL element 15 and light emission efficiency. That is, the current value used for white balancing is fixed for each lot.
  • the currents passed through the EL elements 15 for R, G, and B are Ir (A), Ig (A), and Ib (A), respectively, a ratio of reference currents which can achieve a white balance can be known on a lot-by-lot basis.
  • the duty ratio driving, etc. according to the present invention, once a white balance is achieved, it is applied to all gradations. This is accomplished by synergy between a drive method according to the present invention and source driver circuit according to the present invention.
  • the values of the resistors 691 in the circuits which generate RGB reference currents can be changed on a lot-by-lot basis to achieve a white balance.
  • the resistors 691 must be changed on a lot-by-lot basis.
  • the electronic regulator circuit 561 is controlled from the outside of the source driver circuit (IC) 14 and the value of the reference current Ia is changed by operating switches Sx in the electronic regulator circuit 561 .
  • settings of the electronic regulator circuits 561 can be stored in flash memories 1491 .
  • Values in the flash memories 1491 can be set by the RGB electronic regulator circuits 561 independently of one another. The values in the flash memories 1491 are set, for example, for each lot of EL display panels and read out upon power-up of the source driver IC 14 to set the switches Sx in the electronic regulator circuits 561 .
  • FIG. 150 is a block diagram in which the electronic regulator circuit 561 in FIG. 149 is configured as a resistor array circuit 1501 .
  • reference character Rr denotes an external resistor.
  • Rr may be built into the source driver circuit (IC) 14 .
  • Resistor arrays 1503 are built into the source driver circuit (IC) 14 .
  • Resistors (R 1 to Rn) composing the resistor array are connected in series and the resistors (R 1 to Rn) are connected by short-circuiting wires. Cutting this connection at point a or b, etc. shown in FIG. 150 varies the current Ir flowing through the resistor array 1503 .
  • Changes in the current Ir cause changes to the voltage applied to the positive terminal of the operational amplifier 722 , resulting in changes in the reference current Ia.
  • the point at which the connection will be cut is determined by monitoring the current flowing through the resistor Rr, in such a way as to produce a target reference current.
  • laser light 1502 can be emitted from a laser device 1501 .
  • the RGB reference currents are varied by varying the values of RGB resistors 691 .
  • the RGB reference currents are varied by operating the switches Sx in the electronic regulator circuits 561 using values stored in the flash memories 1491 .
  • the RGB reference currents are varied by trimming the resistance values of the resistor array 1503 .
  • the present invention is not limited to that.
  • the reference currents can be varied by varying the value of each of RGB reference voltages (VrefR, VrefG, and VrefB) in FIGS. 149 and 150 .
  • the RGB reference voltages Vref can be generated easily by an operational amplifier circuit or the like.
  • FIGS. 148, 149 , 150 , etc. by using the resistor Rr as a regulator, it is possible to vary the reference voltage applied to the source driver circuit (IC) 14 , as a result.
  • the present invention allows the values of output current to be changed easily by changing the current mirror factor of the final-stage current sources 633 or current sources ( 631 , 632 , etc.) in preceding stages.
  • the current mirror factor is varied (differed) separately for R, G, and B.
  • the current mirror factor of any current source only for R for example, may be varied (differed) from the other colors (from the current source circuits for the other colors).
  • EL display panels in particular, have different luminous efficiencies for different colors (R, G, and B; or cyan, yellow, and magenta).
  • R, G, and B or cyan, yellow, and magenta
  • the current mirror factor of current sources may be varied (differed) from the other colors (from the current source circuits for the other colors) in an unfixed manner. It may be variable.
  • the current mirror factor can be made variable by providing a plurality of transistors composing a current mirror circuit in a current source and changing, based on external signals, the number of transistors through which current current is passed. This configuration makes it possible to achieve an optimum white balance through adjustments while observing emission condition of manufactured EL display panels in various colors.
  • the present invention in particular is configured to connect current sources (current mirror circuits) in multiple stages.
  • current sources current mirror circuits
  • the present invention in particular is configured to connect current sources (current mirror circuits) in multiple stages.
  • current mirror factor between the first-stage current source 631 and second-stage current sources 632 , it is possible to vary the output currents of a large number of outputs easily using a small number of connections (current mirror circuits and the like). Needless to say, this makes it possible to vary the output currents of a large number of outputs easily using a smaller number of connections (current mirror circuits and the like) than by varying the current mirror factor between the second-stage current sources 632 and third-stage current sources 633 .
  • varying a current mirror factor means varying (adjusting) a magnification factor of current.
  • it is not limited to current mirror circuits.
  • it can be implemented by an operational amplifier circuit for current output or a D/A circuit for current output.
  • the items described above also apply to other examples of the present invention.
  • the current source 631 constituted of the first-stage current mirror circuit is referred to as a parent current source
  • the current sources 632 constituted of the second-stage current mirror circuits are referred to as child current sources
  • the current sources 633 constituted of the third-stage current mirror circuits are referred to as grandchild current sources.
  • the use of an integral multiple for the third-stage current mirror circuits which are the final-stage current mirror circuits makes it possible to minimize variations in the 176 outputs and produce high-accuracy current outputs.
  • the current sources 531 , 632 , and 633 must be placed densely.
  • dense placement means placing the first current source 631 and the second current sources 632 (the current or voltage output and current or voltage input) at least within a distance of 8 mm. More preferably, they are placed within 5 mm. It has been shown analytically that when placed at this density, the current sources can fit into a silicon chip with little difference in transistor characteristics (Vt and mobility ( ⁇ )) Similarly, the second current sources 632 and third current sources 633 (the current output and current input) are placed at least within a distance of 8 mm. More preferably, they are placed within 5 mm. Needless to say, the above items also apply to other examples of the present invention.
  • the current or voltage output and current or voltage input mean the following relationships.
  • the transistor 631 (the output) of the (I)-th current source and the transistor 632 a (the input) of the (I+1)-th current source are placed close to each other.
  • the transistor 631 a (the output) of the (I)-th current source and the transistor 632 b (the input) of the (I+1)-th current source are placed close to each other.
  • FIGS. 65, 66 , etc. it is assumed in FIGS. 65, 66 , etc. that there is one transistor 631 , this is not restrictive.
  • transistor 632 a there is one transistor 632 a, this is not restrictive.
  • the following configurations can be illustrated: a configuration in which one transistor 631 is connected with a plurality of transistors 632 a, a configuration in which a plurality of transistors 631 are connected with one transistor 632 a, and a configuration in which a plurality of transistors 631 are connected with a plurality of transistors 632 a.
  • transistors 633 a and 633 b in FIG. 68 Possible configurations include a configuration in which one transistor 633 a is connected with a plurality of transistors 633 b, a configuration in which a plurality of transistors 633 a are connected with one transistor 633 b, and a configuration in which a plurality of transistors 633 a are connected with a plurality of transistors 633 b.
  • transistors 632 a and 632 b in FIG. 68 preferably a plurality of transistors 633 b are used in FIG. 64 . Similarly, it is preferable to use plurality of transistors 633 in FIGS. 73 and 74 .
  • the unit transistor 634 may be a bipolar transistor, CMOS transistor, Bi-CMOS transistor, or DMOS transistor. However, in terms of reducing variations in the output of the unit transistor 634 , preferably a CMOS transistor is used for the unit transistor 634 .
  • the unit transistor 634 is an N-channel transistor.
  • the unit transistor consisting of a P-channel transistor has 1.5 times larger output variations than the unit transistor consisting of an N-channel transistor.
  • the programming current of the source driver IC 14 is a current drawn from the pixel 16 .
  • the driver transistor 11 a of the pixel 16 is a P-channel transistor.
  • the switching transistor 11 d in FIG. 1 is also a P-channel transistor.
  • the configuration in which the unit transistor 634 in the output stage of the source driver IC (circuit) 14 is an N-channel transistor and the driver transistor 11 a of the pixel 16 is a P-channel transistor is characteristic of the present invention. Incidentally, if all the transistors 11 composing the pixel 16 are illustrated in FIG. 1 , this is more preferable because this can reduce the number of process masks required to produce the pixel 16 .
  • N-channel transistors should be used for the unit transistors 634 (see FIGS. 73, 74 , 126 , and 129 ) of the source driver circuit. That is, the source driver circuit 14 should be configured in such a way as to draw the programming current Iw.
  • the driver transistors 11 a of the pixels 16 are P-channel transistors
  • the unit transistors 634 of the source driver circuit 14 must always be N-channel transistors to ensure that the source driver circuit 14 will draw the programming current Iw.
  • P-channel transistors are used for the pixels 16 and gate driver circuits 12 while N-channel transistors are used as the transistors of drawing current sources of the source drivers.
  • P-channel transistors are used as the transistors 11 of pixels 16 and for the gate driver circuits 12 .
  • unit transistors 634 must be N-channel transistors.
  • the source driver circuit 14 cannot be formed directly on a board 71 .
  • the source driver circuit 14 is made of a silicon chip and the like separately and mounted on the array board 71 .
  • the present invention is configured to mount the source driver IC 14 (means of outputting programming current as video signals) externally.
  • the source driver circuit 14 is made of a silicon chip, this is not restrictive. For example, a large number of source driver circuits may be formed on a glass substrate simultaneously using low-temperature polysilicon technology or the like, cut off into chips, and mounted on boards 71 .
  • a source driver circuit is mounted on a board 71 , this is not restrictive. Any form may be adopted as long as the output terminals 681 of the source driver circuit 14 are connected to the source signal lines 18 of the board 71 .
  • the source driver circuit 14 may be connected to the source signal lines 18 using TAB technology.
  • P-channel transistors are used as selection transistors of pixels 16 and for gate driver circuits is not limited to organic EL or other self-luminous devices (display panels or display apparatus). For example, it is also applicable to liquid crystal display device and FEDs (field emission displays).
  • the switching transistors 11 b and 11 c of a pixel 16 are P-channel transistors, the pixel 16 becomes selected at Vgh, and becomes deselected at Vgl. As described earlier, when the gate signal line 17 a changes from Vgl (on) to Vgh (off), voltage penetrates (penetration voltage). If the driver transistor 11 a of the pixel 16 is a P-channel transistor, the penetration voltage more tightly restricts the flow of current through the transistor 11 a in black display mode. This makes it possible to achieve a proper black display. The problem with the current-driven system is that it is difficult to achieve a black display.
  • the turn-on voltage corresponds to Vgh.
  • the gate driver circuits 12 match well with the pixels 16 constructed from P-channel transistors.
  • the programming current Iw flows from the anode voltage Vdd to the unit transistors 634 of the source driver circuit 14 via the driver transistors 11 a and source signal lines 18 , as is the case with the pixel 16 configuration shown in FIGS. 1, 2 , 32 , 140 , 142 , 144 , and 145 .
  • N-channel transistors are used as the unit transistors 634 of the source driver circuit 14 .
  • unit transistors 634 constituted of N-channel transistors have smaller variations in output current than unit transistors 634 constituted of P-channel transistors.
  • N-channel unit transistors 634 have 1/1.5 to 1/2 as large variations in output current as P-channel unit transistors 634 when they have the same area (W*L). For this reason, it is preferable that N-channel transistors are used as the unit transistors 634 of the source driver IC 14 .
  • FIG. 42 ( b ) shows a configuration in which a programming current Iw flows from an anode voltage Vdd to the unit transistors 634 of a source driver circuit 14 via a programming transistor 11 a and source signal line 18 rather than a configuration in which current flows into the unit transistors 634 of a source driver circuit 14 via a driver transistor 11 b.
  • a good synergistic effect can be produced if P-channel transistors are used for the gate driver circuits 12 and pixels 16 , the source driver circuit 14 is mounted on the substrate, and N-channel transistors are used as the unit transistors 634 of the source driver circuit 14 .
  • the driver transistors 11 a of the pixels 16 are P-channel transistors and the switching transistors 11 b and 11 c are P-channel transistors.
  • the unit transistors 634 in the output stages of the source driver IC 14 are N-channel transistors.
  • preferably P-channel transistors are used for the gate driver circuits 12 .
  • the driver transistors 11 a of the pixels 16 are N-channel transistors and the switching transistors 11 b and 11 c are N-channel transistors.
  • the unit transistors 634 in the output stages of the source driver IC 14 are P-channel transistors.
  • preferably N-channel transistors are used for the gate driver circuits 12 .
  • This configuration also belongs to the present invention.
  • the above items apply not only to an IC which contain a single unit transistor 634 , but also to a source driver IC 14 with another configuration such as a source driver circuit whose current output stage contains a plurality of transistors or current mirrors.
  • source driver circuits 14 also apply to source driver circuits 14 by using semiconductor films of low-temperature polysilicon, high-temperature polysilicon, CGS formed by solid-phase growth, or amorphous silicon. In that case, however, panels are often relatively large. On a large panel, it is hard to visually perceive the effect of some variations in the output from the source signal lines 18 .
  • dense placement means placing the first current source 631 and second current sources 632 (the input and output of current) at least within 30 mm (inclusive) of each other. More preferably, they are within 20 mm (inclusive) of each other. It has been shown analytically that there is little difference in characteristics (Vt and mobility ( ⁇ )) of transistors placed in this range.
  • the second current sources 632 and third current sources 633 are placed at least within 30 mm (inclusive) of each other. More preferably, they are within 20 mm (inclusive) of each other.
  • FIG. 67 shows an example of configuration for current-based delivery.
  • FIG. 66 also shows an example of configuration for current-based delivery.
  • FIGS. 66 and 67 are similar in terms of circuit diagrams and differ in layout configuration, i.e., wiring layout.
  • reference numeral 631 denotes an N-channel transistor for the first-stage current source
  • 632 a denotes an N-channel transistor for a second-stage current source
  • 632 b denotes a P-channel transistor for a second-stage current source.
  • reference numeral 631 a denotes a first-stage N-channel current source transistor
  • 632 a denotes a second-stage N-channel current source transistor
  • 632 b denotes a second-stage P-channel current source transistor.
  • the gate voltage of the first-stage current source consisting of a variable register 651 (used to vary current) and the N-channel transistor 631 is delivered to the gate of the N-channel transistor 632 a of the second-stage current source.
  • this is a layout configuration of a voltage-based delivery type.
  • the gate voltage of the first-stage current source consisting of a variable register 651 and the N-channel transistor 631 a is applied to the gate of the N-channel transistor 632 a of the adjacent second-stage current source, and consequently the value of the current flowing through the transistor is delivered to the P-channel transistor 632 b of the second-stage current source.
  • this is a layout configuration of a current-based delivery type.
  • the N-channel transistor 631 of the first-stage current source and the N-channel transistor 632 a of the second-stage current source composing the current mirror circuit are separated (or liable to get separated, to be precise), and thus the two transistors tend to differ in characteristics. Consequently, the current value of the first-stage current source is not transmitted correctly to the second-stage current source and there can be variations.
  • the N-channel transistor 631 a of the first-stage current source and the N-channel transistor 632 a of the second-stage current source composing the current mirror circuit are located adjacent to each other (easy to place adjacent to each other), and thus the two transistors hardly differ in characteristics. Consequently, the current value of the first-stage current source is transmitted correctly to the second-stage current source and there can be little variations.
  • FIG. 68 shows a current-based delivery version of three-stage current mirror circuit (three-stage current source) shown in FIG. 65 (which, therefore shows a circuit configuration of a voltage-based delivery type).
  • a reference current is created first by the variable register 651 and N-channel transistor 631 .
  • the reference current is adjusted by the variable register 651 , actually the source voltage of the transistor 631 is set and regulated by an electronic regulator formed (or placed) in the source driver IC (circuit) 14 .
  • the reference current is adjusted by directly supplying the source terminal of the transistor 631 with current outputted from a current-type electronic regulator consisting of a large number of unit transistors (single-unit) 634 as shown in FIG. 64 (see FIG. 69 ).
  • the gate voltage of the first-stage current source constituted of the transistor 631 is applied to the gate of the N-channel transistor 632 a of the adjacent second-stage current source, and the current consequently flowing through the transistor is delivered to the P-channel transistor 632 b of the second-stage current source.
  • the gate voltage of the P-channel transistor 632 b of the second-stage current source is applied to the gate of the N-channel transistor 633 a of the adjacent third-stage current source, and the current consequently flowing through the transistor is delivered to the N-channel transistor 633 b of the third-stage current source.
  • a large number of current sources 634 are formed (placed) at the gate of the N-channel transistor 633 b of the third-stage current source according to the required bit count as illustrated in FIG. 64 .
  • the configuration in FIG. 69 is characterized in that the first-stage current source 631 of the multi-stage current mirror circuit is equipped with a current-value adjustment element. This configuration allows output current to be controlled by varying the current value of the first-stage current source 631 .
  • Variations in the Vt of transistors are on the order of 100 mV within a wafer. However, variations in Vt of transistors formed within 100 ⁇ of each other should be 10 mV or less (actual measurement) That is, by configuring a current mirror circuit with transistors formed close to each other, it is possible to reduce variations in the output current of the current mirror circuit. This reduces variations in the output current among terminals of the source driver IC.
  • Vt variations among transistors
  • variations among transistors are not limited to variations in Vt.
  • FIG. 110 shows formation areas of transistors (square millimeter) versus variations in the output current of unit transistors 484 based on measurement results.
  • the variations in the output current are variations in current at a threshold voltage (Vt).
  • Black dots indicate variations in the output current of evaluation sample transistors (10 to 200 in number) created in a formation area.
  • area C a formation area of 2.4 square millimeters or more
  • variations in the output current with respect to the formation area tend to increase sharply.
  • area B a formation area of 0.5 to 2.4 square millimeters
  • variations in the output current are almost proportional to the formation area.
  • the present invention varies (controls) the amount of current flowing through the source signal line 18 by switching the number of currents flowing through the unit transistors 634 using input digital data (D).
  • D digital data
  • the formation area of a transistor group (the transistors among which variations should be suppressed) should be kept within 2 square millimeters as indicated by the results shown in FIG. 110 . More preferably, the output current variations (i.e., variations in the Vt of transistors) should be kept within 0.5%. That is, the formation area of a transistor group 681 can be kept within 1.2 square millimeters as indicated by the results shown in FIG. 110 . Incidentally, the formation area is given by the vertical length multiplied by the horizontal length. For example, a formation area of 1.2 square millimeters results from 1 mm ⁇ 1.2 mm.
  • the above applies to 8-bit (256 gradations) or larger data.
  • variations in output current may be somewhere around 2% (virtually no problem in terms of image display).
  • the formation area of a transistor group 681 can be kept within 5 square millimeters.
  • transistor groups 681 a and 681 b are shown in FIG. 68 ) to satisfy this condition.
  • Effect of the present invention can be achieved if at least one of the transistor groups (one or more transistor groups 681 if there are more than three) satisfy the condition.
  • this condition should be satisfied for a lower level transistor group 681 ( 681 a is higher than 681 b ). This will reduce image display problems.
  • the source driver circuit (IC) 14 of the present invention at least a plurality of current sources, such as consisting of parent, child, and grandchild current sources, are connected in multiple stages (of course there may be two stages consisting of parent and child current sources) and placed densely, as shown in FIG. 68 .
  • Current-based delivery is made between current sources (between the transistor groups 681 ).
  • transistors enclosed by dotted lines in FIG. 68 transistors enclosed by dotted lines in FIG. 68 (transistor groups 681 ) are placed densely.
  • the transistor groups 681 make voltage-based delivery between each other.
  • the parent current source 631 and child current sources 632 a are formed (placed) approximately in the center of the source driver IC chip 14 .
  • the top-level transistor group 681 a is placed at the approximate center of the IC chip.
  • lower-level transistor groups 681 b are placed on the left and right of the IC chip 14 .
  • the transistors are placed, formed, or produced in such a way that approximately equal numbers of lower-level transistor groups 681 b will be on the left and right of the IC chip 14 .
  • the above items are not limited to IC chips 14 , but apply to source driver circuits 14 formed directly on array boards 71 using low-temperature polysilicon technology or high-temperature polysilicon technology. The same is true of the other items.
  • the child transistor groups 681 b are arranged in such a way that their numbers will be equal on the left and right of the chip or that the difference between the number of the child transistor groups 681 b formed or placed on the left with respect to the center of the chip where the parent is formed and the number of the child transistor groups 681 b formed or placed on the right of the chip will be four or less.
  • the difference between the number of the child transistor groups 681 b formed or placed on the left of the chip and the number of the child transistor groups 681 b formed or placed on the right of the chip is one or less.
  • the above items similarly apply to grandchild transistor groups (omitted in FIG. 68 ).
  • the formation area of the transistor group 681 a is kept within 2 square millimeters as shown in FIG. 110 . More preferably, it is kept within 1.2 square millimeters. If the number of gradations is 64 or less, of course, the formation area may be within 5 square millimeters.
  • the transistors 632 a composing the second current sources (child) and the transistors 632 b composing the second current sources (child) should be placed at least within 10 mm of each other as described above.
  • the transistors should be placed or formed within 8 mm. More preferably, they should be placed within 5 mm.
  • the above conditions are satisfied especially by lower-level transistor groups.
  • the transistor group 681 a is at the top level with the transistor groups 681 b lying below it and transistor groups 681 c lying further below them, the current-based delivery between the transistor groups 681 b and transistor groups 681 c should satisfy the above conditions.
  • the transistor groups 681 b are formed, built, or placed in the left-to-right direction of the chip (in the longitudinal direction, i.e., at locations facing the output terminal 761 ).
  • the transistor groups 681 b are formed, built, or placed in the left-to-right direction of the chip (in the longitudinal direction, i.e., at locations facing the output terminal 761 ).
  • the number M of the transistor groups 681 b is 11 (see FIG. 63 ).
  • Voltage-based delivery (voltage connection) is made between the child current sources 632 b and grandchild current sources 633 a.
  • the transistors in the transistor groups 681 b are placed densely as is the case with the transistor group 681 a.
  • the formation area of the transistor group 681 b should be within 2 square millimeters as shown in FIG. 110 . More preferably, it should be within 1.2 square millimeters. However, even slight variations in the Vt of the transistors in the transistor groups 681 b tend to appear on the screen. Thus, preferably the formation area should be area A (0.5 square millimeters or less) in FIG. 110 .
  • the transistors 633 a constituting the third (grandchild) current sources and transistors 633 b constituting the second (grandchild) current sources should be placed within at least 8 mm of each other. More preferably, they should be placed within 5 mm.
  • FIG. 69 shows the current-value adjustment element constituted of an electronic regulator.
  • the electronic regulator consists of a resister 691 (which is formed of polysilicon, controls current, and creates reference voltages), decoder circuit 692 , level-shifter circuit 693 , etc. Incidentally, the electronic regulator outputs current.
  • a transistor 641 functions as an analog switch circuit.
  • transistors may be referred to as current sources. This is because transistors function as current sources in current mirror circuits and the like composed of transistors.
  • Electronic regulators circuits are formed (or placed) according to the number of colors used by the EL display panel. For example, if the three primary colors RGB are used, preferably three electronic regulators are formed (or placed) corresponding to the colors so that the colors can be adjusted independently. However, if one color is used as a reference (is fixed), as many electronic regulators circuits as the number of colors minus 1 should be formed (or placed).
  • FIG. 76 shows a configuration in which resistive elements 651 are formed (or placed) to control reference voltages of the three primary colors RGB independently.
  • the resistive elements 651 may be substituted with electronic regulators.
  • Basic current sources including parent and child current sources such as the current source 631 and current sources 632 are placed densely in an output current circuit 704 in an area illustrated in FIG. 76 . The dense placement reduces variations in outputs from the source signal lines 18 . As illustrated in FIG.
  • the output current circuit 704 may be placed at an end or both ends of the IC chip. Also, they may be formed or placed in parallel with the output current circuit 704 .
  • the unit transistors of the output circuits connected to the output terminals 761 b and 761 c differ in Vt. Even if the unit transistors 634 of the output terminals have equal gate terminal voltage, their output current will vary depending on the Vt distribution of the unit transistors 634 . Consequently, there may be steps of output currents in the center of the panel. The steps of output currents can cause brightness difference between the right and left sides in the center of the screen.
  • FIG. 122 A configuration used to solve this problem is shown in FIG. 122 .
  • FIG. 122 ( a ) shows an exemplary configuration in which an output current circuit 704 is placed on one side of an IC chip.
  • FIG. 122 ( b ) shows an exemplary configuration in which output current circuits 704 are placed on both sides of an IC chip.
  • FIG. 122 ( c ) shows an exemplary configuration in which an output current circuit 704 is placed on the side of input terminals of an IC chip.
  • output terminals are formed orderly in areas not occupied by the output current circuits 704 .
  • transistors 633 a and transistors 633 b are connected in a one-to-one completion.
  • transistors 632 a and transistors 632 b are connected in a one-to-one completion.
  • FIG. 123 an example with an appropriate configuration is shown in FIG. 123 .
  • transmission transistor groups 681 b 681 b 1 , 681 b 2 , and 681 b 3 ) each of which consists of four transistors 633 a
  • transmission transistor groups 681 c 681 c 1 , 681 c 2 , and 681 c 3 ) each of which consists of four transistors 633 b are connected with each other.
  • each of the transistor groups 681 b and 681 c consist of four transistors 633 , this is not restrictive and may consist of less than four or more than four transistors.
  • a reference current Ib flowing through the transistors 633 a is output from a plurality of transistors 633 which form a current mirror circuit together with the transistors 633 a and the output current is received by a plurality of transistors 633 b.
  • the plurality of transistors 633 a and plurality of transistors 633 b are approximately equal in size and equal in number.
  • the unit transistors 634 ( 63 in number in the case of 64 gradations as in FIG. 124 ) each of which produces one output and the transistors 633 b which compose a current mirror together with the unit transistors 634 are also approximately equal in size and equal in number. The above configuration makes it possible to set a current mirror ratio accurately and reduce variations in output current.
  • the current flowing through the transistors 633 b is equal to or more than five times a current Ic 1 passed through the transistors 632 b. This will stabilize the gate potential of the transistors 633 a and suppress transient phenomena caused by output current.
  • the transmission transistor group 681 b 1 and transmission transistor group 681 b 2 are placed adjacent to each other and that each of them consists of four transistors 633 a placed next to one another, this is not restrictive.
  • the transistors 633 a of the transmission transistor group 681 b 1 and the transistors 633 a of the transmission transistor group 681 b 2 may be placed or formed alternately. This will reduce variations in the output current (programming current) of each terminal.
  • the total formation area of the transistors 633 composing a transmission transistor group 681 is an important item. Basically, the larger the total formation area of the transistors 633 , the smaller the variations in output current (programming current flowing in from the source signal line 18 ). That is, the larger the formation area of the transmission transistor group 681 (the total formation area of the transistors 633 ), the smaller the variations. However, a larger formation area of the transistors 633 increases a chip area, increasing the price of the IC chip 14 .
  • the formation area of a transmission transistor group 681 is the sum total of the formation areas of the transistors 633 composing the transmission transistor group 681 .
  • the area of a transistor 633 is the product of the channel length L and channel width W of the transistor 633 .
  • the formation area of the transmission transistor group 681 should be determined in such a way as to maintain a certain relationship with the unit transistors 634 . Also, the transmission transistor group 681 a and transmission transistor group 681 b should maintain a certain relationship.
  • a plurality of unit transistors 634 are connected per one transistor 633 b.
  • the transistor 633 b in FIG. 64 and transmission transistor groups 681 c in FIG. 123 are relevant here.
  • the formation area Ts of the unit transistor group and formation area Tm of the transmission transistor group 681 c have the following relationship: 1/4 ⁇ Tm/Ts ⁇ 6
  • the formation area Ts of the unit transistor group and formation area Tm of the transmission transistor group 681 c have the following relationship: 1/2 ⁇ Tm/Ts ⁇ 4
  • the formation area Tmm of the transmission transistor group 681 b and formation area Tms of the transmission transistor group 681 c have the following relationship: 1/2 ⁇ Tmm/Tms ⁇ 8
  • the formation area Ts of the unit transistor group and formation area Tm of the transmission transistor group 681 c have the following relationship: 1 ⁇ Tm/Ts ⁇ 4
  • output current from the transistor group 681 b 1 is Ic 1
  • output current from the transistor group 681 b 2 is Ic 2
  • output current from the transistor group 681 b 2 is Ic 3 .
  • the output currents Ic 1 , Ic 2 , and Ic 3 must coincide.
  • each transistor group 681 consists of multiple transistors 633 , even if individual transistors 633 have variations, there is no variation in the output current Ic of the transistor group 681 as a whole.
  • the above example is not limited to three-stage current mirror connections (multi-stage current mirror connections) shown in FIG. 68 . Needless to say, it is also applicable to single-stage current mirror connections.
  • the example shown in FIG. 123 involves connecting the transistor groups 681 b ( 681 b 1 , 681 b 2 , 681 b 3 , . . . ) each of which consists of multiple transistors 633 a with the transistor groups 681 c ( 681 c 1 , 681 c 2 , 681 c 3 , . . . ) each of which consists of multiple transistors 633 b.
  • the present invention is not limited to this.
  • the switch 641 a corresponds to the 0th bit
  • the switch 641 b corresponds to the 1st bit
  • the switch 641 c corresponds to the 2nd bit
  • the switch 641 f corresponds to the 5th bit.
  • the 0th bit consists of one unit transistor
  • the 1st bit consists of two unit transistor
  • the 2nd bit consists of four unit transistor
  • the 5th bit consists of thirty-two (32) unit transistor.
  • the source driver circuit 14 is a 6-bit driver supporting 64-gradation display.
  • the 1st bit outputs a twice larger programming current to the 0th bit
  • the 2nd bit outputs a twice larger programming current to the 1st bit
  • the 3rd bit outputs a twice larger programming current to the 2nd bit
  • the 4th bit outputs a twice larger programming current to the 3rd bit
  • the 5th bit outputs a twice larger programming current to the 4th bit.
  • each bit must be able to output twice as large programming current as the next lower-order bit.
  • the configuration in FIG. 124 contains adjustment transistors in addition to the unit transistors 634 for individual bits.
  • the adjustment transistors 1241 correspond to the 5th bit (switch 641 f ) and 4th bit (switch 641 e ).
  • the adjustment transistors 1241 are placed, formed, or constructed at the 5th bit (the unit transistors 634 connected to the switch 641 f ) and 4th bit (the unit transistors 634 connected to the switch 641 d ).
  • Four adjustment transistors 1241 each are placed or formed at the 5th bit and 4th bit.
  • the number of adjustment transistors 1241 for each bit maybe changed.
  • adjustment transistors 1241 may be attached to all the bits (by forming, constructing, or placing them).
  • the adjustment transistors 1241 are made smaller than the unit transistors 634 . Alternatively, they are designed to produce smaller output current than the unit transistors 634 . Even if transistor size is fixed, it is possible to vary output current by varying W/L.
  • the adjustment transistors 1241 and unit transistors 634 are configured or connected so as to share gate terminals, to which the same gate voltage is applied.
  • a current Ib flows through the transistors 633
  • the gate voltage of the unit transistors 634 is established, prescribing the current to be output from the unit transistors 634 .
  • output current of the adjustment transistors 1241 is also defined. That is, the output current of the adjustment transistors 1241 is proportional to the output current of the unit transistors 634 .
  • the output current can be controlled by means of the current Ib to be passed to the transistors 633 which pair up with the unit transistors 634 .
  • the size of one unit transistor 634 is made larger than the total size of two or more adjustment transistors. That is, the size of the unit transistor 634 is larger than the size of the adjustment transistor 1241 . Alternatively, the total size of two or more adjustment transistors 1241 is made larger than the size of the unit transistor 634 . By controlling the number of working adjustment transistors 1241 , it is possible to adjust variations in output current for each bit in small increments.
  • the output current of one unit transistor 634 is made larger than the output current of two or more adjustment transistors. That is, the output current of the unit transistor 634 is larger than the output current of the adjustment transistor 1241 .
  • the number of working adjustment transistors 1241 it is possible to adjust variations in output current for each bit in small increments.
  • FIG. 125 is an explanatory diagram illustrating a method of adjusting the output current for each bit using the adjustment transistors 1241 .
  • FIG. 125 shows four adjustment transistors 1241 which have been formed.
  • Ig is current which flows when all the four adjustment transistors 1241 operate normally, Ig>Ie should always be satisfied even if there are variations in production processes of transistors.
  • the output current Ib exceeds the target output current Ia (Ib>Ia).
  • adjustment transistors 1241 are cut off from the common terminal 1252 to obtain the target output current Ia.
  • Laser cutting is used to cut off the adjustment transistors 1241 . It is appropriate to use a YAG laser for the laser cutting. Besides, neon helium lasers and carbon dioxide lasers are also available. Also, machining such as sand blasting is available as well.
  • the transistors 1241 a and 1241 b are cut off from the common terminal 1252 at two cutting sites 1251 . Consequently, the current Ig is halved. In this way, adjustment transistors 1241 are cut off one by one from the common terminal 1252 until the target output current Ia is obtained. The output current is measured with a microammeter to stop cutting off adjustment transistors 1241 when the measured value reaches the target value.
  • the cutting sites 1251 are cut with laser to adjust the output current
  • this is not restrictive.
  • laser may be emitted directly to adjustment transistors 1241 to adjust the output current by destroying them.
  • analog switches at the cutting sites 1251 turn on and off the analog switches by external control signals, and thereby vary the number of adjustment transistors 1241 to be connected to point g. That is, the present invention forms adjustment transistors 1241 and obtains target output current by turning on and off the adjustment transistors 1241 .
  • other configurations can also be used.
  • the adjustment transistors 1241 are formed in advance, this is not restrictive.
  • FIG. 166 illustrates part of the adjustment transistors 1241 or unit transistors 634 .
  • a plurality of unit transistors 634 (or the adjustment transistors 1241 ) are connected via internal wiring 1622 .
  • the adjustment transistors 1241 have a slit cut in their source terminals (S terminals) for ease of trimming. By making a cut at a cutoff point 1661 b, it is possible to limit the current flowing between channels of the adjustment transistors 1241 . This decreases output current in a current output stage 704 .
  • a slit may be formed not only in the source terminal, but also in the drain or gate terminal. Needless to say, part of the adjustment transistors 1241 can be cut off even if no slit is formed. It is also possible to form a plurality of adjustment transistors 1241 of different shapes, trim the adjustment transistors 1241 after measurement of output current, and thereby select the transistors which will produce output current closest to the target output current.
  • unit transistors 634 or adjustment transistors 1241 are trimmed to adjust output current in the above example, the present invention is not limited to this.
  • output current circuits 704 and adjustment transistors 1241 with their gate terminals and source terminals connected and connect the drain terminals of the adjustment transistors 1241 by a FIB process.
  • the gate terminals of adjustment transistors 1241 in isolation from the gate terminals of unit transistors 634 , which form the output current circuits 704 , and form or place the unit transistors 634 and the adjustment transistors 1241 with their drain terminals and source terminals connected.
  • the potential at the gate terminals of the unit transistors 634 is determined by current Ic as illustrated in FIG. 164 and the like.
  • the potential at the gate terminals of the adjustment transistors 1241 can be adjusted freely. By adjusting this potential, it is possible to change the output current of the adjustment transistors 1241 .
  • the output current of the output current circuits 704 which is a sum total of the output currents from the unit transistors 634 and adjustment transistors 1241 .
  • This method does not require a trimming process or FIB process.
  • the gate terminal voltage of the adjustment transistors 1241 may be adjusted using an electronic regulator or the like.
  • the output current of the adjustment transistors 1241 is adjusted through adjustment of the potential at the gate terminals, this is not restrictive.
  • the output current may be adjusted through adjustment of the voltage applied to the source terminals or drain terminals of the adjustment transistors 1241 . These terminal voltages may also be adjusted using an electronic regulator.
  • the voltages applied to the terminals of the adjustment transistors 1241 are not limited to direct-current voltages. It is also possible to apply rectangular voltages (pulsed voltages or the like) and control output voltages by duration control.
  • the adjustment transistors 1241 may be cut off at a cutoff point 1661 a as illustrated in FIG. 166 . In this way, by trimming all or part of the unit transistors 634 or adjustment transistors 1241 , it is possible to adjust the output current easily. To protect trimming sites from degradation, it is recommended to seal them by vapor-depositing or applying inorganic or organic material to them after trimming so that they will not be exposed to the air.
  • the output current circuits 704 on both ends of the IC chip 14 are equipped with a trimming function.
  • a plurality of source driver ICs 14 must be cascaded. This is because cascade connection makes any difference between output currents of adjacent ICs conspicuous as a boundary.
  • trimming transistors and the like as illustrated in FIG. 166 it is possible to correct output current variations among adjacent output current circuits.
  • FIG. 123 reduces variations in the output current of each terminal by making a plurality of transistors 633 b receive output current from a plurality of transistors 633 a.
  • FIG. 126 shows a configuration which reduces variations in the output current of each terminal by supplying current from both sides of a transistor group. Multiple sources are provided for current Ia. Current Ia 1 and current Ia 2 have the same current value and the transistor which generates the current Ia 1 and the transistor which generates the current Ia 2 compose a current mirror circuit as a pair.
  • a plurality of transistors are formed, placed, or constructed to generate reference currents which prescribe output currents of the unit transistors 634 . More preferably, output currents from the plurality of transistors are connected to current-receiving circuits such as transistors which compose current mirror circuits and the output currents of the unit transistors 634 are controlled by gate voltages generated by the plurality of transistors.
  • FIG. 126 shows transistors 633 b composing current mirror circuits are formed on both sides of the group of the unit transistors 634 .
  • the present invention is not limited to this.
  • a configuration in which transistors 632 a composing current mirrors are placed on both sides of a transistor group 681 b also belongs to the present invention.
  • the transistor group 681 b contains a plurality of transistors 633 a which output current.
  • transistors 632 a 632 a 1 and 632 a 2 ) which share the gate terminals of the transistor group 681 b and form current mirrors circuit in conjunction with transistors 633 a.
  • a reference current Ia 1 flows through the transistor 632 a 1 and a reference current Ia 2 flows through the transistor 632 a 2 .
  • the gate terminal voltage of the transistors 633 a ( 633 a 1 , 633 a 2 , 633 a 3 , 633 a 4 , . . . ) a redefined by the transistors 632 a 1 and 632 a 2 , and define the current outputted from the transistors 633 a.
  • the magnitudes of the reference currents Ia 1 and Ia 2 are made to coincide. This can be accomplished by constant-current circuits such as the current mirror circuit which output the reference currents Ia 1 and Ia 2 .
  • the present invention is not limited to this.
  • the reference currents Ia 1 and Ia 2 may be different from each other.
  • a current Ib 1 outputted by a transistor 633 a 1 can be made smaller than a current Ibn outputted by a transistor 633 an (Ib 1 ⁇ Ibn).
  • the smaller the current Ib 1 the smaller the current outputted by a transistor group 681 c 1 .
  • the larger the current Ibn the larger the current outputted by a transistor group 681 cn.
  • the transistor groups 681 placed or formed between the transistor group 681 c 1 and transistor group 681 cn produce output currents of intermediate magnitudes.
  • the gate terminal voltage differs among the unit transistors 634 .
  • the gate wiring 1261 is formed of polysilicon.
  • the resistance value of the gate wiring between the transistors 632 a 1 and 632 an should be between 2 K ⁇ and 2 M ⁇ (both inclusive). In this way, by increasing the resistance of the gate wiring 1261 , it is possible to produce a slope in the output currents of the transistor groups 681 c.
  • the gate terminal voltage of the transistor 633 a is set at 0.52 to 0.68 V (both inclusive) is a silicon IC chip is used. This range can reduce variations in the output current of the transistor 633 a.
  • the above items similarly apply to other examples of the present invention.
  • the current mirror circuit contains two or more (multiple) transistors 632 a which pair with the transistors 633 a. Since reference current are supplied from both sides, the gate terminal voltage of the transistors 633 a is kept constant reliably in the transistor group 681 a. Consequently, variations in the output current produced by the transistors 633 a are extremely small. Thus, there are extremely small variations in the programming current outputted to the source signal line 18 or programming current drawn from the source signal line 18 .
  • the transistor groups 681 c constitute output-stage circuits connected to respective source signal lines 18 .
  • the transistor groups 681 c by supplying current to the transistor groups 681 c from both sides and eliminating voltage drops or potential distribution of the gate terminals of the unit transistors 634 , it is possible to do away with variations in output currents from the source signal lines 18 .
  • Each transistor group 681 c contains a plurality of unit transistors 634 which output current.
  • transistors 633 b ( 633 b 1 and 633 b 2 ) which share the gate terminals of the transistors 634 and form current mirror circuits in conjunction with the transistors 634 .
  • the reference current Ib 1 flows through the transistor 633 b 1 and the reference current Ib 2 flows through the transistor 633 b 2 .
  • the gate terminal voltage of the unit transistors 634 are defined by the transistors 633 b 1 and 633 b 2 , and define the current outputted from the unit transistors 634 .
  • the magnitudes of the reference currents Ib 1 and Ib 2 are made to coincide. This can be accomplished by constant-current circuits such as the transistors 633 a which output the reference currents Ib 1 and Ib 2 . Even if the reference currents Ib 1 and Ib 2 deviate more or less from each other, this poses little problem because they correct each other.
  • FIG. 127 shows a variation of the example shown in FIG. 126 .
  • FIG. 127 there is a transistor 632 which forms a current mirror circuit in the middle of the transistor group 681 b in addition to the transistors 632 a which form current mirror circuits on both sides of the transistor group 681 b. Consequently, the transistors 633 a have a more constant gate terminal voltage and less variations in its output, compared with the configuration shown in FIG. 126 .
  • FIG. 128 shows another variation of the example shown in FIG. 126 .
  • the transistors 633 a in the transistor group 681 b are connected in sequence with the transistors 633 b which form current mirror circuits in conjunction with the transistor groups 681 c.
  • the transistors 633 a are connected in a different order.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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US11/865,749 Active 2025-12-15 US8063855B2 (en) 2002-04-26 2007-10-02 Drive method of EL display panel
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US12/835,083 Expired - Lifetime US7932880B2 (en) 2002-04-26 2010-07-13 EL display panel driving method

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