TWI287263B - High mobility tri-gate devices and methods of fabrication - Google Patents
High mobility tri-gate devices and methods of fabrication Download PDFInfo
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- TWI287263B TWI287263B TW094118759A TW94118759A TWI287263B TW I287263 B TWI287263 B TW I287263B TW 094118759 A TW094118759 A TW 094118759A TW 94118759 A TW94118759 A TW 94118759A TW I287263 B TWI287263 B TW I287263B
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- GPMBECJIPQBCKI-UHFFFAOYSA-N germanium telluride Chemical compound [Te]=[Ge]=[Te] GPMBECJIPQBCKI-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
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- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
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- 229910052727 yttrium Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Description
I2E7263 ^ (1) 九、發明說明 t胃明所屬之技術領域】 本發明主要有關於半導體積體電路製造領域,更詳而 H之’諸如高移動率三閘電晶體之高移動率三閘裝置以及 其製造方法。 【先前技術】
爲增加裝置性能,已提出用於製造現今積體電路的絕 緣體上覆矽(SOI)電晶體。第1圖描述一標準完全空乏 絕緣體上覆矽(SOI)電晶體100。該SOI電晶體100包 含單晶矽基板1 02,其具有諸如埋設氧化物之絕緣層1 04 形成於其上。單晶矽體1 06形成於絕緣層1 04上。閘極電 介質層108形成於單晶矽體1〇6上,以及閘極電極形成於 閘極電介質層1 08上。源極1 1 2以及汲極1 1 4區域沿著閘 極電極1 1 0相對側橫向地形成於矽體1 06中。
已提出完全空乏SOI作爲電晶體結構以利用完美啓通 流/關斷電流比例之理想的次臨限値梯度。爲了使電晶 體1〇〇達成理想次臨線値梯度,矽體106之厚度(Tsi ) 必須約爲電晶體閘極長度(Lg )尺寸之1/3或著Tsi = Lg/3 。惟,隨著閘極長度的改變,特別當它們接近3 Onm時, 不斷縮減矽薄膜厚度之需要使得此方法更加不可行。在3 0 奈米閘極長度,矽體所需之厚度應爲小於1 0奈米,以及 在20奈米閘極長度約爲6奈米。製造厚度小於1〇奈米之 薄矽薄膜非常地困難。另一方面,達成一奈米程度之晶圓 -5- 1287263 ^ (2) 一致性亦爲困難的挑戰。另一方面,幾乎變得不可能接觸 這些薄膜來形成凸起之源極/汲極區域以降低接面電阻, 因爲於源極/汲極區域中這些薄的矽層會在閘極蝕刻以及 在閘極蝕刻與間隔體鈾刻之後的各種清洗過程中被消耗掉 ,留下不足的矽體1 06供矽生長於上。 已提出一種雙閘極(DG)裝置,如第2A與2B圖所 示,來減輕矽厚度的問題。雙閘極(DG )裝置200包含 矽體202形成於絕緣基板204上。閘極電介質206形成於 矽體202兩側以及閘極電極208與形成於矽體202兩側之 閘極電介質206相鄰形成。一足夠厚之絕緣層209,例如 氮化矽,將閘極電極208自矽體202頂部電性隔離。 雙閘極(DG )裝置200主要具有兩個閘極,各位在 裝置通道兩側。由於雙閘極裝置2 0 0具有閘極在裝置通道 兩側,矽體之厚度(Tsi )可爲單閘極裝置者之兩倍且仍 可獲得完全空乏電晶體之操作。亦及,由於雙閘極裝置 __200的緣故,可形成其中Tsi=(2xLg) /3之完全空乏電晶 體。惟,雙閘極(DG )裝置200最可製造之型式係需要 以比用來圖案化平面裝置(如電晶體1 〇 〇 )之閘極長度( Lg )小0.7倍之光微影技術圖案化矽體202。爲了獲得高 密度積體電路,通常希望對閘極電極208之閘極長度(Lg )使用最積極之微影技術。雖然雙閘極結構使矽薄膜厚度 加倍(由於現在於通道兩側各有一個閘極),但製造這些 結構卻非常地困難。例如,需要能夠產生具有長寬比率約 5:1之矽體202的矽體鈾刻。此外,隨著高裝置性能之要 (3) J287263 求不斷遞增,期望能有增加裝置性能之高移動率裝置。 【發明內容】及【實施方式】 本發明之實施例關於一種新穎的高移動率非平面裝置 或三閘裝置,諸如三閘電晶體結構,以及其製造方法。於 下列說明中,提出各種特定細節以提供本發明更完善的認 識。於其他範例中,將不以特定細節描述眾所周知之半導
體程序以及製造技術以期不必要地模糊本發明實施例。 本發明之實施例關於一種高高移動率非平面裝置(例 如三閘電晶體)。藉由用於形成高移動率非平面裝置之基 板晶圓之參考方位的旋轉或重新定位達成非平面裝置之高 移動率特性。第3圖描述範例非平面裝置3 00 (例如三閘 電晶體)。 於本發明之一實施例中,三閘電晶體3 00係絕緣體上 覆矽(SOI )電晶體。三閘電晶體3 00包含形成於基板 鲁·302上之薄半導體本體3 08 ;基板302可爲絕緣基板(如 包含氧化薄膜之基板302)或半導體基板。半導體本體 30 8包含閘極電介質305,形成於半導體本體308之上表 面以及側壁’以及閘極電極3 0 7形成於在半導體本體3 0 8 上表面上之閘極電介質3 05以及在半導體本體3 08側壁上 形成之閘極電介質3 0 5旁。源極以及汲極區域3 3 0以及 3 3 2分別形成於閘極電極3 0 7相對側上之半導體本體3 0 8 中。由於閘極電極3 0 7以及閘極電介質3 0 5圍繞半導體本 體3 08三側,電晶體3 00主要具有三個個別之通道以及閘 (4) J287263 極。電晶體之閘極寬度等於半導體本體三側每一個之總合
由於有三個個別之通道形成於半導體本體中,當電晶 體被「啓通」時,可完全空乏半導體本體,藉此得以形成 閘極長度小於30奈米之完全空乏電晶體而無需超薄半導 體本體或尺寸小於裝置閘極長度(Lg)的半導體本體之光 微影圖案化。由於本發明之三閘電晶體可以完全空乏方式 操作,裝置之特徵在於理想的次臨界坡度(例如非常陡) 以及小於l〇〇mV//v或理想地60mV/v之減少的汲極引發能 障降低(DIBL; drain induced barrier lowering)短通道效 應,這導致當裝置「關斷」時有較低之漏電流,造成較低 耗電量。 希望諸如三閘電晶體3 00之非平面裝置能成爲高移動 率裝置以增進裝置性能。於本發明實施例中,爲了增進非 平面裝置3 00之移動率,改變半導體本體308之晶面結構 。如第3圖所示,非平面裝置3 00在具有<1〇〇>晶面之半 導體本體308的上表面上具有垂直場。半導體本體308之 側面的垂直場具有<1 1〇>晶面。已證實以移動率而言<100> 以及< 1 1 〇 >晶面之間有顯著的不同。如第4圖所示< 1 1 0 >晶 面具有<1〇〇>晶面移動率約一半的値。如第 4圖所示, <1〇〇>晶面之局木(Takagi)線顯著第局於<110>晶面的局 木線。增進非平面裝置之移動率的一種方法是使半導體本 體3 08之所有側的垂直場具有<1〇〇>晶面。 基板3 02最常由半導體晶圓製成,接著將之處理形成 (5) .1287263 薄膜與結構於其中,以形成半導體裝置如三閘裝置3 00。 於一範例中,基板3 02爲矽塊晶圓。一絕緣層(如二氧化 矽薄膜)形成於基板3 02上,以及裝置品質半導體薄膜( 如單晶矽)形成於絕緣層上。裝置3 00接著形成於裝置品 質半導體薄膜中。於半導體製造領域中於用於形成裝置之 晶圓或諸晶圓上產生參考方位是一種慣例。參考方位通常 爲產生於晶圓中之小凹槽。參考方位有助於設備(如蝕刻 ·>_工具或微影工具)對齊目的並且特別助於製造重複性(例 如諸如微影與蝕刻之裝置處理)。處理工具因此具有對齊 點,其中特定晶圓上的每一個點皆對齊以進行處理。如所 知,矽或其他半導體材料在晶圓不同平面具有不同晶體立 方體方位。因此,針對晶體方位之重複性,產生參考方位 以標記出晶圓一致的方向。參考方位亦提供晶圓到晶圓之 處理的重複性。
於晶圓中產生參考方位的一種方法係在晶圓上特定位 置製造出凹槽。目前,例如矽錠的錠係在<1〇〇>晶面方向 中以種子生長。如第5圖所述,錠502係生長於<1〇〇>晶 面方向中。接著將錠5 02設置於X光衍射工具,以允許找 到<1 10〉晶面方向。在X光衍射過程中,將錠502放射狀 旋轉使得X光衍射光束可顯現並定位< 1 1 0 >位置。一旦找 著<1 1〇>位置,沿著線5 04標記錠5 02使凹槽506可如第 6圖顯示形成凹槽5 0 6。可用輾磨製造線5 0 4。接著使用切 割來切割錠5 02來製造複數個晶圓5 0 8 °如第6圖所示, 晶圓508具有指向頁面外之方向的<100>晶面。凹槽506 (7) •1287263 當非平面裝置所有側面具有<100>晶面時,非平面裝 置將具有高移動率特性,這對高性能裝置而言係希望預見 者。 第9圖描述範例諸如三閘裝置(如三閘電晶體900 ) 之非平面裝置,可藉由使晶圓的凹槽重新定位或旋轉而得 到高移動率特性之優勢。非平面裝置因此爲高移動率非平 面裝置,其可爲高移動率三閘電晶體。
三閘電晶體900係形成於基板902上。於本發明之一 實施例中,基板902爲絕緣基板,包含其上形成諸如二氧 化矽層之絕緣層906之較低單晶矽基板904。惟,三閘電 晶體900可形成於任何已知的絕緣基板,諸如形成自二氧 化矽、氮化物、氧化物以及藍寶石之基板。於本發明一實 施例中,基板9 0 2可爲半導體基板,諸如但不限於單晶矽 基板以及砷化鎵基板。 三閘電晶體900包含半導體本體908形成於絕緣基板 鲁φ 902之絕緣層906上。半導體本體908可形成自半導體薄 膜。當半導體薄膜於絕緣基板9 0 2上時,三閘電晶體9 0 0 可被視爲絕緣層上覆砂(SOI)電晶體。半導體本體908 可以任何已知半導體材料形成,諸如但不限於砂(si )、 鍺(Ge )、矽鍺(SixGey )、砷化鎵(GaAs ) 、inSb、
GaP、GaSb以及奈米碳管。當期望電晶體9〇〇能有最佳電 性能力,例如於微處理器中,則半導體本體9〇8理想地爲 單晶體薄膜。惟,當電晶體900使用於較不嚴苛性能要求 的應用中,例如於液晶顯示器中,半導體本體9〇8可爲多 -11 - J287263 . (8) 晶矽薄膜。處理用於形成半導體本體90 8之晶圓,使半導 體本體90 8所有側面如前述具有<1 10>晶面。 於一實施例中,用於形成半導體本體908之半導體材 料係一晶圓(例如矽晶圓),受到處理或形成有定位在晶 圓上<10 0>晶面位置之參考凹槽。於另一實施例中,用於 形成半導體本體90 8之半導體材料係一晶圓(例如矽晶圓 ),受到處理或形成有定位在晶圓上< 1 1 〇>晶面位置之參 φ 考凹槽。於此另一實施例中,將用於形成半導體本體908 之晶圓旋轉,使參考凹槽偏移45度或-45度。 半導體本體908具有由一距離分隔之橫向相對的一對 側壁9 1 0以及9 1 2,其定義半導體本體寬度9 1 4。此外, 半導體本體908具有相對於形成於基板.902上之下表面 9 1 8的上表面9 1 6。上表面9 1 6以及下表面9 1 8之間的距 離定義本體高度920或半導體本體908之厚度Tsi。於本 發明之一實施例中,本體高度92 0實質上等於本體寬度 ®φ914。於本發明之一實施例中,本體908具有小於30奈米 以及理想地小於20奈米之寬度914以及高度920。於本發 明之一實施例中,本體高度920介於本體寬度914之1/2 至本體寬度9 1 4之2倍。側壁9 1 0以及9 1 2、上表面9 1 6 以及下表面918皆具有擁有<1〇〇>晶面結構之垂直場。 三閘電晶體900具有閘極電介質層922。如第9圖所 示閘極電介質層922形成於半導體本體90 8之上並環繞其 三側。如第9圖所示閘極電介質層922形成於本體90 8之 側壁9 1 2之上或旁邊、上表面9 1 6之上以及側壁9 1 0之上 -12- .1287263 " (9) 或旁邊。閘極電介質層922可爲熟知的閘極電介質層。於 本發明之一實施例中,閘極電介質層爲二氧化矽(S i 〇2 ) 、氧氮化矽(SiOxNy )或氮化矽(Si3N4 )電介質層。於本 發明一實施例中,閘極電介質層922爲形成有厚度介於5-2 0 A之氧氮化砂薄膜。於本發明之一實施例中,閘極電介 質層922爲高K閘極電介質層,諸如金屬氧化電介質,例 如但不限於五氧化鉬(Ta205 )以及氧化鈦(Ti02 )。閘 極電介質層922可爲其他類型之高K電介質,例如但不限 於PZT (鉻鈦酸鉛)。 三閘裝置9 0 0具有閘極電極9 2 4。如第9圖所示閘極 電極924形成於形成在半導體本體908側壁912上之閘極 電介質層92 2之上或旁邊、形成於形成在半導體本體908
上表面916上之閘極電介質層922之上以及形成於形成在 半導體本體908側壁910上之閘極電介質層922之上或旁 邊。閘極電極924具有以一距離分隔之一對橫向相對側壁 926以及928,定義電晶體900之閘極長度930(Lg)。 於本發明之一實施例中,閘極電極924之橫向相對側壁 926以及928以垂直於半導體本體908橫向相對側壁910 以及9 1 2之方向配置。 閘極電極924可以任何適當的閘極電極材料形成。於 本發明一實施例中,閘極電極924包含摻雜濃度密度介於 1x1 〇19原子/立方公分- lxl 〇2G原子/立方公分之多晶矽。於 本發明一實施例中,閘極電極形成自金屬閘極電極,例如 但不限於鎢、鉅以及其氮化物。於本發明一實施例中,閘 -13- (10) 1287263 極電極形成自具有中能隙功函數(mid-gap work function )介於4.6-4.8eV之材料。應能了解到閘極電極924不需 爲單一材料而可爲複合之薄膜堆疊,如但不限於多晶矽/ 金屬電極或金屬/多晶矽電極。 三閘電晶體900具有源極區域93 0以及汲極區域932 。如第9圖所示,源極區域93 0以及汲極區域93 2形成於 閘極電極924之相對策。源極區域93 0以及汲極區域932 •I係由諸如N型或P型導電性之相同導電類型形成。於本發 明一實施例中,源極區域93 0以及汲極區域932具有介於 lxl 019以及1x1 〇21原子/立方公分之間的摻雜濃度。源極 區域93 0以及汲極區域93 2可由一致的濃度或包含不同濃 度或摻雜曲線之次區域如頂端區域(如源極/汲極延伸) 所形成。於本發明一實施例中,當電晶體爲對稱電晶體時 ,源極區域93 0以及汲極區域93 2將具有相同摻雜濃度或 曲線。於本發明一實施例中,當電晶體係由不對稱電晶體 ® φ形成時,則源極區域93 0以及汲極區域93 2之摻雜濃度或 曲線可能會爲了達成特定電性特性而有所變化。 位於源極區域93 0以及汲極區域932之間的半導體本 體908部分定義電晶體900之通道區域95 0。通道區域 950亦可定義成圍繞閘極電極924之半導體本體之區域。 但有時源極/汲極區域會經由擴散稍微延伸至閘極電極之 下而定義稍微小一點的閘極電極長度(Lg )。於本發明一 實施例中,通道區域95 0爲固有或無摻雜之單晶矽。於本 發明一實施例中,通道區域9 5 0爲摻雜的單晶矽。當摻雜 -14- (11) •1287263 通道區域9 5 0時,通常係以介於1x1 ο16至1x1 019原子/立 方公分之導電程度摻雜。於本發明一實施例中,當摻雜通 道區域95 0時,通常係與源極區域93 0以及汲極區域932 導電類型相反摻雜。例如,當源極區域9 3 0以及汲極區域 93 2爲N型導電性時,通道區域950會摻雜成P型導電性 。相同地,當源極區域930以及汲極區域932爲P型導電
性時,通道區域950會爲N型導電性。依此方式,三閘電 晶體900可分別形成NMOS電晶體或PMOS電晶體。可一 致地或不一致或以不同濃度地摻雜通道區域95 0以達成特 定電性特性以及性能特性。例如,若有需要,通道區域 9 5 0可包含熟知的「暈圈」區域。 藉由提供圍繞半導體本體908三側面之閘極電介質以 及閘極電極,三閘電晶體900之特徵在於具有三個通道以 及三個閘極,一個(g 1 )延伸於源極以及汲極區域之間矽 本體908側面912上,第二個(g2 )延伸於源極以及汲極 區域之間矽本體908上表面916上以及第三個(g3 )延伸 於源極以及汲極區域之間矽本體908側面910上。由於半 導體本體9 0 8如則述之構造’鬧極g 1、g 2以及g 3的每一 個皆具有<1〇〇>之晶面結構。因此可藉由三個<100>晶面閘 極增進移動率,使電晶體900成爲高移動率非平面裝置。 電晶體9 00之閘極「寬度」(Gw )爲三個通道區域之寬 度總合。因此,電晶體閘極寬度等於在側壁9 1 0矽本體 908之高度920,加上在上表面916矽本體908之寬度, 加上在側壁912矽本體908之高度920。藉由使用複數個 -15- •1287263 、 (12) 裝置耦合在一起可獲得較大的「寬度」。
由於通道區域95 0係藉由閘極電極924以及閘極電介 質922環繞在半導體本體90 8之三側上。電晶體900可以 完全空乏之方式操作。當電晶體900「啓通」時,通道區 域95 0完全空乏,藉此提供完全空乏電晶體之有益的電性 特性以及性能。此外,當電晶體900「啓通」時,形成完 全空乏區域,並且通道區域950與形成於通道區域950表 面之反轉層係形成於半導體本體908之上表面以及側表面 上。反轉層與源極以及汲極區域具有相同的導電性類型並 且形成導電通道於源極以及汲極區域之間,以允許電流於 其間流動。三閘電晶體900爲非平面電晶體,因爲通道區 域係同時形成於半導體本體9 08中之水平以及垂直方向。 空乏區域從反轉層之下空乏自由載子。空乏區域延伸至通 道區域95 0下方,因此電晶體可稱爲「完全空乏」電晶體 。完全空乏電晶體比非完全空乏或部分空乏電晶體具有更 • φ佳之電性能力。例如,藉由以完全空乏方式操作電晶體 900,電晶體900具有理想或非常陡的次臨界坡度。即使 半導體本體厚度小於 30nm,仍可製造出具有小於 80mV/decade以及理想地約60mV/decade之非常陡的次臨 界坡度之三閘電晶體。此外,隨著完全空乏之電晶體900 ,電晶體900具有實際上爲低之增進的汲極引致能障( DIB L ),其提供更佳「關斷」狀態之漏電量,導致更低的 漏電量以及從而更低的耗電量。於本發明一實施例中,三 閘電晶體900具有小於1 00mV/V以及理想地小於40mV/V -16- J287263 ^ (13) 之DIBL效應。 由於電晶體900具有因<1〇〇>晶面而有高移動率特性 之閘極’電晶體900之電性特性比僅具有上表面擁有 <1〇〇>晶面的裝置更佳。 第1 0圖描述根據本發明實施例用於諸如三閘極電晶 體900之非平面裝置之基板的範例製造方法。於一實施例 中,首先提供基板1 002。基板1 002可爲半導體基板,如 但不限於矽塊基板、單晶矽基板、較低單晶矽基板、多晶 係基板或砷化鎵基板或其他適當的半導體材料。於一實施 例中,基板1 002包含絕緣層1 004如二氧化矽薄膜、氮化 矽薄膜或其他適當電介質薄膜。絕緣層1 004可具有介於 200-2000埃之間的厚度。 將半導體裝置基板1 006結合至基板1 002。於基板 1 0 02包含絕緣層1 004之實施例中,在絕緣層1〇〇4處將半 導體裝置基板1〇〇6結合至基板1 002。半導體裝置基板 • φ 1 006爲製造半導體本體或三閘電晶體本體之基板。於一實 施例中,半導體裝置基板1〇〇6爲高品質矽。於其他實施 例中,半導體裝置基板1 006可爲其他種類的半導體薄膜 ,如但不限於鍺(G〇 、矽化鍺(SiGe )、砷化鎵( GaAs )、締化銦’(InSb )、磷化鎵(GaP )、締化鎵( GaSb )以及奈米碳管。 於本發明一實施例中,半導體裝置基板1 006爲固有 (無摻雜)矽薄膜。於其他實施例中,半導體裝置基板 1 006係以具有介於ΐχΐ〇16至ΐχΐ〇19原子/立方公分之間的 -17- (14) •1287263
濃度程度摻雜成p型或η型導電性。半導體裝置基板1006 可被原位摻雜(如於其沉積的同時摻雜)或在其形成於基 板1 002上之後藉由例如離子佈値摻雜。形成後摻雜允許 能夠輕易地製造NMOS或PMOS三閘裝置兩者於相同絕緣 基板上。於此處之半導體本體之摻雜程度決定非平面裝置 之通道區域之摻雜程度。於一實施例中,半導體裝置基板 1 006包含絕緣層1 008,其可爲二氧化矽薄膜或氮化矽薄 膜或其他適當電介質薄膜。絕緣層1 008可具有介於約200 至約2000埃之間的厚度。 半導體裝置基板具有厚度大約等於後續形成之 半導體本體或製造的三閘電晶體本體之希望的高度。於本 發明一實施例中,半導體裝置基板1〇〇6具有厚度或高度 1 0 1 6小於3 0奈米以及理想地小於2 0奈米。於本發明一實 施例中,半導體裝置基板1 006具有厚度1016約略等於製 造的三閘電晶體希望的閘極「長度」。於本發明一實施例 中,半導體裝置基板1〇〇6具有厚度1016大於欲形成的三 閘電晶體希望的閘極長度。於本發明一實施例中,半導體 裝置基板1 006具有厚度能使製造的三閘電晶體於其希望 的閘極長度(Lg )以完全空乏方式操作。將半導體裝置基 板1006結合至或形成於基板1 002上之後,形成SOI基板 。三閘裝置之半導體本體係形成於半導體裝置基板1006 中。半導體裝置基板結合至基板1 002,得使形成於 半導體裝置基板1006中之三閘裝置的每一側皆具有<1〇〇> 晶面。 -18- J287263 • (15) 半導體裝置基板1 006可以任何熟知方法形成於(結 合至)絕緣基板1 002。於一範例方法中,基板1 002具有 定位在<11〇>晶面位置之凹槽1010。基板1 002可如前述 般自具有參考凹槽產生於<1 1〇>位置之錠切割而來之晶圓 。於一實施例中,半導體裝置基板1 006包含凹槽1012, 亦定位於<11 〇>晶面位置。與基板1 002類似,半導體裝置 基板1 006亦可自具有參考凹槽產生於<1 1〇>位置之錠切割 而來之晶圓。半導體裝置基板1 006可比基板1 002品質更 高。於一實施例中,基板1 002包含絕緣層1 004以及半導 體裝置基板1 006包含絕緣層1 008。使用諸如智慧切割( SMARTCUT)以及已結合並回蝕刻絕緣體上覆矽(BESOI; Bonded and Etch B ack S 01 )之方法或其他結合方法將半 導體裝置基板1 006與基板1 002在絕緣層處結合在一起。 結合在一起之前,旋轉半導體裝置基板1 006,使凹槽 1012相對於凹槽1010偏移45度或-45度。從而改變半導 ® φ體裝置基板1〇〇6之晶面結構。 於SMARTCUT方法中(第11圖),可將半導體裝置 基板1 006氧化,以產生絕緣層1 008。亦可將基板1 002氧 化以產生絕緣層1 〇〇4。接著使用離子佈植將離子植入半導 體裝置基板1 006中特定深度以於半導體裝置基板1 006中 產生深入的微弱層。接著將半導體裝置基板1 006以及基 板1 002清洗並在絕緣層1 004以及1 008處結合。結合前 ,基板1 002以及半導體裝置基板1 006相互偏移約45度 (或-45度)。於一實施例中,基板1002與1006係重疊 -19- (16) •1287263
對齊使得基板1 002之凹槽1010以及半導體裝置基板1006 之凹槽1012相互偏移45度。詳言之,當基板1 006結合 至基板1 002時具有相對於基板1〇〇2凹槽1010旋轉了 45 度或-45度之凹槽1012 (見第10圖)。相對於凹槽1010 凹槽1012之偏移如前述將提供閘極所有側皆擁有<100>晶 面之三閘。接著使用切開方式將在離子佈植之深度的半導 體裝置基板1 006部分切開。半導體裝置基板1 006留下的 部分包含絕緣層1〇〇8係轉移(透過結合)至基板1 002。 可使用退火以及磨光(如化學機械硏磨(CMP ))來完成 SOI基板之形成。具有氧化層1〇〇4以及1008夾於其中之 基板1 002以及半導體裝置基板1〇〇6係稱爲SOI基板。具 有<100>晶面結構於所有側之三閘裝置將形成於半導體裝 置基板1006的表面。 於BES 01方法中(第12圖),可將半導體裝置基板 1 006氧化以產生絕緣層1〇〇8。亦可將基板1 002氧化以產 _馨生絕緣層1〇〇4。接著將半導體裝置基板1 006以及基板 1 0 02清洗並在絕緣層1〇〇4以及1 008處結合。結合前,基 板1 002以及半導體裝置基板1〇〇6相互偏移約45度(或-45度)。於一實施例中’基板1〇〇2與1 006係重疊對齊使 得基板1〇〇2之凹槽1010以及半導體裝置基板1 006之凹 槽1012相互偏移45度。詳言之,當基板1 006結合至基 板1 002時具有相對於基板1〇〇2凹槽1010旋轉了 45度 或-45度之凹槽1012 (見第10圖)。相對於凹槽1010凹 槽1012之偏移如前述將提供閘極所有側皆擁有<1〇〇>晶面 -20- (17) J287263 之三閘。於結合之後,蝕刻並磨光(第11圖)基板1006 以獲得希望之厚度。可使用退火以及磨光(如化學機械硏 磨(CMP ))來完成SOI基板之形成。具有<100>晶面結 構於所有側之三閘裝置將形成於半導體裝置基板1 006的 表面。
於一寳施例中,使用藉氧佈植分隔(SIM0X; Separation by Implantation of Oxygen )之方法形成 SOI 基板。於此實施例中,(第1 3圖),提供基板1 3 00並於 基板1 3 00中執行氧離子深層佈植(通常爲高劑量)形成 SOI基板。將基板1 3 00退火以完成SOI基板之形成。埋 設氧化層1 3 02將形成於基板1 3 00內。於一實施例中,基 板1 3 00爲單晶係基板。三閘裝置將形成於在埋設氧化層 1 3 02之上的矽部分上。因此,在埋設氧化層1 3 02之上的 矽部分主要爲半導體裝置基板1006。於一實施例中,基板 1 3 00係形成自具有參考線產生於<1 1〇>晶面位置之錠,使 得當自該錠切割時,基板1 3 0 0具有產生於< 1 1 〇>晶面位置 之參考凹槽。當置於處理工具上時,相對於處理工具之對 齊點凹槽偏移45度或-45度。因此,並非如傳統般在處理 基板1 3 00中對齊凹槽(如對齊至處理工具上指定給該凹 槽之指定位置),而是將基板1 3 00旋轉使得凹槽於處理 期間偏移。偏移該凹槽將提供如前述具有 <〗00>晶面於閘 極所有側之三閘。於替代實施例中,可自錠〗4 〇 〇產生基 板1 3 00 (第14A圖)’其中參考線定位於<1〇〇>晶面位置 。當錠1400切割成晶圓以產生基板][3〇〇時,在<1〇〇>晶 -21 - •1287263 ^ (18) 面位置產生凹槽1 404。具有<100>凹槽之基板13〇〇可接 著使用如前述SIMOX方法處理。可形成三閘裝置於基板 1 3 00中而無須45度或-45度旋轉基板1 3 00來產生所有側 皆擁有<1〇〇>晶面結構之三閘。 於其他實施例中,除了如第1 1 -1 2圖所示相對於基板 1002旋轉半導體裝置基板1〇〇6或如第13圖所述重新定位 基板1 3 00,可製成非平面裝置之半導體裝置基板以將凹槽 重新定位。甩於形成裝置基板之晶圓的凹槽因而重新定位 至<1〇〇>晶面位置。當需要旋轉裝置基板時,機械旋轉將 支配裝置基板之旋轉的可靠性、準確性以及/或重複性。 例如,當相對於偏移各基板上的凹槽基板1 006以及基板 1 002互相偏移45度或-45度時,偏移之準確度會受到晶 圓結合程序或設備之準確度的影響。因此,基板1 006之 機械相對於基板1 002之旋轉會支配偏移程度(例如數度 )。爲了降低不對齊之可能性,可產生凹槽位在<1〇〇>晶 ® φ面位置(相對於<11 〇>位置)之裝置基板1 006或基板 1 3 00。如第14Α圖所示,用於後續形成裝置基板1 006或 基板1 002之錠1 400可使用X光衍射形成有參考線1402 產生於<1〇〇>晶面位置,其比晶圓結合程序有更準確的機 械旋轉。當切割錠1 400以產生複數個晶圓1 406時,其可 用於形成基板1 006或1 3 00,每個晶圓1 406將具有凹槽 1 406定位在<100>晶面位置。 於第14Β途中,晶圓1 406結合至另一晶圓,基板 1 002,於一實施例中,以產生SOI基板。晶圓1 406可包 -22- 1287263 • (19) 含絕緣層1 408以及基板1 002可包含如前述之絕緣層1004 。如同先前,基板1002包含凹槽1〇1〇如前述產生在 <110>晶面位置。但晶圓1406具有凹槽1404定位在<100> 晶面位置。如第14B圖於處理過程中凹槽1 404以及1010 互相重疊對齊。於處理過程中無須旋轉晶圓1 4 0 6來重新 對齊晶圓1 406之晶體結構。晶圓1 406會具有45度或-45 度之偏移,由於凹槽1 404至<100>晶面位置之重新定位以 重新對齊晶圓1 404中的晶面結構。凹槽1 404至<100>晶 面位置之重新定位允許形成於晶圓1 4 0 6中的非平面裝置 具有高移動率所期望之擁有<1〇〇>晶面平面的所有側。 第15A_15J圖描述根據本發明實施例製造非平面裝置 或裝置1 500 (如三閘電晶體)之範例方法。於第15A圖 中,提供基板1502。該基板1502包含半導體基板1504 ( 如矽塊)以及絕緣薄膜1 5 0 6 (如二氧化矽)。在絕緣薄膜 1 5 0 6之上,形成裝置半導體基板1 5 0 8 (如單晶矽)。基 ® _板1 5 02以及裝置基板1 5 08合倂稱爲前述之SOI基板。裝 置基板1 5 08 ’於一實施例中,具有產生於<1〇〇>晶面位置 之凹槽(未圖示)以及基板1 5 02具有產生於<1 1 〇>晶面位 置之凹槽(未圖示)。如前述互相重疊對齊該些凹槽。於 一替代實施例中,裝置基板1 5 0 8以及基板1 5 0 2兩者皆具 有產生於< 1 1 〇>晶面位置之凹槽。當結合再一起形成S 0 I 基板時,將裝置基板1 5 0 8旋轉4 5度(或-4 5度),以使 諸凹槽如前述般能互相偏移。可在裝置基板1 5 0 8內形成 隔離區域(未圖不)以互相隔離形成於其中的各種電晶體 -23- (20) J287263 。可藉由蝕刻掉環繞三閛電晶體隻裝置基板1 5 082的部分 形成隔離區域,例如藉由熟知的光微影以及蝕刻技術,並 接著以諸如Si02之絕緣薄膜回塡被蝕刻的區域。
接著,如第1 5 B圖所示將光阻遮罩1 5 1 0形成於裝置 基板上。光阻遮罩1510包含圖案或複數個圖案1512,定 義後續將形成裝置1 5 00之半導體本體或鰭1 520之位置。 光阻遮罩1512定義後續形成之半導體本體1 5 20之期望的 寬度1518。於本發明一實施例中,圖案1512定義本體 1 520,其具有寬度1518大於或等於製造的電晶體閘極長 度(Lg)期望之寬度。依此方式,用於製造電晶體之最嚴 苛的光微影限制係與閘極電極圖案化有關而非半導體本體 或鰭之定義。於本發明一實施例中,本體1520會具有小 於或等於3 0奈米且理想地小於或等於2 0奈米之寬度。於 本發明一實施例中,本體1 5 20之圖案15 12具有大約等於 矽本體高度1 5 09之寬度1518。於本發明一實施例中,光 阻圖案1512具有介於半導體本體高度1 5 09之1/2以及半 導體本體高度1 5 09之兩倍之間的寬度1518。 光阻遮罩1510亦可包含圖案1514以及1516,用於定 義將形成源極著陸墊1 522以及汲極著陸墊1 524之位置。 該些著陸墊可用於連接製造的電晶體之各種源極區域在一 起以及連接各種汲極區域在一起。可用熟知的光微影技術 包含遮罩、曝光以及顯影披蓋沉積之光阻薄膜來形成光阻 遮罩1 5 1 0。 接著,如第1 5 C圖所示,與光阻遮罩對齊地蝕刻裝置 -24- .1287263 > (21) 基板1 5 08以形成一或更多矽本體或鰭以及源極與汲極著 陸墊(若有需要)。蝕刻基板1 5 0 8直到暴露出埋設氧化 層1 5 06。熟知的半導體蝕刻技術,如非等向性電漿蝕刻或 反應性離子飩刻可用於蝕刻基板1 5 08。 接著,藉由熟知的技術,諸如化學剝除以及〇2灰化 ,移除光阻遮罩1 5 1 0以產生如第1 5D圖所示中之基板。 接著,閘極電介質層1 526形成於以及圍繞每一個半 ®^導體本體1 520。閘極電介質層1 526形成於每一個半導體 本體1 520上表面1 527以及橫向相對側壁1 52 8以及1529 上。閘極電介質可爲沉積的電介質或生長的電介質。於本 發明一實施例中,閘極電介質層1 52 6係以乾/濕氧化程序 生長之二氧化矽電介質薄膜。於本發明一實施例中,二氧 化矽薄膜係生長有介於5-1 5A之間的厚度。於本發明一實 施例中,閘極電介質薄膜1 526爲沉積的電介質,如但不 限於高電介質常數薄膜,諸如金屬氧化電介質,諸如五氧 ® φ化鉅(Ta205 )以及氧化鈦(Ti02)或其他高K電介質, 如PZT。高電介質常數薄膜可以任何熟知的技術形成,如 化學蒸氣沉積(CVD)。 接著,如第1 5 F圖所示,形成閘極電極1 5 3 0。閘極 電極1 53 0形成於形成在每一個半導體本體1 520上表面 1 527上以及側壁1 528以及1 529旁之閘極電介質層1526 之上。閘極電極1 53 0具有上表面1 5 3 2相對於形成於絕緣 基板1 502上之下表面,並具有一對橫向相對之側壁1534 以及1 5 3 6。相對側壁1 5 3 4以及1 5 3 6之間的距離定義三閘 -25- (22) J287263
電晶體之閘極長度(Lg)。如第15D圖所示可藉由披蓋沉 積適當閘極電極材料於基板上形成閘極電極1 5 3 0。可形成 閘極電極至200-9000A之間的厚度1 5 3 3。於一實施例中 ,閘極電極具有爲半導體本體1 520之高度1 5 09至少三倍 之厚度或高度1 5 3 3。接著以熟知光微影以及蝕刻技術圖案 化閘極電極材料以自閘極電極材料形成閘極電極1 5 3 0。閘 極電極材料可包含多晶砂、多晶砂鍺合金以及金屬,如鎢 、鉅以及其氮化物。於本發明一實施例中,閘極電極1 5 3 0 具有小於或等於30奈米以及理想地小於或等於20奈米之 閘極長度1 5 3 8。 接著,電晶體之源極1 540以及汲極1 524區域形成於 閘極電極1 5 3 0相對側上半導體本體中。於本發明一實施 例中,源極1 540以及汲極1 524區域包含頂端或源極/汲 極延伸區域。可藉由置入摻雜物1 5 44於閘極電極1 5 3 0兩 側壁1 5 3 4以及1 5 3 6上之半導體本體1 5 2 0內形成源極/汲 極區域以及延伸。若使用源極以及汲極著陸墊,亦可在此 時摻雜形成它們。針對PMOS三閘電晶體,半導體鰭或本 體1 5 2 0摻雜成p型導電性並且介於1χ1〇2、1χΐ〇21原子/立 方公分之間的濃度。針對PMOS三閘電晶體,半導體鰭或 本體1 5 20摻雜成η型導電性並且介於ΐχΐ〇2、ιχ102ΐ原子/ 立方公分之間的濃度。於本發明一實施例中,藉由離子佈 植摻雜矽薄膜。於本發明一實施例中,如第1 5 F圖中所示 離子佈植係垂直地發生。當閘極電極1 5 3 0爲多晶矽閘極 電極時,可在離子佈植過程中將之摻雜。閘極電極1 5 3 0 -26- •1287263 * (23) 可作爲遮罩防止離子佈植步驟摻雜三閘電晶體之通道區域 1548。通道區域1548爲位在閘極電極1530之下或周圍之 矽本體1520部分。若閘極電極1530爲金屬電極’可使用 電介質硬式遮罩阻隔在離子佈植期間之摻雜。於其他®施 例中,其他方法,如固體源極擴散可用於摻雜半導體本體 以形成源極以及汲極延伸。 接著,若有需要,可進一步處理第15F圖中所不之基 板以形成額外的特徵,如高摻雜源極/汲極接觸區域、於 源極以及汲極區域與閘極電極上沉積的砂以及於源極/汲 極接觸區域與閘極電極上矽化物之形成。例如,電介質側 壁間隔體1 5 5 0 (第1 5 G圖)可形成於閘極電極1 5 3 0之側 壁上;半導體薄膜1560以及1562(第15Η圖)可形成於 本體1 520暴露的表面上作爲特定應用(如用於形成突起 之源極與汲極區域);可執行額外的摻雜(如形成突起之 源極與汲極區域)(第1 5 J圖);以及耐火金屬矽化物 B φ 1 5 8 0可形成於源極以及汲極區域以及/或閘極電極! 5 3 〇上 (第1 5 J圖)。形成這些構件之技術爲此技藝中習知者。 雖以藉由數個實施例說明本發明,此技藝中具通常知 識者應了解到本發明並不限於所述實施例。本發明之方法 與裝置可以變更與修改實施而不悖離所附申請專利範圍之 精神與範疇。因此本說明應僅視爲例示性而非限制性。 在已揭露範例實施例的情況下,可對揭露的實施例作 出的變更與變化,同時仍在由所附申請專利範圍定義之本 發明精神與範疇內。 -27- (24) .1287263 【圖式簡單說明】 第1圖爲完全空乏基板電晶體剖面圖。 第2A圖與第2B圖描述雙閘極完全空乏基板電晶體。 第3圖爲根據本發明一實施例之三閘電晶體之圖。 第4圖爲<100>以及<110>移動率特性之對照圖。
第5圖爲生長於<100>晶面方向之矽錠並且具有位在 <1 1 〇>晶面之參考方位之圖。 第6圖爲自第5圖之矽錠切割而來之晶圓圖。 第7 A-7B圖爲自第5圖之矽錠切割而來並具有裝置形 成於其上之晶圓圖。 第8A-8B圖描述具有參考凹槽形成在<100>晶面位置 之晶圓。 第9圖爲根據本發明一實施例之三閘電晶體圖。 第1 〇圖爲根據本發明一實施例之形成用於三閘裝置 ® •之高移動率矽基板之方法圖。 第Π · 1 3圖描述根據本發明一實施例之形成用於三閘 裝置之高移動率矽基板之範例方法。 第MA圖描述具有<100>參考凹槽之範例矽錠。 第14B圖描述具有<100>參考凹槽之晶圓至具有 <1 1〇>參考凹槽之晶圓的結合。 第15A-15J圖描述根據本發明一實施例之製造三閘電 晶體之範例方法。 -28- (25) •1287263 【主要元件符號說明】 100 絕緣體上覆矽電晶體 102 基板 1 04 絕緣層 106 矽體 108 閘極電介質層 110 聞極電極
112 源極 114 汲極 200 雙閘極裝置 202 矽體 2 0 4 絕緣基板 206 閘極電介質 2 0 8 閘極電極 2 0 9 絕緣層 3 00 非平面裝置 3 02 基板 3 0 5 閘極電介質 3 07 閘極電極 3 0 8 半導體本體 3 3 0 源極區域 3 3 2 汲極區域 5 02 錠 5 04 線 -29- (26) •1287263
506 凹槽 508 晶圓 5 10 圓形 5 12 箭頭 514 裝置 514-T 頂側 5 1 4-S 側面 802 晶圓 804 凹槽 806 非平面裝置 806-Τ 頂面 806-S 側面 8 10 圓形 900 電晶體 902 絕緣基板 904 較低單晶砂基板 906 絕緣層 908 半導體本體 910 側壁 912 側壁 9 14 寬度 916 上表面 9 18 下表面 920 本體高度 (27) •1287263
922 閘極電介質層 924 閘極電極 926 側壁 928 側壁 930 聞極長度 950 通道區域 1002 基板 1004 絕緣層 1006 基板 1008 絕緣層 1010 凹槽 1016 厚度(高度) 1300 基板 1302 氧化層 1400 錠 1402 線 1404 凹槽 1406 晶圓 1408 絕緣層 1500 裝置 1502 基板 1504 半導體基板 1506 絕緣層 1508 裝置半導體基板 (28) •1287263 1 5 09 高度 1510 光阻遮罩 1512, 1514, 1516 圖案 1518 桌度 1 520 本體 1 5 22 源極著陸墊 1 5 24 汲極著陸墊
1 5 2 6 閘極電介質層 1 5 2 7 上表面 1 5 2 8,1 529 側壁 1 5 3 0 閘極電極 1 5 3 2 上表面 1 5 3 4,1 5 3 6 側壁 1 5 3 3 厚度 1538 閘極長度 1 5 4 0 源極 1542 汲極 1 5 44 摻雜物 1 5 4 8 通道區域 1 5 5 0 電介質側壁間隔體 1 5 60, 1 5 62 半導體薄膜 1 5 8 0 金屬矽化物 -32-
Claims (1)
1287263 (1)
十、申請專利範圍 附件4 : 第94 1 1 8759號專利申請案 中文申請專利範圍替換本 民國96年6月1曰修正 ^一種高移動率半導體組件,包含: φ 第一基板,具有定位在第一基板上<110>晶面位置之 第一參考方位;以及 第二基板,形成在第一基板之上,第二基板具有定位 在第二基板上<1〇〇>晶面位置之第二參考方位, 其中第一參考方位與第二參考方位對齊。 2 ·如申請專利範閨第1項之高移動率半導體組件,進 一步包含: 設置於第一基板與第二基板之間的絕緣層。
3·如申請專利範圍第1項之高移動率半導體組件,其 中第一參考方位以及第二參考方位的每一個包含分別形成 於第一基板以及第二基板之每一個之中的凹槽。 4.如申請專利範圍第1項之高移動率半導體組件,其 中第二基板提供用於形成非平面裝置於其中的表面以及其 中該非平面裝置具有皆擁有<1〇〇>晶面之上表面以及諸側 表面。 5 .如申請專利範圍第1項之高移動率半導體組件’其 中第一基板進一步包含第一絕緣層以及第二基板包含第二 (2) 1287263 ,絕緣層,以及其中第一基板以及第二基板在第一與第二絕 緣層互相結合在一起。 6.如申請專利範圍第1項之高移動率半導體組件,其 中第二基板具有擁有<1〇〇>晶面之上場(field)以及複數 個各擁有<100>晶面之側場。 7·如申請專利範圍第1項之高移動率半導體組件,其 中第一基板係選自於由矽塊、多晶矽、較低單晶矽以及砷 φ 化鎵所組成之群組之材料製成。 8. 如申請專利範圍第1項之高移動率半導體組件,其 中第二基板係選自於由矽、鍺、矽化鍺、砷化鎵、InSb、 GaP、GaSb以及奈米碳管所組成之群組之材料製成。 9. 如申請專利範圍第1項之高移動率半導體組件,進 一步包含形成於第二基板中之非平面裝置,其中該非平面 裝置包含, 半導體本體,具有形成於第一基板上以及第二基板中 # 之上表面以及橫向相對之諸側壁,其中半導體本體之上表 面以及諸橫向相對之側壁各擁有<1〇〇>晶面; 閘極電介質,形成於該半導體本體之上表面上以及諸 橫向相對之側壁上;以及 閘極電極,與形成於該半導體本體之上表面以及諸橫 向相對之側壁上之該閘極電介質相鄰形成。 1 0.如申請專利範圍第9項之高移動率半導體組件, 進一步包含: 一對源極/汲極區域,形成於閘極電極相對側上之矽 -2- 1287263 、 (3) _本體之中。 1 1. 一種高移動率半導體組件,包含: 第一基板,具有定位在第一基板上<11 〇>晶面位置之 第一參考方位;以及 第二基板,形成在第一基板之上,第二基板具有定位 在第二基板上<1 1〇>晶面位置之第二參考方位, 其中第二基板形成於第一基板之上,以及其中第二參 φ 考方位自第一參考方位偏移約45度。 1 2 ·如申請專利範圍第1 1項之高移動率半導體組件, 進一步包含: 設置於第一基板與第二基板之間的絕緣層。 1 3 ·如申請專利範圍第1 1項之高移動率半導體組件, 其中第一參考方位以及第二參考方位的每一個包含分別形 成於第一基板以及第二基板之每一個之中的凹槽。 1 4 ·如申請專利範圍第1 1項之高移動率半導體組件, Φ 其中第一基板進一步包含第一絕緣層以及第二基板包含第 一絕緣層,以及其中第一基板以及第二基板在第一與第二 絕緣層互相結合在一起。 1 5 .如申請專利範圍第丨1項之高移動率半導體組件, 其中第二基板具有擁有<10〇>晶面之上場以及複數個各擁 有<100>晶面之側場。 16·如申請專利範圍第1 1項之高移動率半導體組件, 其中第一基板係選自於由矽塊、多晶矽、低單晶矽以及砷 化鎵所組成之群組之材料製成。 -3 - (4) (4)
1287263 1 7 ·如申請專利範圍第1 1項之高移動率半導體組件, 其中第二基板係選自於由矽、鍺、矽化鍺、砷化鎵、InSb 、GaP、GaSb以及奈米碳管所組成之群組之材料製成。 18·如申請專利範圍第1 1項之高移動率半導體組件, 進一步包含形成於第二基板中之非平面裝置,其中該非平 面裝置包含, 半導體本體,具有形成於第一基板上以及第二基板中 之上表面以及橫向相對之諸側壁,其中半導體本體之上表 面以及諸橫向相對之側壁各擁有<1〇〇>晶面; 閘極電介質,形成於該半導體本體之上表面上以及諸 橫向相對之側壁上;以及 閘極電極,與形成於該半導體本體之上表面以及諸橫 向相對之側壁上之該閘極電介質相鄰形成。 19·如申請專利範圍第18項之高移動率半導體組件, 進一步包含: 一對源極/汲極區域,形成於閘極電極相對側上之矽 本體之中。 2 0.—種製造高移動率半導體組件之方法,包含·· 設置第一基板,其具有定位在第一基板上<11 〇>晶面 位置之第一參考方位;以及 形成第二基板於第一基板之上,第二基板具有定位在 第二基板上<1〇〇>晶面位置之第二參考方位, 其中該形成包含將第一參考方位與第二參考方位對齊 - 4- (5) 1287263 2 1 .如申請專利範圍第20項之製造高移動率半導體組 件之方法’其中第一基板以及第二基板之每一個包含絕緣 層以及其中第二基板以及第一基板係在絕緣層互相結合在 一起。 22.如申請專利範圍第20項之製造高移動率半導體組 件之方法,包含: 形成非平面裝置於第二基板中,其中該非平面裝置具 φ 有皆擁有<1〇〇>晶面之上表面以及諸側表面。 23·如申請專利範圍第20項之製造高移動率半導體組 件之方法,進一步包含: 形成三閘電晶體於第二基板中,其中該三閘電晶體包 含, 半導體本體,具有上表面以及橫向相對之諸側壁,其 中半導體本體之該上表面以及該橫向相對之諸側壁各擁有 <100>晶面;
閘極電介質,形成於該半導體本體之上表面上以及諸 橫向相對之側壁上;以及 閘極電極,與形成於該半導體本體之上表面以及諸橫 向相對之側壁上之該閘極電介質相鄰形成。 24·如申請專利範圍第20項之製造高移動率半導體組 件之方法,其中於第一基板上形成第二基板係包含使用智 慧切割(SMARTCUT)方法以及已結合並回蝕刻(Bonded and Etch Back)方法之任一種將第二基板轉移至第一基板 (6) 1287263 。 25·如申請專利範圍第20項之製造高移動率半導體組 件之方法,其中於第一基板上形成第二基板係進一步包含 設置用於形成第二基板之第三基板,該第三基板具有 定位於第三基板上<100>晶面位置之第三參考方位; 佈植離子至第三基板中預定深度; 將第三基板與第一基板結合,其中第三參考方位實質 φ 上與第一參考方位對齊;以及 切開第三基板以轉移第三基板之一部分至第一基板, 其中第三基板之該轉移的部分形成第二基板。 26·如申請專利範圍第20項之製造高移動率半導體組 件之方法,其中於第一基板上形成第二基板係進一步包含 設置具有絕緣層之第三基板,該第三基板係用於形成 第二基板,該第三基板具有定位於第三基板上<100>晶面 •位置之第三參考方位; 佈植離子至第三基板中預定深度; 將第三基板與第一基板結合,其中第三參考方位實質 上與第一參考方位對齊,其中第一基板進一步包含絕緣層 以及其中第三基板係在絕緣層與第一基板結合;以及 切開第三基板以轉移第三基板之一部分至第一基板, 其中第三基板之該轉移的部分形成第二基板。 27·如申請專利範圍第20項之製造高移動率半導體組 件之方法,其中於第一基板上形成第二基板係進一步包含 -6- (7) 1287263 設置用於形成第二基板之第三基板,該第三基板具有 定位於第三基板上<100>晶面位置之第三參考方位; 將第三基板與第一基板結合,其中第三參考方位實質 上與第一參考方位對齊;以及 蝕刻第三基板至預定深度,留下第三基板之一部分於 第一基板之上,其中第三基板之該部分形成第二基板。
28·如申請專利範圍第20項之製造高移動率半導體組 件之方法,其中於第一基板上形成第二基板係進一步包含 設置具有絕緣層之第三基板,該第三基板係用於形成 第二基板,該第三基板具有定位於第三基板上<1〇〇>晶面 位置之第三參考方位; 將第三基板與第一基板結合,其中第三參考方位實質 上與第一參考方位對齊,其中第一基板進一步包含絕緣層 Φ 以及其中第三基板係在絕緣層與第一基板結合;以及 蝕刻第三基板至預定深度,留下第三基板之一部分於 第一基板之上,其中第三基板之該部分形成第二基板。 29· —種製造高移動率半導體組件之方法,包含: 設置第一基板,其具有定位在第一基板上<11 0>晶面 位置之第一參考方位;以及 形成第二基板於第一基板之上,第二基板具有定位在 第二基板上<1 10>晶面位置之第二參考方位, 其中該形成包含將第二基板形成於第一基板之上,以 (8) 1287263 及其中第二參考方位自第一參考方位偏移約45度。 30·如申請專利範圍第29項之製造高移動率半導體組 件之方法’其中第一基板以及第二基板之每一個包含絕緣 層以及其中第二基板以及第一基板係在絕緣層互相結合在 一起0 31·如申請專利範圍第29項之製造高移動率半導體組 件之方法,包含:
形成非平面裝置於第二基板中,其中該非平面裝置具 有皆擁有<100>晶面之上表面以及諸側表面。 32·如申請專利範圍第29項之製造高移動率半導體組 件之方法,進一步包含: 形成三閘電晶體於第二基板中,其中該三閘電晶體包 含 半導體本體,具有上表面以及橫向相對之諸側壁,其 中半導體本體之該上表面以及該橫向相對之諸側壁各擁有 Φ <1〇〇>晶面; 閘極電介質,形成於該半導體本體之上表面上以及諸 橫向相對之側壁上;以及 閘極電極,與形成於該半導體本體之上表面以及諸橫 向相對之側壁上之該閘極電介質相鄰形成。 33·如申請專利範圍第29項之製造高移動率半導體組 件之方法,其中於第一基板上形成第二基板係包含使用智 慧切割(SMARTCUT)方法以及已結合並回蝕刻(Bonded and Etch Back)方法之任一種將第二基板轉移至第一基板 -8- (9) 1287263 34.如申請專利範圍第29項之製造高移動率半導體組 件之方法,其中於第一基板上形成第二基板係進一步包含 設置用於形成第二基板之第三基板,該第三基板具有 定位於第三基板上<11 〇>晶面位置之第三參考方位; 佈植離子至第三基板中預定深度;
將第三基板與第一基板結合,其中第三參考方位相對 於第一參考方位實質上偏移約45度;以及 切開第三基板以轉移第三基板之一部分至第一基板, 其中第三基板之該轉移的部分形成第二基板。 35.如申請專利範圍第29項之製造高移動率半導體組 件之方法,其中於第一基板上形成第二基板係進一步包含 設置具有絕緣層之第三基板,該第三基板係用於形成 φ 第二基板,該第三基板具有定位於第三基板上<11 0>晶面 位置之第三參考方位; 佈植離子至第三基板中預定深度; 將第三基板與第一基板結合,其中第三參考方位相對 於第一參考方位實質上偏移約45度,其中第一基板進一 步包含絕緣層以及其中第三基板係在絕緣層與第一基板結 合;以及 切開第三基板以轉移第三基板之一部分至第一基板, 其中第三基板之該轉移的部分形成第二基板。 -9- (10) 1287263 36.如申請專利範圍第29項之製造高移動率半導體組 件之方法,其中於第一基板上形成第二基板係進一步包含 設置用於形成第二基板之第三基板,該第三基板具有 定位於第三基板上<11 〇>晶面位置之第三參考方位; 將第三基板與第一基板結合,其中第三參考方位相對 於第一參考方位實質上偏移約45度;以及
蝕刻第三基板至預定深度,留下第三基板之一部分於 第一基板之上,其中第三基板之該部分形成第二基板。 37.如申請專利範圍第29項之製造高移動率半導體組 件之方法,其中於第一基板上形成第二基板係進一步包含 設置具有絕緣層之第三基板,該第三基板係用於形成 第二基板,該第三基板具有定位於第三基板上<11 〇>晶面 位置之第三參考方位; 將第三基板與第一基板結合,其中第三參考方位相對 於第一參考方位實質上偏移約45度,其中第一基板進一 步包含絕緣層以及其中第三基板係在絕緣層與第一基板結 合;以及 蝕刻第三基板至預定深度,留下第三基板之一部分於 第一基板之上,其中第三基板之該部分形成第二基板。 38. —種製造高移動率半導體組件之方法,包含: 設置一基板,其具有定位於基板上<100>晶面位置之 參考方位; -10- (11) 1287263 形成埋設氧化區域於基板中;以及 形成非平面裝置於基板之埋設氧化物上的一部分中, 其中該非平面裝置具有皆擁有<100>晶面之上表面以及諸 側表面。 3 9 ·如申請專利範圍第3 8項之製造高移動率半導體組 件之方法,其中該非平面裝置之形成進一步包含:
形成三閘電晶體於基板之埋設氧化物上之該部分中, 其中該三閘電晶體包含具有上表面以及橫向枏對諸側壁之 半導體本體,其中半導體本體之該上表面以及該橫向相對 之諸側壁各擁有<100>晶面,形成於該半導體本體之上表 面上以及橫向相對之諸側壁上之閘極電介質,以及與形成 於該半導體本體之上表面以及諸橫向相對之側壁上之該閘 極電介質相鄰形成之閘極電極。 40.如申請專利範圍第39項之製造高移動率半導體組 件之方法,進一步包含: 形成源極以及汲極區域於閘極電極相對側上。 41·如申請專利範圍第38項之製造高移動率半導體組 件之方法,其中於基板中形成埋設氧化區域係使用藉氧佈 値分隔(SIMOX )方法來實行。 42·如申請專利範圍第38項之製造高移動率半導體組 件之方法,其中於基板中形成埋設氧化區域係進一步包含 將氧植入基板內並將基板退火。 43.如申請專利範圍第38項之製造高移動率半導體組 件之方法,其中於基板中形成埋設氧化區域係進一步包含 -11 - (12) Γ287263 ,將氧植入基板內並將基板退火以及其中該基板具有定位於 <1〇〇>晶面位置之參考方位。 44·如申請專利範圍第38項之製造高移動率半導體組 件之方法,其中於基板中形成埋設氧化區域係進一步包含 將氧植入基板內並將基板退火以及其中該基板具有定位於 晶面位置之參考方位,以及其中將該基板旋轉約45 度0
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2004
- 2004-06-30 US US10/883,183 patent/US7042009B2/en not_active Expired - Fee Related
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- 2005-06-08 WO PCT/US2005/020339 patent/WO2006007350A1/en active Application Filing
- 2005-06-08 DE DE112005001488.6T patent/DE112005001488B4/de not_active Expired - Fee Related
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9067393B2 (en) | 2012-10-29 | 2015-06-30 | Industrial Technology Research Institute | Method of transferring carbon conductive film |
Also Published As
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WO2006007350A1 (en) | 2006-01-19 |
US20060001109A1 (en) | 2006-01-05 |
KR20070022819A (ko) | 2007-02-27 |
US8084818B2 (en) | 2011-12-27 |
CN1977387B (zh) | 2010-09-01 |
DE112005001488B4 (de) | 2014-04-24 |
DE112005001488T5 (de) | 2007-05-24 |
US20100065888A1 (en) | 2010-03-18 |
TW200625465A (en) | 2006-07-16 |
KR100874960B1 (ko) | 2008-12-19 |
US7042009B2 (en) | 2006-05-09 |
CN1977387A (zh) | 2007-06-06 |
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