543150 A7 B7 五、發明説明（） 發明領域： (請先閲讀背面之注意事項再填寫本頁) 本發明係有關於一種黏合式晶圓（b ο n d e d w a f e r)之結 構，特別是有關於一種元件層的通道（channel)沿著<1 〇〇> 晶格方向且底材的晶格方向則與元件層的晶格方向成45 度角之黏合式晶圓之結構。 發明背景： 絕緣體上石夕薄膜（silicon〇ninsulator; SOI)是一種與互 補金乳半導體（complementary metal oxide semiconductor ; CMOS)的隔離（isolation)有關的技術。SOI的原理是在底材 石夕的表面不遠處增加一層例如為二氧化矽（S i 〇 2)之絕緣 體。此絕緣體可用來隔開用以製作CMOS元件的底材矽之 表面與矽主體。由於建築CMOS的區域並不與底材相連， 因此CMOS電晶體發生閉鎖（latch up)的某些途徑，例如源 極與底材間或井與底材間的連接.，將因為中間這層絕緣層 的隔離而消失，於是使閉鎖現象不復存在。 經濟部智慧財產局員工消費合作社印製 氧植入隔離（separation by implanted oxygen; SIMOX) 為可達成上述SOI之其中一種製程。此製程之目的主要係 利用氧離子對晶圓進行深植入，以便在晶圓的表面石夕與主 材質（bulk)之間製作一層用來做為隔離之用的二氧化矽之 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 經濟部智慧財產局員工消費合作社印製 543150 A7 B7 五、發明説明（) 絕緣層。此製程主要分成兩個步驟。首先，將氧離子植入 加熱至溫度高達約6 0 0 °C之晶圓上。然後，將晶片置於溫度 尚達約1 3 0 0 °C以上的環境下數小時，藉以使經離子植入而 遭破壞的晶片表面之矽結構恢復成低缺陷濃度之單晶石夕。 此時由於在矽底材的表面有一層單晶矽覆蓋在二氧化石夕層 的上方，因此半導體界才會以絕緣體上矽薄膜（siHc〇n 〇n insulator; SOI)來統稱這種表面上具有單晶矽與二氧化石夕層 的晶圓及其製程。 另一種在半導體界所使用的SOI技術則是黏合式晶圓 (bonded wafer)。所謂黏合式晶圓係指使用氧化層薄膜將兩 片晶圓黏合在一起以形成S 01。首先，將此兩片晶圓拋光。 接著，形成氧化層薄膜於兩片晶圓中的至少其中一片之拋 光面上。然後，將此兩片晶圓緊密接觸並使氧化層薄膜介 於此兩片晶圓間。通常，為了加強此兩片晶圓透過氧化層 薄膜的黏合強度，必須進一步施以溫度例如為約8 0 0 °C至約 1400°C之熱處理。 上述黏合式晶圓之兩片晶圓通常都取用晶格方向為 < 1 1 0>之晶圓。所謂晶格方向為< 1 1 〇>之晶圓指晶圓上的凹 槽（notch)對齊<1 10〉之晶格方向。將此兩片晶格方向為 < 1 10>之晶圓如前述步驟黏合後，再於後續製程形成例如 CMOS等元件於其中一片晶圓上，則可形成如第1圖中所 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) (請先閲讀背面之注意事項再填寫本頁)543150 A7 B7 V. Description of the invention () Field of invention: (Please read the notes on the back before filling out this page) The present invention relates to the structure of a bonded wafer (b ο ndedwafer), especially to a component layer The structure of the bonded wafer is a channel having a channel along the < 1〇〇 > lattice direction and a lattice direction of the substrate at an angle of 45 degrees to the lattice direction of the element layer. BACKGROUND OF THE INVENTION: Silicon on insulator (SOI) film is a technology related to isolation of complementary metal oxide semiconductor (CMOS). The principle of SOI is to add a layer of insulator, such as silicon dioxide (Si02), not far from the surface of the substrate Shi Xi. This insulator can be used to separate the surface of the silicon substrate used to make the CMOS device from the silicon body. Because the area of the building CMOS is not connected to the substrate, some ways of latch up of the CMOS transistor, such as the connection between the source and the substrate or between the well and the substrate, will be because of the middle layer of insulation. The isolation of the layers disappeared, so that the lock-up phenomenon ceased to exist. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Separation by implanted oxygen (SIMOX) is one of the processes that can achieve the above-mentioned SOI. The purpose of this process is to deeply implant the wafer with oxygen ions in order to make a layer of silicon dioxide paper for isolation between the surface of the wafer and the bulk material. Applicable to China National Standard (CNS) A4 specification (210X297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 543150 A7 B7 V. Description of the invention () Insulation layer. This process is mainly divided into two steps. First, the oxygen ions are implanted and heated on a wafer with a temperature of up to about 600 ° C. Then, the wafer is placed in an environment where the temperature is still about 130 ° C or higher for several hours, so that the silicon structure on the surface of the wafer damaged by ion implantation is restored to a single crystal with low defect concentration. At this time, because the surface of the silicon substrate is covered with a layer of single crystal silicon over the SiO2 layer, the semiconductor industry will collectively refer to this surface with a silicon thin film on insulator (siHc〇n 〇n insulator; SOI). Wafer with single crystal silicon and dioxide dioxide layer and its process. Another type of SOI technology used in the semiconductor industry is bonded wafers. The so-called bonded wafer refers to the use of an oxide film to bond two wafers together to form S 01. First, the two wafers are polished. Next, an oxide film is formed on the polished surface of at least one of the two wafers. Then, the two wafers are brought into close contact and an oxide film is interposed between the two wafers. Generally, in order to enhance the adhesion strength of the two wafers through the oxide film, a heat treatment must be performed at a temperature of, for example, about 800 ° C to about 1400 ° C. The two wafers of the above-mentioned bonded wafers are usually wafers having a lattice direction of < 1 1 0 >. A wafer having a lattice direction of < 1 1 0 > refers to a lattice direction in which notches on the wafer are aligned with < 1 10>. After bonding the two wafers with the lattice direction < 1 10 > as described above, and then forming components such as CMOS on one of the wafers in the subsequent process, the paper size can be formed as shown in Figure 1 Applicable to China National Standard (CNS) A4 (210x297 mm) (Please read the precautions on the back before filling this page)
543150 A7 B7 五、發明說明（ 繪示之黏合式晶圓1 〇。第1圖中的黏合式晶圓工〇 括底材（即其中一片晶圓）20以及元件層（即其中另〜 圓）30。底材20的材質例如可為矽。元件層3〇的主 亦例如為矽，但在此第1圖中已於後續製程形成 主要包 片晶 要材質 一 ％件7〇於 元件層3 0上，其中此元件7 0例如可為P型金 、 (P-type metal oxide semiconductor ； PMOS) ° it匕夕卜 與元件層3 0由氧化層40所隔開，且此氧化層4〇 ” 係在兩Η 晶圓黏合之前經由形成氧化層薄膜於兩片晶圓中的 ^ 中一片而產生。由於此黏合式晶圓10之底材其 氣半導體 底材2〇 經濟部智慧財產局員工消費合作社印製 f請先閱讀背面之注意事項再場寫本頁) 疋件層 之晶圓 三者上 3 0、以及氧化層40皆由具有第一 <1 10>晶格方向 所形成，因此底材2 0、元件層3 0、以及氧化層 的第一凹槽5 0皆對齊第一 < 1 10>晶格方向6〇。s 另 7，士 ‘ 悉此技術之人士所暸解的，具有源極S、閘椏0 熟 Q、以及匁 D之例如為PM0S之元件70的排列方式係如 叹 第1 繪不 6〇 4〇 外， 圖中 所 上述第1圖中所繪示之習知黏合式晶圓 片晶圓皆採用晶格方向為< 1 1 0>之晶圓來_从 不 乍係由於將 後續切割晶粒的過程變得較為容易。然而，L T 上下兩片晶圓 的晶格方向皆為<11 〇>之黏合式晶圓卻具有電洞移動率 (mobility)較低以及較差的短通道效應（sh〇rt channel e f f e c t ’ S C E)專缺點’因此有必要哥求一解決之道。 本紙張尺度適用中國國家標準(CNS)A4規格(21QX297公釐) 、ι·σ % 543150 A7 B7 五、發明説明（ 發明目的及概述 #於上述發明背景中，習知上下兩片晶圓的晶格方向 皆為<1 1〇>之黏合式晶圓具有電洞移動率較低以及較差的 短通道效應等缺點。因此本發明之_目的為提供__種黏合 式晶圓之結構，可用以改善電洞移動率。 經濟部智慧財產局員工消費合作社印製 本發明之另一目的為提供一種黏合式晶圓之結構，可 用以抑制短通道效應。 依據本發明之上述目的，因此本發明提供一種黏合式 晶圓之結構，至少包括：底材；氧化層覆蓋底材，其中氧 化層與底材共同具有第一 <11〇>晶格方向與第一凹槽，且此 第一 <11 0>晶格方向對齊第一凹槽；以及元件層覆蓋氧化 層，其中元件層具有<10 0>晶格方向與第二凹槽、此<1〇〇> 晶格方向對齊第二凹槽、且第二凹槽對齊第一凹槽。 依據本發明之上述目的’因此本發明提供另一種黏人 式晶圓之結構，至少包括：底材；氧化層覆蓋底材，其中 氧化層與底材共同具有第一 <110>晶格方向與第一凹槽，且 此第一 < 1 1 0 >晶格方向對齊第一凹槽；以及元件層覆蓋氧化 層’且此元件層具有第一 <110〉晶格方向、<1〇〇>晶格方向、 第二凹槽、與第三凹槽，其中第二<11〇>晶格方向對齊第二 (請先閲讀背面之注意事項再填寫本頁) 線一 本紙張尺度適用中國國家標準(CNS)A4規格(2i〇x297公釐) 543150 A7 B7 五、發明説明（） 凹槽、<1 00>晶格方向對齊第三凹槽、第三凹槽對齊第一凹 槽、且第二< 1 1 0>晶格方向與< 1 0 〇>晶格方向間具有例如約 為4 5度之夾角。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下歹|J 圖示做更詳細的闡述，其中： 第1圖係繪示習知黏合式晶圓之立體示意圖； 第2A圖與第2B圖係繪示本發明之一較佳實施例之黏 合式晶圓體示意圖；以及 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 第3 Α組_第3 C圖係繪示本發明之另一較佳實施例之 黏合 式晶圓之意圖。 , 圖號對照說明： 10 黏合式晶圓 20 底材 30 元件層 40 氧化層 50 第一凹槽 60 第一 <1 10>晶格方向 70 元件 100 黏合式晶圓 130 元件層 150 第二凹槽 160 <1 00〉晶格方向 170 元件 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 543150 A7 B7 五、發明説明（） 200黏合式晶圓 250 第二凹槽 3 50 第三凹槽 3 70夾角 G 閘極 2 3 0元件層 260 第二<1 10>晶格方向 360 <100>晶格方向 S 源極 D 汲極 發明詳細說明： 本發明係有關於一種元件層的通道沿著< 1 00>晶格方 向且底材的晶格方向則與元件層的晶格方向成45度角之 黏合式晶圓之結構。請參考第2A圖至第2B圖所繪示之本 發明之一較佳實施例之黏合式晶圓之立體示意圖。第2A圖 係繪示組成此黏合式晶圓之兩片晶圓尚未黏合時之狀態。 第2B圖則是繪示已黏合之黏合式晶圓，且此黏合式晶圓上 已於後續製程形成例如為PMOS等元件。請看以下詳細說 明0 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本發明之一較佳實施例之黏合式晶圓1 00主要由一片 具有第一 <110>晶格方向60之晶圓（即底材20)與另一片具 有<100>晶格方向160之晶圓（即元件層130)所組成。所謂 具有第一 < 1 1 0>晶格方向60之晶圓係指晶圓上的第一凹槽 50對齊第一 <1 10>晶格方向60。同理，所謂具有<100〉晶格 方向160之晶圓指晶圓上的第二凹槽150對齊<100>晶格方 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 543150 經濟部智慧財產局員工消費合作社印製 A 7 B7 五、發明説明（） 向160〇此外，底材20與元件層13〇由氧化層4〇所隔開， 且此氧化層4 0係在兩片晶圓黏合之前經由形成氧化層薄 膜於兩片晶圓中的至少其中一片之過程而產生。在本實施 例中以形成氧化層40於底材2〇上來做舉例。然並不限定 於此。例如氧化層4 0亦可形成於元件層丨3 〇下。 如前述習知中之說明，若元件層13 〇與底材2 0皆採用 具有< 1 1 0 >晶格方向之晶圓來製作，則會產生電洞移動率較 低以及較差的短通道效應等缺點。因此，本實施例中以具 有<100>晶格方向160之晶圓來形成元件層13〇之做法可使 後續形成於元件層130上的pm〇S具有提高電洞移動率與 抑制短通道效應之實質效益。以具有〈⑺^晶格方向160之 晶圓來形成PMOS可提高效能之原因已由Sayaina等人於 1 999年在國際電子元件會議（internati〇nai Electronic Device Meeting ; IEDM)期刊之論文、' Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15/zm Gate Length"中揭露。 至於底材20仍以具有第一 <l 1〇>晶格方向60之晶圓來製作 則仍可保有習知易於切割晶粒之優點。以下接著說明本發 明之一較佳實施例之各元件的連接關係。 此實施例中提供一種黏合式晶圓1 0 0之結構，包括底 材20、氧化層40、以及元件層130等。底材20之材質例 8 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ·:·::·.......费.........訂.........線· (請先閲讀背面之注意事項再填寫本頁) 543150 A7 _B7 五、發明説明（） 如可為石夕，且底材20具有第一〈110>晶格方向60與第一凹 槽50，其中第一 <11〇〉晶格方向60對齊第一凹槽50。氧化 層40覆蓋底材20，其中氧化層40之材質例如可為二氧化 矽。氧化層40與底材20共同具有上述第一 <11〇>晶格方向 60與第一凹槽50。而元件層130則覆蓋氧化層40，其中 元件層130之材質例如可為矽。元件層130具有<100>晶格 方向160與第二凹槽150，且此<1〇〇>晶格方向160對齊第 二凹槽150。此外，第二凹槽150係對齊第一凹槽50。再 者，黏合式晶圓1 〇〇更於後續製程形成元件1 70於元件層 130上，其中元件170例如可為PMOS。另外，如熟悉此技 術之人士所瞭解的，此例如為P Μ 0 S之元件1 7 0具有源極 S、閘極G、以及汲極D，且此元件1 7 0的排列方式係如第 2 Β圖中所繪示。 經濟部智慧財產局員工消費合作社印製 欲達成本發明之黏合式晶圓之結構的目的亦玎使用如 第3 A圖至第3 C圖中所繪示之另一較佳實施例。此另一較 佳實施例之特色在於元件層 230與習知同樣使用具有 < 1 1 0〉晶格方向之晶圓來形成，其中此< 1 1 〇>晶格方句在第 3A圖至第3C圖中即為第二<11〇>晶格方向260。所謂具有 第二<1 10>晶格方向260之晶圓係指元件層230之第二凹槽 250對準第二<11〇>晶格方向260之晶圓。但為了達成本餐 明之目的，元件層2 3 0在使用時必須如第3 A圖所系旋轉某 一角度。亦即，旋轉此角度後，元件層23 0正如以異有<1〇〇> ____ ;-·----·.......0^.........訂 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210Χ 297公釐) 543150 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 晶格方向360之晶圓所形成，且此<100>晶格方向36〇與第 二<1 10>晶格方向260之夾角3 70為約45度。 若將具有第二<1 1〇>晶格方向260之元件層23 0如上述 旋轉夾角3 70則可使元件層23 0如同具有<100>晶袼方向 3 60。但為了使元件層23〇具有第三凹槽35〇，形成元件層 2 3 0之晶圓必須事先經過適當加工，以使後續形成所需之 元件層230時，每一片元件層23〇都能同時具有第二凹槽 250與第三凹槽35〇。至於底材2〇則如習知與前述第一較 佳實施例所示仍使用具有第一 < 1 1 0>晶格方向6〇之晶圓來 形成。以下接著以第3 B圖與第3 C圖說明此本發明之另一 較佳實施例之各元件的連接關係。 第3 B圖係繪示組成此黏合式晶圓之兩片晶圓尚未黏 合時之狀態。第3 C圖則是繪示已黏合之黏合式晶圓200， 且此黏合式晶圓200上已於後續製程形成例如為PMOS等 元件。此另一較佳實施例中提供一種黏合式晶圓2 0 0之結 構，包括底材20、氧化層40、以及元件層230等。底材20 之材質例如可為矽，且底材20具有第一 < 1 1 〇>晶格方向60 與第一凹槽50，其中第一 <11 〇>晶格方向60對齊第一凹槽 50。氧化層40覆蓋底材20，其中氧化層40之材質例如可 為二氧化矽。氧化層40與底材20共同具有上述第一 <11〇> 晶格方向60與第一凹槽50。而元件層230則覆蓋氧化層 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) ! Γ ........0.........訂.........線_ (請先閲tlf背面之注意事項再填寫本頁) 543150 A7 B7 五、發明説明（） 4 0，其中元件層2 3 0之材質例如可為矽。元件層2 3 0具有 第二<110>晶格方向260與<100〉晶格方向360，其中第二 < 1 1 0 >晶格方向2 6 0與< 1 〇 〇 >晶格方向3 6 0間之夾角例如約 為45度。此外，元件層230更具有第二凹槽250與第三凹 槽3 50，其中第二<1 10>晶格方向260對齊第二凹槽25〇， 且<100>晶格方向360對齊第三凹槽350。而第三凹槽35〇 則對齊第一凹槽5 0。再者，黏合式晶圓2 0 0更於後續製程 形成元件2 7 0於元件層2 3 0上，其中元件2 7 0例如可為 P Μ 0 S。另外，如熟悉此技術之人士所瞭解的，此例如為 PMOS之元件270具有源極S、閘極〇、以及汲極D，且 此元件270的排列方式係如第3C圖中所繪示。 .......f . (請先閱41»背面之注意事項再填寫本頁} 結 構，可用以改善電洞移動率 可 構 結 之 圓 晶 式 合 黏 種 1 供 提 為 點 。 優應 一 效 另道 之通 明短 發制 本抑 以 用 訂 經濟部智慧財產局員工消費合作社印製 知 習 有 具 。 能點 仍優 構之 結粒 之晶 圓割 晶切 式於 合易 黏的 之有 明具 發所 本構 用結 運之 ’ 一口見 外晶 此式 合 黏 所 員 人 之 術 技j 此例 悉施 熟實 如佳 較 之 已 而 以 用 hr 並 的 以 本 定 明範 發利 本專 為請 僅申 述之 所明 上發 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 543150 A7 B7 五、發明説明（） 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 …·——·.......费.........、玎......... (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 12 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐)543150 A7 B7 V. Description of the invention (the bonded wafer 1 shown in the drawing. The bonded wafer worker shown in Figure 1 includes the substrate (ie one of the wafers) 20 and the component layer (ie, the other ~ round). 30. The material of the substrate 20 may be, for example, silicon. The host of the element layer 30 is also, for example, silicon, but in this figure 1 the main package chip has been formed in the subsequent process. 0, where the element 70 may be, for example, P-type gold, (P-type metal oxide semiconductor; PMOS) ° It is separated from the element layer 30 by an oxide layer 40, and the oxide layer 40. " It is generated by forming an oxide film on one of the two wafers before the two wafers are bonded. Because the substrate of this bonded wafer 10 is a semiconductor substrate, it is consumed by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. Cooperative printed f, please read the notes on the back before writing this page.) The three layers of the wafer 30 and the oxide layer 40 are formed by the first < 1 10 > lattice direction, so Substrate 2 0, element layer 3 0, and first groove 50 of oxide layer are aligned first < 1 10 > Lattice direction 60 s. Another person who understands this technology knows that the arrangement of elements 70 such as PM0S with source S, gate Q0 and QD is astonishing. In addition to the first drawing, the conventional bonded wafer wafers shown in the above first drawing are all made of wafers with a lattice direction of < 1 1 0 > At first glance, it is easier to cut the die later. However, the bonded wafers with the crystal directions of the two wafers on the top and bottom of the LT having <11 〇> have hole mobility. Low and poor short channel effect (SCE) special shortcomings', so it is necessary to find a solution. This paper size applies the Chinese National Standard (CNS) A4 specification (21QX297 mm), ι · σ % 543150 A7 B7 V. Description of the invention (Purpose of the invention and summary # In the above background of the invention, it is known that the bonded wafers with the lattice directions of both the upper and lower wafers being < 1 1〇 > have hole mobility. Shortcomings such as lower and worse short channel effects. Therefore, the purpose of the present invention is to provide __ kinds of sticky The structure of the wafer can be used to improve the mobility of the holes. The employee's cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed another object of the present invention to provide an adhesive wafer structure that can be used to suppress the short channel effect. According to the present invention The above object, therefore, the present invention provides a structure of an adhesive wafer, including at least: a substrate; an oxide layer covering the substrate, wherein the oxide layer and the substrate have a first < 11〇 > lattice direction and a first And the first < 11 0 > lattice direction is aligned with the first groove; and the element layer covers the oxide layer, wherein the element layer has a < 10 0 > lattice direction and the second groove, and < 1 〇〇 > The lattice direction is aligned with the second groove, and the second groove is aligned with the first groove. According to the above-mentioned object of the present invention ', the present invention provides another structure of a sticky wafer including at least: a substrate; an oxide layer covering the substrate, wherein the oxide layer and the substrate have a first < 110 > And the first groove, and the first < 1 1 0 > lattice direction is aligned with the first groove; and the element layer covers the oxide layer, and the element layer has a first < 110> lattice direction, < 1〇 > lattice direction, second groove, and third groove, where the second < 11〇 > lattice direction is aligned second (please read the precautions on the back before filling this page) Line 1 This paper size applies to China National Standard (CNS) A4 specification (2i0x297 mm) 543150 A7 B7 V. Description of the invention () Groove, < 1 00 > Lattice direction alignment Third groove, Third groove alignment The first groove and the second < 1 1 0 > lattice direction and the < 1 0 〇 > lattice direction have an included angle of about 45 degrees, for example. Brief description of the drawings: The preferred embodiment of the present invention will be supplemented by the following 歹 | J icon in the following explanatory text, in which: Figure 1 is a three-dimensional schematic view of a conventional adhesive wafer Figures 2A and 2B are schematic diagrams of a bonded wafer body according to a preferred embodiment of the present invention; and (please read the precautions on the back before filling this page) The third group A_3C is a diagram illustrating the intention of another type of bonded wafer of the present invention. Comparison of drawing numbers: 10 Adhesive wafer 20 Substrate 30 Element layer 40 Oxidation layer 50 First groove 60 First < 1 10 > Lattice direction 70 Element 100 Adhesive wafer 130 Element layer 150 Second recess Slot 160 < 1 00> Lattice direction 170 components This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) 543150 A7 B7 V. Description of the invention (200) Adhesive wafer 250 Second groove 3 50 Third groove 3 70 Angle G Gate 2 3 0 Element layer 260 Second < 1 10 > Lattice direction 360 < 100 > Lattice direction S Source D Drain Detailed description of the invention: The present invention relates to a The structure of a bonded wafer in which the channel of the element layer is along the < 1 00 > lattice direction and the lattice direction of the substrate is at an angle of 45 degrees to the lattice direction of the element layer. Please refer to FIG. 2A to FIG. 2B for three-dimensional schematic diagrams of the bonded wafer according to a preferred embodiment of the present invention. Figure 2A shows the state when the two wafers constituting the bonded wafer have not been bonded. Figure 2B shows the bonded wafer, and components such as PMOS have been formed on the bonded wafer in subsequent processes. Please see the following detailed description 0 (Please read the notes on the back before filling out this page) The Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperative, printed a bonded wafer 100 according to a preferred embodiment of the present invention. < 110 > A wafer having a lattice direction of 60 (i.e., the substrate 20) and another wafer having a < 100 > lattice direction of 160 (i.e., the element layer 130). A wafer having a first < 1 1 0 > lattice direction 60 means that the first groove 50 on the wafer is aligned with the first < 1 10 > lattice direction 60. Similarly, a wafer with a <100> lattice direction of 160 means that the second groove 150 on the wafer is aligned with the <100> lattice. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm ) 543150 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A 7 B7 V. Description of the invention () To 160 ° In addition, the substrate 20 and the element layer 13 are separated by an oxide layer 40, and this oxide layer 40 is Before the two wafers are bonded, it is generated by a process of forming an oxide film on at least one of the two wafers. In this embodiment, an oxide layer 40 is formed on the substrate 20 as an example. Of course, it is not limited to this. For example, the oxide layer 40 may also be formed under the element layer 3-30. As explained in the foregoing practice, if both the element layer 13 and the substrate 20 are made of a wafer having a < 1 1 0 > lattice direction, a short hole mobility and a poor shortness will occur. Channel effects and other disadvantages. Therefore, in this embodiment, the method of forming the element layer 13 by using a wafer having a <100> lattice direction 160 can make the subsequent PMS formed on the element layer 130 improve the hole mobility and suppress the short channel. The substantial benefits of the effect. The reason why PMOS can be formed by a wafer with a <160 lattice direction 160 has been described by Sayaina et al. In a paper of the International Internatiion Electronic Device Meeting (IEDM) in 1999, 'Effect of < 100 > Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15 / zm Gate Length ". As long as the substrate 20 is still fabricated from a wafer having the first < 110 > lattice direction 60, it still retains the advantage that it is conventionally easy to cut the crystal grains. The following describes the connection relationship of the components of a preferred embodiment of the present invention. In this embodiment, a structure of an adhesive wafer 100 is provided, which includes a substrate 20, an oxide layer 40, and an element layer 130. Example 8 of the material of the substrate 20 The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) · :::: ............ Fees ......... Order .. ....... Line · (Please read the notes on the back before filling this page) 543150 A7 _B7 V. Description of the invention () If it can be Shi Xi, and the substrate 20 has the first <110> lattice direction 60 is aligned with the first groove 50, wherein the first < 110 > lattice direction 60 is aligned with the first groove 50. The oxide layer 40 covers the substrate 20, and the material of the oxide layer 40 may be, for example, silicon dioxide. The oxide layer 40 and the substrate 20 have the above-mentioned first < 110 > lattice direction 60 and the first groove 50 in common. The element layer 130 covers the oxide layer 40. The material of the element layer 130 may be silicon, for example. The element layer 130 has a < 100 > lattice direction 160 and a second groove 150, and the < 100 > lattice direction 160 is aligned with the second groove 150. In addition, the second groove 150 is aligned with the first groove 50. In addition, the bonded wafer 100 further forms a component 1 70 on the component layer 130 in a subsequent process. The component 170 may be, for example, PMOS. In addition, as will be understood by those familiar with this technology, the element 170, which is, for example, P M 0 S, has a source S, a gate G, and a drain D, and the arrangement of this element 170 is as 2 Β pictured. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The purpose of the structure of the adhesive wafer invented by the invention is to use another preferred embodiment as shown in Figs. 3A to 3C. The feature of this another preferred embodiment is that the element layer 230 is formed using a wafer having a < 1 1 0> lattice direction as in the conventional method, wherein the < 1 1 〇 > Figures 3 to 3C show the second < 11〇 > lattice direction 260. A wafer having a second < 1 10 > lattice direction 260 refers to a wafer in which the second groove 250 of the element layer 230 is aligned with the second < 110 > lattice direction 260. However, in order to achieve cost-effectiveness, the component layer 230 must be rotated at an angle as shown in Figure 3A during use. That is to say, after rotating this angle, the element layer 23 0 is different from the following < 1〇〇 >____;-· ----......... 0 ^ ......... Order (please read the notes on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 543150 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. Description of the invention ( ) A wafer having a lattice direction of 360 is formed, and an angle 3 70 between this < 100 > lattice direction 36 and the second < 1 10 > lattice direction 260 is about 45 degrees. If the element layer 230 having a second < 1 10 > lattice direction 260 as described above is rotated by the included angle 3 70 as described above, the element layer 230 can be made to have a < 100 > crystal orientation 3 60. However, in order for the element layer 23 to have the third groove 35o, the wafer forming the element layer 230 must be appropriately processed in advance, so that when the required element layer 230 is subsequently formed, each of the element layers 230 can The second groove 250 and the third groove 350 are provided at the same time. The substrate 20 is formed using a wafer having a first < 1 1 0 > lattice direction 60 as shown in the conventional and the first preferred embodiment. Next, the connection relationship of the components of another preferred embodiment of the present invention will be described with reference to Figs. 3B and 3C. Figure 3B shows the state when the two wafers constituting the bonded wafer have not been bonded. Figure 3C shows the bonded wafer 200 that has been bonded, and components such as PMOS have been formed on the bonded wafer 200 in subsequent processes. In another preferred embodiment, a structure of a bonded wafer 2000 is provided, which includes a substrate 20, an oxide layer 40, and an element layer 230. The material of the substrate 20 may be, for example, silicon, and the substrate 20 has a first < 1 1 〇 > lattice direction 60 and a first groove 50, wherein the first < 11 〇 > A groove 50. The oxide layer 40 covers the substrate 20, and the material of the oxide layer 40 may be, for example, silicon dioxide. The oxide layer 40 and the substrate 20 have the above-mentioned first < 11〇 > lattice direction 60 and the first groove 50 in common. The element layer 230 covers the oxide layer. The paper size is applicable to China National Standard (CNS) A4 specifications (210X 297 mm)! Γ ........ 0 ......... Order ... ... line_ (please read the precautions on the back of tlf before filling in this page) 543150 A7 B7 V. Description of the invention () 40, where the material of the element layer 2 3 0 can be silicon, for example. The element layer 2 3 0 has a second < 110 > lattice direction 260 and < 100> a lattice direction 360, wherein the second < 1 1 0 > lattice direction 2 6 0 and < 1 〇〇 > The included angle between the lattice directions 360 is about 45 degrees, for example. In addition, the element layer 230 further has a second groove 250 and a third groove 3 50, wherein the second < 1 10 > lattice direction 260 is aligned with the second groove 25 and the < 100 > lattice direction 360 is aligned. Third groove 350. The third groove 35o is aligned with the first groove 50. In addition, the adhesive wafer 200 is further formed in a subsequent process to form an element 270 on the element layer 230. The element 270 may be, for example, P MOS. In addition, as understood by those skilled in the art, the element 270, which is, for example, PMOS, has a source S, a gate 0, and a drain D, and the arrangement of the elements 270 is as shown in FIG. 3C. ....... f. (Please read 41 »Notes on the back before filling in this page} Structure, which can be used to improve the hole movement rate of the round crystal composite adhesive 1 can be provided. The clear short hair production system should be used in a different way to suppress the printing of printed materials by the consumer co-operatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Youmingmingfa's main structure is used to carry it '. See the external crystal. This example shows the technique of bonding the members. This example shows that Shishu is better than using hr. This paper is only for the purpose of submitting the stated specifications. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 543150 A7 B7. 5. Description of the invention (); all others without departing from the spirit disclosed by the invention All equivalent changes or modifications should be included in the scope of the patent application described below......... ... (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 12 This paper size applies to China National Standard (CNS) A4 (210X 297 mm)