JP2007266044A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, with which parasitic capacity and parasitic resistance can be reduced than theretofore, during the normal manufacturing step of a semiconductor device. <P>SOLUTION: Only a semiconductor layer (epitaxial layer and single-crystal silicon layer) wherein semiconductor elements are formed is left, and a semiconductor substrate or an insulating layer (embedded silicon oxide layer) is removed, or the semiconductor layer (epitaxial layer and single-crystal silicon layer) is further removed, in a manner that it does not lose functions as a semiconductor element, and a desired support substrate (second support substrate) is stuck and is divided into pieces. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device in which an active element and a passive element (semiconductor element) are formed on a silicon substrate or a compound semiconductor substrate, and in particular, a semiconductor device free from characteristic deterioration due to parasitic capacitance and parasitic resistance caused by the semiconductor substrate. It relates to the manufacturing method.

  In conventional semiconductor devices, performance such as high speed or high frequency characteristics is often limited by the parasitic capacitance of the semiconductor element. In particular, it is known that the performance of a semiconductor device is greatly improved by reducing the capacitance (substrate capacitance) generated between individual semiconductor elements and a semiconductor substrate among parasitic capacitances.

  In order to reduce the substrate capacity, there is a method of using an SOI (Silicon On Insulator) substrate having a single crystal silicon layer stacked on an insulating layer (buried silicon oxide layer) on a support substrate made of a semiconductor. For example, when a MOS transistor is formed in a single crystal silicon layer of an SOI substrate, an impurity region constituting a source region and a drain region is diffused until reaching a buried silicon oxide layer, so that the drain-substrate, source-substrate The capacity between them can be greatly reduced.

  In addition, by forming a thin semiconductor layer over an insulating substrate and forming a semiconductor element in this semiconductor layer, the substrate capacity can be significantly reduced. Specifically, there is a method using an SOS (Silicon on sapphire) substrate in which a single crystal silicon layer is epitaxially grown on a sapphire substrate. For example, when a MOS transistor is formed in a single crystal silicon layer of an SOS substrate, impurity regions constituting the source region and the drain region are diffused until reaching the sapphire substrate, so that between the drain and the substrate and between the source and the substrate. The capacity can be greatly reduced.

  On the other hand, the performance of semiconductor devices for power use is often degraded by parasitic resistance. For example, in a semiconductor device (for example, a vertical double diffusion MOS transistor) having a structure in which an electrode of a semiconductor element is taken out from the back surface of a semiconductor substrate, the semiconductor substrate becomes a parasitic resistance in series and causes deterioration in performance. Therefore, after forming the semiconductor element, it is necessary to reduce the parasitic resistance by reducing the thickness of the semiconductor substrate.

  In the conventional method for manufacturing a semiconductor device, the parasitic capacitance of the semiconductor device is reduced by using an SOI substrate in order to reduce the parasitic capacitance. However, since the thickness of the buried silicon oxide layer cannot be increased so much in the manufacturing process, the effect of reducing the parasitic capacitance is limited. In the case of using an SOS substrate, sapphire is an insulating substrate, so that the effect of reducing parasitic capacitance is greater than that of an SOI substrate. However, the SOS substrate is expensive, and sapphire is difficult to process in a manufacturing process using a general silicon semiconductor device manufacturing apparatus, and is only used in some semiconductor devices.

  On the other hand, in order to reduce the parasitic resistance, the method of thinning the semiconductor substrate causes warpage of the semiconductor substrate due to the stress of the laminated film (protective film or wiring layer) formed on the surface of the semiconductor substrate as the thickness is reduced. Also, the mechanical strength is lowered, and handling in the subsequent assembly process becomes very difficult. Therefore, the thickness of the semiconductor substrate is limited to about 50 μm, and the effect of reducing the parasitic resistance is also limited.

  An object of the present invention is to solve these problems, and to provide a method for manufacturing a semiconductor device that can reduce parasitic capacitance and parasitic resistance more than ever by using a normal semiconductor device manufacturing apparatus.

  In order to achieve the above object, the invention according to claim 1 of the present application includes a step of preparing a semiconductor substrate in which a semiconductor element is formed on the surface of a semiconductor layer laminated on the substrate, and a first support substrate is attached to the surface of the semiconductor layer. Attaching, a step of leaving at least the semiconductor layer on which the semiconductor element is formed, removing the substrate or a part of the substrate and the semiconductor layer, and attaching a second support substrate to the exposed semiconductor layer And removing the first support substrate to expose the surface of the semiconductor layer, and then cutting the semiconductor layer and the second support substrate to form the semiconductor element on the second support substrate. And a step of dividing into individual semiconductor devices to which the semiconductor layer is bonded.

  According to a second aspect of the present invention, in the method for manufacturing a semiconductor device according to the first aspect, the semiconductor layer is formed by laminating a first semiconductor layer having a higher impurity concentration than the semiconductor substrate and the first semiconductor layer. Preparing a semiconductor substrate comprising a second semiconductor layer having an impurity concentration lower than that of the first semiconductor layer and having the semiconductor element formed on the surface of the second semiconductor layer; and at least the second semiconductor element having the semiconductor element formed thereon. And removing the substrate, or the substrate and the first semiconductor layer, or a part of the substrate, the first semiconductor layer, and the second semiconductor layer. And

  According to a third aspect of the present invention, in the semiconductor device manufacturing method according to the second aspect, the semiconductor layer is formed by stacking a P-type semiconductor layer having a higher impurity concentration than the semiconductor substrate and the P-type semiconductor layer. It is characterized by comprising an N-type or P-type semiconductor layer having an impurity concentration lower than that of the P-type semiconductor layer.

  According to a fourth aspect of the present invention, there is provided a step of preparing a semiconductor substrate in which a semiconductor element is formed on a surface of a single crystal semiconductor layer stacked on an insulating layer on a substrate, and a first support substrate is provided on the surface of the single crystal semiconductor layer. A pasting step, and leaving at least the single crystal semiconductor layer on which the semiconductor element is formed, and removing the substrate, or the substrate and the insulating layer, or the substrate, the insulating layer, and a part of the single crystal semiconductor layer; A step of attaching a second support substrate to the exposed insulating layer or the single crystal semiconductor layer; and removing the first support substrate to expose the surface of the single crystal semiconductor layer; The single crystal semiconductor layer, the insulating layer and the second support substrate, or the single crystal semiconductor layer and the second support substrate are cut, and the half-layer is formed on the second support substrate via the insulating layer. And a step of singulating into a semiconductor device in which the single crystal semiconductor layer in which a body element is formed or the single crystal semiconductor layer in which the semiconductor element is formed on the second supporting substrate is bonded. .

  The invention according to claim 5 is the method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor substrate is a semiconductor substrate in which a single crystal silicon layer is stacked on a semiconductor substrate with a silicon oxide layer interposed therebetween. To do.

  According to a sixth aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the first to fifth aspects, the semiconductor device includes a wiring layer connecting electrodes of a plurality of semiconductor elements, and a bump connected to the wiring layer. An electrode and a resin layer covering a part of the wiring layer and the bump electrode are provided.

  According to the manufacturing method of the present invention, only the normal semiconductor device manufacturing process leaves only the semiconductor layer on which the semiconductor element is formed (specifically, about 10 to 20 μm in thickness), and removes the substrate and the like. be able to. Therefore, by configuring the second support substrate with an insulating material, the parasitic capacitance of the semiconductor element can be significantly reduced, and the semiconductor device formed according to the present invention exhibits excellent performance in high speed and high frequency characteristics. Is expected to do. In addition, by configuring the second support substrate with metal, the parasitic resistance can be greatly reduced. In particular, the parasitic resistance can be greatly reduced for a semiconductor device having a vertical structure. Improvements in the characteristics of semiconductor devices are expected.

  In addition, when a semiconductor element is formed on a single crystal silicon layer formed over an SOI substrate by the manufacturing method of the present invention, the insulating layer (buried silicon oxide layer) serves as an etching stopper, and the substrate can be selectively removed. The semiconductor device can be formed with good controllability. Similarly, when using a semiconductor substrate having semiconductor layers with different conductivity types or impurity concentrations stacked on the substrate, etching with different selectivity is possible due to differences in conductivity types or differences in impurity concentration. A semiconductor device can be formed well. Note that a semiconductor layer having a different conductivity type can be left as a semiconductor layer constituting a part of the semiconductor element. Further, when a semiconductor substrate including semiconductor layers having different conductivity types is used, there is an advantage that a semiconductor device can be formed at a very low cost compared to an SOI substrate.

  The semiconductor substrate used in the manufacturing method of the present invention forms a so-called wafer level chip size package in which a wiring layer for connecting semiconductor elements and a bump electrode and a resin layer as a protective film are formed on the wiring layer. Therefore, the semiconductor substrate can be prepared. Therefore, the manufacturing method of the present invention becomes a part of the manufacturing process of the wafer level chip size package, and even if the present invention is used, there is an advantage that the manufacturing cost of the package is not greatly increased.

  In particular, when the manufacturing method of the present invention is part of the manufacturing process of a wafer level chip size package, the thickness of the semiconductor layer on which the semiconductor element is formed should be reduced to a conventional thickness of 1/5 to 2/5. This is suitable as a method for manufacturing a thin package.

  The present invention leaves only a semiconductor layer (for example, an epitaxial layer or a single crystal silicon layer) on which a semiconductor element is formed, a semiconductor substrate, a semiconductor layer or an insulating layer (for example, a buried silicon oxide layer) having a different conductivity type, or Furthermore, by removing a part of the semiconductor layer in which the semiconductor element is formed within a range that does not impair the function as a semiconductor element, attaching a desired support substrate (second support substrate), A semiconductor device having a very small parasitic capacitance or parasitic resistance can be formed. Hereinafter, the production method of the present invention will be described in detail according to examples.

  First, as a first embodiment, a method for forming a semiconductor device with a small parasitic capacitance using an SOI substrate will be described. An SOI substrate (semiconductor substrate) in which a buried silicon oxide layer 2 (insulating layer) and a single crystal silicon layer 3 (single crystal semiconductor layer) are stacked on a semiconductor substrate 1 (substrate) made of silicon by a normal manufacturing method is prepared. In order to form a desired integrated circuit in the single crystal silicon layer 3 on the buried silicon oxide layer 2, semiconductor elements such as transistors, diodes, resistors, and the like are formed, and the semiconductor elements are connected by a wiring layer. A protective film 11 is formed (FIG. 1a). Here, when a MOS transistor is formed as one of the semiconductor elements, a source region 5 and a drain region 6 are formed on a single crystal silicon layer 3 separated by a LOCOS oxide film 4 as shown in FIG. The buried silicon oxide layer 2 is formed. 7 is a gate electrode, 8 is a source electrode, 9 is a drain electrode, and 10 is a wiring layer. In FIG. 1, the structure of the semiconductor element is not shown except for the protective film 11.

  An adhesive resin 12 is applied to the surface of the protective film 11 and a first support substrate 13 is attached (FIG. 1b). Here, the first support substrate 13 is a glass plate, and the adhesive resin 12 is an acrylic resin.

  Next, the semiconductor substrate 1 is completely removed, and the buried silicon oxide layer 2 is exposed (FIG. 1c). Here, after the semiconductor substrate 1 is thinned by polishing, the slightly remaining semiconductor substrate 1 made of silicon is etched with a sodium hydroxide warm aqueous solution. Since the buried silicon oxide layer 2 has a much slower etching rate than that of silicon in an aqueous solution of sodium hydroxide, etching stops when all the buried silicon oxide layer 2 is exposed (becomes an etching stopper), and the semiconductor substrate 1 has good controllability. Can be removed. The semiconductor substrate 1 can be entirely removed by etching with an aqueous sodium hydroxide solution without performing thinning by polishing. Further, the etching solution is not limited to the sodium hydroxide warm aqueous solution, and other etching solutions can be used.

  Next, a second support substrate 14 is attached to the exposed buried silicon oxide layer 2 surface (FIG. 1d). Here, the second support substrate 14 can be attached without using an adhesive by using an epoxy resin film and thermocompression bonding to the exposed embedded silicon oxide layer 2 surface. The second support substrate 14 may be selected from a material having desired characteristics in consideration of mechanical strength, thermal stability, and electrical characteristics. In addition to thermocompression bonding, a method of bonding by applying a resin and heat-treating to volatilize the solvent and a method of bonding using an adhesive can be used.

  Next, the first support substrate 13 is removed by immersing in a solution for dissolving the adhesive resin 12 (FIG. 1e). Depending on the type of the adhesive resin 12, the first support substrate 13 can be removed by heating to deteriorate the adhesive property or by irradiating ultraviolet rays to change the adhesive property. Needless to say, the protective film 11 and the second support substrate 14 are not peeled off in the step of removing the first support substrate 13.

  Thereafter, as in the case of an individual semiconductor device singulation process, the dicing saw is used to cut and divide the second support substrate 14 together with the protective film 11, the single crystal silicon layer 3, and the buried silicon oxide layer 2 into individual pieces. A semiconductor device can be formed.

  Since the semiconductor device thus formed has a structure in which an insulating second support substrate 14 is bonded to the buried silicon oxide layer 2 instead of the semiconductor substrate 1, for example, the MOS transistor shown in FIG. Is formed, the capacitance between the source region 5 and the second support substrate 14 or the capacitance between the drain region 6 and the second support substrate 14 is smaller than the substrate capacitance with the semiconductor substrate 1 remaining. can do. Furthermore, since the capacitance between the wiring layer 10 and the second support substrate 14 can be greatly reduced, an improvement in high frequency characteristics is expected.

  Next, a second embodiment of the present invention will be described with reference to FIG. First, as in the first embodiment, an SOI substrate (semiconductor substrate) in which a buried silicon oxide layer 2 (insulating layer) and a single crystal silicon layer 3 (single crystal semiconductor layer) are stacked on a semiconductor substrate 1 (substrate) made of silicon. prepare. In order to form a desired integrated circuit in the single crystal silicon layer 3 on the buried silicon oxide layer 2, semiconductor elements such as transistors, diodes, resistors, and the like are formed, and the semiconductor elements are connected by a wiring layer. A protective film 11 is formed (FIG. 3a). Here, when forming a vertical double diffusion MOS transistor as one of the semiconductor elements, a body region 15 is formed on the single crystal silicon layer 3 as shown in FIG. The source region 5 is formed. Reference numeral 16 denotes a source / body electrode connected to the source region 5 and the body region 15. In FIG. 3, the structure of the semiconductor element is not shown except for the protective film 11.

  An adhesive resin 12 is applied to the surface of the protective film 11 and a first support substrate 13 is attached (FIG. 3b). Here, the first support substrate 13 is a glass plate, and the adhesive resin 12 is an acrylic resin.

  Next, all the semiconductor substrate 1 is removed, and the buried silicon oxide layer 2 is exposed. Here, the semiconductor substrate 1 is thinned by polishing, and the semiconductor substrate 1 made of slightly remaining silicon is etched with a sodium hydroxide warm aqueous solution. Since the buried silicon oxide layer 2 has a much slower etching rate than that of silicon in the aqueous sodium hydroxide solution, the etching stops when the buried silicon oxide layer 2 is completely exposed, and the semiconductor substrate 1 can be removed with good controllability. it can. Next, unlike the first embodiment, the exposed buried silicon oxide layer 2 is also removed by hydrofluoric acid (FIG. 3c). The semiconductor substrate 1 can be entirely removed by etching in a sodium hydroxide warm aqueous solution without thinning by polishing. Further, the etching solution is not limited to the aqueous sodium hydroxide solution, and other etching solutions can be used, and an etching solution that can continuously etch the buried silicon oxide layer 2 can also be used. When removing the buried silicon oxide layer 2, the buried silicon oxide layer 2 can be selectively removed, and a part of the single crystal silicon layer 3 can be removed within a range not impairing the function of the semiconductor element. is there.

  Thereafter, the second support substrate 14 is attached to the exposed single crystal silicon layer 3 (FIG. 3d). Here, a metal plate is used as the second support substrate 14. Specifically, an aluminum plate having low resistance and high mechanical strength is used. The method of adhering the aluminum plate and the single crystal silicon layer 3 is to put the adhering surface into a vacuum device facing each other, irradiate the adhering surface with an ion beam, and then press-bond, thereby reducing the resistance of the adhering surface. be able to. Alternatively, it can be attached using a conductive adhesive.

  Thereafter, as in the first embodiment, the first support substrate 13 is removed by immersing it in a solution for dissolving the adhesive resin 12 (FIG. 3e). Depending on the type of the adhesive resin 12, the first support substrate 13 can be removed by heating to deteriorate the adhesive property or by irradiating ultraviolet rays to change the adhesive property. Needless to say, the protective film 11 and the second support substrate 14 are not peeled off in the step of removing the first support substrate 13.

  Next, in the same way as a process for dividing a normal semiconductor device, a dicing saw is used to cut and divide the second support substrate 14 together with the protective film 11 and the single crystal silicon layer 3 to form a semiconductor device. can do.

  In the semiconductor device formed in this way, the second support substrate 14 operates as a drain electrode. The second support substrate 14 directly bonded to the single crystal silicon layer 3 is formed on the semiconductor substrate because it is very close to the single crystal silicon layer 3 and is disposed in the very vicinity of the single crystal silicon layer 3. Compared to a conventional semiconductor device, a semiconductor device having almost no parasitic resistance can be realized, and improvement in characteristics is expected as a semiconductor device for power use.

  In the first and second embodiments, the method for forming the semiconductor device using the SOI substrate has been described. However, since an SOI substrate is more expensive than a normal semiconductor substrate, a manufacturing method using the normal semiconductor substrate will be described next.

  A third embodiment of the present invention is shown in FIG. In this embodiment, instead of the SOI substrate, a P-type high concentration layer 17 having a higher impurity concentration than the semiconductor substrate 1 and a P-type high concentration layer are formed on the N-type semiconductor substrate 1 made of silicon by an ordinary semiconductor device manufacturing method. A semiconductor substrate on which an N-type single crystal silicon layer 3 having an impurity concentration lower than that of the concentration layer 17 is prepared. In order to form a desired integrated circuit in the single crystal silicon layer 3 on the P-type high-concentration layer 17, semiconductor elements such as transistors, diodes, and resistors are formed, and the semiconductor elements are connected by a wiring layer. The necessary protective film 11 is formed (FIG. 5a). As in the first embodiment, when a MOS transistor is formed as one of the semiconductor elements, the source is formed on the single crystal silicon layer 3 separated by the LOCOS oxide film 4 as shown in FIG. Region 5 and drain region 6 are formed. The P-type high concentration layer 17 can be formed by implanting impurity ions with high energy from the surface of the single crystal silicon layer 3 or by forming the P-type high concentration layer 17 on the surface of the semiconductor substrate 1 and then forming the single crystal silicon layer 3 epitaxially. It can form by the method to do. In FIG. 5, the structure of the semiconductor element is not shown except for the protective film 11.

  An adhesive resin 12 is applied to the surface of the protective film 11 and a first support substrate 13 is attached (FIG. 5b). Here, the first support substrate 13 is a glass plate, and the adhesive resin 12 is an acrylic resin.

  Next, the semiconductor substrate 1 is completely removed, and the P-type high concentration layer 17 is exposed (FIG. 5c). Here, after the semiconductor substrate 1 is thinned by polishing, the slightly remaining N-type semiconductor substrate 1 made of silicon is etched with an aqueous potassium hydroxide solution. Since the P-type high concentration layer 17 cannot be etched with an aqueous potassium hydroxide solution, the etching stops (becomes an etching stopper) when the P-type high concentration layer 17 is completely exposed, and the semiconductor substrate 1 can be removed with good control. The etching solution for the semiconductor substrate 1 can remove the semiconductor substrate 1 with good selectivity by using a hot nitric acid solution having an optimized composition ratio in addition to the aqueous potassium hydroxide solution.

  Next, the P-type high concentration layer 17 is removed, and the single crystal silicon layer 3 is exposed. The removal of the P-type high concentration layer 17 uses reactive ion etching. This is because reactive ion etching is less dependent on impurity concentration, and the required amount can be etched with high accuracy. For this etching, other methods can be used without any problem if the accuracy can be ensured. Moreover, there is no problem even if a part of the single crystal silicon layer 3 is removed as long as the function of the semiconductor element is not impaired. When the P-type high concentration layer 17 is used as a part of the semiconductor element, the etching process of the P-type high concentration layer 17 may be omitted.

  Next, the surface of the exposed single crystal silicon layer 3 (the surface of the P-type high concentration layer 17 when the P-type high concentration layer 17 is not removed, and the description of the case where the P-type high concentration layer 17 is not removed is omitted below) In the case where the P-type high concentration layer 17 is not removed, the second support substrate 14 is attached to the “single crystal silicon layer 3” as “P-type high concentration layer 17” (FIG. 5d). Here, the second support substrate 14 can be attached without using an adhesive by using an epoxy resin film and thermally pressing the exposed surface of the single crystal silicon layer 3. The second support substrate 14 may be selected from a material having desired characteristics in consideration of mechanical strength, thermal stability, and electrical characteristics. As the bonding method, in addition to thermocompression bonding, a method in which a resin is applied and a solvent is volatilized by heat treatment and a method of bonding using an adhesive can be used.

  Next, the first support substrate 13 is removed by immersing in a solution for dissolving the adhesive resin 12 (FIG. 5e). Depending on the type of the adhesive resin 12, the first support substrate 13 can be removed by heating to deteriorate the adhesive property or by irradiating ultraviolet rays to change the adhesive property. Needless to say, the protective film 11 and the second support substrate 14 are not peeled off in the step of removing the first support substrate 13.

  Hereinafter, as in the case of a normal semiconductor device singulation process, using a dicing saw, the protective film 11 and the single crystal silicon layer 3 (including the P-type high concentration layer 17 when the P-type high concentration layer 17 is not removed) are used. ) And the second support substrate 14 are cut and separated into individual pieces, whereby a semiconductor device can be formed.

  Since the semiconductor device thus formed has a structure in which the insulating second support substrate 14 is bonded to the single crystal silicon layer 3 instead of the semiconductor substrate 1, for example, the MOS type transistor shown in FIG. In this case, the capacitance between the source region 5 and the second support substrate 14 or the capacitance between the drain region 6 and the second support substrate 14 is made smaller than the substrate capacitance leaving the semiconductor substrate. be able to. Furthermore, since the capacitance between the wiring layer 10 and the second support substrate 14 can be greatly reduced, an improvement in high frequency characteristics is expected. There is also an advantage that an inexpensive semiconductor substrate can be used.

  The first to third embodiments of the present invention have been described above. However, the first support substrate and the second support substrate used in the present invention are not limited to those used in the above embodiments. What is necessary is just to select suitably, For example, it can use combining a film-form resin, a glass plate, a ceramic plate, a metal plate, etc. Also, the bonding method may be appropriately selected in consideration of the material of the selected support substrate.

  The combination of semiconductor layers having different impurity concentrations or conductivity types is not limited to the above embodiment. Furthermore, it is possible to stack semiconductor layers having the same conductivity type but different impurity concentrations on a semiconductor substrate substrate, and to remove the substrate and the semiconductor layer, respectively. Furthermore, a semiconductor substrate in which a semiconductor layer (for example, an epitaxial layer) is formed on a semiconductor substrate without using a semiconductor layer or an insulating layer having different conductivity types may be used. In that case, when removing the substrate, it is necessary to appropriately select a method for uniformly removing the substrate.

  Next, a fourth embodiment will be described. In the first to third embodiments, the case where the electrodes of the semiconductor element are connected by the wiring layer as shown in FIGS. 2, 4, and 6 has been described. The present invention may have a structure in which electrodes of a semiconductor element are connected by a wiring layer, and further bump electrodes are connected to the wiring layer. That is, the present invention can use a substrate prepared for forming a wafer level chip size package. Specifically, a semiconductor substrate in which bump electrodes are formed in a region (not shown) of the semiconductor substrate shown in FIGS. 2, 4, and 6 and a resin layer (not shown) is formed on the surface of the semiconductor substrate is used. A resin layer (not shown) covers the surface of the semiconductor substrate and exposes a part of the bump electrode. When a semiconductor device is formed by the manufacturing method of the present invention using a semiconductor substrate having such a structure, the semiconductor device after separation is a wafer level chip size package, which is improved in performance, size, and thickness. A semiconductor device can be formed. In addition, after removing the first support substrate and exposing the surface of the semiconductor substrate, it is possible to add a step of forming a solder bump on the bump electrode. Furthermore, when the first support substrate is removed, if the bump electrode is not exposed by being covered with a resin, a step of removing the resin and exposing the bump electrode can be added.

It is explanatory drawing of the 1st Example of this invention. It is sectional drawing of the MOS type transistor formed in the semiconductor substrate used in the 1st Example of this invention. It is explanatory drawing of the 2nd Example of this invention. It is sectional drawing of the vertical double diffusion MOS type transistor formed in the semiconductor substrate used in the 2nd Example of this invention. It is explanatory drawing of the 3rd Example of this invention. It is sectional drawing of the MOS type transistor formed in the semiconductor substrate used in the 3rd Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1; Semiconductor substrate, 2; Embedded silicon oxide layer, 3 single-crystal silicon layer, 4; LOCOS oxide film, 5; Source region, 6; Drain region, 7: Gate electrode, 8: Source electrode, 9; Wiring layer 11 protective film 12 adhesive resin 13 first support substrate 14 second support substrate 15 body region 16 source body electrode 17 P-type high concentration layer

Claims (6)

Preparing a semiconductor substrate having a semiconductor element formed on the surface of the semiconductor layer laminated on the substrate;
Attaching a first support substrate to the semiconductor layer surface;
Leaving at least the semiconductor layer on which the semiconductor element is formed, removing the substrate, or part of the substrate and the semiconductor layer;
Attaching a second support substrate to the exposed semiconductor layer;
After removing the first support substrate and exposing the surface of the semiconductor layer, the semiconductor layer and the second support substrate are cut, and the semiconductor element is formed on the second support substrate A method of manufacturing a semiconductor device, comprising the step of separating the semiconductor device to which the layer is bonded. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor layer includes a first semiconductor layer having an impurity concentration higher than that of the semiconductor substrate and a second semiconductor layer having an impurity concentration lower than that of the first semiconductor layer stacked on the first semiconductor layer. Preparing a semiconductor substrate on which the semiconductor element is formed on the surface of the semiconductor layer,
The substrate, or the substrate and the first semiconductor layer, or the substrate, the first semiconductor layer, and a part of the second semiconductor layer, leaving at least the second semiconductor layer on which the semiconductor element is formed And a step of removing the semiconductor device. The method of manufacturing a semiconductor device according to claim 2.
The semiconductor layer includes a P-type semiconductor layer having a higher impurity concentration than the semiconductor substrate and an N-type or P-type semiconductor layer having a lower impurity concentration than the P-type semiconductor layer stacked on the P-type semiconductor layer. A method for manufacturing a semiconductor device. Preparing a semiconductor substrate having a semiconductor element formed on the surface of the single crystal semiconductor layer laminated on the substrate via an insulating layer;
Attaching a first support substrate to the surface of the single crystal semiconductor layer;
Leaving at least the single crystal semiconductor layer on which the semiconductor element is formed, removing the substrate, or the substrate and the insulating layer, or part of the substrate, the insulating layer, and the single crystal semiconductor layer;
A step of attaching a second support substrate to the exposed insulating layer or the single crystal semiconductor layer;
After removing the first support substrate and exposing the surface of the single crystal semiconductor layer, the single crystal semiconductor layer, the insulating layer and the second support substrate, or the single crystal semiconductor layer and the second crystal The single crystal semiconductor layer in which the support substrate is cut and the semiconductor element is formed on the second support substrate through the insulating layer, or the single crystal in which the semiconductor element is formed on the second support substrate A method of manufacturing a semiconductor device, the method including: a step of dividing the semiconductor device into a semiconductor device to which the semiconductor layer is bonded. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the semiconductor substrate is a semiconductor substrate in which a single crystal silicon layer is stacked over a semiconductor substrate with a silicon oxide layer interposed therebetween. In the manufacturing method of the semiconductor device in any one of Claims 1 thru | or 5,
The semiconductor device includes a wiring layer that connects electrodes of a plurality of semiconductor elements, a bump electrode that is connected to the wiring layer, and a resin layer that covers a part of the wiring layer and the bump electrode. A method of manufacturing a semiconductor device.

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