JP7202992B2 - Manufacturing method of microdisplay substrate - Google Patents

Description

The present invention relates to a method of manufacturing a microdisplay substrate.

Liquid crystal panels are generally used as display devices for televisions, personal computer displays, mobile terminals, and the like. Such a display device includes a device that projects an image, such as a projector, in addition to a device that allows the display panel to be viewed directly. Small display devices include a head-up display (HUD) and a head-mounted display (HMD). A head-mounted display that has been miniaturized as an eyeglass type is called smart glasses.

Small display devices, including projectors, use a small display device called a microdisplay, which is magnified so that it can be seen by the observer and projected onto a screen, or guided to the observer's field of view through a reflective member. are doing Among them, the head-mounted display is attracting attention as one of the wearable terminals because the information of the information terminal can be viewed hands-free. A head-mounted display is worn like spectacles and displayed near the eyes (see Patent Documents 1 and 2, for example). Therefore, miniaturization of the device itself is required.

A head-mounted display uses a small display device called a microdisplay. There are transmissive liquid crystal panels that control transmitted light with liquid crystals, and reflective liquid crystal panels that use liquid crystals to control the polarization direction of reflected light that is reflected by electrodes. There is a panel, a micromirror drive panel that controls the direction of the reflected light of the micromirror.

Each panel above refers to the components of a single panel, and in fact, a display device requires a light source, optical components for guiding light to the panel, and optical components for guiding the emitted light to the output side. . Since the transmissive liquid crystal panel emits the incident light in the same direction, the front and rear optical systems can be simplified, and the size of the display device can be made compact. A reflective liquid crystal panel outputs reflected light, but since the incident light and the reflected light are on the same plane with respect to the panel surface, it is necessary to separate the light with an optical component called a polarizing beam splitter (PBS). The size of the display device increases. A micromirror-driven panel also requires an optical component (for example, a total internal reflection prism (TIR prism)) to utilize reflected light, which increases the size of the display device.

Transmissive LCD panels have the same structure as direct-view LCD panels used in mobile devices such as LCD TVs and smartphones, but microdisplays have the number of pixels required for display in a size of 1 inch or less. Therefore, a very small pixel size is required. For example, when forming 640×480 pixels on a 0.3 inch diagonal panel, the width of one pixel is about 10 μm, and when forming 1280×720 pixels on a 0.2 inch diagonal panel, The width of one pixel is 3.5 μm, and the size of the display portion is 4.4×2.5 mm. The latter is the size required to display high-definition image quality on smart glasses, and has very small pixels. In order to build a pixel circuit of this size, it is limited to a semiconductor manufacturing process that uses single crystal silicon (hereinafter also referred to as single crystal Si). This is not possible with the manufacturing process used.

A liquid crystal panel using single-crystal Si is called LCOS (Liquid Crystal On Silicon), which is distinguished from a normal liquid crystal display (LCD). When manufacturing a pixel circuit from single crystal Si, a Si substrate or an SOI (Silicon on Insulator) substrate is usually used. However, since Si does not transmit light, it cannot be used as a display device as it is. SOQ (Silicon on Quartz) substrates, in which a single-crystal Si film is formed on a quartz glass substrate, are ideal for microdisplays because small transistors can be produced and light can pass through areas without pixel circuits. . However, it is necessary to deal with a substrate that transmits light, and a semiconductor process simply using single-crystal Si cannot be used. For this reason, it is necessary to form the pixel circuits using a Si or SOI substrate and then make the portions other than the circuits light-transmissive.

A method of forming a pixel circuit on an SOI substrate, bonding the circuit portion to a transparent substrate with an adhesive, and then removing the SOI substrate to fabricate a pixel circuit substrate is described (see, for example, Patent Document 3). reference). By doing so, it is possible to use a normal semiconductor processing apparatus, and it is possible to form a compact and high-performance circuit, which can be used for a transmissive liquid crystal panel.

It is known that when a circuit is formed on a light-transmissive substrate, the transistor is also exposed to light, causing a light leak current to flow and affect the characteristics of the transistor. This is remarkable in amorphous Si, and it is also known that the effect can be reduced by increasing the crystallinity and changing the structure of the transistor. Patent Document 3 discloses forming a light shielding layer to solve the problem.

Japanese Patent No. 5678460 JP 2010-32997 A U.S. Pat. No. 5,256,562

As noted above, it is conceivable to use SOQ substrates to fabricate microdisplay substrates, but SOQ substrates present two problems in using conventional semiconductor processing equipment. First, because it is light transmissive, it will not be detected by sensors that use light to check for the presence or absence of the substrate. Another problem is that the electrostatic chuck used in the semiconductor process equipment cannot be used for adsorption. Because of these problems, modification of the semiconductor process equipment is required, and it is not possible to directly apply this to all semiconductor process equipment. At present, semiconductor processing equipment specially adapted to form circuits on SOQ substrates is limited to substrates with a small diameter, for example, an outer diameter of 150 mm. has the problem of not being able to handle

In order to use a semiconductor process with a large diameter, it is necessary to use a Si substrate or an SOI substrate, and the method disclosed in the aforementioned Patent Document 3 can be considered. When an SOI substrate is used, the Si substrate on the back side is ground to be thin, the embedded oxide film is used as an etching stop layer, and the remaining Si portion is etched to leave only the circuit layer. However, since SOI substrates are more expensive than Si substrates, it may be difficult to meet the cost reduction requirements of microdisplays. On the other hand, when a Si substrate is used, the dimensional accuracy of grinding and polishing is several percent, so processing that leaves only the circuit layer (for example, 1 μm thick) is impossible. The normal substrate thickness is 775 μm for a wafer with a diameter of 300 mm, and if the thickness accuracy is ±0.5%, a variation of ±4 μm occurs when grinding 770 μm, and it is difficult to leave only a circuit layer of about 1 μm. be.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a microdisplay substrate at low cost using a large-diameter substrate process.

The inventors of the present invention have devised a method for separating a circuit portion that is difficult to separate by grinding or ordinary Si etching by using an inexpensive Si substrate without using an expensive SOI substrate, and completed the present invention. reached.

Thus, the present invention, according to one embodiment, is a method of manufacturing a microdisplay substrate, comprising:
(i) On a P-type Si substrate, a low-resistivity P-type Si layer with an electrical resistivity of 0.001 Ω·cm or less and a high-resistivity P-type Si layer with an electrical resistivity of 10 Ω·cm or more are epitaxially grown in this order. forming a first substrate by
(ii) forming a circuit layer on the surface of the high resistance P-type Si layer of the first substrate;
(iii) bonding a second substrate with an adhesive to the surface of the first substrate on which the circuit layer is formed;
(iv) thinning the first substrate to expose the circuit layer;
(v) bonding a third substrate, which is a transparent substrate, to the thinned first substrate;
(vi) removing the second substrate from the first substrate bonded to the third substrate;
(vii) removing the adhesive on the surface of the first substrate from which the second substrate has been separated to expose the surface of the circuit layer;

According to another embodiment of the present invention, there is provided a transmissive microdisplay substrate having a circuit layer laminated on a transparent substrate via an adhesive layer or an oxide layer, wherein the circuit layer is an active a layer, a gate layer, and a wiring layer, wherein the wiring layer is provided in a positional relationship that shields the active layer and the gate layer from incident light from the opposite side of the transparent substrate, and the wiring layer serves as a light shielding layer. It relates to a transmissive microdisplay substrate, forming.

According to the manufacturing method of the present invention, a microdisplay substrate can be manufactured using a relatively inexpensive silicon substrate and using a process for a large-diameter substrate. In addition, the microdisplay substrate used for transmissive liquid crystal panels does not require a separate step of forming a light-shielding layer made of metal such as aluminum, which has conventionally been essential for avoiding exposure of transistors to light. can be obtained. The microdisplay substrate obtained by this manufacturing method is free from the influence of light leak current and can exhibit good operation as a transmissive liquid crystal panel.

FIG. 1 is a diagram schematically showing a process according to a first aspect of a method for manufacturing a microdisplay substrate according to a first embodiment of the invention. FIG. 2 is a diagram schematically showing the cross-sectional structure of the first substrate according to the present invention. FIG. 3 is a diagram schematically showing a cross-sectional structure of a pixel circuit in the microdisplay substrate of the invention. FIG. 4 is a diagram schematically showing the structure of a liquid crystal panel. FIG. 5 is a schematic diagram of an active matrix. FIG. 6 is a diagram schematically showing an example of the circuit layout of the liquid crystal panel. FIG. 7 is a diagram schematically showing an example of circuit arrangement on a pixel substrate.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited by the embodiments described below.

[First Embodiment: Microdisplay Substrate Manufacturing Method]
The present invention, according to a first embodiment, relates to a method for manufacturing a microdisplay substrate. The manufacturing method includes the following steps (i) to (vii).
(i) On a P-type Si substrate, a low-resistivity P-type Si layer with an electrical resistivity of 0.001 Ω·cm or less and a high-resistivity P-type Si layer with an electrical resistivity of 10 Ω·cm or more are epitaxially grown in this order. (ii) forming a circuit layer on the surface of the high-resistance P-type Si layer of the first substrate; (iii) bonding to the surface of the first substrate on which the circuit layer is formed; (iv) thinning the first substrate to expose the circuit layer; (v) attaching a third transparent substrate to the thinned first substrate; (vi) removing the second substrate from the first substrate bonded to the third substrate (vii) removing the adhesive on the surface of the first substrate from which the second substrate has been separated; Removing and exposing the circuit layer surface

A microdisplay substrate obtained by the manufacturing method according to the first embodiment of the present invention will be described. The microdisplay substrate includes an active layer, a gate layer, a wiring layer, and optionally a pixel electrode. The circuit layer is formed on a transparent substrate. be done. FIG. 1 is a diagram schematically showing a process according to a first aspect of a method for manufacturing a microdisplay substrate according to a first embodiment of the invention. A microdisplay substrate obtained by the process according to the first aspect is illustrated in FIG. there is The circuit layer 113' includes active layers, gate layers and wiring layers, and may optionally include pixel electrodes and protective films. Also, in the microdisplay substrate obtained by the process according to the second aspect of the present embodiment, a circuit layer is formed on the third substrate, which is a transparent substrate, via an oxide film layer (not shown). The definition of the circuit layer is the same as for the microdisplay substrate according to the first aspect. In the microdisplay substrate according to the second aspect, preferably the oxide film layer in contact with the circuit layer is directly bonded to the transparent substrate without an adhesive layer interposed.

These microdisplay substrates can be combined with a substrate having a counter electrode formed thereon, cut into panel sizes, and filled with liquid crystal to form a liquid crystal panel. A schematic structure of such a liquid crystal panel is shown in FIG. In FIG. 4, a layer composed of a pixel electrode 34, a circuit 33 including a transistor region and a wiring layer made of a high-resistance P-type Si layer, an adhesive layer 17, and a third substrate 13 is a pixel substrate. The substrate constitutes the microdisplay substrate 20 . In the liquid crystal panel 30 shown in FIG. 4, a counter electrode 37 and a counter substrate 38 are arranged on the pixel electrode 34 side of the microdisplay substrate 20 with spacers 36 interposed therebetween. A liquid crystal 35 is filled between the counter electrode 37 and the pixel electrode 34 . A first deflection plate 31a is provided on the main surface of the opposing substrate 38 opposite to the opposing electrode 37, and a second deflection plate 31b is provided on the main surface of the microdisplay substrate 20 on the third substrate side. Such a liquid crystal panel 30 constitutes a microdisplay in combination with a light source (not shown). At this time, the direction of the light R ₁ emitted from the light source and the light R ₂ transmitted through the liquid crystal panel 30 is limited to the direction from the first polarizing plate 31a to the second polarizing plate 31b. Although FIG. 4 exemplifies a microdisplay substrate provided with an adhesive layer 17 according to the first embodiment described in detail below, the microdisplay substrate of the present invention is mirror-polished instead of the adhesive layer 17. It may be a microdisplay substrate according to the second aspect comprising an oxide layer.

A circuit pattern is formed on the pixel substrate. FIG. 6 is a diagram conceptually showing a circuit pattern. The circuit pattern 40 includes a pixel portion 41, a column selection circuit 42a, and a row selection circuit 42b. The pixel portion 41 in FIG. 6 becomes the portion through which light passes in FIG. 4, and the column selection circuit 42a and the row selection circuit 42b around it become the peripheral circuit 33b in FIG. A transistor region made of single-crystal Si and a wiring layer connected thereto become the pixel circuit 33a in FIG. In FIG. ₄ , the light R3 passes through a portion where the pixel circuit 33a does not exist, that is, between two adjacent pixel circuits 33a.

The circuit pattern 40 shown in FIG. 6 is arranged over the entire surface of the pixel substrate. FIG. 7 is a diagram conceptually showing a substrate on which a circuit pattern is arranged (formed) over the entire surface. For example, a plurality of circuit patterns 40 can be formed by arranging a plurality of them on the entire surface of one substrate 11 having an orientation flat 51 on a part of the outer edge. A circuit 40 comprising a pixel circuit 41 and peripheral circuits 42a and 42b corresponds to one liquid crystal panel. As shown in FIG. 7, many panels can be fabricated from one substrate.

FIG. 5 is a diagram for explaining the outline of the circuit in the circuit pattern 40 shown in FIG. FIG. 5(a) shows an outline of the circuit of the active matrix driving system, and FIG. 5(b) is an enlarged schematic view of part A in FIG. 5(a). In FIG. 5A, a plurality of column selection signal lines Cl (also called data lines) connected from the column selection circuit 42a to the source of the pixel circuit are arranged in the vertical direction, and from the row selection circuit 42b to the gate of the pixel circuit. A plurality of connected row selection signal lines R are arranged in the horizontal direction. Then, referring to FIG. 5(b), a thin film transistor (field effect transistor) is provided at the intersection A thereof, and the source of the thin film transistor is connected to the column selection signal line Cl, and the gate is connected to the row selection signal line R. A liquid crystal electrode L and an auxiliary capacitor (transistor or capacitor) Ca are connected to the drain. The column selection circuit 42a is a first wiring layer made of metal, and the row selection signal line R is made of polysilicon, forming a gate layer.

Next, referring to FIG. 3, the cross-sectional structure of the circuit layer will be schematically described. FIG. 3 is a schematic cross-sectional view of a portion corresponding to the circuit 33 and the pixel electrode 34 in FIG. The circuit 33 includes an active layer 21 fabricated by implanting impurities into a high-resistance P-type Si layer 113, a gate layer 22 fabricated by depositing polysilicon, a first wiring layer 23, and a second wiring layer 24. , are provided in this order. The active layer 21 and the gate layer 22 are collectively referred to as a transistor region. Each layer is insulated by an insulating film 26, and a contact hole for electrically connecting these layers is opened to form a wiring 25 in which a metal is embedded. A transparent electrode, which is a pixel electrode 34, is provided on the surface of the second wiring layer 24 opposite to the transistor region. A layer including the pixel electrode 34 may be called a circuit layer. In the figure, _R1 indicates the light emitted from the light source and incident on the circuit 33, _R2 indicates the light transmitted through the circuit 33, and its direction is from the pixel electrode 34 toward the transistor area. The first wiring layer 23 and the second wiring layer 24 shield the active layer 21 and the gate layer 22 in the transistor region from the incident light _R1 . That is, the region where the first wiring layer 23 and the second wiring layer 24 exist becomes the light shielding portion S, and the region where the first wiring layer 23 and the second wiring layer 24 do not exist becomes the light transmission region T. FIG. The light shielding portion S corresponds to one pixel circuit, and in the figure, 22a corresponds to the row selection signal line, 23a corresponds to the column selection signal line, and 24a corresponds to the ground (GND). P indicates a pixel selection circuit region, and C indicates an auxiliary capacitance region for applying charge to the liquid crystal.

In the circuit 33, the first wiring layer 23 and the second wiring layer 24 are metal layers, and these portions do not transmit light. In the illustrated embodiment, the wiring layer is composed of two layers, the first wiring layer and the second wiring layer, but the present invention is not limited to this embodiment. The number of wiring layers may be three or more. By arranging the wiring layers 23 and 24 so as to cover the active layer 21 and the gate layer 22 in the transistor area as shown in FIG. 3, the transistor area can be shielded from light by hiding the transistor area. With such a structure, there is no need to separately form a light shielding layer, and the cost can be reduced. As shown in FIGS. 3 and 4, the light is applied from the pixel electrode 34 side toward the transistor region. That is, the directions of the incident light _R1 and the transmitted light _R2 are limited to the illustrated directions, and it is sufficient to block the light in these directions.

Such an arrangement for hiding the transistor region is such that, in a plan view from the incident light _R1 side of the circuit 33 in which the active layer 21, the gate layer 22, the first wiring layer 23, and the second wiring layer 24 are superimposed, the first This can be realized by designing the layout so that the transistor region cannot be viewed from above by the wiring layer 23 and the second wiring layer 24, and manufacturing according to the design. At this time, in the plan view of the circuit 33 from the side of the incident light _R1 , even if the line indicating the outer edge of the wiring layer and the line indicating the outer edge of the transistor region overlap, the "hidden arrangement" can be said. can. Also, in the plan view of the circuit 33 from the side of the incident light _R1 , if the wiring layer protrudes outside the outer edge of the transistor region, it can be said to be a hidden arrangement. When a plurality of wiring layers hide the transistor region together, even if there is a portion where the first wiring layer and the second wiring layer overlap when a plan view from the incident light _R1 side is created, Often, a line indicating the outer edge of the first wiring layer and a line indicating the outer edge of the second wiring layer overlap to form a boundary between the first wiring layer and the second wiring layer, and also form a boundary between the first wiring layer and the second wiring layer. The wiring layer may be integrated with the transistor region to shield the transistor region from the incident light _R1 .

[Method for producing a microdisplay substrate according to the first aspect]
A method of manufacturing a microdisplay substrate according to the first aspect of the present invention will now be described with reference to FIG. FIG. 1 is a diagram schematically showing a manufacturing method according to the present invention. The operation steps will be described below. In carrying out the manufacturing method according to the present embodiment, a third substrate shown in FIG. 1(c) and a second substrate shown in FIG. 1(d) are prepared.

The third substrate 13 shown in FIG. 1(c) is a substrate to which the circuit layer is finally transferred, and is a colorless and transparent substrate because it is necessary to transmit light as a microdisplay. The colorless and transparent substrate in the present invention means a substrate having a transmittance of 80% or more, preferably 90% or more, for visible light having a wavelength of approximately 400 to 700 μm. As the third substrate 13, quartz glass may be used, or alkali-free glass or optical glass used in normal liquid crystal panels may be used.

The second substrate 12 shown in FIG. 1D is a substrate that is temporarily bonded to the first substrate. It is desirable that the second substrate 12 and the third substrate 13 are made of the same material. This is to prevent the generation of thermal stress during heat curing of the adhesive when the third substrate 13 is adhered. Also, the outer diameter of the second substrate 12 is preferably substantially the same as the outer diameter of the third substrate 13, and more preferably the same. This is for the purpose of facilitating positioning when bonding the third substrate, and for uniforming the pressure during bonding. If the outer diameters of the second substrate and the third substrate are different, it is necessary to provide a positioning mechanism for that purpose, or prepare a jig for applying pressure to the area where the second substrate and the third substrate do not overlap. It may be a factor that deteriorates the quality of adhesion.

(i) Step of Forming First Substrate Step (i) is a step of forming the first substrate 11a shown in FIG. 1(a). Referring to FIG. 2, the first substrate 11a includes a P-type Si substrate 111, a low-resistivity P-type Si epitaxial layer 112 with an electrical resistivity of 0.001 Ω·cm or less, and a high-resistivity P-type Si epitaxial layer 112 with an electrical resistivity of 10 Ω·cm or more. This is the substrate on which the type Si epitaxial layers 113 are laminated in this order. Note that FIG. 2 is a schematic cross-sectional view, and the thickness ratio of each layer is not limited to the illustrated ratio. The low-resistance P-type Si epitaxial layer 112 with an electrical resistivity of 0.001 Ω·cm or less is sometimes referred to as a P+ layer in this specification. Also, the high resistance P-type Si epitaxial layer 113 having an electrical resistivity of 10 Ω·cm or more is sometimes referred to as a P layer in this specification.

The P-type Si substrate 111 preferably has a diameter of 300 mm and a thickness of 775 μm from the viewpoint of the number of panels to be obtained and the cost of the process. However, the substrate is not limited to this, and a substrate having a diameter of 200 mm and a thickness of 725 μm may be used, or any other substrate may be used. The P-type Si substrate 111 may also be referred to as the back silicon layer of the first substrate 11a.

The low-resistance P-type Si epitaxial layer 112 may be a layer in which epitaxially grown single-crystal Si is doped with an impurity selected from boron (B), aluminum (Al), and gallium (Ga). It is a layer of 0.001Ω·cm or less. This is because it is removed by etching with a mixed acid, which will be described later.

The high-resistance P-type Si epitaxial layer 113 may be a layer obtained by doping epitaxially grown single-crystal Si with an impurity selected from boron (B), aluminum (Al), and gallium (Ga). It is a layer of 10Ω·cm or more. In particular, it is preferable that the electrical resistivity is 10 to 20 Ω·cm. The thickness of the high-resistance P-type Si epitaxial layer 113 can be appropriately determined by those skilled in the art according to circuit design and process conditions. The high-resistance P-type Si epitaxial layer 113 may also be referred to as the surface layer of the first substrate 11a.

The first substrate 11a can be formed by epitaxially growing a low-resistance P-type Si layer 112 and a high-resistance P-type Si layer 113 on a P-type Si substrate 111 in this order. _The conditions for epitaxially growing the layers 112 and 113 are not particularly limited, and can be appropriately carried out by those skilled in the art based _on general conditions. By changing it, the resistivity can be changed.

(ii) Step of Forming Circuit Layer In step (ii), a circuit layer 113′ is formed on the first substrate 11a shown in FIG. 1(a) using a semiconductor process. Formation of the circuit layer 113' can be carried out by a method commonly used in semiconductor processes. Specifically, the active layer 21 is formed by implanting impurities into the high-resistance P-type Si epitaxial layer 113 (P layer), which is the surface layer of the first substrate 11a, and polysilicon is formed on the active layer 21. A circuit 33 is formed by including a step of forming a gate layer 22 by film forming and a step of forming a first wiring layer 23 and then a second wiring layer 24 . A configuration example of the active layer 21, the gate layer 22, the first wiring layer 23, and the second wiring layer 24 is shown in FIG. After fabrication of the circuit 33, a transparent electrode forming the pixel electrode 34, typically an ITO (Indium Tin Oxide) layer, can be formed and patterned. Since the ITO film requires film formation at a high temperature or heat treatment after film formation in order to increase characteristics such as resistance, it is desirable to form the circuit 33 on the first substrate. The circuit 33 and optionally the pixel electrode 34 can be referred to as a circuit layer 113', and the step of forming the ITO film can also be included in the step of forming the circuit layer 113'. Optionally, a protective film can be formed on the pixel electrode 34 layer after this step. This is because damage in subsequent steps can be prevented. The protective film is preferably formed of a photoresist used for transistor fabrication. This is because the pixels to be fabricated are as small as several μm and the grooves between the ITO electrodes are 1 μm or less, so that the protective layer can be reliably removed from the grooves. Formation of the protective film can also be carried out during application of the adhesive prior to bonding.

As for the structure of the circuit 33, the first wiring layer 23 and the second wiring layer 24 of the pixel cover the transistor area as described above. By doing so, it is not necessary to form a light shielding film between the pixel electrode 34 and the circuit 33 after the circuit 33 is formed, and the process can be simplified and the yield can be improved. If the light shielding film is separately formed, it is necessary to pattern the light shielding film after forming the circuit 33 and before forming the transparent electrode which is the pixel electrode 34 . In this case, the contact portion that electrically connects the circuit 33 and the pixel electrode 34 on the surface layer needs to be provided so as to pass through the light shielding film, which complicates the design and the patterning process of the light shielding film. FIG. 1(b) is a diagram schematically showing a first substrate 11b on which a circuit layer 113' including circuits and pixel electrodes is formed.

(iii) Step of bonding the second substrate to the first substrate In the step (ii), the second substrate is attached to the circuit layer-formed surface of the circuit layer-formed first substrate 11b using an adhesive. Paste. Since this step is a step of temporarily bonding the second substrate to the first substrate for the grinding step of the first substrate in the subsequent step (iv), it can also be called a temporary bonding step.

In this step, an adhesive that can withstand grinding in the subsequent step (iv) and that can be removed after bonding to the third substrate in step (v) described below is selected. As the temporary bonding adhesive 16, an adhesive that is resistant to the chemical solution during grinding and can be easily peeled and separated can be used. Although the adhesive 16 for temporary joining can be used, it is not limited to these. As a specific example of the former, WSS (manufactured by 3M) can be used. Specific examples of the latter include TA1070T/TA2570V3/TA4070 (manufactured by Shin-Etsu Chemical Co., Ltd.). TA1070T can function as an adhesive layer for circuit protection, TA2570V3 can function as an adhesive layer that serves as a peeling surface, and TA4070 can function as an adhesive layer with the second substrate 12 . In particular, it is preferable to use the latter temporary bonding adhesive 16 whose main component is the thermosetting modified silicone because of its resistance to chemicals.

In this step, the surface of the first substrate 11b on which the circuit layer is formed and/or one main surface of the second substrate 12 is applied with a temporary bonding adhesive 16 by a spin coating method. Temporary bonding can be performed by coating to about 100 μm and depending on the usage conditions of the temporary bonding adhesive 16 to be used, for example, by UV irradiation or heating. It is preferable to apply so as to cover not only the surface on which the circuit layer is formed, but also the side surfaces of the circuit layer and the side surfaces of the low-resistance P-type Si epitaxial layer 112 . As a result, the joined body shown in FIG. 1(e) is obtained.

(iv) Thinning step In this step, the P-type Si substrate layer (back surface silicon layer) 111 and the low-resistance P-type Si layer 112 of the first substrate 11b are ground and thinned in the bonded body obtained in the step (iii). This includes a step of exposing the low-resistance P-type Si layer 112 and a step of etching away the low-resistance P-type Si layer 112 remaining after the grinding and thinning step.

In the grinding thinning process, for example, the P-type Si substrate 111 and the low-resistance P-type Si layer 112 can be thinned by combining different types of grindstones for processing.

Then, the low-resistance P-type Si layer 112 (P+ layer) thinned by grinding and exposed is selectively etched. The etching solution used is a mixed acid of hydrofluoric acid (HF) with a concentration of 49% by weight or more, nitric acid (HNO ₃ ) with a concentration of 60% by weight or more, and acetic acid (CH ₃ COOH) with a concentration of 98% by weight or more. The ratio of acid:nitric acid:acetic acid can be 1:2-4:7-9. This is a mixed acid obtained by mixing hydrofluoric acid with nitric acid in a volume ratio of 2 to 4 times and acetic acid in a volume ratio of 7 to 9 times. More preferably, the volume ratio is hydrofluoric acid:nitric acid:acetic acid=1:2.5-3.5:7.5-8.5, and more preferably the volume ratio of hydrofluoric acid:nitric acid:acetic acid. is approximately 1:3:8.

Regarding etching of silicon (Si), it is known that the etching rate varies depending on the resistivity of Si. For example, Japanese Patent Application Laid-Open No. 08-139297 discloses an etching rate with respect to the impurity amount of Si, that is, the so-called dopant amount. Further, Japanese Patent Application Laid-Open No. 05-082535 discloses etching rates for both dopant amount and resistivity. From these disclosures, by using a mixed acid with a composition of hydrofluoric acid: nitric acid: acetic acid = 1:3:8, it is not etched at 0.07 Ω cm or more, and the etching rate is high at a low resistance of 0.07 Ω cm or less. understood. The applicant of the present invention investigated whether it is possible to separate circuit layers by using the difference in etching rate due to this resistivity, and provided a low-resistance P-type Si layer 112 on a P-type Si substrate 111, and formed a circuit thereon. By using the first substrate 11 provided with the high resistance P-type Si layer 113 forming the , the low resistance Si layer of the intermediate layer can be removed with the mixed acid to separate the circuit layer.

The thickness of the low-resistance P-type Si layer 112 removed by selective etching is set to a thickness controllable range by grinding, that is, a thickness that does not expose the circuit layer 113' due to over-grinding. Specifically, the thickness can be set in the range of 20 to 100 μm, but is not limited to a specific thickness. The etching time is set according to the thickness of the low-resistance P-type Si layer 112 remaining after grinding, variations in removal during grinding, and a margin. Since the etching rate varies depending on the resistivity, the etching rate of the low-resistance P-type Si layer 112 (P+ layer) can be experimentally obtained, and the etching time can be set by calculation from the etching rate and the removal amount.

This selective etching with mixed acid can completely remove the low resistance P-type Si layer 112 (P+ layer) under the circuit layer 113' to expose the circuit layer 113'. By bonding the circuit layer 113' and the transparent substrate, which is the third substrate 13, it is possible to form a pixel portion that transmits light. FIG. 1(f) schematically shows a joined body of the thinned first substrate 11c (circuit layer 113') and the second substrate 12 obtained by this step.

(v) Step of Bonding Third Substrate In step (v), the third substrate 13 is bonded to the first substrate 11c (circuit layer 113') thinned in the previous step (iv). In the method of manufacturing a microdisplay substrate according to the first aspect, lamination can be performed using an adhesive. The adhesive used in this step can also be called a transfer adhesive 17 . The transfer adhesive 17 is desirably made of a material that is translucent in the visible light range, and is preferably an epoxy-based adhesive. The translucency in the region of visible light as used herein may be the same as the definition of transparency of the transparent substrate defined above. In order not to cause stress deformation of the device after transfer, it is preferable to use a low-stress adhesive as the transfer adhesive 17, and the thickness of the adhesive layer after curing is 0.1 to 5 μm or less. It is more preferable to adhere as follows. As such a transfer adhesive 17, it is particularly preferable to use thermosetting epoxy-modified silicone. By using such a transfer adhesive 17, it is possible to perform transfer that is translucent in the visible light region, has low stress, and is excellent in heat resistance. The transfer adhesive 17 can be applied to the exposed circuit layer 113′ of the thinned first substrate 11c or to the third substrate (transfer substrate) side. is more preferable. FIG. 1(g) schematically shows a bonded body of the second substrate 12, the circuit layer 113' (thinned first substrate 11c), and the third substrate 13 obtained by this step.

(vi) A step of removing the second substrate from the first substrate Next, the temporarily bonded second substrate 12 is separated and removed from the circuit layer 113' (the thinned first substrate 11c) (FIG. 1(h)). ). Separation of the second substrate 12 and the circuit layer 113' (the thinned first substrate 11c) is performed by applying a force F to both the second substrate 12 and the third substrate 13 to separate the first substrate 11 and the second substrate 13'. A blade 18 is inserted into the transfer adhesive 17 portion of the bonding surface of 12 to form an opening, and further a separating force F is continuously applied to separate both at the transfer adhesive 17 portion. be able to.

(vii) Step of exposing circuit layer surface In step (vii), the residue of the transfer adhesive 17 on the surface of the circuit layer 113′ (thinned first substrate 11c) from which the second substrate 12 has been separated is removed with an organic solvent. This is the step of removing. The organic solvent can be appropriately selected by those skilled in the art depending on the type of the transfer adhesive 17. For example, when using the transfer adhesive 17 mainly composed of thermosetting epoxy-modified silicone, p-menthane Organic solvents such as can be used. In this way, the circuit layer of the microdisplay can be transferred to the third substrate 13 to produce the microdisplay substrate. FIG. 1(i) is a diagram schematically showing the obtained microdisplay substrate 20. FIG.

According to the method for manufacturing a microdisplay substrate according to the first aspect, an inexpensive Si substrate is used, the circuit portion can be separated without increasing the accuracy of the grinding process, and an inexpensive and high-performance transmissive micrometer is used. A display substrate can be manufactured. In particular, by using the transfer adhesive 17 for bonding the third substrate 13, it is possible to secure the required light transmittance with a small number of steps and obtain a cost-effective microdisplay substrate. There is

[Method for producing a microdisplay substrate according to the second aspect]
Next, a method for manufacturing a microdisplay substrate according to the second aspect of this embodiment will be described. In a method of manufacturing a microdisplay substrate according to the second aspect, the steps of (i) forming a first substrate, (ii) forming a circuit layer, (iii) laminating a second substrate to the first substrate, and ( iv) The step of thinning can be performed in the same manner as the method of manufacturing the microdisplay substrate according to the first aspect described with reference to FIG. 1, so description thereof will be omitted.

In the second aspect, the step (v) of bonding the third substrate is performed by direct bonding without using an adhesive, and includes the following steps.
(v-1) forming an oxide film on the bottom surface of the exposed circuit layer after removing the low-resistance P-type Si layer of the first substrate; (v-2) mirror-polishing the surface of the oxide film; (v-3) a step of directly bonding the surface of the third substrate to the mirror-polished oxide film surface;

(v-1) In the step of forming an oxide film, an oxide film is deposited at room temperature or low temperature on the bottom surface of the thinned and exposed circuit layer (main surface not in contact with the second substrate). The oxide film may be an oxide film of Si (SiO ₂ ). Specifically, the method of depositing the film may be a method that does not heat the substrate, and sputtering or low-temperature plasma CVD can be used. The deposited thickness of the oxide film may be about 300 to 700 nm, preferably about 400 to 600 nm, but is not limited to a specific thickness. This thickness is determined in consideration of the thickness of the oxide film removed by polishing and the thickness capable of planarizing the _SiO2 oxide film protruding from the active layer due to the manufacturing method of the previous step (ii). A person skilled in the art can determine it appropriately.

In the previous step (ii) forming the circuit layer, an oxide layer (SiO ₂ ) is formed between the actives to provide electrical isolation between the transistors. Methods for forming an oxide film for element isolation include a LOCOS (Local Oxidation of Silicon) method and an STI (shallow trench isolation) method, both of which require forming an oxide film thicker than the active layer of a transistor. Therefore, in the previous (iv) thinning step, the SiO ₂ oxide film protrudes from the active layer after removing the P+ layer. In the step (v-1) of the second aspect, an oxide film is formed so as to eliminate the step of the SiO ₂ portion protruding from the active layer and enable direct bonding. The protrusion of the _SiO2 oxide film from the active layer is several tens of nm. Therefore, in the case of the step (v) of bonding the circuit layer and the third substrate with the adhesive according to the first aspect, the adhesive can absorb the stepped portion, and the formation of an oxide film and polishing are unnecessary. can be

Next, in the step of (v-2) mirror polishing, the surface is mirror-finished by polishing the deposited oxide film. A specific polishing method includes, but is not limited to, a method using a slurry and a polishing cloth. Also, the degree of specular surface to be achieved is preferably 0.3 nm or less in terms of RMS (root mean square).

(v-3) In the step of bonding by direct bonding, the third substrate is bonded to the mirror-polished oxide film surface. Bonding is performed at room temperature, and bonding is started by lightly pressing a part, and can be completed by propagating over the entire surface. In addition, after bonding, it is preferable to apply heat treatment at 120 to 200° C. under normal pressure for about 20 to 30 hours. As a result, the circuit layer and the third substrate can be strongly bonded via the oxide film, and the second substrate, which is a temporary bonding substrate, can be peeled off in a subsequent step.

The direct bonding method according to the second aspect is advantageous in that it can improve light transmittance, especially in microdisplay substrates. Compared to the first mode, the present mode increases the cost by the amount of steps of forming an oxide film on the bottom surface of the circuit layer and polishing, compared to the above-described bonding using an adhesive. However, especially when manufacturing a liquid crystal panel with small pixels and a small area through which light is transmitted, increasing the amount of transmitted light according to this embodiment can reduce the size of the panel and add value.

[Second Embodiment: Transmissive Microdisplay Substrate]
The present invention, according to a second embodiment, relates to a transmissive microdisplay substrate. The transmissive microdisplay substrate is a transmissive microdisplay substrate in which a circuit layer is laminated on a transparent substrate via an adhesive layer or an oxide film layer, wherein the circuit layer comprises an active layer and a gate layer. , and a wiring layer, wherein the wiring layer is provided in a positional relationship to shield the active layer and the gate layer from incident light from the opposite side of the transparent substrate, and the wiring layer forms a light shielding layer. be.

The transmissive microdisplay substrate according to this embodiment is typically the microdisplay substrate 20 shown in FIG. It may be a microdisplay substrate manufactured by a manufacturing method according to embodiments. Since the structure and application have been described in the first and second aspects, the description is omitted here. The circuit layer may include a pixel electrode layer formed on the surface of the wiring layer opposite to the gate layer, and the pixel electrode layer may be a transparent electrode such as an ITO film. A transmissive microdisplay substrate can be used as a member of a microdisplay liquid crystal panel.

EXAMPLES The present invention will be specifically described below with reference to Examples, but the present invention is not limited to these.

(Example 1)
A microdisplay substrate was made by the manufacturing method shown in FIG. 1 according to the first aspect of the first embodiment of the present invention. A P-type Si substrate 111 having an outer diameter of 200 mm and a thickness of 725 μm and a resistivity of 15 Ω·cm is prepared, and a B-doped Si layer (P+ layer) 112 having a resistivity of 0.001 Ω·cm is epitaxially grown thereon to a thickness of 30 μm. formed by Further, a B-doped Si layer (P layer) 113 having a resistivity of 10 Ω·cm and a thickness of 250 nm was formed on the P+ layer 112 . The surface of this laminate was polished and washed to finish the thickness of the P layer 113 to 150 nm, thereby forming the first substrate 11a.

A circuit was formed by a semiconductor process on the surface Si layer (P layer, 150 nm) 113 of the first substrate 11a. Next, an ITO (Indium Tin Oxide) film is formed on the surface of the substrate on which the circuit is formed, and after the film formation, grooves are formed in the ITO film so as to separate the pixels, thereby fabricating the pixel electrode 34. Then, a first substrate 11b having a circuit layer 113' formed thereon was obtained.

As the second substrate 12 and the third substrate 13, the same synthetic quartz glass substrate having an outer diameter of 200 mm and a thickness of 725 μm was prepared. The adhesive used to temporarily bond the first substrate 11b and the second substrate 12 together was selected in consideration of workability when separating later and heat resistance during heat treatment after bonding the third substrate. . Here, TA1070T, TA2570V3, and TA4070 manufactured by Shin-Etsu Chemical Co., Ltd., which are thermosetting modified Si-based adhesives, were used. That is, on the first substrate 11b, TA1070T with a thickness of 10 μm, TA2570V3 with a thickness of 10 μm, and TA4070 with a thickness of 90 μm were laminated on the first substrate 11b by spin coating to obtain a total thickness of 110 μm. TA1070T functions as a protection layer for the circuit layer, TA2570V3 functions as a peeling layer at the time of substrate separation, and TA4070 functions as an adhesive layer with the second substrate. For bonding, after pressing the second substrate 12 against the first substrate 11b with a force of 0.1 MPa, the substrates are horizontally set in an oven with the jig attached, and heat-treated at 190° C. for 2 hours. It was carried out by curing the adhesive.

Next, the back surface of the first substrate 11b to which the second substrate 12 was temporarily bonded was ground with a grinding wheel using a polish grinder PG300 manufactured by Tokyo Seimitsu Co., Ltd. to reduce the thickness of the first substrate to 20 μm. After grinding, the remaining 20 μm of P+ layer was removed by immersion etching. The etching solution used was hydrofluoric acid with a concentration of 49% by weight, nitric acid with a concentration of 60% by weight or more, and acetic acid with a concentration of 98% by weight or more. . The etching rate was set to 1 μm/min, the removal amount was set to 25 μm, and the etching time was calculated to be 25 minutes. Based on the calculation results, the P+ layer 112 was etched by immersion in mixed acid for 25 minutes. After etching, it was confirmed that there was no Si residue in the active layer (Si layer)-free region of the circuit 113', and that the P+ layer 112 was completely removed.

Next, the third substrate 13 made of synthetic quartz glass was attached to the thinned first substrate 11c, exposing the circuit layer 113', with an adhesive. As the adhesive, TA4070, which is an epoxy-modified silicone adhesive, was diluted with cyclopentanone, and the concentration of the adhesive was adjusted to 0.5 wt %. This was spin-coated onto the third substrate 13 to form an adhesive layer with a thickness of 1 μm. The third substrate 13 coated with the adhesive was heat-treated at 150° C. for 5 minutes to remove the solvent and perform half-curing. The half-cured third substrate 13 and the thinned first substrate 11c were bonded using a wafer bonder SynapseSi manufactured by Tokyo Electron. The bonding was carried out by raising the temperature to 190° C., applying a load of 3 kgf/cm ² , and holding at 130° C. under vacuum for 10 minutes. After cooling, it was taken out to obtain a bonded substrate.

Next, the temporarily bonded second substrate 12 was separated. Using a dedicated peeling device, the back surface of the third substrate 13 (the surface not bonded to the thinned first substrate 11c) faces downward, and the back surface of the second substrate 12 (bonded to the thinned first substrate 11c) is placed downward. The second substrate 12 is placed on the adsorption stage so that the non-existent surface (the non-existent surface) faces upward, and in a state in which the third substrate 13 is adsorbed, a suction tool having a mechanism for lifting upward is attached to the back surface of the second substrate 12, and the second substrate 12 and the third substrate 12 are attached. A force F was applied in the direction of separating the substrates 13 from each other. While applying the force, the blade 18 was inserted into the adhesive layer 16 which is the interface between the thinned first substrate 11 c and the second substrate 12 . An opening was formed in a part of the adhesive by inserting the blade 18, and since a force was applied to separate the substrates from each other, the opening gradually widened and the separation proceeded. Finally, the second substrate 12 is separated from the thinned first substrate 11c and the portion adhered by the adhesive. At this time, the first substrate 11c thinned from the third substrate 13 was not separated.

After separation of the second substrate 12, the residue of the adhesive on the thinned first substrate 11c was removed by immersion in p-menthane of an organic solvent for 5 minutes. In the thinned first substrate 11c bonded to the third substrate 13, the interface bonded with the adhesive could not be visually confirmed, and the portion without the circuit was transparent.

A sealing adhesive is applied to the thus-obtained microdisplay substrate by screen printing, and a glass substrate having an ITO film formed on the entire surface, which is separately prepared as a counter substrate, is attached to form a predetermined gap. The sealing material was cured while maintaining the gap between the microdisplay substrate and the counter substrate as shown in FIG. After curing the sealing material, the bonded wafer was cut into individual panels by dicing to obtain panels. Liquid crystal was injected into the panel in vacuum to obtain a liquid crystal panel for microdisplay.

Polarizing plates were placed on both sides of the liquid crystal panel in the thickness direction, and the operation was confirmed. It worked normally, and a microdisplay substrate could be obtained by exposing the circuit layer by selective etching and bonding. No effect of light leakage current was observed.

(Example 2)
A microdisplay substrate was produced by the manufacturing method according to the second aspect of the first embodiment of the present invention. In addition, since the code|symbol is common to FIG.1(f) of the 1st mode, the 2nd mode will be demonstrated with reference to the code|symbol in FIG. 1 for convenience. A P-type Si substrate 111 having an outer diameter of 200 mm and a thickness of 725 μm and a resistivity of 15 Ω·cm is prepared, and a B-doped Si layer (P+ layer) 112 having a resistivity of 0.001 Ω·cm is epitaxially grown thereon to a thickness of 30 μm. A B-doped Si layer (P layer) 113 having a resistivity of 10 Ω·cm was formed thereon to a thickness of 250 nm. The surface of this substrate was polished and washed, and the thickness of the P layer was finished to 150 nm. The surface of this laminate was polished and washed to finish the thickness of the P layer 113 to 150 nm, thereby forming the first substrate 11a.

A circuit was formed on the surface Si layer (P layer, 150 nm) 113 by a semiconductor process. A film of ITO (Indium Tin Oxide, Indium Tin Oxide) was formed on the surface of the circuit-formed substrate, and after the film formation, grooves were formed in the ITO film so as to separate the pixels, thereby fabricating pixel electrodes. As a result, the first substrate 11b with the circuit layer 113' formed thereon was obtained.

As the second substrate 12 and the third substrate 13, the same synthetic quartz glass substrate having an outer diameter of 200 mm and a thickness of 725 μm was prepared. The adhesive used to temporarily bond the first substrate 11b and the second substrate 12 together was selected in consideration of workability when separating later and heat resistance during heat treatment after bonding the third substrate. . Here, TA1070T, TA2570V3, and TA4070 manufactured by Shin-Etsu Chemical Co., Ltd., which are thermosetting modified Si-based adhesives, were used. That is, on the first substrate 11b, TA1070T with a thickness of 10 μm, TA2570V3 with a thickness of 10 μm, and TA4070 with a thickness of 90 μm were laminated on the first substrate 11b by spin coating to obtain a total thickness of 110 μm. TA1070T functions as a protection layer for the circuit layer, TA2570V3 functions as a peeling layer at the time of substrate separation, and TA4070 functions as an adhesive layer with the second substrate. For bonding, after pressing the second substrate 12 against the first substrate 11b with a force of 0.1 MPa, the substrates are horizontally set in an oven with the jig attached, and heat-treated at 190° C. for 2 hours. It was carried out by curing the adhesive.

Next, the back surface of the first substrate 11b to which the second substrate 12 was temporarily bonded was ground with a grinding wheel using a polish grinder PG300 manufactured by Tokyo Seimitsu Co., Ltd. to reduce the thickness of the first substrate to 20 μm. After grinding, the remaining 20 μm of P+ layer was removed by immersion etching. The etching solution used was hydrofluoric acid with a concentration of 49% by weight, nitric acid with a concentration of 60% by weight or more, and acetic acid with a concentration of 98% by weight or more. . The etching rate was set to 1 μm/min, the removal amount was set to 25 μm, and the etching time was calculated to be 25 minutes. Based on the calculation results, the P+ layer 112 was etched by immersion in mixed acid for 25 minutes. After etching, it was confirmed that there was no Si residue in the active layer (Si layer)-free region of the circuit 113', and that the P+ layer 112 was completely removed.

Next, an oxide film (SiO ₂ ) with a thickness of 500 nm was deposited by sputtering on the exposed circuit layer 113′ of the first substrate 11c at room temperature. The surface of the oxide film was polished to a mirror finish. Polishing was carried out in two steps, with the purpose of planarizing the first step and improving the surface roughness of the second step. The first-stage polishing was performed using SUBA800 of Nitta Haas as a polishing cloth and ILD4013, a fumed silica slurry of Nitta Haas as a slurry, with a stock removal of about 200 nm. The second-stage polishing was performed using a lamination-type polishing cloth of Nitta Haas IC1000/SUBA400, and using colloidal silica slurry COMPOL-80 of Fujimi Incorporation as the slurry, with a removal of about 100 nm. . After polishing, cleaning was performed to remove the slurry, and then finish cleaning was performed by RCA cleaning.

After activating the surface of the third substrate 13 made of synthetic quartz glass with plasma, the plasma-activated surface of the third substrate 13 and the mirror-finished oxide film surface of the first substrate were directly bonded. . After the bonding, the substrates were heated at 150° C. for 24 hours to strengthen the bonding of the bonding surfaces, and the second substrate was separated.

Separation of the second substrate was performed in the same manner as in Example 1. Finally, the second substrate was peeled off from the portion that had been adhered to the first substrate by the adhesive, and the separation of the second substrate was completed. At this time, the first substrate was not separated from the third substrate.

After the separation of the second substrate, the residue of the adhesive on the first substrate was removed in the same manner as in Example 1 by immersing the substrate in the organic solvent p-menthane for 5 minutes. In the first substrate bonded to the third substrate, the interface of direct bonding could not be visually confirmed, and the portion without the circuit was transparent.

A microdisplay liquid crystal panel was obtained in the same manner as in Example 1 using the thus obtained microdisplay substrate. Polarizing plates were placed on both sides of the liquid crystal panel in the thickness direction, and the operation was confirmed. It was possible to obtain a substrate for a microdisplay even by a production method in which the substrates were laminated via an oxide film which operated normally and had a mirror finish. In addition, no influence of light leakage current was observed.

11a first substrate 11b first substrate on which circuit layer is formed 11c thinned first substrate 111 P-type Si substrate layer 112 low resistance P-type Si layer (P+ layer )
113 High resistance P-type Si layer (P layer) with electrical resistivity of 10 Ω cm or more
113′ circuit layer (a layer including an active layer implanted with impurities into a high-resistance P-type Si layer, a gate layer formed on its front surface, and a wiring layer)
12 second substrate, 13 third substrate, 16 temporary bonding adhesive, 17 transfer adhesive,
18 blades,
21 active layer, 22 gate layer, 23 first wiring layer, 24 second wiring layer,
25 wiring, 26 insulating film (oxide film),
30 liquid crystal panel, 31a, b polarizing plate, 33 circuit, 34 pixel electrode, 35 liquid crystal,
36 sealing material, 37 counter electrode, 38 counter substrate

Claims (7)

(i) On a P-type Si substrate, a low-resistivity P-type Si layer with an electrical resistivity of 0.001 Ω·cm or less and a high-resistivity P-type Si layer with an electrical resistivity of 10 Ω·cm or more are epitaxially grown in this order. forming a first substrate by
(ii) forming a circuit layer on the surface of the high resistance P-type Si layer of the first substrate;
(iii) bonding a second substrate with an adhesive to the surface of the first substrate on which the circuit layer is formed;
(iv) thinning the first substrate to expose the circuit layer;
(v) bonding a third substrate, which is a transparent substrate, to the thinned first substrate;
(vi) removing the second substrate from the first substrate bonded to the third substrate;
(vii) removing the adhesive on the surface of the first substrate from which the second substrate has been separated to expose the circuit layer surface. Thinning the first substrate to expose the circuit layer (iv) comprises:
grinding the P-type Si substrate and part of the low-resistance P-type Si layer;
2. The manufacturing method according to claim 1, further comprising a step of removing said remaining low-resistance P-type Si layer with a mixed acid of hydrofluoric acid, nitric acid and acetic acid. 3. The production method according to claim 2, wherein the volume ratio of said hydrofluoric acid, nitric acid and acetic acid in said mixed acid is 1:2-4:7-9. 4. The manufacturing method according to claim 1, wherein said third substrate is a glass substrate or a quartz glass substrate. The step (v) of bonding the third substrate is a step of bonding the third substrate to the exposed bottom surface of the circuit layer with an adhesive after removing the low-resistance P-type Si layer of the first substrate. The manufacturing method according to any one of claims 1 to 4, comprising The step (v) of bonding the third substrate includes
forming an oxide film on the bottom surface of the exposed circuit layer after removing the low-resistance P-type Si layer of the first substrate;
a step of mirror-polishing the surface of the oxide film;
5. The manufacturing method according to claim 1, further comprising a step of directly bonding the surface of said third substrate to said mirror-polished oxide film surface. 7. The method of claim 6, wherein said oxide film is a _SiO2 film.

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