JP2004259907A - Pn junction diode device and method of manufacturing the same - Google Patents

Pn junction diode device and method of manufacturing the same Download PDF

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JP2004259907A
JP2004259907A JP2003048523A JP2003048523A JP2004259907A JP 2004259907 A JP2004259907 A JP 2004259907A JP 2003048523 A JP2003048523 A JP 2003048523A JP 2003048523 A JP2003048523 A JP 2003048523A JP 2004259907 A JP2004259907 A JP 2004259907A
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concentration
type semiconductor
semiconductor region
main surface
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Yoshio Kadota
義生 門田
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a pn junction diode device which can further be reduced in size and also provide a method of manufacturing the same pn junction diode device. <P>SOLUTION: Both cathode electrode 22 and anode electrode 23 are bonded to a lead frame 26 without connection through a wire or the like, by forming the cathode electrode 22 and anode electrode 23 of the pn junction diode on one principal surface of a silicon substrate 10. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、ＰＮ接合ダイオード装置及びその製造方法に関する。
【０００２】
【従来の技術】
従来、ＰＮ接合ダイオードとしてｎ型の半導体基体の第１の主面側に高濃度ｐ型半導体領域を形成する一方、この高濃度ｐ型半導体領域から離れるようにして、第２の主面側に高濃度ｎ型半導体領域を形成したものがある。この種のＰＮ接合ダイオードは、製造方法が比較的簡易なこともあって、一般に広く用いられている。このＰＮ接合ダイオードにおいては、ダイオードの種類としてメサ型ダイオード、反転防止型ダイオード等があるが、いずれも一方の主面に形成された高濃度ｐ型半導体領域上にアノード電極を、他方の主面に形成された高濃度ｎ型半導体領域にカソード電極を形成している（例えば、特許文献１参照。）。
【０００３】
このように半導体基体の両主面に電極を形成しているため、リードフレームを備えたパッケージにダイオードを配置し、配線する場合は、一方の主面の電極から金等のワイヤーを使用して、インナーリード部等と接続する。反転防止型シリコンダイオード装置を例にとり、図６を用いて説明する。シリコン基板６０はパッケージ６６に収められている。シリコン基板６０においては、その第１の主面側に第１の高濃度ｎ型半導体領域６１が形成されており、また、領域６１の上にはカソード電極６２が形成されている。また、第２の主面側に、高濃度Ｐ型半導体領域６４及び領域６４から離れて第２の高濃度ｎ型半導体領域である反転防止層６３が形成されている。この反転防止層６３によって、高濃度ｐ型半導体領域６４からの基板表面リーク電流は抑制される。また、高濃度ｐ型半導体領域６４上にアノード電極６５が形成されている。
【０００４】
このように構成されたシリコンチップ６０ａにおいては、カソード電極６２がリードフレーム６７の上に接着するように実装されている。一方、アノード電極６５には金ワイヤー６９が金ボール６８によって接着され、金ワイヤー６９が、更にもう一方のリードフレーム６７に接続されている。パッケージ６６内のシリコンチップ６６ａは図示しない樹脂で封止されており、更に、パッケージの外枠７０によって覆われ、保護されている。
【０００５】
【特許文献１】
特許第３，３１３，５６６号公報（第４頁、図４）
【０００６】
【発明が解決しようとする課題】
このようなＰＮ接合ダイオード装置の用途を拡大するうえで、より一層の小型化が要求されており、外形の高さや幅を更に縮小することが課題となっている。
【０００７】
本発明はこのような事情に鑑みてなされたもので、その目的は、より一層の小型化が可能なＰＮ接合ダイオード装置及びその製造方法を提供することにある。
【０００８】
【課題を解決するための手段】
上記の課題を解決するため、本発明の第１の発明は、ｎ型半導体で構成される第１の半導体基体の第１の主面側に第１の高濃度ｎ型半導体領域を形成する工程と、前記第１の半導体基体の第１の主面と、少なくとも第１の主面側に第２の高濃度ｎ型半導体領域が形成されている第２の半導体基体の前記第１の主面とを接着して半導体基板を形成する工程と、前記第１の半導体基体の第２の主面側に高濃度ｐ型半導体領域を形成する工程と、前記第１の半導体基体の第２の主面側に、前記高濃度ｐ型半導体領域から離れて、且つ前記第１の高濃度ｎ型半導体領域と接続する第３の高濃度ｎ型半導体領域を形成する工程と、前記高濃度ｐ型半導体領域上及び前記第３の高濃度ｎ型半導体領域上にそれぞれ電極を形成する工程とを有することを特徴とする。
【０００９】
また、第２の発明は、ｎ型半導体基板の第１の主面側の一部に第１の高濃度ｎ型半導体領域を形成する工程と、前記半導体基板の第１の主面側に、前記第１の高濃度ｎ型半導体領域より浅く第２の高濃度ｎ型半導体領域を形成する工程と、前記半導体基板の第２の主面側に高濃度ｐ型半導体領域を形成する工程と、前記半導体基板の第２の主面側の前記高濃度ｐ型半導体領域から離れて、且つ前記第１の高濃度ｎ型半導体領域と接続する第３の高濃度ｎ型半導体領域を形成する工程と、前記高濃度ｐ型半導体領域及び前記第３の高濃度ｎ型半導体領域上にそれぞれ電極を形成する工程とを有することを特徴とすることを特徴とする。
【００１０】
本発明の第１の発明及び第２の発明によれば、同じ主面上に高濃度ｐ型半導体領域及び前記第３の高濃度ｎ型半導体領域が存在することにより、それぞれの電極を同じ主面側でパッケージのリードフレームに接着して接続することが可能になる。従って、小型化が可能なＰＮ接合ダイオード装置の製造方法を提供することができる。
【００１１】
更に、本発明の第３の発明は、ｎ型半導体基板と、前記半導体基板の第１の主面側に形成された高濃度ｐ型半導体領域と、前記半導体基板の前記高濃度ｐ型半導体領域から離れて前記第１の主面側に形成された第３の高濃度ｎ型半導体領域と、前記高濃度ｐ型半導体領域及び第３の高濃度ｎ型半導体領域から離れ、且つ前記半導体基板に形成された第２の高濃度ｎ型半導体領域と、前記高濃度ｐ型半導体領域から離れ、且つ前記第３の高濃度ｎ型半導体領域及び前記第２の高濃度ｎ型半導体領域と接続し、前記半導体基板に形成された第１の高濃度ｎ型半導体領域と、前記高濃度ｐ型半導体領域上及び前記第３の高濃度ｎ型半導体領域上にそれぞれ形成された電極とを有することを特徴とする。
【００１２】
本発明によれば、同じ主面上に高濃度ｐ型半導体領域及び前記第３の高濃度ｎ型半導体領域が存在することにより、それぞれの電極を同じ主面側でパッケージのリードフレームに接着して接続することが可能になる。従って、小型化が可能なＰＮ接合ダイオード装置を提供することができる。
【００１３】
【発明の実施の形態】
以下、本発明の実施例を、図面を参照して説明する。
【００１４】
（第１の実施の形態）
図１及び図２は本発明によるＰＮ接合ダイオード装置の製造方法の第１の実施の形態を工程順に示す断面図である。また、図２（ｆ）は本発明によるＰＮ接合ダイオード装置の第１の実施の形態を示す断面図である。
【００１５】
先ず、図１（ａ）に示すように半導体基体としてｎ型シリコン基板１０を用意する。次に、後の不純物拡散のマスクとして、ＣＶＤ法を用いて第１のシリコン酸化膜１１をｎ型シリコン基板１０の上に形成し、続いてリソグラフィ法とエッチング法を用いてパターニングする。更に、その上に第１の燐添加シリコン酸化膜１２をＣＶＤ法で形成した後、ｎ型不純物の外方拡散を防止するため、第１のキャップ膜１２ａをＣＶＤ法で形成する。次に、熱処理を行って、燐をｎ型シリコン基板１０の中に拡散させ、第１の高濃度ｎ型半導体領域１３を形成する。
【００１６】
続いて、ｎ型シリコン基板１０の上の、第１のキャップ膜１２ａ、第１の燐添加シリコン酸化膜１２及び第１のシリコン酸化膜１１をウェットエッチングで除去する。次に、高濃度ｎ型シリコン基板１４を用意し、図１（ｂ）に示すように、ｎ型シリコン基板１０の高濃度ｎ型半導体領域１３を形成した主面と高濃度ｎ型シリコン基板１４の一方の主面とを、両方の表面のシリコン原子が化学的に結合するように、貼り合せ法によって接着させる。更に、ｎ型シリコン基板１０のｎ層全面が露出している主面側からｎ型シリコン基板１０を研削することによって、研削層１０ａを除去し、貼り合せシリコン基板１５を形成する。
【００１７】
次に、図１（ｃ）に示すように、貼り合せシリコン基板１５のｎ層が全面に露出している主面の上に、後の不純物拡散のマスクとして、ＣＶＤ法を用いて第２のシリコン酸化膜１６を形成し、続いてリソグラフィ法とエッチング法を用いてパターニングする。次に、ボロン添加シリコン酸化膜１７をＣＶＤ法で形成した後、ｐ型不純物の外方拡散を防止するため、第２のキャップ膜１７ａをＣＶＤ法で形成する。更に、熱処理を行って、ボロンを貼り合せシリコン基板１５の中に拡散させ、高濃度ｐ型半導体領域１８を形成する。この時、高濃度ｎ型シリコン基板１４の部分であった第２の高濃度ｎ型半導体領域１４ａからｎ型不純物がｎ型シリコン基板１０に拡散し、しみ出し層１４ｂが形成される。続いて、第２のキャップ膜１７ａ、ボロン添加シリコン酸化膜１７及び第２のシリコン酸化膜１６をウェットエッチングで除去する。
【００１８】
次に、図１（ｄ）に示すように、後の不純物拡散のマスクとして、ＣＶＤ法を用いて、貼り合せシリコン基板１５における高濃度ｐ型半導体領域１８を形成した主面側の上に第３のシリコン酸化膜１９を形成し、続いてリソグラフィ法とエッチング法を用いてパターニングする。更に、その上に第２の燐添加シリコン酸化膜２０をＣＶＤ法で形成した後、ｎ型不純物の外方拡散を防止するため、第３のキャップ膜２０ａをＣＶＤ法で形成する。更に、熱処理を行って、燐を貼り合せシリコン基板１５の中に拡散させ、燐が第１の高濃度ｎ型半導体領域１３まで届くように、第３の高濃度ｎ型半導体層２１を形成する。この時、第１の高濃度ｎ型半導体領域１３が存在することによって、第３の高濃度ｎ型半導体領域２１の深さが比較的浅くて良いため、しみ出し層１４ｂの更なる拡散は少なく抑制される。続いて、貼り合せシリコン基板１５の上の、第３のキャップ膜２０ａ、第２の燐添加シリコン酸化膜２０及び第３のシリコン酸化膜１９をウェットエッチングで除去する。
【００１９】
次に、図２（ｅ）に示すように、貼り合せシリコン基板１５の高濃度ｐ型半導体領域１８を形成した主面側の上に、スパッタ法或いは蒸着法によるＣｒ−Ｎｉ−Ａｇ膜の成膜と、リソグラフィ法、リフトオフ法、エッチング法等によるパターニングを行って、カソード電極２２及びアノード電極２３を形成し、ＰＮ接合ダイオードを完成させる。
【００２０】
貼り合せシリコン基板１５に複数のＰＮ接合ダイオードが形成されている場合には、次に、図示しないが、貼り合せシリコン基板１５を、例えばダイヤモンドブレードによりダイシングし、シリコンチップ２４に分割する。続いて、分割したシリコンチップ２４を図２（ｆ）に示すように、パッケージ２５に配置する。
即ち、電極２２、２３がリードフレーム２６の部分２６ａ、２６ｂに接着するようにシリコンチップ２４をマウントし、図示しない樹脂でシリコンチップ２４を封止し、更に保護用としてパッケージの外枠２７を被せてＰＮ接合ダイオード装置が完成する。
【００２１】
本実施の形態によれば、ＰＮ接合ダイオードのカソード電極２２及びアノード電極２３を共に、貼り合せシリコン基板１５の一方の主面に形成することにより、小型化が可能になる。特に、電極とリードフレームをワイヤー等で接続することなく、接着することが可能になる。このため、ＰＮ接合ダイオードを小型なパッケージに実装可能になる。また、一方の主面の高濃度ｎ型不純物領域と他方の主面の高濃度ｎ型半導体領域を接続する熱処理を抑えることにより、しみ出し層１４ｂを小さくし、ＰＮ接合ダイオードの容量及び抵抗を小さく抑えることができる。
【００２２】
（第２の実施の形態）
図３は本発明によるＰＮ接合ダイオード及びその製造方法の第２の実施の形態を示す断面図である。本実施の形態では、第１の実施の形態とパッケージの形態が異なり、更に、小型化が可能になる。第２の実施の形態では、第１の実施の形態による図１（ａ）〜（ｄ）及び図２（ｅ）までのＰＮ接合ダイオードを形成する工程までは同じである。即ち、不純物導入及び貼り合せ法によるｎ型シリコン基板と高濃度ｎ型シリコン基板の接着を経て、アノード電極及びカソード電極を形成し、更に、貼り合せシリコン基板をダイシングし、シリコンチップに分割する。
【００２３】
その後、本実施の形態では、図３に示すように、シリコンチップ２４を、パッケージ２５におけるパッケージ基板２５ａに同一化されて形成してあるリードフレーム２５ｂの部分２５ｃ、２５ｄにカソード電極２２及びアノード電極２３が接着するようにマウントし、図示しない樹脂で封止し、パッケージの外枠２７を被せてＰＮ接合ダイオード装置が完成する。
【００２４】
本実施の形態によれば、ＰＮ接合ダイオードのアノード電極２２及びカソード電極２３を共に、貼り合せシリコン基板１５の第１の主面に形成すること、及びパッケージ基板２５ａに同一化して形成してあるリードフレーム２５ｂを用いることによって、ワイヤー等で接続することなく、より小型化が可能ななＰＮ接合ダイオードが得られる。
【００２５】
（第３の実施の形態）
図４及び図５は本発明によるＰＮ接合ダイオード装置の製造方法の第３の実施の形態を示す断面図である。また、図５（ｆ）は本発明によるＰＮ接合ダイオード装置の第３の実施の形態を示す断面図である。
【００２６】
先ず、図４（ａ）に示すように半導体基体としてｎ型シリコン基板３０を用意する。次に、後の不純物拡散のマスクとして、ＣＶＤ法を用いて第１のシリコン酸化膜３１をｎ型シリコン基板３０の上に形成し、続いてリソグラフィ法とエッチング法を用いてパターニングする。更に、その上に第１の燐添加シリコン酸化膜３２をＣＶＤ法で形成した後、ｎ型不純物の外方拡散を防止するため、第１のキャップ膜３３をＣＶＤ法で形成する。次に、熱処理を行って、燐をｎ型シリコン基板３０の中に拡散させ、第１の高濃度ｎ型半導体領域３４を形成する。
【００２７】
続いて、ｎ型シリコン基板３０の上の、第１のキャップ膜３３、第１の燐添加シリコン酸化膜３２及び第１のシリコン酸化膜３１をウェットエッチングで除去する。
【００２８】
次に、図４（ｂ）に示すように、ｎ型シリコン基板３０の全面に第２の燐添加シリコン酸化膜３５をＣＶＤ法で形成した後、ｎ型不純物の外方拡散を防止するため、第２のキャップ膜３６をＣＶＤ法で形成する。次に、熱処理を行って、燐をｎ型シリコン基板３０の中に拡散させ、第２の高濃度ｎ型半導体領域３７を形成する。この時、第１の高濃度ｎ型半導体領域３４の燐は更に基板中に深く拡散する。
【００２９】
次に、図４（ｃ）に示すように、ｎ型シリコン基板３０のｎ型半導体層が露出している主面の上に、後の不純物拡散のマスクとして、ＣＶＤ法を用いて第２のシリコン酸化膜３８を形成し、続いてリソグラフィ法とエッチング法を用いてパターニングする。続いて、ボロン添加シリコン酸化膜３９をＣＶＤ法で形成した後、ｐ型不純物の外方拡散を防止するため、第３のキャップ膜４０をＣＶＤ法で形成する。更に、熱処理を行って、ボロンをｎ型シリコン基板３０の中に拡散させ、高濃度ｐ型半導体層４１を形成する。この時、第２の高濃度ｎ型半導体領域３７からｎ型半導体層に燐が拡散し、しみ出し層４２を形成する。続いて、第３のキャップ膜４０、ボロン添加シリコン酸化膜３９及び第２のシリコン酸化膜３８をウェットエッチングで除去する。
【００３０】
更に、図４（ｄ）に示すように、後の不純物拡散のマスクとして、ＣＶＤ法を用いて第３のシリコン酸化膜４３をｎ型シリコン基板３０の高濃度ｎ型半導体領域４１を形成した主面側の上に形成し、続いてリソグラフィ法とエッチング法を用いてパターニングする。更に、その上に第３の燐添加シリコン酸化膜４４をＣＶＤ法で形成した後、ｎ型不純物の外方拡散を防止するため、第４のキャップ膜４５をＣＶＤ法で形成する。更に、熱処理を行って、燐が第１の高濃度ｎ型半導体領域３４まで届くように、燐をｎ型シリコン基板３０の中に拡散させ、第３の高濃度ｎ型半導体領域４６を形成する。続いて、ｎ型シリコン基板３０上の第４のキャップ膜４５、第３の燐添加シリコン酸化膜４４及び第３のシリコン酸化膜４３をウェットエッチングで除去する。
【００３１】
次に、図５（ｅ）に示すように、ｎ型シリコン基板３０の高濃度ｐ型半導体領域４１を形成した主面側の上に、スパッタ法或いは蒸着法によるＣｒ−Ｎｉ−Ａｇ膜の成膜と、リソグラフィ法、リフトオフ法、エッチング法等によるパターニングを行って、カソード電極４７及びアノード電極４８を形成し、ＰＮ接合ダイオードを完成させる。
【００３２】
ｎ型シリコン基板３０に複数のＰＮ接合ダイオードが形成されている場合には、次に、図示しないが、ｎ型シリコン基板３０を、例えばダイヤモンドブレードによりダイシングし、シリコンチップ４９に分割する。続いて、分割したシリコンチップ４９を図５（ｆ）に示すようにパッケージ５０に配置する。即ち、電極４７、４８がリードフレーム５１の部分５１ａ、５１ｂに接着するようにシリコンチップ４９をマウントし、図示しない樹脂でシリコンチップ４９を封止し、更に保護用としてパッケージの外枠２７を被せてＰＮ接合ダイオード装置が完成する。
【００３３】
本実施の形態によれば、ＰＮ接合ダイオードのカソード電極４７アノード電極４８及びアノード電極４８を共に、シリコン基板３０の第１の主面に形成することにより、小型化を達成できる。特に、電極４７、４８とリードフレーム５１をワイヤー等で接続することなく、直接に接着することが可能になる。このため、小型化が可能なＰＮ接合ダイオード装置が得られる。
【００３４】
なお、本発明は上述した実施形態に何ら限定されるものではなく、例えば、半導体基体としてはシリコン基板だけでなく、化合物半導体であっても良い。また、不純物導入方法は拡散法だけでなく、イオン注入法でも良く、不純物種も燐、ボロンに限るものではない。電極材料はＡｌ、Ｃｕ、Ａｕ等をベースにしても良い。その他、本発明の主旨を逸脱しない範囲内で種々変更して実施することができる。
【００３５】
【発明の効果】
以上、詳述したように、本発明によれば、ＰＮ接合ダイオードのアノード電極及びカソード電極を共に、シリコン基板の第１の主面に形成することにより、小型化が可能になる。
【図面の簡単な説明】
【図１】本発明によるＰＮ接合ダイオード装置の製造方法の第１の実施の形態を工程順に示す断面図。
【図２】本発明によるＰＮ接合ダイオード装置の製造方法の第１の実施の形態を工程順に示す断面図。
【図３】本発明によるＰＮ接合ダイオード装置の製造方法の第２の実施の形態を工程順に示す断面図。
【図４】本発明によるＰＮ接合ダイオード装置の製造方法の第３の実施の形態を工程順に示す断面図。
【図５】本発明によるＰＮ接合ダイオード装置の製造方法の第３の実施の形態を工程順に示す断面図。
【図６】従来例を示す断面図。
【符号の説明】
１０、３０、６０ ｎ型シリコン基板
１０ａ 研削層
１１、３１ 第１のシリコン酸化膜
１２、３２ 第１の燐添加シリコン酸化膜
１２ａ、３３ 第１のキャップ膜
１３、３４ 第１の高濃度ｎ型半導体領域
１４ 高濃度ｎ型シリコン基板
１４ａ、３７ 第２の高濃度ｎ型半導体領域
１４ｂ、４２、６１ａ しみ出し層
１５ 貼り合せシリコン基板
１６、３８ 第２のシリコン酸化膜
１７、３９ ボロン添加シリコン酸化膜
１７ａ、３６ 第２のキャップ膜
１８、４１、６４ 高濃度ｐ型半導体領域
１９、４３ 第３のシリコン酸化膜
２０、３５ 第２の燐添加シリコン酸化膜
２０ａ、４０ 第３のキャップ膜
２１、４６ 第３の高濃度ｎ型半導体領域
２２、４７ カソード電極
２３、４８、６５ アノード電極
２４、４９、６０ａ シリコンチップ
２５、５０、６６ パッケージ
２５ａ、５０ａ、６６ａ パッケージ基板
２６、２５ｂ、５１、６７ リードフレーム
２６ａ、２６ｂ、２５ｃ、２５ｄ、５１ａ、５１ｂ リードフレームの部分
２７、５２、７０ 外枠
４４ 第３の燐添加シリコン酸化膜
４５ 第４のキャップ膜
６１ 高濃度ｎ型半導体領域
６３ 反転防止層
６８ 金ボール
６９ 金ワイヤー[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a PN junction diode device and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, a high-concentration p-type semiconductor region is formed on the first main surface side of an n-type semiconductor substrate as a PN junction diode, while being separated from the high-concentration p-type semiconductor region on the second main surface side. In some cases, a high-concentration n-type semiconductor region is formed. This type of PN junction diode is generally widely used because of its relatively simple manufacturing method. In this PN junction diode, there are a mesa diode, an inversion prevention diode, and the like as a diode type. In each case, an anode electrode is formed on a high concentration p-type semiconductor region formed on one main surface, and the other main surface is formed. The cathode electrode is formed in the high-concentration n-type semiconductor region formed as described above (for example, see Patent Document 1).
[0003]
Since electrodes are formed on both main surfaces of the semiconductor substrate in this way, when a diode is arranged in a package having a lead frame and wiring is performed, use a wire such as gold from the electrode on one main surface. , And the inner lead part. An inversion prevention type silicon diode device will be described as an example with reference to FIG. The silicon substrate 60 is contained in a package 66. In the silicon substrate 60, a first high-concentration n-type semiconductor region 61 is formed on the first main surface side, and a cathode electrode 62 is formed on the region 61. On the second main surface side, a high-concentration P-type semiconductor region 64 and an inversion prevention layer 63 that is a second high-concentration n-type semiconductor region apart from the region 64 are formed. The inversion prevention layer 63 suppresses a substrate surface leak current from the high-concentration p-type semiconductor region 64. An anode electrode 65 is formed on the high-concentration p-type semiconductor region 64.
[0004]
In the silicon chip 60 a thus configured, the cathode electrode 62 is mounted on the lead frame 67 so as to adhere thereto. On the other hand, a gold wire 69 is bonded to the anode electrode 65 by a gold ball 68, and the gold wire 69 is further connected to the other lead frame 67. The silicon chip 66a in the package 66 is sealed with a resin (not shown), and further covered and protected by an outer frame 70 of the package.
[0005]
[Patent Document 1]
Patent No. 3,313,566 (page 4, FIG. 4)
[0006]
[Problems to be solved by the invention]
In order to expand the applications of such PN junction diode devices, further miniaturization is required, and there is a need to further reduce the height and width of the outer shape.
[0007]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a PN junction diode device that can be further miniaturized and a method of manufacturing the same.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, a first invention of the present invention is a step of forming a first high-concentration n-type semiconductor region on a first main surface side of a first semiconductor substrate composed of an n-type semiconductor. A first main surface of the first semiconductor substrate; and a first main surface of a second semiconductor substrate having a second high-concentration n-type semiconductor region formed on at least the first main surface. Bonding a first semiconductor substrate, forming a high-concentration p-type semiconductor region on the second main surface side of the first semiconductor substrate, and forming a second main region of the first semiconductor substrate. Forming a third high-concentration n-type semiconductor region on the surface side, which is apart from the high-concentration p-type semiconductor region and connected to the first high-concentration n-type semiconductor region; Forming electrodes on the region and on the third high-concentration n-type semiconductor region, respectively. To.
[0009]
In a second aspect of the present invention, a step of forming a first high-concentration n-type semiconductor region on a part of the first main surface side of the n-type semiconductor substrate; Forming a second high-concentration n-type semiconductor region shallower than the first high-concentration n-type semiconductor region; and forming a high-concentration p-type semiconductor region on a second main surface side of the semiconductor substrate; Forming a third high-concentration n-type semiconductor region apart from the high-concentration p-type semiconductor region on the second main surface side of the semiconductor substrate and connected to the first high-concentration n-type semiconductor region; Forming electrodes on the high-concentration p-type semiconductor region and the third high-concentration n-type semiconductor region, respectively.
[0010]
According to the first and second aspects of the present invention, the presence of the high-concentration p-type semiconductor region and the third high-concentration n-type semiconductor region on the same main surface allows each electrode to have the same It becomes possible to bond and connect to the package lead frame on the surface side. Accordingly, it is possible to provide a method of manufacturing a PN junction diode device that can be downsized.
[0011]
Furthermore, a third invention of the present invention provides an n-type semiconductor substrate, a high-concentration p-type semiconductor region formed on the first main surface side of the semiconductor substrate, and the high-concentration p-type semiconductor region of the semiconductor substrate. A third high-concentration n-type semiconductor region formed on the first main surface side, away from the high-concentration p-type semiconductor region and the third high-concentration n-type semiconductor region; Forming the second high-concentration n-type semiconductor region, away from the high-concentration p-type semiconductor region, and connecting to the third high-concentration n-type semiconductor region and the second high-concentration n-type semiconductor region; A first high-concentration n-type semiconductor region formed on the semiconductor substrate; and electrodes formed on the high-concentration p-type semiconductor region and the third high-concentration n-type semiconductor region, respectively. And
[0012]
According to the present invention, the presence of the high-concentration p-type semiconductor region and the third high-concentration n-type semiconductor region on the same main surface allows the respective electrodes to be bonded to the package lead frame on the same main surface. Connection. Therefore, it is possible to provide a PN junction diode device that can be reduced in size.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
(First Embodiment)
1 and 2 are sectional views showing a first embodiment of a method for manufacturing a PN junction diode device according to the present invention in the order of steps. FIG. 2F is a cross-sectional view showing a first embodiment of the PN junction diode device according to the present invention.
[0015]
First, as shown in FIG. 1A, an n-type silicon substrate 10 is prepared as a semiconductor substrate. Next, as a mask for impurity diffusion later, a first silicon oxide film 11 is formed on the n-type silicon substrate 10 by using a CVD method, and then patterned by using a lithography method and an etching method. Further, after a first phosphorus-doped silicon oxide film 12 is formed thereon by a CVD method, a first cap film 12a is formed by a CVD method in order to prevent outward diffusion of an n-type impurity. Next, heat treatment is performed to diffuse phosphorus into the n-type silicon substrate 10 to form a first high-concentration n-type semiconductor region 13.
[0016]
Subsequently, the first cap film 12a, the first phosphorus-doped silicon oxide film 12, and the first silicon oxide film 11 on the n-type silicon substrate 10 are removed by wet etching. Next, a high-concentration n-type silicon substrate 14 is prepared, and as shown in FIG. 1B, the main surface of the n-type silicon substrate 10 on which the high-concentration n-type semiconductor region 13 is formed and the high-concentration n-type silicon substrate 14. Is bonded by a bonding method such that silicon atoms on both surfaces are chemically bonded. Further, the ground layer 10a is removed by grinding the n-type silicon substrate 10 from the main surface side where the entire surface of the n-layer of the n-type silicon substrate 10 is exposed, and the bonded silicon substrate 15 is formed.
[0017]
Next, as shown in FIG. 1 (c), a second impurity diffusion mask is formed on the main surface of the bonded silicon substrate 15 where the n-layer is entirely exposed, using a CVD method as a mask for impurity diffusion later. A silicon oxide film 16 is formed and subsequently patterned by using a lithography method and an etching method. Next, after the boron-added silicon oxide film 17 is formed by the CVD method, a second cap film 17a is formed by the CVD method in order to prevent outward diffusion of the p-type impurity. Further, heat treatment is performed to diffuse boron into the bonded silicon substrate 15 to form a high-concentration p-type semiconductor region 18. At this time, the n-type impurity diffuses into the n-type silicon substrate 10 from the second high-concentration n-type semiconductor region 14a, which is the portion of the high-concentration n-type silicon substrate 14, and the exudation layer 14b is formed. Subsequently, the second cap film 17a, the boron-added silicon oxide film 17 and the second silicon oxide film 16 are removed by wet etching.
[0018]
Next, as shown in FIG. 1D, as a mask for impurity diffusion later, the CVD method is used to form a mask on the main surface side of the bonded silicon substrate 15 where the high-concentration p-type semiconductor region 18 is formed. A silicon oxide film 19 of No. 3 is formed, and subsequently patterned by using a lithography method and an etching method. Further, after a second phosphorus-containing silicon oxide film 20 is formed thereon by a CVD method, a third cap film 20a is formed by a CVD method in order to prevent outward diffusion of an n-type impurity. Further, heat treatment is performed to diffuse phosphorus into the bonded silicon substrate 15, and a third high-concentration n-type semiconductor layer 21 is formed so that the phosphorus reaches the first high-concentration n-type semiconductor region 13. . At this time, since the first high-concentration n-type semiconductor region 13 is present, the depth of the third high-concentration n-type semiconductor region 21 may be relatively shallow, so that the further diffusion of the seepage layer 14b is small. Be suppressed. Subsequently, the third cap film 20a, the second phosphorus-containing silicon oxide film 20, and the third silicon oxide film 19 on the bonded silicon substrate 15 are removed by wet etching.
[0019]
Next, as shown in FIG. 2E, a Cr—Ni—Ag film is formed on the main surface side of the bonded silicon substrate 15 on which the high-concentration p-type semiconductor region 18 is formed by sputtering or vapor deposition. The film is patterned by a lithography method, a lift-off method, an etching method or the like to form a cathode electrode 22 and an anode electrode 23, thereby completing a PN junction diode.
[0020]
In the case where a plurality of PN junction diodes are formed on the bonded silicon substrate 15, the bonded silicon substrate 15 is then diced by a diamond blade, for example, and is divided into silicon chips 24, though not shown. Subsequently, the divided silicon chip 24 is arranged in a package 25 as shown in FIG.
That is, the silicon chip 24 is mounted so that the electrodes 22 and 23 adhere to the portions 26a and 26b of the lead frame 26, the silicon chip 24 is sealed with a resin (not shown), and the outer frame 27 of the package is further covered for protection. Thus, a PN junction diode device is completed.
[0021]
According to the present embodiment, since both the cathode electrode 22 and the anode electrode 23 of the PN junction diode are formed on one main surface of the bonded silicon substrate 15, the size can be reduced. In particular, it is possible to bond the electrode and the lead frame without connecting them with a wire or the like. Therefore, the PN junction diode can be mounted in a small package. Further, by suppressing the heat treatment for connecting the high-concentration n-type impurity region on one main surface to the high-concentration n-type semiconductor region on the other main surface, the exudation layer 14b is reduced, and the capacitance and resistance of the PN junction diode are reduced. It can be kept small.
[0022]
(Second embodiment)
FIG. 3 is a sectional view showing a second embodiment of a PN junction diode and a method for manufacturing the same according to the present invention. In the present embodiment, the form of the package is different from that of the first embodiment, and further downsizing is possible. In the second embodiment, the steps up to the step of forming the PN junction diode shown in FIGS. 1A to 1D and 2E according to the first embodiment are the same. That is, an anode electrode and a cathode electrode are formed through bonding of an n-type silicon substrate and a high-concentration n-type silicon substrate by an impurity introduction and bonding method, and then the bonded silicon substrate is diced and divided into silicon chips.
[0023]
Thereafter, in the present embodiment, as shown in FIG. 3, a silicon chip 24 is provided on a portion 25c, 25d of a lead frame 25b formed in the same manner as a package substrate 25a of a package 25, by a cathode electrode 22 and an anode electrode. 23 is mounted so as to adhere to it, sealed with a resin (not shown), and covered with an outer frame 27 of the package, thereby completing a PN junction diode device.
[0024]
According to the present embodiment, both the anode electrode 22 and the cathode electrode 23 of the PN junction diode are formed on the first main surface of the bonded silicon substrate 15 and are formed identically on the package substrate 25a. By using the lead frame 25b, it is possible to obtain a PN junction diode that can be further reduced in size without being connected by a wire or the like.
[0025]
(Third embodiment)
4 and 5 are sectional views showing a third embodiment of the method for manufacturing a PN junction diode device according to the present invention. FIG. 5F is a sectional view showing a third embodiment of the PN junction diode device according to the present invention.
[0026]
First, as shown in FIG. 4A, an n-type silicon substrate 30 is prepared as a semiconductor substrate. Next, as a mask for impurity diffusion later, a first silicon oxide film 31 is formed on the n-type silicon substrate 30 by using the CVD method, and then patterned by using the lithography method and the etching method. Further, after a first phosphorus-containing silicon oxide film 32 is formed thereon by a CVD method, a first cap film 33 is formed by a CVD method in order to prevent outward diffusion of an n-type impurity. Next, heat treatment is performed to diffuse phosphorus into the n-type silicon substrate 30 to form a first high-concentration n-type semiconductor region 34.
[0027]
Subsequently, the first cap film 33, the first phosphorus-doped silicon oxide film 32, and the first silicon oxide film 31 on the n-type silicon substrate 30 are removed by wet etching.
[0028]
Next, as shown in FIG. 4B, after a second phosphorus-doped silicon oxide film 35 is formed on the entire surface of the n-type silicon substrate 30 by a CVD method, in order to prevent outward diffusion of n-type impurities, The second cap film 36 is formed by a CVD method. Next, heat treatment is performed to diffuse phosphorus into the n-type silicon substrate 30 to form a second high-concentration n-type semiconductor region 37. At this time, the phosphorus in the first high-concentration n-type semiconductor region 34 further diffuses deep into the substrate.
[0029]
Next, as shown in FIG. 4C, a second impurity diffusion mask is formed on the main surface of the n-type silicon substrate 30 where the n-type semiconductor layer is exposed, using a CVD method. A silicon oxide film 38 is formed, and subsequently patterned using a lithography method and an etching method. Subsequently, after the boron-added silicon oxide film 39 is formed by the CVD method, a third cap film 40 is formed by the CVD method in order to prevent outward diffusion of the p-type impurity. Further, heat treatment is performed to diffuse boron into the n-type silicon substrate 30 to form a high-concentration p-type semiconductor layer 41. At this time, phosphorus diffuses from the second high-concentration n-type semiconductor region 37 into the n-type semiconductor layer to form a seepage layer 42. Subsequently, the third cap film 40, the boron-added silicon oxide film 39, and the second silicon oxide film 38 are removed by wet etching.
[0030]
Further, as shown in FIG. 4D, a third silicon oxide film 43 is formed using a CVD method as a mask for impurity diffusion later, in which the high-concentration n-type semiconductor region 41 of the n-type silicon substrate 30 is formed. It is formed on the surface side, and is subsequently patterned using lithography and etching. Further, after a third phosphorus-added silicon oxide film 44 is formed thereon by a CVD method, a fourth cap film 45 is formed by a CVD method in order to prevent outward diffusion of an n-type impurity. Further, a heat treatment is performed to diffuse phosphorus into the n-type silicon substrate 30 so that the phosphorus reaches the first high-concentration n-type semiconductor region 34 to form a third high-concentration n-type semiconductor region 46. . Subsequently, the fourth cap film 45, the third phosphorus-doped silicon oxide film 44, and the third silicon oxide film 43 on the n-type silicon substrate 30 are removed by wet etching.
[0031]
Next, as shown in FIG. 5E, a Cr—Ni—Ag film is formed on the main surface side of the n-type silicon substrate 30 on which the high-concentration p-type semiconductor region 41 is formed by a sputtering method or a vapor deposition method. The film is patterned by a lithography method, a lift-off method, an etching method or the like to form a cathode electrode 47 and an anode electrode 48, thereby completing a PN junction diode.
[0032]
In the case where a plurality of PN junction diodes are formed on the n-type silicon substrate 30, the n-type silicon substrate 30 is then diced by a diamond blade, for example, and is divided into silicon chips 49, though not shown. Subsequently, the divided silicon chips 49 are arranged in a package 50 as shown in FIG. That is, the silicon chip 49 is mounted so that the electrodes 47 and 48 adhere to the portions 51a and 51b of the lead frame 51, the silicon chip 49 is sealed with a resin (not shown), and the outer frame 27 of the package is further covered for protection. Thus, a PN junction diode device is completed.
[0033]
According to the present embodiment, downsizing can be achieved by forming both the cathode electrode 47 and the anode electrode 48 of the PN junction diode on the first main surface of the silicon substrate 30. In particular, it is possible to directly bond the electrodes 47 and 48 to the lead frame 51 without connecting them with wires or the like. Therefore, a PN junction diode device that can be reduced in size can be obtained.
[0034]
Note that the present invention is not limited to the above-described embodiment at all. For example, the semiconductor substrate may be not only a silicon substrate but also a compound semiconductor. Further, the impurity introduction method may be not only the diffusion method but also an ion implantation method, and the impurity species is not limited to phosphorus and boron. The electrode material may be based on Al, Cu, Au or the like. In addition, various changes can be made without departing from the spirit of the present invention.
[0035]
【The invention's effect】
As described in detail above, according to the present invention, by forming both the anode electrode and the cathode electrode of the PN junction diode on the first main surface of the silicon substrate, miniaturization becomes possible.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a first embodiment of a method for manufacturing a PN junction diode device according to the present invention in the order of steps.
FIG. 2 is a sectional view illustrating a first embodiment of a method for manufacturing a PN junction diode device according to the present invention in the order of steps.
FIG. 3 is a sectional view illustrating a second embodiment of the method of manufacturing the PN junction diode device according to the present invention in the order of steps.
FIG. 4 is a sectional view showing a third embodiment of a method for manufacturing a PN junction diode device according to the present invention in the order of steps.
FIG. 5 is a sectional view showing a third embodiment of a method for manufacturing a PN junction diode device according to the present invention in the order of steps.
FIG. 6 is a sectional view showing a conventional example.
[Explanation of symbols]
10, 30, 60 n-type silicon substrate 10a ground layer 11, 31 first silicon oxide film 12, 32 first phosphorus-doped silicon oxide film 12a, 33 first cap film 13, 34 first high-concentration n-type Semiconductor region 14 High-concentration n-type silicon substrate 14a, 37 Second high-concentration n-type semiconductor region 14b, 42, 61a Exudation layer 15 Bonded silicon substrate 16, 38 Second silicon oxide film 17, 39 Boron-doped silicon oxide Films 17a, 36 second cap films 18, 41, 64 high-concentration p-type semiconductor regions 19, 43 third silicon oxide films 20, 35 second phosphorus-doped silicon oxide films 20a, 40 third cap films 21, 46 Third high-concentration n-type semiconductor regions 22, 47 Cathode electrodes 23, 48, 65 Anode electrodes 24, 49, 60a Silicon chips 25, 50, 66 Cages 25a, 50a, 66a Package substrates 26, 25b, 51, 67 Lead frames 26a, 26b, 25c, 25d, 51a, 51b Lead frame portions 27, 52, 70 Outer frame 44 Third phosphorus-doped silicon oxide film 45 4 cap film 61 high-concentration n-type semiconductor region 63 inversion prevention layer 68 gold ball 69 gold wire

Claims (8)

ｎ型半導体で構成される第１の半導体基体の第１の主面側に第１の高濃度ｎ型半導体領域を形成する工程と、
前記第１の半導体基体の第１の主面と、少なくとも第１の主面側に第２の高濃度ｎ型半導体領域が形成されている第２の半導体基体の前記第１の主面とを接着して半導体基板を形成する工程と、
前記第１の半導体基体の第２の主面側に高濃度ｐ型半導体領域を形成する工程と、
前記第１の半導体基体の第２の主面側に、前記高濃度ｐ型半導体領域から離れて、且つ前記第１の高濃度ｎ型半導体領域と接続する第３の高濃度ｎ型半導体領域を形成する工程と、
前記高濃度ｐ型半導体領域上及び前記第３の高濃度ｎ型半導体領域上にそれぞれ電極を形成する工程とを有することを特徴とするＰＮ接合ダイオード装置の製造方法。forming a first high-concentration n-type semiconductor region on a first main surface side of a first semiconductor substrate composed of an n-type semiconductor;
A first main surface of the first semiconductor substrate, and a first main surface of a second semiconductor substrate having a second high-concentration n-type semiconductor region formed at least on the first main surface side; Bonding and forming a semiconductor substrate;
Forming a high concentration p-type semiconductor region on the second main surface side of the first semiconductor substrate;
A third high-concentration n-type semiconductor region which is separated from the high-concentration p-type semiconductor region and connected to the first high-concentration n-type semiconductor region is provided on the second main surface side of the first semiconductor substrate. Forming,
Forming electrodes on the high-concentration p-type semiconductor region and on the third high-concentration n-type semiconductor region, respectively. ｎ型半導体基板の第１の主面側の一部に第１の高濃度ｎ型半導体領域を形成する工程と、
前記半導体基板の第１の主面側に、前記第１の高濃度ｎ型半導体領域より浅く第２の高濃度ｎ型半導体領域を形成する工程と、
前記半導体基板の第２の主面側に高濃度ｐ型半導体領域を形成する工程と、
前記半導体基板の第２の主面側の前記高濃度ｐ型半導体領域から離れて、且つ前記第１の高濃度ｎ型半導体領域と接続する第３の高濃度ｎ型半導体領域を形成する工程と、
前記高濃度ｐ型半導体領域及び前記第３の高濃度ｎ型半導体領域上にそれぞれ電極を形成する工程とを有することを特徴とするＰＮ接合ダイオード装置の製造方法。forming a first high-concentration n-type semiconductor region on a portion of the first main surface side of the n-type semiconductor substrate;
Forming a second high-concentration n-type semiconductor region shallower than the first high-concentration n-type semiconductor region on the first main surface side of the semiconductor substrate;
Forming a high-concentration p-type semiconductor region on the second main surface side of the semiconductor substrate;
Forming a third high-concentration n-type semiconductor region apart from the high-concentration p-type semiconductor region on the second main surface side of the semiconductor substrate and connected to the first high-concentration n-type semiconductor region; ,
Forming electrodes on the high-concentration p-type semiconductor region and the third high-concentration n-type semiconductor region, respectively. 前記高濃度ｐ型半導体領域上及び前記第３の高濃度ｎ型半導体領域上に電極を形成する工程の後に、前記第１の半導体基体の第２の主面側をリードフレームに対向させ、前記電極を前記リードフレームに接着させる工程を有することを特徴とする請求項１に記載するＰＮ接合ダイオード装置の製造方法。After a step of forming electrodes on the high-concentration p-type semiconductor region and the third high-concentration n-type semiconductor region, the second main surface side of the first semiconductor base is opposed to a lead frame, 2. The method according to claim 1, further comprising the step of bonding an electrode to the lead frame. 前記高濃度ｐ型半導体領域上及び前記第３の高濃度ｎ型半導体領域上に電極を形成する工程の後に、前記ｎ型半導体基板の第２の主面側をリードフレームに対向させ、前記電極を前記リードフレームに接着させる工程を有することを特徴とする請求項２に記載するＰＮ接合ダイオード装置の製造方法。After a step of forming an electrode on the high-concentration p-type semiconductor region and on the third high-concentration n-type semiconductor region, the second main surface side of the n-type semiconductor substrate is opposed to a lead frame, and 3. A method for manufacturing a PN junction diode device according to claim 2, further comprising the step of: bonding the PN junction to the lead frame. 前記リードフレームはパッケージ基板と同一化して形成されていることを特徴とする請求項３及び請求項４に記載するＰＮ接合ダイオード装置の製造方法。5. The method according to claim 3, wherein the lead frame is formed in the same manner as a package substrate. ｎ型半導体基板と、
前記半導体基板の第１の主面側に形成された高濃度ｐ型半導体領域と、
前記半導体基板の前記高濃度ｐ型半導体領域から離れて前記第１の主面側に形成された第３の高濃度ｎ型半導体領域と、
前記高濃度ｐ型半導体領域及び第３の高濃度ｎ型半導体領域から離れ、且つ前記半導体基板に形成された第２の高濃度ｎ型半導体領域と、
前記高濃度ｐ型半導体領域から離れ、且つ前記第３の高濃度ｎ型半導体領域及び前記第２の高濃度ｎ型半導体領域と接続し、前記半導体基板に形成された第１の高濃度ｎ型半導体領域と、
前記高濃度ｐ型半導体領域上及び前記第３の高濃度ｎ型半導体領域上にそれぞれ形成された電極とを有することを特徴とするＰＮ接合ダイオード装置。an n-type semiconductor substrate;
A high-concentration p-type semiconductor region formed on the first main surface side of the semiconductor substrate;
A third high-concentration n-type semiconductor region formed on the first main surface side away from the high-concentration p-type semiconductor region of the semiconductor substrate;
A second high-concentration n-type semiconductor region which is separated from the high-concentration p-type semiconductor region and the third high-concentration n-type semiconductor region and is formed on the semiconductor substrate;
A first high-concentration n-type formed on the semiconductor substrate, separated from the high-concentration p-type semiconductor region and connected to the third high-concentration n-type semiconductor region and the second high-concentration n-type semiconductor region; A semiconductor region;
A PN junction diode device, comprising: electrodes formed on the high-concentration p-type semiconductor region and on the third high-concentration n-type semiconductor region, respectively. 前記電極を接着するリードフレームを有するパッケージを具備したことを特徴とする請求項６に記載するＰＮ接合ダイオード装置。The PN junction diode device according to claim 6, further comprising a package having a lead frame to which the electrodes are bonded. 前記リードフレームは前記パッケージが有するパッケージ基板に同一化して形成されていることを特徴とする請求項７に記載するＰＮ接合ダイオード装置。The PN junction diode device according to claim 7, wherein the lead frame is formed identically to a package substrate of the package.
JP2003048523A 2003-02-26 2003-02-26 Pn junction diode device and method of manufacturing the same Pending JP2004259907A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109300892A (en) * 2018-09-04 2019-02-01 中国电子科技集团公司第五十五研究所 Super high power limiter MMIC and preparation method based on bonding transfer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109300892A (en) * 2018-09-04 2019-02-01 中国电子科技集团公司第五十五研究所 Super high power limiter MMIC and preparation method based on bonding transfer
CN109300892B (en) * 2018-09-04 2021-01-26 中国电子科技集团公司第五十五研究所 MMIC (monolithic microwave Integrated Circuit) of ultrahigh-power amplitude limiter based on bonding transfer and preparation method

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