JP2927158B2 - Semiconductor light emitting device - Google Patents
Semiconductor light emitting deviceInfo
- Publication number
- JP2927158B2 JP2927158B2 JP26573293A JP26573293A JP2927158B2 JP 2927158 B2 JP2927158 B2 JP 2927158B2 JP 26573293 A JP26573293 A JP 26573293A JP 26573293 A JP26573293 A JP 26573293A JP 2927158 B2 JP2927158 B2 JP 2927158B2
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- Prior art keywords
- semiconductor region
- region
- semiconductor
- light emitting
- groove
- Prior art date
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＧａＰ発光ダイオード
等の半導体発光素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device such as a GaP light emitting diode.
【０００２】[0002]
【従来の技術】ｎ型半導体基板側即ちカソード電極が設
けられた側を上面にして実装するに適したＧａＰ発光ダ
イオードチップ構造として、本願出願人は先に特願平５
−５２８８４号で図１０に示すような半導体発光素子を
提案した。この半導体発光素子は、ｎ型ＧａＰ基板１ａ
とエピタキシャル成長層から成るｎ型半導体領域１ｂと
ｐ型半導体領域２とｐ+ 型の半導体領域３を有する。ｎ
型領域１ｂとｐ型領域２との間のｐｎ接合４ａは主面に
対して平行に延びているが、ｎ型領域１ｂとｐ+型領域
３との間のｐｎ接合４ｂはチップの底面から遠ざかるよ
うに延びている。チップの下面には絶縁膜５が形成さ
れ、この中央の開口を通してアノード電極６がｐ型半導
体領域２に接続されている。アノード電極６は導電性支
持体７に対する接続を確実に達成するために絶縁膜５の
上に延在し、半田８によって支持体７に固着されてい
る。チップの上面には環状にカソード電極９が設けら
れ、光を取り出すためのウインドウ領域１０が生じてい
る。この発光素子は半田８のｐｎ接合への付着が生じな
い利点、及びｐｎ接合の中心領域の電流密度を大きくし
て高輝度が図れる利点を有する。2. Related Background Art As a GaP light emitting diode chip structure suitable for mounting with the n-type semiconductor substrate side, that is, the side on which the cathode electrode is provided, facing the top, the applicant of the present invention has previously described Japanese Patent Application No. Hei.
No. 5,288,881 proposed a semiconductor light emitting device as shown in FIG. This semiconductor light emitting device has an n-type GaP substrate 1a.
And an n-type semiconductor region 1b, a p-type semiconductor region 2, and a p + -type semiconductor region 3 made of an epitaxial growth layer. n
The pn junction 4a between the p-type region 1b and the p-type region 2 extends parallel to the main surface, while the pn junction 4b between the n-type region 1b and the p + -type region 3 It extends away. An insulating film 5 is formed on the lower surface of the chip, and an anode electrode 6 is connected to the p-type semiconductor region 2 through this central opening. The anode electrode 6 extends on the insulating film 5 in order to reliably connect to the conductive support 7, and is fixed to the support 7 by solder 8. A cathode electrode 9 is provided annularly on the upper surface of the chip, and a window region 10 for extracting light is formed. This light-emitting element has an advantage that the solder 8 does not adhere to the pn junction and an advantage that the current density in the central region of the pn junction can be increased to achieve high luminance.
【０００３】[0003]
【発明が解決しようとする課題】ところで、最近、発光
素子の輝度を更に高めることが要求されている。この要
求に応えるために、本件出願人は、図１０の構造の発光
素子のチップ面積を小さくして中心領域での電流密度の
向上を試みた。しかし、支持体に対して安定的に固着す
ることが困難になるのみでなく、光の周辺方向（横方
向）への拡散やカソード電極９による遮光のために期待
通りの高輝度化は達成されなかった。By the way, recently, it is required to further increase the luminance of the light emitting element. In order to meet this demand, the present applicant has attempted to improve the current density in the central region by reducing the chip area of the light emitting device having the structure shown in FIG. However, not only is it difficult to stably adhere to the support, but also the expected high brightness is achieved due to diffusion of light in the peripheral direction (lateral direction) and light shielding by the cathode electrode 9. Did not.
【０００４】そこで、本発明の目的は、支持体への安定
的な取付けが可能であると共に高輝度化が可能な半導体
発光素子を提供することにある。Accordingly, an object of the present invention is to provide a semiconductor light emitting device which can be stably mounted on a support and which can achieve high luminance.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
の本発明は、第１導電型の第１の半導体領域と、ｐｎ接
合を形成するように前記第１の半導体領域に隣接してい
る第２導電型の第２の半導体領域とを有する半導体基体
と、前記半導体基体の一方の主面において前記第１の半
導体領域に接続された第１の電極と、前記半導体基体の
他方の主面において前記第２の半導体領域に接続された
第２の電極とを備え、前記第２の電極を支持体に接続す
るように構成された半導体発光素子において、前記第２
の半導体領域と同一の第２の導電型を有し且つ前記第２
の半導体領域よりも高い不純物濃度を有する第３の半導
体領域が前記半導体基体の前記他方の主面の中央領域を
除く周辺領域に設けられ、前記第３の半導体領域が、前
記第１の半導体領域と前記第２の半導体領域との間のｐ
ｎ接合面の周縁よりも前記半導体基体の一方の主面側ま
で延在しており、前記半導体基体の他方の主面を開口を
有して被覆する絶縁膜が設けられ、前記開口は前記第２
の半導体領域の中央部分に配置され、前記第２の電極は
前記開口を介して前記第２の半導体領域に接続されてい
ると共に前記絶縁膜の上にも設けられており、前記第２
の半導体領域の中央部分と周縁部分との間に電気的分離
領域が設けられていることを特徴とする半導体発光素子
に係わるものである。なお、請求項２に示すように分離
領域を溝とすることが望ましい。In order to achieve the above object, according to the present invention, a first conductive type first semiconductor region is adjacent to the first semiconductor region so as to form a pn junction. A semiconductor substrate having a second semiconductor region of a second conductivity type, a first electrode connected to the first semiconductor region on one main surface of the semiconductor substrate, and the other main surface of the semiconductor substrate And a second electrode connected to the second semiconductor region, and wherein the second electrode is connected to a support .
Having the same second conductivity type as the semiconductor region of
Semiconductor having an impurity concentration higher than that of the first semiconductor region
The body region corresponds to a central region of the other main surface of the semiconductor substrate.
And the third semiconductor region is provided in a peripheral region except for the first region.
The p between the first semiconductor region and the second semiconductor region
the one main surface side of the semiconductor substrate from the periphery of the n-junction surface.
And an insulating film that covers the other main surface of the semiconductor substrate with an opening.
The second electrode is connected to the second semiconductor region through the opening and is also provided on the insulating film, and the second electrode is provided on the insulating film.
A semiconductor light-emitting device, wherein an electrical isolation region is provided between a central portion and a peripheral portion of the semiconductor region. Preferably, the isolation region is a groove.
【０００６】[0006]
【発明の作用及び効果】本発明における第２の半導体領
域の中央部分と周辺部分との間の電気的分離領域は、電
流の周辺部分への広がりを制限する働きを有し、中央部
分の電流密度の向上に寄与し、高輝度化が達成される。
また、第２の半導体領域の周辺部分は絶縁膜及び第２の
電極を介して支持体への取付け領域としての機能を有す
るので、支持体への安定的な取付けが可能になる。ま
た、半導体基体の側面に露出するｐｎ接合の位置を支持
体から遠ざけることができ、支持体に対する固着が容易
になる。また、請求項２の発明によれば、溝によって電
気的分離領域を容易に得ることができる。According to the present invention, the electrical isolation region between the central portion and the peripheral portion of the second semiconductor region in the present invention has a function of limiting the spread of the current to the peripheral portion, and the current in the central portion is reduced. This contributes to an increase in density and achieves higher luminance.
Further, the peripheral portion of the second semiconductor region has a function as a region for attachment to the support via the insulating film and the second electrode, so that stable attachment to the support can be performed. Ma
Also supports the position of the pn junction exposed on the side of the semiconductor substrate
Can be kept away from the body and easily fixed to the support
become. According to the second aspect of the present invention, the electrical isolation region can be easily obtained by the groove.
【０００７】[0007]
【実施例】次に、本発明の一実施例に係わる緑色ＧａＰ
発光素子即ち緑色発光ダイオード（ＬＥＤ）及びその製
造方法について図１〜図９を参照して説明する。まず、
図１に示すように、ｎ型ＧａＰ（ガリウム・リン）半導
体基板（以下、ｎ型基板と呼ぶ）１１の上に液相エピタ
キシャル成長法でｎ型ＧａＰ半導体領域１２を形成し、
更にこの上にエピタキシャル成長法でｐ型ＧａＰ半導体
領域１３を形成した半導体ウエハ１４を用意する。な
お、ｐｎ接合１５を形成するｎ型半導体領域１２には導
電型決定不純物としてのＴｅ（テルル）の他に窒素がド
ープされ、ｐ型半導体領域１３には導電型決定不純物と
してのＺｎ（亜鉛）の他に窒素がドープされている。ま
た、ｎ型及びｐ型半導体領域１２、１３の厚さはｎ型基
板１１の厚さに比べて大幅に薄い。ｎ型基板１１とｎ型
半導体領域１２が第１の半導体領域として機能し、ｐ型
半導体領域１３が第２の半導体領域として機能する。Next, a green GaP according to an embodiment of the present invention will be described.
A light emitting element, that is, a green light emitting diode (LED) and a method for manufacturing the same will be described with reference to FIGS. First,
As shown in FIG. 1, an n-type GaP (gallium-phosphorus) semiconductor substrate (hereinafter referred to as an n-type substrate) 11 is formed with an n-type GaP semiconductor region 12 by a liquid phase epitaxial growth method.
Further, a semiconductor wafer 14 having a p-type GaP semiconductor region 13 formed thereon by an epitaxial growth method is prepared. The n-type semiconductor region 12 forming the pn junction 15 is doped with nitrogen in addition to Te (tellurium) as a conductivity type determining impurity, and the p-type semiconductor region 13 is Zn (zinc) as a conductivity type determining impurity. In addition, nitrogen is doped. Further, the thicknesses of the n-type and p-type semiconductor regions 12 and 13 are significantly smaller than the thickness of the n-type substrate 11. The n-type substrate 11 and the n-type semiconductor region 12 function as a first semiconductor region, and the p-type semiconductor region 13 functions as a second semiconductor region.
【０００８】次に、図２に示すようにウエハ１４のｐ型
半導体領域１３側の表面からダイシングを施して相対的
に深い第１の溝１６とこれよりも浅い第２の溝１７を形
成する。第１及び第２の溝１６、１７は図８に示すよう
に碁盤の目状に形成されており、４本の第１の溝１６に
よって包囲された平面四角形の中に４本の第２の溝１７
によって包囲された平面四角形が収まっている。第１の
溝１６で区画された領域１８、１９等がそれぞれ１素子
となる。Next, as shown in FIG. 2, dicing is performed from the surface of the wafer 14 on the side of the p-type semiconductor region 13 to form a relatively deep first groove 16 and a shallower second groove 17. . The first and second grooves 16 and 17 are formed in a grid pattern as shown in FIG. 8, and four second quadrangles are formed in a plane square surrounded by the four first grooves 16. Groove 17
The flat rectangle surrounded by is enclosed. The regions 18, 19 and the like defined by the first grooves 16 each constitute one element.
【０００９】次に、図２に示すウエハ１４にエッチング
を施して、図３に示すように第１及び第２の溝１６、１
７の側壁を傾斜させてその開口幅を拡げる。第１及び第
２の溝１６、１７はいずれもｐｎ接合１５を越えてｎ型
半導体領域１２に達する深さで形成される。なお、第１
及び第２の溝１６、１７は図３のエッチング工程におい
てｐｎ接合１５よりも深く形成されるようにしてもよ
い。本実施例では、第２の溝１７もｐｎ接合１５を越え
る深さで形成しているが、第２の溝１７は必ずしもｐｎ
接合１５よりも深く形成する必要はなく、ｐ型半導体領
域１３を分離できるようにｐｎ接合１５に到達していれ
ばよい。また、図２のダイシング工程を省略してエッチ
ングのみで図３のウエハを得ることもできる。Next, the wafer 14 shown in FIG. 2 is etched to form first and second grooves 16 and 1 as shown in FIG.
7 is inclined to widen the opening width. Each of the first and second grooves 16 and 17 is formed to a depth reaching the n-type semiconductor region 12 beyond the pn junction 15. The first
The second grooves 16 and 17 may be formed deeper than the pn junction 15 in the etching step of FIG. In the present embodiment, the second groove 17 is also formed at a depth exceeding the pn junction 15, but the second groove 17 is not necessarily a pn junction.
It is not necessary to form the p-type semiconductor region 13 deeper than the junction 15 as long as it reaches the pn junction 15 so that the p-type semiconductor region 13 can be separated. Further, the wafer of FIG. 3 can be obtained only by etching without the dicing step of FIG.
【００１０】次に、第２の溝１７で包囲されたｐ型半導
体領域１３の表面にマスク図（図示せず）を形成し、ウ
エハ１４の上面側に選択的にｐ型不純物を導入して図４
に示すようにｐ型の第３の半導体領域としてｐ+ 型半導
体領域２０を形成する。ｐ型半導体領域１３よりも不純
物濃度の高いｐ+ 型半導体領域２０は、図３において第
１及び第２の溝１６、１７に露出していたｎ型及びｐ型
半導体領域１２、１３のｐｎ接合を覆うように形成さ
れ、ｎ型半導体領域１２との間に新しいｐｎ接合２１が
生じている。なお、基板１１側にマスクを形成せずに不
純物拡散を行った結果、基板１１に反転層が生じた時に
は、研摩又はエッチングによってこの反転層を除去す
る。また、ｐ+ 型半導体領域２０をウエハ上面の全面に
わたって形成した後に、第２の溝１７に包囲されたｐ型
半導体領域１３に形成されたｐ+ 型半導体領域２０をエ
ッチング除去してｐ型半導体領域１３をウエハ上面に露
出させてもよい。Next, a mask (not shown) is formed on the surface of the p-type semiconductor region 13 surrounded by the second groove 17, and p-type impurities are selectively introduced into the upper surface of the wafer 14. FIG.
As shown in FIG. 7, ap + type semiconductor region 20 is formed as a p type third semiconductor region. The p + -type semiconductor region 20 having an impurity concentration higher than that of the p-type semiconductor region 13 is a pn junction of the n-type and p-type semiconductor regions 12 and 13 exposed in the first and second trenches 16 and 17 in FIG. , And a new pn junction 21 is formed between the pn junction 21 and the n-type semiconductor region 12. When an inversion layer is formed on the substrate 11 as a result of impurity diffusion without forming a mask on the substrate 11 side, the inversion layer is removed by polishing or etching. Further, p + -type semiconductor region 20 after the formation over the entire surface of the wafer top surface, the p-type p + -type semiconductor region 20 formed in the p-type semiconductor region 13 surrounded by a second trench 17 is removed by etching the semiconductor The region 13 may be exposed on the upper surface of the wafer.
【００１１】次に、ウエハ１４の上面全体にシリコン酸
化膜を形成した後に選択的にこれにエッチングを施し、
図５に示すように第２の溝１７に包囲されたｐ型半導体
領域１３の中央部分の表面を露出させる開口２２を有す
る絶縁膜２３を形成する。Next, after a silicon oxide film is formed on the entire upper surface of the wafer 14, it is selectively etched,
As shown in FIG. 5, an insulating film 23 having an opening 22 for exposing the surface of the central portion of the p-type semiconductor region 13 surrounded by the second groove 17 is formed.
【００１２】次に、ウエハ１４の上面全体にＡｕ（金）
を真空蒸着して開口２２を通じてｐ型半導体領域１３に
オーミックコンタクトするアノード電極（第２の電極）
２４を形成する。また、ウエハ１４の下面にもＡｕを真
空蒸着して基板１１にオーミックコンタクトするカソー
ド電極（第１の電極）２５を形成する。カソード電極２
５はウエハ１４の下面に平面環状形状に形成されてお
り、平面透視的に見てアノード電極２４とｐ型半導体領
域１３とのオーミックコンタクト面２６を離間して包囲
する。本実施例では、カソード電極２５を第２の溝１７
に対向させている。後に、第１の溝１６に沿うラインＬ
でウエハ１４を切断分離することで、図７に示す個別化
した発光ダイオードチップが完成する。チップには図３
の第１の溝１６に対応する傾斜側面部１６ａと第２の溝
１７に対応する溝１７ａが生じる。Next, Au (gold) is formed on the entire upper surface of the wafer 14.
Electrode (second electrode) that is vacuum-deposited and is in ohmic contact with the p-type semiconductor region 13 through the opening 22
24 are formed. Au is also vacuum-deposited on the lower surface of the wafer 14 to form a cathode electrode (first electrode) 25 that makes ohmic contact with the substrate 11. Cathode electrode 2
Numeral 5 is formed in a planar annular shape on the lower surface of the wafer 14, and surrounds the ohmic contact surface 26 between the anode electrode 24 and the p-type semiconductor region 13 with a space therebetween when viewed in a plan view. In this embodiment, the cathode electrode 25 is connected to the second groove 17.
Facing. Later, a line L along the first groove 16
Then, the individualized light emitting diode chips shown in FIG. 7 are completed. Fig. 3
An inclined side surface portion 16a corresponding to the first groove 16 and a groove 17a corresponding to the second groove 17 are formed.
【００１３】図７は本実施例で形成された発光ダイオー
ドチップをカソード電極２５が設けられた側を上にして
支持体２７に半田２８で固着したところを示す。FIG. 7 shows a state in which the light emitting diode chip formed in this embodiment is fixed to a support 27 with solder 28 with the side on which the cathode electrode 25 is provided facing up.
【００１４】本実施例の発光ダイオードチップは次の作
用効果を有する。 （１） 第２の溝１７がｐｎ接合１５を分断しており、
ｐｎ接合１５のうち第２の溝１７によって包囲された領
域のみが電流径路となる。結果として、ｐｎ接合１５の
中心側における電流密度を増大させ、輝度を高めること
ができる。 （２） 傾斜溝１７内のシリコン酸化膜から成る光反射
性を有する絶縁膜２３が反射膜として機能するから、ｐ
ｎ接合１５の中心側で発生した光をここでの反射で素子
の上方のウインドウ領域２９に効率良く導くことができ
る。 （３） ｎ型基板１１とｎ型半導体領域１２とｐ型半導
体領域１３とｐ+ 型半導体領域２０とから成る半導体基
体（チップ）の平面サイズをあまり小さくせずにｐｎ接
合１５の面積を小さくできるので、発光量が大きいｐｎ
接合１５の中心側上方に比較的大きい面積でウインドウ
領域２９を設けることができる。このため、光を外部に
効率良く取り出すことができる。 （４） 第１の溝１６と第２の溝１７の間の突出部分が
素子の支持脚として機能するから、ｐ型領域１３とアノ
ード電極２４とのコンタクト面積は小さくなっているが
素子の安定性は向上している。なお、上記（１）〜
（３）項の作用が相俟って高輝度化が達成される。 （５） 第２の溝１７がｐ型半導体領域１３を環状に囲
む部分のみに設けられず、素子の囲縁に至るように延び
ているので、半田２８による支持体２７に対する固着時
に溶融半田が溝１７ａを通って良好に流れ、残留気泡の
少ない良好な半田付が達成される。The light emitting diode chip of this embodiment has the following operation and effects. (1) The second groove 17 divides the pn junction 15,
Only the area of the pn junction 15 surrounded by the second groove 17 becomes the current path. As a result, the current density on the center side of the pn junction 15 can be increased, and the luminance can be increased. (2) Since the light reflecting insulating film 23 made of a silicon oxide film in the inclined groove 17 functions as a reflecting film, p
Light generated on the center side of the n-junction 15 can be efficiently guided to the window region 29 above the element by reflection here. (3) The area of the pn junction 15 is reduced without significantly reducing the planar size of the semiconductor substrate (chip) including the n-type substrate 11, the n-type semiconductor region 12, the p-type semiconductor region 13, and the p + -type semiconductor region 20. Pn with high light emission
The window region 29 can be provided with a relatively large area above the center side of the joint 15. Therefore, light can be efficiently extracted to the outside. (4) Since the projecting portion between the first groove 16 and the second groove 17 functions as a support leg of the element, the contact area between the p-type region 13 and the anode electrode 24 is small, but the element is stable. Sex is improving. In addition, the above (1)-
High brightness is achieved by the combination of the effects of the item (3). (5) Since the second groove 17 is not provided only in the portion surrounding the p-type semiconductor region 13 in an annular shape but extends to the surrounding edge of the element, the molten solder is fixed to the support 27 by the solder 28. It flows well through the groove 17a, and good soldering with little residual air bubbles is achieved.
【００１５】[0015]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） 図７のチップからｐ+ 型半導体領域２０を省い
て図１１に示すように構成してもよい。ｐ+ 型半導体領
域２０は発光に寄与しない漏れ電流を減少させるために
形成した方が望ましいが、必ずしも設ける必要はない。
なお、図１１において図７と共通する部分には同一の符
号が付されている。 （２） 開口２２及びウインドウ領域２９を円形にする
ことができる。 （３） 半田２８を別の導電性接合材にすることができ
る。 （４） 溝１７を埋めるように光反射性絶縁層を形成す
ることができる。 （５） ４本の第２の溝１７で包囲された四角形と４本
の第１の溝１６で包囲された四角形との間を結ぶように
半田の流れを助けるための溝を更に追加して設けてもよ
い。即ち、水平及び／又は垂直方向に延びる第１及び第
２の溝１６、１７の相互間に更に溝を設けても良い。 （６） 第１の溝１６と第２の溝１７のいずれか一方又
は両方をエッチングで形成することができる。第２の溝
１７をエッチングによって形成する場合には４本の第２
の溝１７によって四角形のみを形成し、この四角形から
第１の溝１６に延在する第２の溝１７を省くことができ
る。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The chip shown in FIG. 7 may be configured as shown in FIG. 11 by omitting the p + type semiconductor region 20. The p + -type semiconductor region 20 is preferably formed to reduce leakage current that does not contribute to light emission, but is not necessarily provided.
In FIG. 11, the same reference numerals are given to portions common to FIG. (2) The opening 22 and the window region 29 can be made circular. (3) The solder 28 can be another conductive bonding material. (4) A light-reflective insulating layer can be formed so as to fill the groove 17. (5) A groove for assisting the flow of the solder is further added so as to connect between the square surrounded by the four second grooves 17 and the square surrounded by the four first grooves 16. It may be provided. That is, a further groove may be provided between the first and second grooves 16 and 17 extending in the horizontal and / or vertical directions. (6) Either one or both of the first groove 16 and the second groove 17 can be formed by etching. When the second groove 17 is formed by etching, four second grooves 17 are formed.
Only the square is formed by the groove 17, and the second groove 17 extending from the square to the first groove 16 can be omitted.
【図１】本発明の実施例の発光ダイオードを作るための
ウエハを示す断面図である。FIG. 1 is a sectional view showing a wafer for manufacturing a light emitting diode according to an embodiment of the present invention.
【図２】第１及び第２の溝を形成したウエハを示す断面
図である。FIG. 2 is a cross-sectional view showing a wafer on which first and second grooves are formed.
【図３】図２の溝をエッチングした後のウエハを示す断
面図である。FIG. 3 is a cross-sectional view showing the wafer after etching the grooves of FIG. 2;
【図４】ｐ+ 型半導体領域を形成したウエハを示す断面
図である。FIG. 4 is a sectional view showing a wafer on which ap + type semiconductor region is formed.
【図５】絶縁膜を形成したウエハを示す断面図である。FIG. 5 is a sectional view showing a wafer on which an insulating film is formed.
【図６】カソード電極及びアノード電極を形成したウエ
ハを示す断面図である。FIG. 6 is a sectional view showing a wafer on which a cathode electrode and an anode electrode are formed.
【図７】発光ダイオードを支持体に固着した状態を示す
断面図である。FIG. 7 is a cross-sectional view showing a state where the light emitting diode is fixed to a support.
【図８】図２のウエハの平面図である。FIG. 8 is a plan view of the wafer of FIG. 2;
【図９】図７の発光ダイオードをアノード側から見た平
面図である。FIG. 9 is a plan view of the light emitting diode of FIG. 7 as viewed from the anode side.
【図１０】従来の発光ダイオードを支持体に取付けた状
態を示す断面図である。FIG. 10 is a cross-sectional view showing a state where a conventional light emitting diode is mounted on a support.
【図１１】変形例の発光ダイオードを支持体に取付けた
状態を示す断面図である。FIG. 11 is a cross-sectional view showing a state where a light emitting diode of a modification is mounted on a support.
１２ ｎ型半導体領域 １３ ｐ型半導体領域 １６ 第１の溝 １７ 第２の溝 ２３ 絶縁膜 ２４ アノード電極 ２５ カソード電極 Reference Signs List 12 n-type semiconductor region 13 p-type semiconductor region 16 first groove 17 second groove 23 insulating film 24 anode electrode 25 cathode electrode
Claims (2)
接合を形成するように前記第１の半導体領域に隣接して
いる第２導電型の第２の半導体領域とを有する半導体基
体と、 前記半導体基体の一方の主面において前記第１の半導体
領域に接続された第１の電極と、 前記半導体基体の他方の主面において前記第２の半導体
領域に接続された第２の電極とを備え、前記第２の電極
を支持体に接続するように構成された半導体発光素子に
おいて、前記第２の半導体領域と同一の第２の導電型を有し且つ
前記第２の半導体領域よりも高い不純物濃度を有する第
３の半導体領域が前記半導体基体の前記他方の主面の中
央領域を除く周辺領域に設けられ、 前記第３の半導体領域が、前記第１の半導体領域と前記
第２の半導体領域との間のｐｎ接合面の周縁よりも前記
半導体基体の一方の主面側まで延在しており、 前記半導体基体の他方の主面を開口を有して被覆する絶
縁膜が設けられ、 前記開口は前記第２の半導体領域の中央部分に配置さ
れ、 前記第２の電極は前記開口を介して前記第２の半導体領
域に接続されていると共に前記絶縁膜の上にも設けられ
ており、 前記第２の半導体領域の中央部分と周縁部分との間に電
気的分離領域が設けられていることを特徴とする半導体
発光素子。A first semiconductor region of a first conductivity type;
A semiconductor substrate having a second conductivity type second semiconductor region adjacent to the first semiconductor region so as to form a junction; and a first semiconductor region on one main surface of the semiconductor substrate. A first electrode connected to the semiconductor substrate, and a second electrode connected to the second semiconductor region on the other main surface of the semiconductor substrate, wherein the second electrode is connected to a support. Semiconductor light-emitting device having the same second conductivity type as the second semiconductor region;
A second semiconductor region having a higher impurity concentration than the second semiconductor region;
3 is the semiconductor region in the other main surface of the semiconductor substrate.
The third semiconductor region is provided in a peripheral region excluding a center region, and the third semiconductor region is
Than the peripheral edge of the pn junction surface between the second semiconductor region
An insulating film extending to one main surface side of the semiconductor substrate and covering the other main surface of the semiconductor substrate with an opening is provided, and the opening is provided at a central portion of the second semiconductor region. The second electrode is connected to the second semiconductor region via the opening and is also provided on the insulating film; and a central portion and a peripheral portion of the second semiconductor region And an electrical isolation region provided between the semiconductor light emitting device and the semiconductor light emitting device.
他方の主面から一方の主面に向って延びる溝であり、こ
の溝は前記第１の半導体領域にも至るように形成されて
いることを特徴とする請求項１記載の半導体発光素子。2. The electric isolation region is a groove extending from the other main surface of the semiconductor base toward one main surface, and the groove is formed so as to reach the first semiconductor region. 2. The semiconductor light emitting device according to claim 1, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26573293A JP2927158B2 (en) | 1993-09-29 | 1993-09-29 | Semiconductor light emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26573293A JP2927158B2 (en) | 1993-09-29 | 1993-09-29 | Semiconductor light emitting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07106631A JPH07106631A (en) | 1995-04-21 |
| JP2927158B2 true JP2927158B2 (en) | 1999-07-28 |
Family
ID=17421232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26573293A Expired - Lifetime JP2927158B2 (en) | 1993-09-29 | 1993-09-29 | Semiconductor light emitting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2927158B2 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| JPH07106631A (en) | 1995-04-21 |
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