JP7010692B2

JP7010692B2 - Semiconductor light emitting device

Info

Publication number: JP7010692B2
Application number: JP2017252273A
Authority: JP
Inventors: 一陽堤; 敬雄藤盛
Original assignee: Rohm Co Ltd
Current assignee: Rohm Co Ltd
Priority date: 2017-12-27
Filing date: 2017-12-27
Publication date: 2022-01-26
Anticipated expiration: 2037-12-27
Also published as: JP2019117905A

Description

本発明は、半導体発光装置に関する。 The present invention relates to a semiconductor light emitting device.

特許文献１は、たとえばサファイアなどからなる基板と、基板の表面に設けられ、窒化物半導体からなる第１導電形層および第２導電形層を含む半導体積層部と、半導体積層部の表面側の第１導電形層（たとえばｐ形層）に電気的に接続された第１電極（たとえばｐ側電極）と、半導体積層部の第２導電形層（たとえばｎ形層）に電気的に接続された第２電極（たとえばｎ側電極）とを含む、半導体発光素子を開示している。 Patent Document 1 describes a substrate made of, for example, sapphire, a semiconductor laminated portion provided on the surface of the substrate and including a first conductive type layer and a second conductive type layer made of a nitride semiconductor, and a surface side of the semiconductor laminated portion. A first electrode (for example, a p-side electrode) electrically connected to a first conductive layer (for example, a p-shaped layer) and a second conductive layer (for example, an n-shaped layer) of a semiconductor laminated portion are electrically connected. A semiconductor light emitting element including a second electrode (for example, an n-side electrode) is disclosed.

特開２００６－２５３６４７号公報Japanese Unexamined Patent Publication No. 2006-253647

近年注目されているウェアラブル機器のような小型デバイスにおいては、さらなる小型化に伴い、搭載される半導体発光装置の低背化が要求される。低背機種では、製品の高さを低く抑えるために、たとえば、ループが形成されないボンディング手法が用いられることがある。
しかしながら、この手法では、ボンディングワイヤが基板上の半導体積層構造に接近して配置されるので、樹脂封止工程の際にワイヤ流れが発生し、当該ワイヤが半導体積層構造に接触することがある。しかも、半導体積層構造のｐ型半導体層の周囲にｎ型半導体層が露出しており、このｎ型半導体層にｐ側のワイヤが接触するとリークが発生する。また、この種の不具合は、ワイヤにループが形成されていても、ワイヤ流れの度合いによっては生じることがある。 In small devices such as wearable devices, which have been attracting attention in recent years, it is required to reduce the height of the mounted semiconductor light emitting device with further miniaturization. In low-profile models, for example, a bonding method in which loops are not formed may be used in order to keep the height of the product low.
However, in this method, since the bonding wire is arranged close to the semiconductor laminated structure on the substrate, a wire flow may occur during the resin sealing step, and the wire may come into contact with the semiconductor laminated structure. Moreover, an n-type semiconductor layer is exposed around the p-type semiconductor layer having a semiconductor laminated structure, and when the p-side wire comes into contact with the n-type semiconductor layer, a leak occurs. Further, even if a loop is formed in the wire, this kind of defect may occur depending on the degree of wire flow.

本発明の目的は、従来に比べて、より信頼性の高い半導体発光装置を提供することである。 An object of the present invention is to provide a more reliable semiconductor light emitting device as compared with the conventional one.

本発明の一実施形態に係る半導体発光装置は、基板と、前記基板上に順に積層された第１導電型半導体層、発光層および第２導電型半導体層を含み、前記第２導電型半導体層から前記発光層を介して前記第１導電型半導体層に至る壁面を有する構造部と、前記構造部の周囲に配置され、前記第１導電型半導体層が露出する上面を有する第１部分とを含む半導体積層構造と、前記構造部の上面に配置された第２電極と、前記半導体積層構造の第１部分の前記上面に配置された第１電極とを含み、前記半導体積層構造は、前記第２電極の周囲において前記構造部から分離して配置され、前記第１導電型半導体層、前記発光層および前記第２導電型半導体層の積層構造からなる第１積層部を含む。 The semiconductor light emitting device according to the embodiment of the present invention includes a substrate, a first conductive semiconductor layer, a light emitting layer, and a second conductive semiconductor layer laminated in this order on the substrate, and the second conductive semiconductor layer. A structural portion having a wall surface extending from the light emitting layer to the first conductive semiconductor layer, and a first portion arranged around the structural portion and having an upper surface on which the first conductive semiconductor layer is exposed. The semiconductor laminated structure includes a second electrode arranged on the upper surface of the structural portion, and a first electrode arranged on the upper surface of the first portion of the semiconductor laminated structure, and the semiconductor laminated structure is the first. A first laminated portion composed of a laminated structure of the first conductive semiconductor layer, the light emitting layer, and the second conductive semiconductor layer, which is arranged around the two electrodes separately from the structural portion, is included.

図１は、本発明の一実施形態に係る半導体発光装置の模式的な切断端面図である。FIG. 1 is a schematic cut end view of a semiconductor light emitting device according to an embodiment of the present invention. 図２は、図１の半導体発光素子の模式的な平面図である。FIG. 2 is a schematic plan view of the semiconductor light emitting device of FIG. 図３は、図２のIII－III断面における切断端面図である。FIG. 3 is a cut end view in the III-III cross section of FIG. 図４Ａおよび図４Ｂは、前記半導体発光装置の製造工程の一部を示す図である。4A and 4B are views showing a part of the manufacturing process of the semiconductor light emitting device. 図５Ａおよび図５Ｂは、図４Ａおよび図４Ｂの次の工程を示す図である。5A and 5B are views showing the next steps of FIGS. 4A and 4B. 図６Ａおよび図６Ｂは、図５Ａおよび図５Ｂの次の工程を示す図である。6A and 6B are diagrams showing the next steps of FIGS. 5A and 5B. 図７は、図６の次の工程を示す図である。FIG. 7 is a diagram showing the next step of FIG. 図８は、図７の次の工程を示す図である。FIG. 8 is a diagram showing the next step of FIG. 7. 図９Ａおよび図９Ｂは、図８の次の工程を示す図である。9A and 9B are diagrams showing the next step of FIG. 図１０は、図９の次の工程を示す図である。FIG. 10 is a diagram showing the next step of FIG. 図１１は、図１０の次の工程を示す図である。FIG. 11 is a diagram showing the next step of FIG. 10. 図１２は、図１１の次の工程を示す図である。FIG. 12 is a diagram showing the next step of FIG. 図１３は、リーク防止構造の変形例を示す図である。FIG. 13 is a diagram showing a modified example of the leak prevention structure. 図１４は、リーク防止構造の変形例を示す図である。FIG. 14 is a diagram showing a modified example of the leak prevention structure. 図１５は、リーク防止構造の変形例を示す図である。FIG. 15 is a diagram showing a modified example of the leak prevention structure. 図１６は、リーク防止構造の変形例を示す図である。FIG. 16 is a diagram showing a modified example of the leak prevention structure. 図１７は、リーク防止構造の変形例を示す図である。FIG. 17 is a diagram showing a modified example of the leak prevention structure. 図１８は、リーク防止構造の変形例を示す図である。FIG. 18 is a diagram showing a modified example of the leak prevention structure.

以下では、本発明の実施の形態を、添付図面を参照して詳細に説明する。
図１は、本発明の一実施形態に係る半導体発光装置１の模式的な切断端面図である。図２は、図１の半導体発光素子５の模式的な平面図である。図３は、図２のIII－III断面における切断端面図である。なお、図１～図３は、半導体発光装置１を模式的に示すものであって、各構成要素同士の大きさの比率は、必ずしも実際のものと一致しているわけではない。また、図１は、半導体発光装置１の構成の説明を理解しやすいよう、説明に必要な構成要素の端面を便宜的に組み合わせて表したものであり、半導体発光装置１の特定の切断面における端面を示すものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cut end view of the semiconductor light emitting device 1 according to the embodiment of the present invention. FIG. 2 is a schematic plan view of the semiconductor light emitting device 5 of FIG. FIG. 3 is a cut end view in the III-III cross section of FIG. It should be noted that FIGS. 1 to 3 schematically show the semiconductor light emitting device 1, and the size ratio of each component does not necessarily match the actual one. Further, FIG. 1 shows a convenient combination of end faces of components necessary for explanation so that the description of the configuration of the semiconductor light emitting device 1 can be easily understood, and is shown in a specific cut surface of the semiconductor light emitting device 1. It does not indicate the end face.

半導体発光装置１は、基材２と、ｐ側配線３（アノード配線）と、ｎ側配線４（カソード配線）と、半導体発光素子５と、封止樹脂６とを含む。
基材２は、平板状の金属フレーム（たとえば、Ｃｕ合金等）からなり、たとえば、５０μｍ～３００μｍの厚さを有している。基材２は、互いに分離されたｐ側基材７およびｎ側基材８を含む。ｎ側基材８は、ｐ側基材７よりも相対的に大きく形成されており、その表面８Ａに、半導体発光素子５用のボンディング領域９を有している。なお、基材２は、金属フレームである必要はなく、たとえば、絶縁性の基材（たとえば、透明性樹脂基板、有色樹脂基板等）であってもよい
ｐ側配線３は、ｐ側基材７の表面７Ａに形成されている。ｐ側配線３は、たとえば、Ｃｕ、Ｎｉ、Ａｕ、Ａｇ、Ｐｄ、Ｓｎ等の金属材料からなり、封止樹脂６の内外に跨る所定パターンで配置されている。より具体的には、ｐ側配線３は、封止樹脂６で封止されたｐ側内部配線１０と、ｐ側内部配線１０から封止樹脂６の外側へ延びて露出する外部接続用のｐ側端子１１（アノード端子）とを一体的に含む。 The semiconductor light emitting device 1 includes a base material 2, a p-side wiring 3 (anode wiring), an n-side wiring 4 (cathode wiring), a semiconductor light emitting element 5, and a sealing resin 6.
The base material 2 is made of a flat metal frame (for example, a Cu alloy or the like) and has a thickness of, for example, 50 μm to 300 μm. The base material 2 includes a p-side base material 7 and an n-side base material 8 separated from each other. The n-side base material 8 is formed to be relatively larger than the p-side base material 7, and has a bonding region 9 for the semiconductor light emitting device 5 on the surface 8A thereof. The base material 2 does not have to be a metal frame, and may be, for example, an insulating base material (for example, a transparent resin substrate, a colored resin substrate, etc.). The p-side wiring 3 is a p-side base material. It is formed on the surface 7A of 7. The p-side wiring 3 is made of, for example, a metal material such as Cu, Ni, Au, Ag, Pd, Sn, and is arranged in a predetermined pattern straddling the inside and outside of the sealing resin 6. More specifically, the p-side wiring 3 is a p-side internal wiring 10 sealed with the sealing resin 6 and a p for external connection extending from the p-side internal wiring 10 to the outside of the sealing resin 6 and exposed. It integrally includes the side terminal 11 (anode terminal).

ｎ側配線４は、ｎ側基材８の表面８Ａに形成されている。ｎ側配線４は、たとえば、Ｃｕ、Ｎｉ、Ａｕ、Ａｇ、Ｐｄ、Ｓｎ等の金属材料からなり、封止樹脂６の内外に跨る所定パターンで配置されている。より具体的には、ｎ側配線４は、封止樹脂６で封止されたｎ側内部配線１２と、ｎ側内部配線１２から封止樹脂６の外側へ延びて露出する外部接続用のｎ側端子１３（カソード端子）とを一体的に含む。ｎ側内部配線１２は、ボンディング領域９を露出させるように、当該ボンディング領域９を避けて形成されている。 The n-side wiring 4 is formed on the surface 8A of the n-side base material 8. The n-side wiring 4 is made of, for example, a metal material such as Cu, Ni, Au, Ag, Pd, Sn, and is arranged in a predetermined pattern straddling the inside and outside of the sealing resin 6. More specifically, the n-side wiring 4 includes the n-side internal wiring 12 sealed with the sealing resin 6 and n for external connection extending from the n-side internal wiring 12 to the outside of the sealing resin 6 and exposed. It integrally includes the side terminal 13 (cathode terminal). The n-side internal wiring 12 is formed so as to avoid the bonding region 9 so as to expose the bonding region 9.

半導体発光素子５は、ｎ側基材８のボンディング領域９に、たとえばダイアタッチ剤（ペースト）等を介して、ダイボンディングされている。半導体発光素子５は、基材２に対して、配線を介さずに直接ボンディングされている。
半導体発光素子５は、基板１４と、ｎ型半導体層１５と、発光層１６と、ｐ型半導体層１７と、ｎ側電極１８と、ｐ側電極１９とを含む。ｎ型半導体層１５、発光層１６およびｐ型半導体層１７は、半導体積層構造２０を構成している。 The semiconductor light emitting device 5 is die-bonded to the bonding region 9 of the n-side base material 8 via, for example, a die-attaching agent (paste). The semiconductor light emitting device 5 is directly bonded to the base material 2 without using wiring.
The semiconductor light emitting device 5 includes a substrate 14, an n-type semiconductor layer 15, a light emitting layer 16, a p-type semiconductor layer 17, an n-side electrode 18, and a p-side electrode 19. The n-type semiconductor layer 15, the light emitting layer 16 and the p-type semiconductor layer 17 constitute a semiconductor laminated structure 20.

基板１４は、たとえば、サファイア等の絶縁性基板であってもよいし、ＧａＮ、ＳｉＣ等の半導体基板であってもよい。基板１４は、平面視長方形状に形成されている。基板１４の厚さは、たとえば、８０μｍ～１００μｍである。基板１４では、図１における上面が表面１４Ａであり、図１における下面が裏面１４Ｂである。この実施形態では、基板１４の表面１４Ａ側、つまり、基板１４に対して半導体積層構造２０側は、光が取り出される光取出し面となっている。 The substrate 14 may be, for example, an insulating substrate such as sapphire, or a semiconductor substrate such as GaN or SiC. The substrate 14 is formed in a rectangular shape in a plan view. The thickness of the substrate 14 is, for example, 80 μm to 100 μm. In the substrate 14, the upper surface in FIG. 1 is the front surface 14A, and the lower surface in FIG. 1 is the back surface 14B. In this embodiment, the surface 14A side of the substrate 14, that is, the semiconductor laminated structure 20 side with respect to the substrate 14, is a light extraction surface from which light is taken out.

半導体積層構造２０は、ｎ型半導体層１５、発光層１６およびｐ型半導体層１７を含む。ｎ型半導体層１５は発光層１６に対して基板１４側に配置されており、ｐ型半導体層１７は発光層１６に対してｎ型半導体層１５の反対側に配置されている。こうして、発光層１６が、ｎ型半導体層１５およびｐ型半導体層１７によって挟持されていて、ダブルヘテロ接合が形成されている。発光層１６には、ｎ型半導体層１５から電子が注入され、ｐ型半導体層１７から正孔が注入される。これらが発光層１６で再結合することによって、光が発生するようになっている。 The semiconductor laminated structure 20 includes an n-type semiconductor layer 15, a light emitting layer 16 and a p-type semiconductor layer 17. The n-type semiconductor layer 15 is arranged on the substrate 14 side with respect to the light emitting layer 16, and the p-type semiconductor layer 17 is arranged on the opposite side of the n-type semiconductor layer 15 with respect to the light emitting layer 16. In this way, the light emitting layer 16 is sandwiched between the n-type semiconductor layer 15 and the p-type semiconductor layer 17, and a double heterojunction is formed. Electrons are injected into the light emitting layer 16 from the n-type semiconductor layer 15, and holes are injected from the p-type semiconductor layer 17. Light is generated by recombination of these in the light emitting layer 16.

また、半導体積層構造２０は、基板１４と同様に、平面視長方形状に形成されており、互いに対向する短辺に沿う第１短端面２０Ａおよび第２短端面２０Ｂ、ならびに互いに対向する長辺に沿う第１長端面２０Ｃおよび第２長端面２０Ｄを有している。また、半導体積層構造２０は、互いに対角関係となる第１角部２０Ｅおよび第２角部２０Ｆ、ならびに互いに対角関係となる第３角部２０Ｇおよび第４角部２０Ｈを有している。第１短端面２０Ａの各端部に、第１角部２０Ｅおよび第３角部２０Ｇが配置され、第２短端面２０Ｂの各端部に、第２角部２０Ｆおよび第４角部２０Ｈが配置されている。 Further, the semiconductor laminated structure 20 is formed in a rectangular shape in a plan view like the substrate 14, and is formed on the first short end surface 20A and the second short end surface 20B along the short sides facing each other, and the long sides facing each other. It has a first long end face 20C and a second long end face 20D along the line. Further, the semiconductor laminated structure 20 has a first corner portion 20E and a second corner portion 20F that are diagonally related to each other, and a third corner portion 20G and a fourth corner portion 20H that are diagonally related to each other. The first corner portion 20E and the third corner portion 20G are arranged at each end of the first short end surface 20A, and the second corner portion 20F and the fourth corner portion 20H are arranged at each end of the second short end surface 20B. Has been done.

また、半導体積層構造２０は、ｎ型半導体層１５、発光層１６およびｐ型半導体層１７のトータルで５μｍ～１０μｍの厚さを有している。
ｎ型半導体層１５は、基板１４上に積層されている。ｎ型半導体層１５は、この実施形態では、発光層１６の発光波長λに対して透明なIII－V族窒化物半導体からなっていてもよい。ｎ型半導体層１５の厚さは、たとえば、３μｍ～６μｍであってもよい。 Further, the semiconductor laminated structure 20 has a total thickness of 5 μm to 10 μm of the n-type semiconductor layer 15, the light emitting layer 16 and the p-type semiconductor layer 17.
The n-type semiconductor layer 15 is laminated on the substrate 14. In this embodiment, the n-type semiconductor layer 15 may be made of a group III-V nitride semiconductor transparent to the emission wavelength λ of the light emitting layer 16. The thickness of the n-type semiconductor layer 15 may be, for example, 3 μm to 6 μm.

より具体的には、ｎ型半導体層１５は、ｎ型コンタクト層を含んでいてもよい。ｎ型コンタクト層は、たとえばｎ型不純物としてのシリコンがドーピングされたｎ型ＧａＮ層からなっていてもよい。ｎ型コンタクト層のｎ型不純物濃度は、たとえば１×１０^１８ｃｍ^－３程度であってもよい。ｎ型コンタクト層の厚さは、たとえば０．５μｍ～５．０μｍであってもよい。なお、ｎ型コンタクト層と基板１４との間に、アンドープ（不純物無添加）の層（たとえば、０．１μｍ～４．０μｍ厚さ）がさらに介在していてもよい。 More specifically, the n-type semiconductor layer 15 may include an n-type contact layer. The n-type contact layer may be composed of, for example, an n-type GaN layer doped with silicon as an n-type impurity. The concentration of n-type impurities in the n-type contact layer may be, for example, about 1 × 10 ¹⁸ cm ^-3 . The thickness of the n-type contact layer may be, for example, 0.5 μm to 5.0 μm. An undoped (no impurities added) layer (for example, 0.1 μm to 4.0 μm thickness) may be further interposed between the n-type contact layer and the substrate 14.

発光層１６は、たとえばＩｎＧａＰを含むＭＱＷ(multiple-quantum well)構造（多重量子井戸構造）を有していてもよく、電子と正孔とが再結合することによって光が発生し、その発生した光を増幅させるための層である。発光層１６の厚さは、たとえば、０．１μｍ～０．３μｍであってもよい。
より具体的には、発光層１６は、ＩｎＧａＰ層からなる量子井戸層（たとえば５ｎｍ厚）とＡｌＩｎＧａＰ層からなる障壁層（たとえば４ｎｍ厚）とを交互に複数周期繰り返し積層して構成された多重量子井戸（ＭＱＷ：Multiple-Quantum Well）構造を有していてもよい。 The light emitting layer 16 may have an MQW (multiple-quantum well) structure (multiple-quantum well structure) containing, for example, InGaP, and light is generated by recombination of electrons and holes, and the light is generated. It is a layer for amplifying light. The thickness of the light emitting layer 16 may be, for example, 0.1 μm to 0.3 μm.
More specifically, the light emitting layer 16 is a multiple quantum structure in which a quantum well layer made of an InGaP layer (for example, 5 nm thick) and a barrier layer made of an AlInGaP layer (for example, 4 nm thick) are alternately and repeatedly laminated for a plurality of cycles. It may have a well (MQW: Multiple-Quantum Well) structure.

ｐ型半導体層１７は、発光層１６上に形成されている。ｐ型半導体層１７は、この実施形態では、発光層１６の発光波長λに対して透明なIII－V族窒化物半導体からなっていてもよい。ｐ型半導体層１７の厚さは、たとえば、０．１μｍ～０．３μｍであってもよい。
より具体的には、ｐ型半導体層１７は、発光層１６上に形成されたｐ型電子阻止層と、ｐ型電子阻止層上に形成されたｐ型コンタクト層とを含んでいてもよい。 The p-type semiconductor layer 17 is formed on the light emitting layer 16. In this embodiment, the p-type semiconductor layer 17 may be made of a group III-V nitride semiconductor transparent to the emission wavelength λ of the light emitting layer 16. The thickness of the p-type semiconductor layer 17 may be, for example, 0.1 μm to 0.3 μm.
More specifically, the p-type semiconductor layer 17 may include a p-type electron blocking layer formed on the light emitting layer 16 and a p-type contact layer formed on the p-type electron blocking layer.

ｐ型電子阻止層は、たとえばｐ型不純物としてのマグネシウムがドーピングされたｐ型ＡｌＧａＮ層からなっていてもよい。ｐ型電子阻止層のｐ型不純物濃度は、たとえば３×１０^１９ｃｍ^－３程度であってもよい。ｐ型電子阻止層の厚さは、たとえば１ｎｍ～１００ｎｍであってもよい。
ｐ型コンタクト層は、たとえばｐ型不純物としてのマグネシウムがドーピングされたｐ型ＧａＮ層からなっていてもよい。ｐ型コンタクト層は、ｐ型電子阻止層のｐ型不純物濃度よりも大きいｐ型不純物濃度を有していてもよい。ｐ型コンタクト層のｐ型不純物濃度は、たとえば１×１０^２０ｃｍ^－３程度であってもよい。ｐ型コンタクト層の厚さは、たとえば０．０１μｍ～０．１μｍであってもよい。 The p-type electron blocking layer may be composed of, for example, a p-type AlGaN layer doped with magnesium as a p-type impurity. The concentration of p-type impurities in the p-type electron blocking layer may be, for example, about 3 × 10 ¹⁹ cm ^-3 . The thickness of the p-type electron blocking layer may be, for example, 1 nm to 100 nm.
The p-type contact layer may be composed of, for example, a p-type GaN layer doped with magnesium as a p-type impurity. The p-type contact layer may have a p-type impurity concentration higher than the p-type impurity concentration of the p-type electron blocking layer. The concentration of p-type impurities in the p-type contact layer may be, for example, about 1 × 10 ²⁰ cm ^-3 . The thickness of the p-type contact layer may be, for example, 0.01 μm to 0.1 μm.

半導体積層構造２０は、部分的に構造部２１を形成している。
より具体的には、ｐ型半導体層１７から発光層１６を介してｎ型半導体層１５に至る壁面２２を有する構造部２１が形成されている。構造部２１は、この実施形態では、半導体積層構造２０の全周に亘る壁面２２を有するメサ形状に形成されている。
構造部２１の周囲には、ｎ型半導体層１５が露出する上面２３Ａを有する本発明の第１部分の一例としての段部２３が、構造部２１の全周を取り囲むように形成されている。これにより、構造部２１の壁面２２は、全周にわたって、半導体積層構造２０の短端面２０Ａ，２０Ｂおよび長端面２０Ｃ，２０Ｄに対して、内側に後退した位置に配置されている。 The semiconductor laminated structure 20 partially forms the structural portion 21.
More specifically, a structural portion 21 having a wall surface 22 from the p-type semiconductor layer 17 to the n-type semiconductor layer 15 via the light emitting layer 16 is formed. In this embodiment, the structural portion 21 is formed in a mesa shape having a wall surface 22 extending over the entire circumference of the semiconductor laminated structure 20.
Around the structural portion 21, a stepped portion 23 as an example of the first portion of the present invention having an upper surface 23A on which the n-type semiconductor layer 15 is exposed is formed so as to surround the entire circumference of the structural portion 21. As a result, the wall surface 22 of the structural portion 21 is arranged at a position retracted inward with respect to the short end faces 20A and 20B and the long end faces 20C and 20D of the semiconductor laminated structure 20 over the entire circumference.

また、壁面２２は、図３に示すように、段部２３の上面２３Ａに対して４５°～９０°の角度θ_１で傾斜している。
この実施形態では、構造部２１は、半導体積層構造２０の第１短端面２０Ａから第２短端面２０Ｂへ向かって先細りとなる形状を有しており、当該先細り部分の側方に、ｎ側電極１８用の電極領域２４が形成されている。電極領域２４には、段部２３の上面２３Ａとしてｎ型半導体層１５が露出している。 Further, as shown in FIG. 3, the wall surface 22 is inclined at an angle θ ₁ of 45 ° to 90 ° with respect to the upper surface 23A of the step portion 23.
In this embodiment, the structural portion 21 has a shape that tapers from the first short end surface 20A of the semiconductor laminated structure 20 toward the second short end surface 20B, and the n-side electrode is lateral to the tapered portion. The electrode region 24 for 18 is formed. The n-type semiconductor layer 15 is exposed as the upper surface 23A of the step portion 23 in the electrode region 24.

より具体的には、構造部２１は、半導体積層構造２０の長辺に沿う方向における略中央と第１短端面２０Ａとの間に形成された平面視四角形状の本体部２５と、当該本体部２５から第２短端面２０Ｂへ向かって本体部２５よりも狭い幅で延びる、前記先細り部分としての延出部２６とを一体的に有している。この実施形態では、電極領域２４が半導体積層構造２０の第２角部２０Ｆに形成されるように、延出部２６は、第４角部２０Ｈに配置されており、半導体積層構造２０の長辺に沿って本体部２５の側面２５Ａと面一に連続する（段差なく連続する）側面２６Ａを有している。 More specifically, the structural portion 21 includes a main body portion 25 having a rectangular shape in a plan view formed between the substantially center and the first short end surface 20A in the direction along the long side of the semiconductor laminated structure 20, and the main body portion. It integrally has an extending portion 26 as the tapered portion extending from 25 toward the second short end surface 20B with a width narrower than that of the main body portion 25. In this embodiment, the extending portion 26 is arranged in the fourth corner portion 20H so that the electrode region 24 is formed in the second corner portion 20F of the semiconductor laminated structure 20, and the long side of the semiconductor laminated structure 20 is arranged. It has a side surface 25A that is continuous with the side surface 25A of the main body 25 and is continuous (continuous without a step).

ｎ側電極１８は、電極領域２４（第２角部２０Ｆ）に１つ配置されている。ｎ側電極１８は、この実施形態では、平面視円形状に形成されている。
また、ｎ側電極１８は、この実施形態では、ＡｕまたはＡｕを含む合金で構成されている。たとえば、ｎ側電極１８は、（基板１４側）Ｔｉ／Ａｕ／Ｍｏ／Ａｕで示される積層構造であってもよい。また、ｎ側電極１８は、構造部２１の上面２１Ａよりも低い高さ位置に上面１８Ａを有している。これにより、上面２１Ａに対して、ｎ側電極１８の上面１８Ａは相対的に低い位置にあり、ｐ側電極１９の上面１９Ａは相対的に高い位置にあり、上面１８Ａと上面１９Ａとの間に高低差が設けられている。たとえば、ｎ側電極１８の厚さは、１．０μｍ～４．０μｍである。 One n-side electrode 18 is arranged in the electrode region 24 (second corner portion 20F). In this embodiment, the n-side electrode 18 is formed in a circular shape in a plan view.
Further, the n-side electrode 18 is made of Au or an alloy containing Au in this embodiment. For example, the n-side electrode 18 may have a laminated structure represented by Ti / Au / Mo / Au (on the substrate 14 side). Further, the n-side electrode 18 has an upper surface 18A at a height lower than the upper surface 21A of the structural portion 21. As a result, the upper surface 18A of the n-side electrode 18 is relatively low with respect to the upper surface 21A, and the upper surface 19A of the p-side electrode 19 is relatively high, between the upper surface 18A and the upper surface 19A. There is a height difference. For example, the thickness of the n-side electrode 18 is 1.0 μm to 4.0 μm.

ｐ側電極１９は、構造部２１の上面２１Ａにおいて、半導体積層構造２０の第１角部２０Ｅに１つ配置されている。ｐ側電極１９は、この実施形態では、平面視円形状に形成されている。
また、ｐ側電極１９は、この実施形態では、ＡｕまたはＡｕを含む合金で構成されている。たとえば、ｐ側電極１９は、（基板１４側）Ｔｉ／Ａｕ／Ｍｏ／Ａｕで示される積層構造であってもよい。また、ｐ側電極１９の厚さは、たとえば、１．０μｍ～４．０μｍである。 One p-side electrode 19 is arranged on the upper surface 21A of the structural portion 21 at the first corner portion 20E of the semiconductor laminated structure 20. In this embodiment, the p-side electrode 19 is formed in a circular shape in a plan view.
Further, the p-side electrode 19 is made of Au or an alloy containing Au in this embodiment. For example, the p-side electrode 19 may have a laminated structure represented by Ti / Au / Mo / Au (on the substrate 14 side). The thickness of the p-side electrode 19 is, for example, 1.0 μm to 4.0 μm.

このように、この半導体発光素子５では、ｎ側電極１８およびｐ側電極１９が、互いに対角関係となるように配置されている。
また、半導体発光素子５の半導体積層構造２０には、構造部２１から分離して配置され、構造部２１と同じ積層構造を有する第１積層部２７、第２積層部２８、第３積層部２９および第４積層部３０が形成されている。すなわち、第１～第４積層部２７～３０は、半導体積層構造２０と同様に、基板１４側から順に、ｎ型半導体層１５、発光層１６およびｐ型半導体層１７が順に積層されてなる構造を有している。 As described above, in the semiconductor light emitting device 5, the n-side electrode 18 and the p-side electrode 19 are arranged so as to be in a diagonal relationship with each other.
Further, the semiconductor laminated structure 20 of the semiconductor light emitting element 5 is arranged separately from the structural portion 21, and has the same laminated structure as the structural portion 21, the first laminated portion 27, the second laminated portion 28, and the third laminated portion 29. And the fourth laminated portion 30 is formed. That is, the first to fourth laminated portions 27 to 30 have a structure in which the n-type semiconductor layer 15, the light emitting layer 16 and the p-type semiconductor layer 17 are laminated in order from the substrate 14 side, similarly to the semiconductor laminated structure 20. have.

より具体的には、第１積層部２７は、本発明のリーク防止構造の一例として構成されており、第１角部２０Ｅにおいて、第１短端面２０Ａ側およびこれに直交する第１長端面２０Ｃ側の両側からｐ側電極１９を挟むように、平面視Ｌ字状に形成されている。つまり、第１短端面２０Ａに沿う第１直線部３１と、第１長端面２０Ｃに沿う第２直線部３２とを一体的に含む壁状の第１積層部２７が、構造部２１の角部を２方向から取り囲んでいる。 More specifically, the first laminated portion 27 is configured as an example of the leak prevention structure of the present invention, and in the first corner portion 20E, the first short end surface 20A side and the first long end surface 20C orthogonal to the first short end surface 20A side. It is formed in an L-shape in a plan view so as to sandwich the p-side electrode 19 from both sides. That is, the wall-shaped first laminated portion 27 integrally including the first straight line portion 31 along the first short end surface 20A and the second straight line portion 32 along the first long end surface 20C is a corner portion of the structural portion 21. Surrounds from two directions.

さらに、この実施形態では、第１積層部２７は、基板１４と面一な半導体積層構造２０の端面２０Ａ，２０Ｃの一部を構成するように形成されている。つまり、半導体積層構造２０の第１角部２０Ｅにおいて、第１短端面２０Ａは第１直線部３１の端面で構成されており、第１長端面２０Ｃは第２直線部３２の端面で構成されている。
また、この実施形態では、図２に示すＸ方向に沿って、後述するｐ側ボンディングワイヤ３６がｐ側電極１９に接続される。したがって、第１積層部２７の第１直線部３１は、第１長端面２０Ｃを基準にして、Ｘ方向に直交するＹ方向におけるｐ側電極１９の端部よりも第２長端面２０Ｄ側に端部を有するように、その長さが設定されることが好ましい。これにより、Ｘ方向に沿ってどの方向からｐ側ボンディングワイヤ３６がｐ側電極１９に接続されても、当該ｐ側ボンディングワイヤ３６がｎ型半導体層１５に接触することを確実に防止することができる。 Further, in this embodiment, the first laminated portion 27 is formed so as to form a part of the end faces 20A and 20C of the semiconductor laminated structure 20 which is flush with the substrate 14. That is, in the first corner portion 20E of the semiconductor laminated structure 20, the first short end surface 20A is composed of the end face of the first straight line portion 31, and the first long end face 20C is composed of the end face of the second straight line portion 32. There is.
Further, in this embodiment, the p-side bonding wire 36 described later is connected to the p-side electrode 19 along the X direction shown in FIG. Therefore, the first straight line portion 31 of the first laminated portion 27 ends on the second long end surface 20D side of the end portion of the p-side electrode 19 in the Y direction orthogonal to the X direction with respect to the first long end surface 20C. It is preferable that the length is set so as to have a portion. This makes it possible to reliably prevent the p-side bonding wire 36 from coming into contact with the n-type semiconductor layer 15 regardless of which direction the p-side bonding wire 36 is connected to the p-side electrode 19 along the X direction. can.

第２積層部２８は、第２角部２０Ｆにおいて、ｎ側電極１８から離れて配置され、第２短端面２０Ｂと第２長端面２０Ｄとの交点部を構成する平面視ドット状に形成されている。つまり、第２積層部２８は、第２短端面２０Ｂと第２長端面２０Ｄとの交点部において、基板１４と面一な半導体積層構造２０の端面２０Ｂ，２０Ｄの一部を構成するように形成されている。 The second laminated portion 28 is arranged in the second corner portion 20F away from the n-side electrode 18, and is formed in a plan view dot shape forming an intersection portion between the second short end surface 20B and the second long end surface 20D. There is. That is, the second laminated portion 28 is formed so as to form a part of the end faces 20B and 20D of the semiconductor laminated structure 20 flush with the substrate 14 at the intersection portion between the second short end face 20B and the second long end face 20D. Has been done.

第３積層部２９は、第３角部２０Ｇにおいて、半導体積層構造２０の第２長端面２０Ｄに沿うライン状に形成されている。この第３積層部２９の長さは、第１積層部２７の第２直線部３２の長さと同じである。さらに、この実施形態では、第３積層部２９は、基板１４と面一な半導体積層構造２０の第２長端面２０Ｄの一部を構成するように形成されている。 The third laminated portion 29 is formed in a line shape along the second long end surface 20D of the semiconductor laminated structure 20 in the third square portion 20G. The length of the third laminated portion 29 is the same as the length of the second straight line portion 32 of the first laminated portion 27. Further, in this embodiment, the third laminated portion 29 is formed so as to form a part of the second long end surface 20D of the semiconductor laminated structure 20 which is flush with the substrate 14.

第４積層部３０は、第４角部２０Ｈにおいて、半導体積層構造２０の第２短端面２０Ｂに沿うライン状に形成されている。この第４積層部３０の長さは、第１積層部２７の第１直線部３１の長さと同じである。さらに、この実施形態では、第４積層部３０は、基板１４と面一な半導体積層構造２０の第２短端面２０Ｂの一部を構成するように形成されている。 The fourth laminated portion 30 is formed in a line shape along the second short end surface 20B of the semiconductor laminated structure 20 in the fourth square portion 20H. The length of the fourth laminated portion 30 is the same as the length of the first straight line portion 31 of the first laminated portion 27. Further, in this embodiment, the fourth laminated portion 30 is formed so as to form a part of the second short end surface 20B of the semiconductor laminated structure 20 which is flush with the substrate 14.

また、半導体積層構造２０の最表面には、図３に示すように、絶縁膜３３が形成されている。絶縁膜３３は、たとえば酸化シリコン（ＳｉＯ_２）等の絶縁材料からなる。絶縁膜３３は、ｐ側電極１９を覆うと共に、構造部２１の壁面２２を介して、構造部２１の上面２１Ａと段部２３の上面２３Ａとの間に跨るように形成されている。この実施形態では、前述の第１～第４積層部２７～３０が形成された領域において、絶縁膜３３の端縁３４は、第１～第４積層部２７～３０の内壁面（図３では、第１積層部２７の内壁面２７Ａのみ示している。）よりも内側に配置されている。つまり、第１～第４積層部２７～３０は絶縁膜３３で覆われておらず、第１～第４積層部２７～３０の各ｐ型半導体層１７は露出している。また、絶縁膜３３のｐ側電極１９を覆う部分には、ｐ側電極１９の上面１９Ａの一部をパッドとして露出させる開口３５が形成されている。また、絶縁膜３３の厚さは、たとえば、１０００Å～２００００Å（好ましくは、４５００Å～５５００Å）である。 Further, as shown in FIG. 3, an insulating film 33 is formed on the outermost surface of the semiconductor laminated structure 20. The insulating film 33 is made of an insulating material such as silicon oxide (SiO ₂ ). The insulating film 33 covers the p-side electrode 19 and is formed so as to straddle between the upper surface 21A of the structural portion 21 and the upper surface 23A of the step portion 23 via the wall surface 22 of the structural portion 21. In this embodiment, in the region where the first to fourth laminated portions 27 to 30 are formed, the edge 34 of the insulating film 33 is the inner wall surface of the first to fourth laminated portions 27 to 30 (in FIG. 3). , Only the inner wall surface 27A of the first laminated portion 27 is shown). That is, the first to fourth laminated portions 27 to 30 are not covered with the insulating film 33, and each p-type semiconductor layer 17 of the first to fourth laminated portions 27 to 30 is exposed. Further, an opening 35 is formed in a portion of the insulating film 33 that covers the p-side electrode 19 to expose a part of the upper surface 19A of the p-side electrode 19 as a pad. The thickness of the insulating film 33 is, for example, 1000 Å to 20000 Å (preferably 4500 Å to 5500 Å).

そして、半導体発光素子５のｐ側電極１９およびｎ側電極１８は、それぞれ、ｐ側ボンディングワイヤ３６およびｎ側ボンディングワイヤ３７によって、基材２上のｐ側配線３およびｎ側配線４に接続されている。各ボンディングワイヤ３６，３７は、たとえばＡｕワイヤからなり、たとえば、１５μｍ～３５μｍの径を有している。
ｐ側ボンディングワイヤ３６は、図１に示すように、ｐ側配線３にボールボンド部３８を有し、ｐ側電極１９にウェッジボンド部３９を有しており、ボールボンド部３８とウェッジボンド部３９との間のワイヤ部がループ状に形成されていない。つまり、ｐ側ボンディングワイヤ３６は、図１に示す断面視において、ｐ側電極１９に対してほぼ鉛直上方に延び、放物線を描くようにｐ側配線３に延びるようなループ状ではなく、ｐ側電極１９上のウェッジボンド部３９から低い傾斜角度で側方に延び、ボールボンド部３８に至っている。図３に示すように、たとえば、ｐ側電極１９の上面１９Ａに対するｐ側ボンディングワイヤ３６の傾斜角度θ_２は、５°～４５°（好ましくは、１０°～１５°）であり、ｐ側電極１９の上面１９Ａからｐ側ボンディングワイヤ３６の頂部までの高さＨ_１は、たとえば、５０μｍ～２００μｍ（好ましくは、１００μｍ～１５０μｍである。これにより、半導体積層構造２０の上方へのｐ側ボンディングワイヤ３６の膨出量を低く抑えることができるので、半導体発光装置１（パッケージ）の低背化を達成することができる。 The p-side electrode 19 and the n-side electrode 18 of the semiconductor light emitting device 5 are connected to the p-side wiring 3 and the n-side wiring 4 on the base material 2 by the p-side bonding wire 36 and the n-side bonding wire 37, respectively. ing. Each of the bonding wires 36, 37 is made of, for example, Au wire and has a diameter of, for example, 15 μm to 35 μm.
As shown in FIG. 1, the p-side bonding wire 36 has a ball bond portion 38 on the p-side wiring 3 and a wedge bond portion 39 on the p-side electrode 19, and has a ball bond portion 38 and a wedge bond portion. The wire portion between the 39 and the 39 is not formed in a loop shape. That is, in the cross-sectional view shown in FIG. 1, the p-side bonding wire 36 does not have a loop shape extending substantially vertically upward with respect to the p-side electrode 19 and extending to the p-side wiring 3 so as to draw a parabola, but the p-side. It extends laterally from the wedge bond portion 39 on the electrode 19 at a low inclination angle and reaches the ball bond portion 38. As shown in FIG. 3, for example, the inclination angle θ ₂ of the p-side bonding wire 36 with respect to the upper surface 19A of the p-side electrode 19 is 5 ° to 45 ° (preferably 10 ° to 15 °), and the p-side electrode The height H ₁ from the upper surface 19A of 19 to the top of the p-side bonding wire 36 is, for example, 50 μm to 200 μm (preferably 100 μm to 150 μm. Thereby, the p-side bonding wire upward of the semiconductor laminated structure 20). Since the amount of swelling of 36 can be suppressed to a low level, it is possible to achieve a low profile of the semiconductor light emitting device 1 (package).

また、ｐ側ボンディングワイヤ３６は、ボールボンド部３８とウェッジボンド部３９との間に、下方へ膨出するように凹む凹部４０を有している。この凹部４０は、後述する樹脂の重み等によって形成されるものである。
また、図２に破線で示すように、ｐ側ボンディングワイヤ３６は、第１積層部２７を超えるように、半導体発光素子５の上方領域とその周辺領域との間を跨っている。つまり、半導体発光素子５の周縁部においては、ｐ側ボンディングワイヤ３６と、第１積層部２７のｐ型半導体層１７とが上下方向に対向している。なお、図２では、ｐ側ボンディングワイヤ３６が第１積層部２７の第１直線部３１を超える場合を示しているが、むろん、ｐ側ボンディングワイヤ３６は、第１積層部２７の第２直線部３２を超えるように配置されていてもよい。 Further, the p-side bonding wire 36 has a recess 40 recessed between the ball bond portion 38 and the wedge bond portion 39 so as to bulge downward. The recess 40 is formed by the weight of the resin or the like, which will be described later.
Further, as shown by the broken line in FIG. 2, the p-side bonding wire 36 straddles between the upper region of the semiconductor light emitting device 5 and the peripheral region thereof so as to exceed the first laminated portion 27. That is, in the peripheral portion of the semiconductor light emitting element 5, the p-side bonding wire 36 and the p-type semiconductor layer 17 of the first laminated portion 27 face each other in the vertical direction. Note that FIG. 2 shows a case where the p-side bonding wire 36 exceeds the first straight line portion 31 of the first laminated portion 27, but of course, the p-side bonding wire 36 is the second straight line of the first laminated portion 27. It may be arranged so as to exceed the portion 32.

ｎ側ボンディングワイヤ３７は、図１に示すように、ｎ側配線４にボールボンド部４１を有し、ｎ側電極１８にウェッジボンド部４２を有しており、ボールボンド部４１とウェッジボンド部４２との間のワイヤ部がループ状に形成されていない。つまり、ｎ側ボンディングワイヤ３７は、図１に示す断面視において、ｎ側電極１８に対してほぼ鉛直上方に延び、放物線を描くようにｎ側配線４に延びるようなループ状ではなく、ｎ側電極１８上のウェッジボンド部４２から低い傾斜角度で側方に延び、ボールボンド部４１に至っている。つまり、図３に示したｐ側ボンディングワイヤ３６の形態と同じである。 As shown in FIG. 1, the n-side bonding wire 37 has a ball bond portion 41 on the n-side wiring 4 and a wedge bond portion 42 on the n-side electrode 18, and has a ball bond portion 41 and a wedge bond portion. The wire portion between the wire and the 42 is not formed in a loop shape. That is, in the cross-sectional view shown in FIG. 1, the n-side bonding wire 37 does not have a loop shape extending substantially vertically upward with respect to the n-side electrode 18 and extending to the n-side wiring 4 so as to draw a parabola, but the n-side. It extends laterally from the wedge bond portion 42 on the electrode 18 at a low inclination angle and reaches the ball bond portion 41. That is, it is the same as the form of the p-side bonding wire 36 shown in FIG.

また、ｎ側ボンディングワイヤ３７は、ボールボンド部４１とウェッジボンド部４２との間に、下方へ膨出するように凹む凹部４３を有している。この凹部４３は、後述する樹脂の重み等によって形成されるものである。
また、図２に破線で示すように、ｎ側ボンディングワイヤ３７は、第２積層部２８と第４積層部３０との間を超えるように、半導体発光素子５の上方領域とその周辺領域との間を跨っている。つまり、半導体発光素子５の周縁部においては、ｎ側ボンディングワイヤ３７と、電極領域２４のｎ型半導体層１５とが上下方向に対向している。図２では、ｎ側ボンディングワイヤ３７が第２積層部２８と第４積層部３０との間を超える場合を示しているが、むろん、ｎ側ボンディングワイヤ３７は、第２積層部２８と第３積層部２９との間を超えるように配置されていてもよい。 Further, the n-side bonding wire 37 has a recess 43 recessed between the ball bond portion 41 and the wedge bond portion 42 so as to bulge downward. The recess 43 is formed by the weight of the resin or the like, which will be described later.
Further, as shown by a broken line in FIG. 2, the n-side bonding wire 37 has a region above the semiconductor light emitting device 5 and a peripheral region thereof so as to extend beyond the space between the second laminated portion 28 and the fourth laminated portion 30. It straddles the space. That is, in the peripheral portion of the semiconductor light emitting device 5, the n-side bonding wire 37 and the n-type semiconductor layer 15 in the electrode region 24 face each other in the vertical direction. FIG. 2 shows a case where the n-side bonding wire 37 exceeds between the second laminated portion 28 and the fourth laminated portion 30, but of course, the n-side bonding wire 37 has the second laminated portion 28 and the third laminated portion 28. It may be arranged so as to exceed the space between the laminated portion 29 and the laminated portion 29.

なお、ｎ側ボンディングワイヤ３７は、図２に一点鎖線で示すように第４積層部３０を超えるように、半導体発光素子５の上方領域とその周辺領域との間を跨っていてもよいし、第２積層部２８を超えていてもよい。この場合、ｎ側ボンディングワイヤ３７がこれら積層部２８，３０のｐ型半導体層１７に接近し、場合によっては接触することがある。しかしながら、当該ｐ型半導体層１７は、その下方のｎ型半導体層１５を介して、構造部２１のｐ型半導体層１７と分離されている。そのため、たとえｎ側ボンディングワイヤ３７が積層部２８，３０のｐ型半導体層１７に接触しても、この接触に起因して半導体発光素子５にリークが発生することはない。 The n-side bonding wire 37 may straddle between the upper region of the semiconductor light emitting device 5 and the peripheral region thereof so as to exceed the fourth laminated portion 30 as shown by the alternate long and short dash line in FIG. It may exceed the second laminated portion 28. In this case, the n-side bonding wire 37 may approach the p-type semiconductor layer 17 of the laminated portions 28 and 30 and may come into contact with the p-type semiconductor layer 17 in some cases. However, the p-type semiconductor layer 17 is separated from the p-type semiconductor layer 17 of the structural portion 21 via the n-type semiconductor layer 15 below the p-type semiconductor layer 17. Therefore, even if the n-side bonding wire 37 comes into contact with the p-type semiconductor layer 17 of the laminated portions 28 and 30, leakage does not occur in the semiconductor light emitting element 5 due to this contact.

封止樹脂６は、たとえばシリコーン樹脂等の透光性樹脂からなり、半導体発光素子５、ボンディングワイヤ３６，３７、ｐ側配線３（一部）およびｎ側配線４（一部）を覆うように、基材２上に設けられている。封止樹脂６は、この実施形態では、基材２の長手方向両側に傾斜面４４，４４を有する、側面視等脚台形状に形成されている。また、封止樹脂６の高さＨ_２（基材２の上面から封止樹脂６の上面までの高さ）は、たとえば、１００μｍ～２００μｍ（好ましくは、１００μｍ～１５０μｍ）である。 The sealing resin 6 is made of a translucent resin such as a silicone resin so as to cover the semiconductor light emitting element 5, the bonding wires 36 and 37, the p-side wiring 3 (part) and the n-side wiring 4 (part). , Is provided on the base material 2. In this embodiment, the sealing resin 6 is formed in an isosceles trapezoidal shape having inclined surfaces 44, 44 on both sides in the longitudinal direction of the base material 2. The height H ₂ of the sealing resin 6 (height from the upper surface of the base material 2 to the upper surface of the sealing resin 6) is, for example, 100 μm to 200 μm (preferably 100 μm to 150 μm).

図４～図１２は、半導体発光装置１の製造工程の一部を工程順に示す図である。図４～図１２では、各工程の説明を分かりやすくするために、各工程に合わせた平面図もしくは断面図を提供している。また、図４～図１２の各図において、図面の明瞭化のため、説明にあたって特に必要でない参照符号については省略している。したがって、図１～図３に示した参照符号が、図４～図１２に示されていない場合があり、また、図４～図１２のいくつかの図で示した参照符号が、図４～図１２の他の図で示されていない場合がある。 4 to 12 are diagrams showing a part of the manufacturing process of the semiconductor light emitting device 1 in the order of processes. In FIGS. 4 to 12, in order to make the explanation of each process easy to understand, a plan view or a cross-sectional view tailored to each process is provided. Further, in each of FIGS. 4 to 12, reference numerals that are not particularly necessary for explanation are omitted for the sake of clarity of the drawings. Therefore, the reference numerals shown in FIGS. 1 to 3 may not be shown in FIGS. 4 to 12, and the reference numerals shown in some of FIGS. 4 to 12 may be shown in FIGS. 4 to 12. It may not be shown in other figures of FIG.

半導体発光装置１を製造するには、半導体発光素子５が製造される。たとえば、図４Ａおよび図４Ｂに示すように、ウエハ状態の基板１４が準備される。ウエハ状態の基板１４には、破線で示すように、半導体発光素子５が１つずつ形成される素子領域４５を分割する境界ライン４６が設定されている。図４Ａおよび図４Ｂでは、それぞれ、４つの素子領域４５および２つの素子領域４５のみが示されているが、実際には、ウエハ状態の基板１４に多数の素子領域４５が形成されることとなる。 To manufacture the semiconductor light emitting device 1, the semiconductor light emitting device 5 is manufactured. For example, as shown in FIGS. 4A and 4B, the substrate 14 in a wafer state is prepared. As shown by the broken line, the substrate 14 in the wafer state is set with a boundary line 46 that divides the element region 45 in which the semiconductor light emitting elements 5 are formed one by one. In FIGS. 4A and 4B, only four element regions 45 and two element regions 45 are shown, respectively, but in reality, a large number of element regions 45 are formed on the substrate 14 in a wafer state. ..

そして、基板１４上に、いわゆるエピタキシャル成長（たとえば、気相エピタキシャル成長（VPE：Vapor Phase Epitaxy）、液相エピタキシャル成長（LPE：Liquid Phase Epitaxy）、固相エピタキシャル成長（SPE：Solid Phase Epitaxy）、分子線エピタキシャル成長（MBE：Molecular Beam Epitaxy）等）で、ｎ型半導体層１５、発光層１６およびｐ型半導体層１７をこの順で積層することによって、半導体積層構造２０が形成される。 Then, on the substrate 14, so-called epitaxial growth (for example, vapor phase epitaxial growth (VPE: Vapor Phase Epitaxy), liquid phase epitaxial growth (LPE: Liquid Phase Epitaxy), solid phase epitaxial growth (SPE: Solid Phase Epitaxy), molecular beam epitaxial growth (MBE)) : Molecular Beam Epitaxy) etc.), the semiconductor laminated structure 20 is formed by laminating the n-type semiconductor layer 15, the light emitting layer 16 and the p-type semiconductor layer 17 in this order.

次に、図５Ａおよび図５Ｂに示すように、半導体積層構造２０の一部が選択的に除去される。たとえば、半導体積層構造２０の表面から、ｐ型半導体層１７、発光層１６およびｎ型半導体層１５の一部が半導体積層構造２０の全周に亘ってエッチング除去される。これにより、構造部２１が形成されると共に、構造部２１の周囲に、ｎ型半導体層１５、発光層１６およびｐ型半導体層１７の構造からなる積層部４７が形成される。積層部４７は、図５Ａに示すように、互いに隣り合う素子領域４５の境界ライン４６を跨ぐように形成される。より具体的には、格子状に形成された境界ライン４６の第１方向（図５ＡのＹ方向）に沿って境界ライン４６に重なる第１直線部４８と、当該第１方向に直交する第２方向（図５ＡのＸ方向）に沿って境界ライン４６に重なる第２直線部４９とを一体的に含む平面視Ｌ字状に形成される。これにより、積層部４７は、格子状の境界ライン４６の交点５０に対して、左下の第１の素子領域４５（Ａ）、当該第１の素子領域４５（Ａ）と対角関係にある右上の第２の素子領域４５（Ｂ）、右下の第３の素子領域４５（Ｃ）および当該第３の素子領域４５（Ｃ）と対角関係にある左上の第４の素子領域４５（Ｄ）に跨って形成される。 Next, as shown in FIGS. 5A and 5B, a part of the semiconductor laminated structure 20 is selectively removed. For example, a part of the p-type semiconductor layer 17, the light emitting layer 16 and the n-type semiconductor layer 15 is removed by etching from the surface of the semiconductor laminated structure 20 over the entire circumference of the semiconductor laminated structure 20. As a result, the structural portion 21 is formed, and a laminated portion 47 having the structure of the n-type semiconductor layer 15, the light emitting layer 16 and the p-type semiconductor layer 17 is formed around the structural portion 21. As shown in FIG. 5A, the laminated portion 47 is formed so as to straddle the boundary line 46 of the element regions 45 adjacent to each other. More specifically, a first straight line portion 48 overlapping the boundary line 46 along the first direction (Y direction in FIG. 5A) of the boundary line 46 formed in a grid pattern, and a second orthogonal to the first direction. It is formed in an L-shape in a plan view integrally including a second straight line portion 49 overlapping the boundary line 46 along the direction (X direction in FIG. 5A). As a result, the laminated portion 47 has an upper right diagonal relationship with the first element region 45 (A) at the lower left and the first element region 45 (A) with respect to the intersection 50 of the grid-like boundary lines 46. Second element region 45 (B), lower right third element region 45 (C), and upper left fourth element region 45 (D) diagonally related to the third element region 45 (C). ) Is formed.

次に、図６Ａおよび図６Ｂに示すように、たとえばスパッタ法で電極材料が堆積され、当該電極材料がパターニングされることによって、ｎ側電極１８およびｐ側電極１９が形成される。
次に、図７に示すように、たとえばＣＶＤ法によって、半導体積層構造２０の最表面全体に絶縁膜３３が形成される。 Next, as shown in FIGS. 6A and 6B, the electrode material is deposited by, for example, a sputtering method, and the electrode material is patterned to form the n-side electrode 18 and the p-side electrode 19.
Next, as shown in FIG. 7, the insulating film 33 is formed on the entire outermost surface of the semiconductor laminated structure 20 by, for example, the CVD method.

次に、図８に示すように、絶縁膜３３が選択的にエッチングされることによって、ｐ側電極１９を露出させる開口３５が形成されると共に、積層部４７を覆っていた絶縁膜３３の部分も除去される。これにより、絶縁膜３３の端縁３４が、積層部４７の内壁面よりも内側に配置されることとなる。
次に、図９Ａおよび図９Ｂに示すように、基板１４の裏面側から、境界ライン４６に沿ってスクライブ加工を施される。スクライブ加工は、レーザ加工機（レーザスクライバ）によって行ってもよいし、ダイヤモンドスクライバによって行ってもよい。スクライブ加工によって、基板１４には、境界ライン４６に沿って、連続した端面加工痕５１が形成されることになる。次に、基板１４の表面側から、境界ライン４６に沿ってブレード５２（たとえばセラミックブレード）をあてがって、基板１４に外力が加えられる。これにより、基板１４は、端面加工痕５１に沿って劈開される。 Next, as shown in FIG. 8, the insulating film 33 is selectively etched to form an opening 35 that exposes the p-side electrode 19, and a portion of the insulating film 33 that covers the laminated portion 47. Is also removed. As a result, the edge 34 of the insulating film 33 is arranged inside the inner wall surface of the laminated portion 47.
Next, as shown in FIGS. 9A and 9B, scribe processing is performed along the boundary line 46 from the back surface side of the substrate 14. The scribe processing may be performed by a laser processing machine (laser scriber) or a diamond scriber. By scribe processing, continuous end face processing marks 51 are formed on the substrate 14 along the boundary line 46. Next, an external force is applied to the substrate 14 by applying a blade 52 (for example, a ceramic blade) along the boundary line 46 from the surface side of the substrate 14. As a result, the substrate 14 is cleaved along the end face processing mark 51.

こうして、図２に示した半導体積層構造２０の短端面２０Ａ，２０Ｂおよび長端面２０Ｃ，２０Ｄが形成され、個々の半導体発光素子５が得られる。４つの素子領域４５に跨る積層部４７は、この劈開時に、各素子領域４５（Ａ）～（Ｄ）に残るように４分割される。具体的には、第１の素子領域４５（Ａ）内の部分が、図２の第１積層部２７として残り、第２の素子領域４５（Ｂ）内の部分が、図２の第２積層部２８として残り、第３の素子領域４５（Ｃ）内の部分が、図２の第３積層部２９として残り、第４の素子領域４５（Ｄ）内の部分が、図２の第４積層部３０として残る。 In this way, the short end faces 20A and 20B and the long end faces 20C and 20D of the semiconductor laminated structure 20 shown in FIG. 2 are formed, and individual semiconductor light emitting devices 5 are obtained. The laminated portion 47 straddling the four element regions 45 is divided into four so as to remain in the element regions 45 (A) to (D) at the time of cleavage. Specifically, the portion in the first element region 45 (A) remains as the first laminated portion 27 in FIG. 2, and the portion in the second element region 45 (B) is the second laminated portion in FIG. 2. The portion remaining as the portion 28, the portion in the third element region 45 (C) remains as the third laminated portion 29 in FIG. 2, and the portion in the fourth element region 45 (D) is the fourth laminated portion in FIG. It remains as part 30.

次に、図１０に示すように、半導体発光素子５が、ダイアタッチ剤等を介して、基材２にダイボンディングされる。
次に、図１１に示すように、ｐ側ボンディングワイヤ３６およびｎ側ボンディングワイヤ３７のボンディング工程が行われる。たとえば、ｐ側ボンディングワイヤ３６のボンディング工程では、まず、キャピラリに形成されたボールを、ｐ側配線３に超音波振動を印加しながら押し付けることによって、ｐ側配線３にボールボンド部３８が形成される。次に、ボールボンド部３８が形成されたワイヤをキャピラリで保持した状態で、ｐ側電極１９まで延ばし、ｐ側電極１９上において、当該ワイヤに、超音波振動を印加しながらキャピラリを押し付けることによって切断し、ウェッジボンド部３９が形成される。ｎ側ボンディングワイヤ３７も、同様の工程で形成される。 Next, as shown in FIG. 10, the semiconductor light emitting device 5 is die-bonded to the base material 2 via a die attachant or the like.
Next, as shown in FIG. 11, a bonding step of the p-side bonding wire 36 and the n-side bonding wire 37 is performed. For example, in the bonding step of the p-side bonding wire 36, first, the ball formed in the capillary is pressed against the p-side wiring 3 while applying ultrasonic vibration to form the ball bond portion 38 on the p-side wiring 3. Ru. Next, while the wire on which the ball bond portion 38 is formed is held by the capillary, it is extended to the p-side electrode 19, and the capillary is pressed onto the wire while applying ultrasonic vibration to the wire. It is cut to form a wedge bond portion 39. The n-side bonding wire 37 is also formed in the same process.

次に、図１２に示すように、半導体発光素子５、ボンディングワイヤ３６，３７、ｐ側配線３（一部）およびｎ側配線４（一部）を覆うように、基材２上に封止樹脂６が形成される。この際、樹脂の流れや重みによってボンディングワイヤ３６，３７が下方に押されるワイヤ流れが生じる。ボンディングワイヤ３６，３７の凹部４０，４３は、このワイヤ流れによって形成される。以上の工程を経て、半導体発光装置１が得られる。 Next, as shown in FIG. 12, the semiconductor light emitting element 5, the bonding wires 36 and 37, the p-side wiring 3 (part) and the n-side wiring 4 (part) are sealed on the base material 2 so as to cover them. Resin 6 is formed. At this time, a wire flow is generated in which the bonding wires 36 and 37 are pushed downward due to the flow and weight of the resin. The recesses 40, 43 of the bonding wires 36, 37 are formed by this wire flow. Through the above steps, the semiconductor light emitting device 1 is obtained.

この半導体発光装置１によれば、図２に示すように、ｐ側電極１９の周囲に、上面がｐ型半導体層１７からなるリーク防止構造としての第１積層部２７が形成されている。これにより、ｐ側電極１９に接続されたｐ側ボンディングワイヤ３６がワイヤ流れ等によって変形しても、第１積層部２７に接触させることで、段部２３に露出したｎ型半導体層１５とｐ側ボンディングワイヤ３６との接触を防止することができる。その結果、ｐ側ボンディングワイヤ３６と半導体積層構造２０との接触によるリーク電流の発生を防止することができる。 According to the semiconductor light emitting device 1, as shown in FIG. 2, a first laminated portion 27 as a leak prevention structure having a p-type semiconductor layer 17 on the upper surface is formed around the p-side electrode 19. As a result, even if the p-side bonding wire 36 connected to the p-side electrode 19 is deformed due to wire flow or the like, the n-type semiconductor layer 15 and p are exposed on the stepped portion 23 by being brought into contact with the first laminated portion 27. Contact with the side bonding wire 36 can be prevented. As a result, it is possible to prevent the generation of leakage current due to the contact between the p-side bonding wire 36 and the semiconductor laminated structure 20.

このようなｐ側ボンディングワイヤ３６の接触によるリークを防止することは、段部２３の上面を絶縁膜で覆うことでも達成し得る。しかしながら、図９Ａおよび図９Ｂに示したように、ブレーキング工程によって基板１４を劈開して半導体発光素子５を得る場合には、劈開時に当該絶縁膜が剥がれるおそれがある。これに対し、この実施形態の半導体発光素子５では、ｎ型半導体層１５、発光層１６およびｐ型半導体層１７が互いの結晶として結合しているため、当該ブレーキング工程によって剥がれることがない。よって、リーク防止構造を確実に残すことができる。 Preventing such leakage due to contact of the p-side bonding wire 36 can also be achieved by covering the upper surface of the stepped portion 23 with an insulating film. However, as shown in FIGS. 9A and 9B, when the substrate 14 is cleaved to obtain the semiconductor light emitting element 5 by the braking step, the insulating film may be peeled off at the time of cleavage. On the other hand, in the semiconductor light emitting device 5 of this embodiment, since the n-type semiconductor layer 15, the light emitting layer 16 and the p-type semiconductor layer 17 are bonded to each other as crystals, they are not peeled off by the braking step. Therefore, the leak prevention structure can be reliably left.

また、図３に示すように、ｐ側ボンディングワイヤ３６を第１積層部２７に接触させておけば、ｐ側ボンディングワイヤ３６の頂部までの高さＨ_１を小さくできるので、半導体発光装置１をより一層低背化することができる。なお、ｐ側ボンディングワイヤ３６と第１積層部２７との接触は、半導体発光装置１の製造時に発生していなくても、たとえば、半導体発光装置１の実装時のリフロー熱によって発生することがある。封止樹脂６のような樹脂材と、ｐ側ボンディングワイヤ３６のような金属材とでは、互いに線膨張係数が異なるためである。 Further, as shown in FIG. 3, if the p-side bonding wire 36 is brought into contact with the first laminated portion 27, the height H ₁ to the top of the p-side bonding wire 36 can be reduced, so that the semiconductor light emitting device 1 can be used. The height can be further reduced. The contact between the p-side bonding wire 36 and the first laminated portion 27 may be generated, for example, by the reflow heat at the time of mounting the semiconductor light emitting device 1, even if it is not generated at the time of manufacturing the semiconductor light emitting device 1. .. This is because the linear expansion coefficient of the resin material such as the sealing resin 6 and the metal material such as the p-side bonding wire 36 are different from each other.

図１３～図１８は、半導体発光素子５のリーク防止構造（第１積層部２７）の変形例を示す図である。
図１～図３では、第１積層部２７は、基板１４と面一な半導体積層構造２０の端面２０Ａ，２０Ｃの一部を構成するように、平面視Ｌ字状に形成されていた。
これに対し、図１３に示すように、第１積層部２７は、基板１４と面一な半導体積層構造２０の全ての端面２０Ａ，２０Ｂ，２０Ｃ，２０Ｄを構成するように、平面視四角環状に形成されていてもよい。 13 to 18 are views showing a modified example of the leak prevention structure (first laminated portion 27) of the semiconductor light emitting device 5.
In FIGS. 1 to 3, the first laminated portion 27 is formed in an L-shape in a plan view so as to form a part of the end faces 20A and 20C of the semiconductor laminated structure 20 flush with the substrate 14.
On the other hand, as shown in FIG. 13, the first laminated portion 27 has a rectangular annular shape in a plan view so as to constitute all the end faces 20A, 20B, 20C, 20D of the semiconductor laminated structure 20 flush with the substrate 14. It may be formed.

また、図１４～図１６に示すように、第１積層部２７は、半導体積層構造２０の端面２０Ａ，２０Ｃから半導体積層構造２０の内方領域に離れた領域において、ｐ側電極１９の周囲にのみ選択的に形成されていてもよい。この場合、図１４に示すように、平面視Ｌ字状に形成されていてもよいし、図１５に示すように、第１短端面２０Ａと第１長端面２０Ｃとの交点部で、第１直線部３１と第２直線部３２とが分断されていてもよい。また、図１６に示すように、構造部２１を取り囲む平面視環状に形成されていてもよい。 Further, as shown in FIGS. 14 to 16, the first laminated portion 27 is formed around the p-side electrode 19 in a region separated from the end faces 20A and 20C of the semiconductor laminated structure 20 to the inner region of the semiconductor laminated structure 20. Only may be selectively formed. In this case, as shown in FIG. 14, it may be formed in an L shape in a plan view, or as shown in FIG. 15, at the intersection of the first short end surface 20A and the first long end surface 20C, the first The straight line portion 31 and the second straight line portion 32 may be separated. Further, as shown in FIG. 16, it may be formed in a planar view ring surrounding the structural portion 21.

また、第１積層部２７は、前述のように、半導体積層構造２０の端面２０Ａ，２０Ｂ，２０Ｃ，２０Ｄに沿うライン状に形成されている必要はない。
たとえば、図１７および図１８に示すように、第１積層部２７は、半導体積層構造２０の端面２０Ａ，２０Ｂ，２０Ｃ，２０Ｄに沿って配列された複数のドット状に形成されていてもよい。この場合、図１７に示すように、ｐ側電極１９の周囲にのみ平面視Ｌ字状で配列されていてもよいし、図１８に示すように、構造部２１を取り囲む平面視環状に配列されていてもよい。 Further, as described above, the first laminated portion 27 does not need to be formed in a line shape along the end faces 20A, 20B, 20C, 20D of the semiconductor laminated structure 20.
For example, as shown in FIGS. 17 and 18, the first laminated portion 27 may be formed in a plurality of dots arranged along the end faces 20A, 20B, 20C, 20D of the semiconductor laminated structure 20. In this case, as shown in FIG. 17, they may be arranged in a plan view L-shape only around the p-side electrode 19, or as shown in FIG. 18, they are arranged in a plan view ring surrounding the structural portion 21. May be.

以上、本発明の一実施形態を説明したが、本発明は、他の形態で実施することもできる。
たとえば、前述の実施形態では、第１積層部２７のｐ型半導体層１７が露出していたが、当該ｐ型半導体層１７は、絶縁膜３３で覆われていてもよい。
また、たとえば、半導体発光装置１の各半導体部分の導電型を反転した構成が採用されてもよい。たとえば、半導体発光装置１において、ｐ型の部分がｎ型であり、ｎ型の部分がｐ型であってもよい。その場合、ｐ側配線３およびｎ側配線４は、それぞれ、ｎ側配線およびｐ側配線と称されてもよく、ｐ側電極１９およびｎ側電極１８は、それぞれ、ｎ側電極およびｐ側電極と称されてもよい。 Although one embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.
For example, in the above-described embodiment, the p-type semiconductor layer 17 of the first laminated portion 27 is exposed, but the p-type semiconductor layer 17 may be covered with the insulating film 33.
Further, for example, a configuration in which the conductive type of each semiconductor portion of the semiconductor light emitting device 1 is inverted may be adopted. For example, in the semiconductor light emitting device 1, the p-type portion may be n-type and the n-type portion may be p-type. In that case, the p-side wiring 3 and the n-side wiring 4 may be referred to as n-side wiring and p-side wiring, respectively, and the p-side electrode 19 and the n-side electrode 18 are the n-side electrode and the p-side electrode, respectively. May be referred to as.

本発明の半導体発光装置は、たとえば、小型携帯電子機器、医療機器等、低背化した半導体発光装置が要求されるデバイスに好適に使用することができる。
その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。
たとえば、前述の図面に基づいた実施形態より抽出される本発明の一実施形態に係る半導体発光装置は、基板と、前記基板上に順に積層された第１導電型半導体層、発光層および第２導電型半導体層を含み、前記第２導電型半導体層から前記発光層を介して前記第１導電型半導体層に至る壁面を有する構造部と、前記構造部の周囲に配置され、前記第１導電型半導体層が露出する上面を有する第１部分とを含む半導体積層構造と、前記構造部の上面に配置された第２電極と、前記半導体積層構造の第１部分の前記上面に配置された第１電極とを含み、前記半導体積層構造は、前記第２電極の周囲において前記構造部から分離して配置され、前記第１導電型半導体層、前記発光層および前記第２導電型半導体層の積層構造からなる第１積層部を含む。 The semiconductor light emitting device of the present invention can be suitably used for devices that require a low-profile semiconductor light emitting device, such as small portable electronic devices and medical devices.
In addition, various design changes can be made within the scope of the matters described in the claims.
For example, the semiconductor light emitting device according to the embodiment of the present invention extracted from the embodiment based on the above-mentioned drawings includes a substrate, a first conductive semiconductor layer, a light emitting layer, and a second light emitting layer sequentially laminated on the substrate. A structural portion including a conductive semiconductor layer and having a wall surface extending from the second conductive semiconductor layer to the first conductive semiconductor layer via the light emitting layer, and a structural portion arranged around the structural portion, the first conductive. A semiconductor laminated structure including a first portion having an upper surface on which the type semiconductor layer is exposed, a second electrode arranged on the upper surface of the structural portion, and a first portion arranged on the upper surface of the first portion of the semiconductor laminated structure. The semiconductor laminated structure includes one electrode and is arranged separately from the structural portion around the second electrode, and the first conductive semiconductor layer, the light emitting layer, and the second conductive semiconductor layer are laminated. Includes a first laminated portion of the structure.

この構成によれば、第２電極の周囲に、上面が第２導電型半導体層からなる第１積層部が形成されている。これにより、第２電極に接続されたボンディングワイヤがワイヤ流れ等によって変形しても、第１積層部に接触させることで、半導体積層構造の第１部分に露出した第１導電型半導体層とボンディングワイヤとの接触を防止することができる。その結果、ボンディングワイヤと半導体積層構造との接触によるリーク電流の発生を防止することができる。よって、従来に比べて、より信頼性の高い半導体発光装置を提供することができる。 According to this configuration, a first laminated portion whose upper surface is composed of a second conductive semiconductor layer is formed around the second electrode. As a result, even if the bonding wire connected to the second electrode is deformed due to wire flow or the like, the bonding wire is brought into contact with the first laminated portion to bond with the first conductive semiconductor layer exposed in the first portion of the semiconductor laminated structure. It is possible to prevent contact with the wire. As a result, it is possible to prevent the generation of leakage current due to the contact between the bonding wire and the semiconductor laminated structure. Therefore, it is possible to provide a more reliable semiconductor light emitting device as compared with the conventional case.

本発明の一実施形態に係る半導体発光装置では、前記第１積層部は、前記半導体積層構造の端面に沿うライン状に形成されていてもよい。
本発明の一実施形態に係る半導体発光装置では、前記第１積層部は、前記基板の端面と面一な前記半導体積層構造の端面の一部を構成するように形成されていてもよい。
本発明の一実施形態に係る半導体発光装置では、前記第１積層部は、前記半導体積層構造の端面に沿って配列された複数のドット状に形成されていてもよい。 In the semiconductor light emitting device according to the embodiment of the present invention, the first laminated portion may be formed in a line shape along the end face of the semiconductor laminated structure.
In the semiconductor light emitting device according to the embodiment of the present invention, the first laminated portion may be formed so as to form a part of the end face of the semiconductor laminated structure flush with the end face of the substrate.
In the semiconductor light emitting device according to the embodiment of the present invention, the first laminated portion may be formed in a plurality of dots arranged along the end face of the semiconductor laminated structure.

本発明の一実施形態に係る半導体発光装置では、前記第１積層部は、前記半導体積層構造の端面に沿って、前記半導体積層構造の全周にわたって形成されていてもよい。
本発明の一実施形態に係る半導体発光装置では、前記第１積層部は、前記半導体積層構造の端面から前記半導体積層構造の内方領域に離れた領域において、前記第２電極の周囲にのみ選択的に形成されていてもよい。 In the semiconductor light emitting device according to the embodiment of the present invention, the first laminated portion may be formed along the end face of the semiconductor laminated structure over the entire circumference of the semiconductor laminated structure.
In the semiconductor light emitting device according to the embodiment of the present invention, the first laminated portion is selected only around the second electrode in a region separated from the end face of the semiconductor laminated structure to the inner region of the semiconductor laminated structure. May be formed.

本発明の一実施形態に係る半導体発光装置では、前記半導体積層構造は、平面視四角形状に形成され、互いに対角関係となる第１角部と第２角部、および互いに対角関係となる第３角部と第４角部を有し、前記第２電極が、前記第１角部に配置されており、前記第１電極が、前記第２角部に配置されており、前記第１積層部は、前記第１角部において、前記基板の端面と面一な前記半導体積層構造の端面の一部を構成し、前記第２電極を取り囲むように形成されており、前記半導体積層構造は、前記第１積層部と同じ積層構造からなり、前記第２角部、前記第３角部および前記第４角部のそれぞれにおいて、前記第１積層部とは分離されて配置された、第２積層部、第３積層部および第４積層部を含んでいてもよい。 In the semiconductor light emitting device according to the embodiment of the present invention, the semiconductor laminated structure is formed in a rectangular shape in a plan view, and has a diagonal relationship between the first and second corner portions and a diagonal relationship with each other. It has a third corner portion and a fourth corner portion, the second electrode is arranged in the first corner portion, and the first electrode is arranged in the second corner portion, and the first The laminated portion constitutes a part of the end surface of the semiconductor laminated structure flush with the end surface of the substrate at the first corner portion, and is formed so as to surround the second electrode, and the semiconductor laminated structure is formed. , The second laminated portion has the same laminated structure as the first laminated portion, and is arranged separately from the first laminated portion in each of the second corner portion, the third corner portion, and the fourth corner portion. The laminated portion, the third laminated portion, and the fourth laminated portion may be included.

本発明の一実施形態に係る半導体発光装置は、前記構造部の前記壁面を介して、前記構造部の前記上面と前記第１部分の前記上面との間に跨るように形成された絶縁膜をさらに含んでいてもよい。
本発明の一実施形態に係る半導体発光装置では、前記絶縁膜は、前記半導体積層構造の端面から前記半導体積層構造の内方領域に離れた位置に端縁を有していてもよい。 The semiconductor light emitting device according to the embodiment of the present invention has an insulating film formed so as to straddle between the upper surface of the structural portion and the upper surface of the first portion via the wall surface of the structural portion. It may be further included.
In the semiconductor light emitting device according to the embodiment of the present invention, the insulating film may have an edge at a position distant from the end face of the semiconductor laminated structure to the inner region of the semiconductor laminated structure.

本発明の一実施形態に係る半導体発光装置は、前記基板を支持し、第２配線および第１配線を有する基材と、前記第１積層部を超えるように配置され、前記第２配線にボールボンド部を有し、前記第２電極にウェッジボンド部を有するボンディングワイヤと、前記基材、前記基板、前記半導体積層構造および前記ボンディングワイヤを封止する封止樹脂とを含んでいてもよい。 The semiconductor light emitting device according to the embodiment of the present invention is arranged so as to support the substrate and have a base material having a second wiring and a first wiring so as to exceed the first laminated portion, and a ball is connected to the second wiring. It may contain a bonding wire having a bond portion and having a wedge bond portion on the second electrode, and a sealing resin for sealing the base material, the substrate, the semiconductor laminated structure, and the bonding wire.

この構成によれば、ボンディングワイヤが、第２配線に比べて相対的に高い位置にある第２電極にウェッジボンド部を有しているため、ボンディングワイヤにループが形成されていない。そのため、パッケージの低背化を達成することができる。
本発明の一実施形態に係る半導体発光装置では、前記封止樹脂の高さが、１５０μｍ～２００μｍであってもよい。 According to this configuration, since the bonding wire has a wedge bond portion on the second electrode located at a position relatively higher than the second wiring, no loop is formed on the bonding wire. Therefore, it is possible to achieve a low profile of the package.
In the semiconductor light emitting device according to the embodiment of the present invention, the height of the sealing resin may be 150 μm to 200 μm.

本発明の一実施形態に係る半導体発光装置では、前記基板が、８０μｍ～１００μｍの厚さを有し、前記半導体積層構造が、前記第１導電型半導体層、前記発光層および前記第２導電型半導体層のトータルで５μｍ～１０μｍの厚さを有していてもよい。
本発明の一実施形態に係る半導体発光装置では、前記構造部の前記壁面は、前記第１部分の前記上面に対して４５°～９０°の角度で傾斜していてもよい。 In the semiconductor light emitting device according to the embodiment of the present invention, the substrate has a thickness of 80 μm to 100 μm, and the semiconductor laminated structure is the first conductive type semiconductor layer, the light emitting layer, and the second conductive type. The semiconductor layer may have a total thickness of 5 μm to 10 μm.
In the semiconductor light emitting device according to the embodiment of the present invention, the wall surface of the structural portion may be inclined at an angle of 45 ° to 90 ° with respect to the upper surface of the first portion.

本発明の一実施形態に係る半導体発光装置では、前記基板は、サファイア基板を含んでいてもよい。 In the semiconductor light emitting device according to the embodiment of the present invention, the substrate may include a sapphire substrate.

１半導体発光装置
２基材
３ｐ側配線
４ｎ側配線
５半導体発光素子
６封止樹脂
１４基板
１５ｎ型半導体層
１６発光層
１７ｐ型半導体層
１８ｎ側電極
１９ｐ側電極
２０半導体積層構造
２０Ａ第１短端面
２０Ｂ第２短端面
２０Ｃ第１長端面
２０Ｄ第２長端面
２０Ｅ第１角部
２０Ｆ第２角部
２０Ｇ第３角部
２０Ｈ第４角部
２１構造部
２１Ａ上面
２２壁面
２３段部
２３Ａ上面
２７第１積層部
２８第２積層部
２９第３積層部
３０第４積層部
３１第１直線部
３２第２直線部
３３絶縁膜
３４端縁
３６ｐ側ボンディングワイヤ
３８ボールボンド部
３９ウェッジボンド部 1 Semiconductor light emitting device 2 Base material 3 p-side wiring 4 n-side wiring 5 Semiconductor light-emitting element 6 Encapsulating resin 14 Substrate 15 n-type semiconductor layer 16 Light-emitting layer 17 p-type semiconductor layer 18 n-side electrode 19 p-side electrode 20 Semiconductor laminated structure 20A 1st short end surface 20B 2nd short end surface 20C 1st long end surface 20D 2nd long end surface 20E 1st corner part 20F 2nd corner part 20G 3rd corner part 20H 4th corner part 21 Structural part 21A Top surface 22 Wall surface 23 Steps 23A Top surface 27 1st laminated part 28 2nd laminated part 29 3rd laminated part 30 4th laminated part 31 1st straight part 32 2nd straight part 33 Insulation film 34 Edge edge 36 p-side bonding wire 38 Ball bond part 39 Wedge bond Department

Claims

With the board
It includes a first conductive semiconductor layer, a light emitting layer, and a second conductive semiconductor layer laminated in this order on the substrate, and reaches the first conductive semiconductor layer from the second conductive semiconductor layer via the light emitting layer. A semiconductor laminated structure including a structural portion having a wall surface and a first portion arranged around the structural portion and having an upper surface on which the first conductive semiconductor layer is exposed.
The second electrode arranged on the upper surface of the structural part and
A first electrode arranged on the upper surface of the first portion of the semiconductor laminated structure is included.
The semiconductor laminated structure is arranged separately from the structural portion around the second electrode, and is composed of a laminated structure of the first conductive semiconductor layer, the light emitting layer, and the second conductive semiconductor layer. Including the part
The first laminated portion is formed in a line shape along the end face of the semiconductor laminated structure, and is formed so as to form a part of the end face of the semiconductor laminated structure flush with the end face of the substrate. , Semiconductor light emitting device.

The semiconductor light emitting device according to claim 1 , wherein the first laminated portion is formed along the end face of the semiconductor laminated structure over the entire circumference of the semiconductor laminated structure.

The semiconductor laminated structure is formed in a rectangular shape in a plan view, and has a first corner portion and a second corner portion that are diagonally related to each other, and a third corner portion and a fourth corner portion that are diagonally related to each other.
The second electrode is arranged at the first corner portion, and the second electrode is arranged.
The first electrode is arranged at the second corner portion, and the first electrode is arranged.
The first laminated portion constitutes a part of the end surface of the semiconductor laminated structure flush with the end surface of the substrate in the first corner portion, and is formed so as to surround the second electrode.
The semiconductor laminated structure has the same laminated structure as the first laminated portion, and is arranged separately from the first laminated portion in each of the second corner portion, the third corner portion, and the fourth corner portion. The semiconductor light emitting device according to claim 1 , further comprising a second laminated portion, a third laminated portion, and a fourth laminated portion.

With the board
It includes a first conductive semiconductor layer, a light emitting layer, and a second conductive semiconductor layer laminated in this order on the substrate, and reaches the first conductive semiconductor layer from the second conductive semiconductor layer via the light emitting layer. A semiconductor laminated structure including a structural portion having a wall surface and a first portion arranged around the structural portion and having an upper surface on which the first conductive semiconductor layer is exposed.
The second electrode arranged on the upper surface of the structural part and
A first electrode arranged on the upper surface of the first portion of the semiconductor laminated structure is included.
The semiconductor laminated structure is arranged separately from the structural portion around the second electrode, and is composed of a laminated structure of the first conductive semiconductor layer, the light emitting layer, and the second conductive semiconductor layer. Including the part
The first laminated portion is a semiconductor light emitting device selectively formed only around the second electrode in a region separated from the end face of the semiconductor laminated structure to the inner region of the semiconductor laminated structure.

With the board
It includes a first conductive semiconductor layer, a light emitting layer, and a second conductive semiconductor layer laminated in this order on the substrate, and reaches the first conductive semiconductor layer from the second conductive semiconductor layer via the light emitting layer. A semiconductor laminated structure including a structural portion having a wall surface and a first portion arranged around the structural portion and having an upper surface on which the first conductive semiconductor layer is exposed.
The second electrode arranged on the upper surface of the structural part and
A first electrode arranged on the upper surface of the first portion of the semiconductor laminated structure is included.
The semiconductor laminated structure is arranged separately from the structural portion around the second electrode, and is composed of a laminated structure of the first conductive semiconductor layer, the light emitting layer, and the second conductive semiconductor layer. Including the part
The semiconductor laminated structure is formed in a rectangular shape in a plan view, and has a first corner portion and a second corner portion that are diagonally related to each other, and a third corner portion and a fourth corner portion that are diagonally related to each other.
The second electrode is arranged at the first corner portion, and the second electrode is arranged.
The first electrode is arranged at the second corner portion, and the first electrode is arranged.
The first laminated portion constitutes a part of the end surface of the semiconductor laminated structure flush with the end surface of the substrate in the first corner portion, and is formed so as to surround the second electrode.
The semiconductor laminated structure has the same laminated structure as the first laminated portion, and is arranged separately from the first laminated portion in each of the second corner portion, the third corner portion, and the fourth corner portion. A semiconductor light emitting device including a second laminated portion, a third laminated portion, and a fourth laminated portion.

The semiconductor light emitting device according to claim 4 or 5, wherein the first laminated portion is formed in a line shape along an end face of the semiconductor laminated structure.

The semiconductor light emitting device according to claim 4, wherein the first laminated portion is formed in a plurality of dots arranged along the end face of the semiconductor laminated structure.

Claims 1 to 7 further include an insulating film formed so as to straddle between the upper surface of the structural portion and the upper surface of the first portion of the semiconductor laminated structure via the wall surface of the structural portion. The semiconductor light emitting device according to any one of the above.

With the board
It includes a first conductive semiconductor layer, a light emitting layer, and a second conductive semiconductor layer laminated in this order on the substrate, and reaches the first conductive semiconductor layer from the second conductive semiconductor layer via the light emitting layer. A semiconductor laminated structure including a structural portion having a wall surface and a first portion arranged around the structural portion and having an upper surface on which the first conductive semiconductor layer is exposed.
The second electrode arranged on the upper surface of the structural part and
A first electrode arranged on the upper surface of the first portion of the semiconductor laminated structure is included.
The semiconductor laminated structure is arranged separately from the structural portion around the second electrode, and is composed of a laminated structure of the first conductive semiconductor layer, the light emitting layer, and the second conductive semiconductor layer. Including the part
A semiconductor light emitting device further comprising an insulating film formed so as to straddle between the upper surface of the structural portion and the upper surface of the first portion of the semiconductor laminated structure via the wall surface of the structural portion.

The semiconductor light emitting device according to claim 9, wherein the first laminated portion is formed in a line shape along an end face of the semiconductor laminated structure.

The semiconductor light emitting device according to claim 9, wherein the first laminated portion is formed in a plurality of dots arranged along the end face of the semiconductor laminated structure.

The semiconductor light emitting device according to any one of claims 9 to 11, wherein the first laminated portion is formed along the end face of the semiconductor laminated structure over the entire circumference of the semiconductor laminated structure.

The semiconductor light emitting device according to any one of claims 8 to 12 , wherein the insulating film has an edge edge at a position distant from the end face of the semiconductor laminated structure to the inner region of the semiconductor laminated structure.

A substrate that supports the substrate and has a second wiring and a first wiring,
A bonding wire arranged so as to exceed the first laminated portion, having a ball bond portion in the second wiring, and having a wedge bond portion in the second electrode.
The semiconductor light emitting device according to any one of claims 1 to 13 , comprising the substrate, the substrate, the semiconductor laminated structure, and a sealing resin for sealing the bonding wire.

The semiconductor light emitting device according to claim 14 , wherein the height of the sealing resin is 150 μm to 200 μm.

The substrate has a thickness of 80 μm to 100 μm.
The semiconductor light emission according to claim 14 or 15 , wherein the semiconductor laminated structure has a total thickness of 5 μm to 10 μm of the first conductive type semiconductor layer, the light emitting layer, and the second conductive type semiconductor layer. Device.

The semiconductor light emission according to any one of claims 14 to 16 , wherein the wall surface of the structural portion is inclined at an angle of 45 ° to 90 ° with respect to the upper surface of the first portion of the semiconductor laminated structure. Device.

The semiconductor light emitting device according to any one of claims 1 to 17 , wherein the substrate includes a sapphire substrate.