CN116979000A

CN116979000A - Light-emitting diode chip and light-emitting device

Info

Publication number: CN116979000A
Application number: CN202311000412.0A
Authority: CN
Inventors: 蔡琳榕; 廖生地; 连文黎; 杨力勋
Original assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Current assignee: Quanzhou Sanan Semiconductor Technology Co Ltd
Priority date: 2021-11-23
Filing date: 2021-11-23
Publication date: 2023-10-31
Also published as: CN114267762A; CN114267762B

Abstract

The application provides a light-emitting diode chip with high reliability, which comprises a semiconductor epitaxial lamination layer, a first conductive type semiconductor layer, a light-emitting layer and a second conductive type semiconductor layer from top to bottom; a concave region located at the edge of the semiconductor epitaxial lamination and at least penetrating through the first conductive type semiconductor layer and the light-emitting layer; the electrode is arranged on the concave surface; taking the normal direction of the horizontal plane of the semiconductor epitaxial lamination as the overlooking direction, and a first interval is arranged between the electrode and the side wall of the concave region and is more than or equal to 30 mu m from the overlooking direction; the two non-active light-emitting areas are positioned at the edge of the semiconductor epitaxial lamination and penetrate through the first conductive type semiconductor layer and the light-emitting layer to expose the non-active light-emitting surface; the wavelength conversion layer covers the upper area and the side wall area of the semiconductor epitaxial lamination; the two non-active light emitting areas are respectively axisymmetric with the concave area.

Description

Light-emitting diode chip and light-emitting device

The application is a divisional application of an application patent application of 2021, 11, 23, 202111395335.4 and entitled "a light emitting diode chip and a light emitting device".

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a light emitting diode chip and a light emitting device.

Background

A light emitting diode (LED for short, english Light Emitt ing Diode) includes different light emitting materials and light emitting components, and is a solid semiconductor light emitting element. The LED display device has the advantages of low cost, low power consumption, high light efficiency, small volume, energy conservation, environmental protection, good photoelectric property and the like, and is widely applied to various scenes such as illumination, visible light communication, luminous display and the like.

Disclosure of Invention

The invention provides a light emitting diode chip with high reliability.

The technical scheme adopted by the invention is as follows:

specifically, an embodiment of the present invention provides a light emitting diode chip, including:

a semiconductor epitaxial stack having opposite first and second surfaces, the semiconductor epitaxial stack comprising a first conductivity type semiconductor layer, a light emitting layer, and a second conductivity type semiconductor layer in that order along a direction from the first surface to the second surface;

a recessed region located at an edge of the semiconductor epitaxial stack and penetrating at least the first conductivity type semiconductor layer and the light emitting layer to expose a recessed surface;

At least one electrode disposed on the recessed surface;

taking the normal direction of the horizontal plane of the semiconductor epitaxial lamination as the overlooking direction, and a first interval is arranged between the electrode and the side wall of the concave region in the overlooking direction, wherein the first interval is more than or equal to 30 mu m;

the non-active light-emitting region is positioned at the edge of the semiconductor epitaxial lamination and penetrates through the first conductive type semiconductor layer and the light-emitting layer to expose a non-active light-emitting surface;

a wavelength conversion layer covering at least the upper region and the sidewall region of the semiconductor epitaxial stack;

the light emitting diode chip comprises a concave region and two non-active light emitting regions, wherein the two non-active light emitting regions comprise a second non-active light emitting region and a third non-active light emitting region, and the second non-active light emitting region and the third non-active light emitting region are respectively axisymmetric with the concave region.

Another embodiment of the present invention provides a light emitting diode chip, including:

at least one electrode disposed on the recessed surface;

the light emitting diode chip comprises two concave areas and two non-active light emitting areas, wherein the two concave areas are respectively arranged at four corners of the semiconductor epitaxial lamination, and the two concave areas are respectively positioned on the same side of the semiconductor epitaxial lamination.

An embodiment of the present invention provides a light emitting device having the light emitting diode chip described above.

Based on the above, compared with the prior art, the light-emitting diode chip provided by the invention can effectively solve the light leakage phenomenon caused by the offset of the wavelength conversion layer.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

For a clearer description of embodiments of the invention or of the solutions of the prior art, the drawings that are needed in the description of the embodiments or of the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention, and that other drawings can be obtained from them without inventive effort for a person skilled in the art; the positional relationships described in the drawings in the following description are based on the orientation of the elements shown in the drawings unless otherwise specified.

Fig. 1 is a top view of a light emitting diode chip according to an embodiment of the present invention;

FIG. 1A is a top view and a side cross-sectional view at X-X' of a light emitting diode chip of the embodiment shown in FIG. 1;

FIG. 1B is a top view and a side cross-sectional view at Y-Y' of a light emitting diode chip of the embodiment shown in FIG. 1;

FIG. 1C is a side cross-sectional view of the LED chip with a wavelength conversion layer on the top surface of the embodiment of FIG. 1;

fig. 1D is a top view of a light emitting diode chip according to another embodiment of the present invention;

fig. 2 is a top view of a light emitting diode chip according to another embodiment of the present invention;

FIG. 2A is an enlarged schematic view of the structure within the dashed box of the embodiment shown in FIG. 2;

FIG. 3 is a top view of a light emitting diode chip according to an embodiment of the present invention;

FIG. 3A is a top view of a LED array formed by LED chips according to the embodiment of FIG. 3

FIG. 3B is an enlarged schematic view of the structure in the dashed box in FIG. 3A;

fig. 4 is a top view of a light emitting diode chip according to another embodiment of the present invention;

FIG. 4A is a top view of an LED array formed by the LED chips of the embodiment of FIG. 4;

FIG. 4B is an enlarged schematic view of the structure within the dashed box of the embodiment shown in FIG. 4A;

FIG. 4C is a side cross-sectional view of a first row of LED chips of the LED array of FIG. 4A;

fig. 5 is a top view of a light emitting diode chip according to another embodiment of the present invention;

FIG. 5A is a top view of an LED array formed by the LED chips of the embodiment of FIG. 5;

Fig. 6 is a top view of a light emitting diode chip according to another embodiment of the present invention;

FIG. 6A is a top view of an LED array formed by the LED chips of the embodiment of FIG. 6;

fig. 7 is a top view of a light emitting diode chip according to another embodiment of the present invention;

FIG. 7A is a top view of an LED array formed by the LED chips of the embodiment of FIG. 7;

fig. 8 is a cross-sectional view of a light emitting diode chip according to another embodiment of the present invention;

fig. 9 is a cross-sectional view of the led chip with a wavelength conversion layer on the upper surface of the embodiment shown in fig. 8.

Reference numerals:

a substrate: 10

The upper surface: 11

The lower surface: 12

Semiconductor epitaxial stack: 20. 320, 420, 520, 620, 720, 820

A first surface: 20a, 820a

The second surface: 20b

A first conductivity type semiconductor layer: 21. 821

Light emitting layer: 22. 822, 822

Second conductivity type semiconductor layer: 23. 823 (823)

Recess: 24

An electrode: 30. 330, 430A, 430B, 530A, 530B, 530C, 630, 730A, 730B, 830

A first electrode: 31. 831 (831)

A second electrode: 32

Wavelength conversion layer: 40. 840, and

a first electrical connection layer: 51

A second electrical connection layer: 52

Recessed area: A. a1, A2, A3, A4,

Recessed surface: a ', A1', A2', A3', A4'

Inactive light emitting region: B. 3B1, 3B2, 3B3, 4B1, 4B2, 5B, 6B, 7B1, 7B2

Inactive light emitting surface: b'.

Distance/distance: d1, D2, D3, D4, D5, D6, D1', D2', D3', D21, D22

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention; the technical features designed in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other; all other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the present invention, it should be noted that all terms used in the present invention (including technical terms and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs and are not to be construed as limiting the present invention; it will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The different embodiments disclosed below may reuse the same reference symbols and/or labels. These repetition are for the purpose of simplicity and clarity and do not in itself dictate a particular relationship between the various embodiments and/or configurations discussed;

in the following description, for convenience, an orthogonal coordinate system xyz is defined, and the positive side in the z direction is set to the upper side, that is, the normal direction of the horizontal plane in which the semiconductor epitaxial layer is located, and the semiconductor epitaxial layer is located in a region having a positive value in the coordinate system formed by the x axis, the y axis, and the z axis. Unless otherwise indicated, in general, the term "about" is intended to include the range of ±10%, experimental or instrumental errors associated with obtaining the stated values, and preferably includes the greater of these values;

hereinafter, the led chip and the light emitting device described are used in a general meaning in a semiconductor process, and means a die (d ie) separated from a wafer by a singulation process. And, the wavelength converting region may be provided to the light emitting diode chip before or after singulation. The "light emitting device" refers to a device in which a light emitting diode chip is mounted on a secondary substrate or base. Any device may be named as long as the light emitting diode chip is mounted on the substrate, and for example, the device may be named as a light emitting device including a specific application.

Fig. 1 is a schematic top view of a light emitting diode chip according to an embodiment of the invention.

Referring to FIG. 1, to achieve at least one of the advantages and other advantages, one embodiment of the present invention provides a light emitting diode chip capable ofIs a conventionally sized light emitting diode chip. The light emitting diode chip may have a thickness of about 90000 μm ² Above and about 2000000 μm ² The following horizontal sectional areas.

The light emitting diode chip may also be a small-sized or micro-sized light emitting diode chip. The light emitting diode chip may have a thickness of about 90000 μm ² The following horizontal sectional areas. For example, the light emitting diode chip may have a length and/or a width of 100 μm or more and 300 μm or less, and further may have a thickness of 40 μm or more and 100 μm or less.

The light emitting diode chip may also be a miniature light emitting diode chip of smaller size. The light emitting diode chip may have a thickness of about 10000 μm ² The following light emitting diode chips of horizontal cross-sectional area. For example, the light emitting diode chip may have a length and/or width of 2 μm or more and 100 μm or less, and further may have a thickness of 2 μm or more and 100 μm or less. The light emitting diode chip of the present embodiment may have the horizontal sectional area and thickness as described above, and thus the light emitting diode chip may be easily applied to various electronic devices requiring a small and/or micro light emitting device.

Fig. 1A and 1B are schematic side cross-sectional views of the led chip of fig. 1 at different positions. It should be noted that, the led chip of fig. 1A is shown along the line X-X 'of fig. 1, the led chip of fig. 1B is shown along the line Y-Y' of fig. 1, and the led chip of fig. 1C is a schematic side view cross-section covered with the wavelength conversion layer.

Referring to fig. 1, fig. 1A and fig. 1B together, the led chip of the present embodiment includes a substrate 10, a semiconductor epitaxial stacked layer 20, a first electrode 31, a second electrode 32, a recessed region a (one is schematically shown in fig. 1), an inactive light emitting region B (a plurality is schematically shown in fig. 1), and a wavelength conversion layer 40. A substrate 10 having an upper surface 11 and a lower surface 12 on opposite sides; the substrate 10 may be, for example, a plastic substrate, a glass substrate, or a sapphire substrate, which may have a fixed and flat surface, but is not limited thereto. A semiconductor epitaxial stack 20 is located on the upper surface 11 of the substrate 10.

Referring to fig. 1A and 1B again, a semiconductor epitaxial stack 20 is disposed on the upper surface 11 of the substrate 10. The semiconductor epitaxial stack 20 has a first surface 20a and a second surface 20b opposite the first surface 20 a. The semiconductor epitaxial stacked layer 20 includes, in order from top to bottom, a first conductive type semiconductor layer 21, a light emitting layer 22 capable of generating a first light of a first wavelength, and a second conductive type semiconductor layer 23, wherein a portion of the first surface 20a is provided by an upper surface of the first conductive type semiconductor layer 21, and the second surface 20b is provided by a lower surface of the second conductive type semiconductor layer 23, but the embodiment of the disclosure is not limited thereto.

The first conductive type semiconductor layer 21, the light emitting layer 22 and the second conductive type semiconductor layer 23 may be formed on a growth substrate through an epitaxial growth process. For example, the epitaxial growth process may include metal organic chemical vapor deposition (metal organic chemical vapor deposition, MOCVD), hydride vapor phase epitaxy (hydride vapor phase epitaxy, HVPE), molecular beam epitaxy (molecular beam epitaxy, MBE), other suitable methods, or combinations thereof, but the embodiments of the present disclosure are not limited thereto. In other embodiments, the semiconductor epitaxial layer 20 may also be peeled off from the growth substrate and connected to the substrate 10 by an adhesive layer (not shown), which is preferably a light-transmitting or semi-transmitting material, such as silicon dioxide, aluminum oxide, etc.

In some embodiments of the present invention, the doping of the first conductive type semiconductor layer 21 is N-type. For example, the first conductive type semiconductor layer 21 may be formed of a ii-vi material (e.g., zinc selenide (ZnSe)) or a iii-v nitride material (e.g., gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN)), and the material of the first conductive type semiconductor layer 21 may include a dopant such as silicon (Si) or germanium (Ge), but the embodiment of the disclosure is not limited thereto. In the embodiment of the present disclosure, the first conductive type semiconductor layer 21 may be a single-layer or multi-layer structure.

In some embodiments of the present invention, light with different wavelengths may be generated according to the material of the light emitting layer 22, for example, when the material of the epitaxial structure 20 is InGaN series, the light emitting layer 22 may emit blue light with a wavelength between 400nm and 490nm, deep blue light, or green light with a wavelength between 490nm and 550 nm. When the material of the epitaxial structure 20 is AlGaN series, the light emitting layer 22 can emit violet light with a wavelength between 250nm and 400 nm; in some embodiments of the present invention, the light emitting layer 22 may comprise at least one undoped semiconductor layer or at least one low doped layer. For example, the light emitting layer 22 may be a Quantum Well (QW) layer, which increases the electron hole collision probability, thereby increasing the electron hole combination rate and the light emitting efficiency, and may include indium gallium nitride (indium gallium nitride, inxGa 1-xN) or gallium nitride (GaN), but the embodiment of the disclosure is not limited thereto. In some embodiments of the present invention, the light emitting layer 22 may be a single heterostructure (single heterostructure, SH), a double heterostructure (double heterostructure, DH), a double-sided double heterostructure (DDH), or a multi-quantum well (MQW), but the embodiments of the present disclosure are not limited thereto.

In some embodiments of the present invention, the second conductivity type semiconductor layer 23 is doped P-type. For example, the second conductive type semiconductor layer 23 is a iii-v nitride material (such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN)), and the material of the second conductive type semiconductor layer 23 may include dopants such as magnesium (Mg), carbon (C), etc., but the embodiment of the disclosure is not limited thereto. In the embodiment of the present disclosure, the second conductive type semiconductor layer 23 may be a single-layer or multi-layer structure.

It should be noted that the led chip of the present invention is not limited to include only one semiconductor light emitting stack 20, and may include a plurality of semiconductor light emitting stacks 20 on the substrate 10, wherein a wire structure may be disposed between the plurality of semiconductor light emitting stacks 20 to electrically connect the plurality of semiconductor light emitting stacks 20 to each other on the substrate 10 in series, parallel, serial-parallel, etc.

With continued reference to fig. 1, 1A and 1B, a recessed region a is located at an edge of the semiconductor epitaxial stack 20, and at least penetrates the first conductivity-type semiconductor layer 21 and the light-emitting layer 22 to expose a recessed surface a'. It should be understood that the recessed area a may be also understood as being formed by recessing from the side surface of the semiconductor epitaxial stacked layer 20, and removing at least the first conductivity type semiconductor layer 21 and the light emitting layer 22, so that the recessed area a is formed by at least two side surfaces and a bottom surface, wherein the two side surfaces may be understood as the side walls of the recessed area a, and the bottom surface is the recessed surface a', and of course, the light emitting diode chip provided by the embodiment shown in fig. X may have a recessed area a formed by three side surfaces and a bottom surface; in some embodiments, a plurality of recessed areas a may also be included. Thus, in the embodiment shown in fig. 1, 1A and 1B, the semiconductor epitaxial stack 20 includes: a recess region a in which a portion of the first conductive type semiconductor layer 21, the light emitting layer 22 and the second conductive type semiconductor layer 23 is removed, but the embodiment of the disclosure is not limited thereto. In some other embodiments, the second conductivity type semiconductor layer 23 in the recess region a is completely reserved. While in other embodiments, the first conductivity-type semiconductor layer 21, the light emitting layer 22 and the second conductivity-type semiconductor layer 23 in the recessed region a are all completely removed. In some embodiments of the present invention, the sidewalls of the recessed area a may be tapered in an upward direction, and thus, the recessed area a may have inclined sidewall surfaces. The top view shape of the recessed area a includes square or square-like (e.g., as shown in fig. 1), rectangular or rectangular-like (e.g., as shown in fig. 1D), circular, fan-shaped, horseshoe-shaped, oval, etc.

With continued reference to fig. 1, fig. 1A and fig. 1B, the inactive light emitting region B is located at an edge of the semiconductor epitaxial stack 20, and the inactive light emitting region B and the recessed region a are disposed at an edge of the semiconductor epitaxial stack 20 in an axisymmetric and/or centrosymmetric manner, where the center may refer to a geometric center of the semiconductor epitaxial stack when viewed in a top view, a direction of a normal line of a horizontal plane of the semiconductor epitaxial stack 20 facing the semiconductor epitaxial stack 20 is a top view direction, and an axis may be a straight line passing through the center is a symmetry axis, so as to perform symmetrical disposition, for example, be disposed at a corner position (for example, B2 in fig. 1) of the recessed region a on the semiconductor epitaxial stack 20 on a same side of the semiconductor epitaxial stack 20, or be disposed at a corner position (for example, B1 or B3 in fig. 1) of the semiconductor epitaxial stack 20 symmetrically with the recessed region a, respectively, or a combination of a plurality of the above positions, but the embodiments are not limited thereto. In some embodiments, the distance from the sidewall of the inactive light emitting region to the edge of the light emitting diode chip is above 15 μm, so as to ensure that no light leakage occurs after the wavelength conversion layer 40 is covered. Optionally, a distance from a sidewall of the inactive light emitting region to an edge of the light emitting diode chip is 20 μm or more. In some embodiments, the area of the inactive light emitting region is less than or equal to 25% of the area of the concave region in a top view, so as to ensure the light emitting area of the light emitting diode chip as much as possible under the condition of no light leakage, thereby improving the overall light emitting efficiency. In some other embodiments, the area of the inactive light emitting region is less than or equal to 20% of the area of the recessed region.

The inactive light emitting region B penetrates at least the first conductive type semiconductor layer 21 and the light emitting layer 22 to expose an inactive light emitting surface B'. It should be understood that the inactive light emitting region B may be formed by recessing the side wall of the semiconductor epitaxial stacked layer 20, and removing at least the first conductive type semiconductor layer 21 and the light emitting layer 22, so that the inactive light emitting region B is formed by at least two side surfaces and a bottom surface, wherein the two side surfaces may be understood as the side wall of the inactive light emitting region B, and the bottom surface may be the inactive light emitting surface B', and of course, the light emitting diode chip provided by the embodiment shown in fig. 6 may have an inactive light emitting region B formed by three side surfaces and a bottom surface. In the embodiment shown in fig. 1, 1A and 1B, the semiconductor epitaxial stacked layer 20 includes: the three inactive light emitting regions B1, B2, B3, and a portion of the first conductive type semiconductor layer 21, the light emitting layer 22, and the second conductive type semiconductor layer 23 in the three inactive light emitting regions B1, B2, B3 are removed, but the embodiment of the present disclosure is not limited thereto. In some other embodiments, the second conductive type semiconductor layer 23 in the inactive light emitting region B is completely preserved. While in other embodiments, the first conductivity type semiconductor layer 21, the light emitting layer 22 and the second conductivity type semiconductor layer 23 in the three inactive light emitting regions B are all completely removed, of course. Therefore, in the embodiments shown in fig. 1, 1A and 1B, each of the inactive light emitting regions B1, B2 and B3 may have the same epitaxial layer stack removal embodiment, or may be any combination of the three epitaxial layer stack removal embodiments, which is not limited to the embodiments of the disclosure.

In some embodiments, the total area of the inactive light emitting area is less than or equal to 10% of the total area of the active light emitting area in a top view, so that the light emitting area of the light emitting diode chip is increased as much as possible under the condition of ensuring no light leakage, thereby improving the overall light emitting efficiency.

It should be noted that "non-active light emitting region" and "active light emitting region" are understood as the common meaning used in the light emitting semiconductor field; for example, an "inactive light emitting region" may be understood as having no light emitting structures or materials within the region such that it is unable to directly generate light during subsequent applications; an "active light emitting region" is understood to mean a region within which a light-emitting structure or material, etc., is present, which is capable of generating light during subsequent applications.

With continued reference to fig. 1, 1A and 1B, a second electrode 32 is disposed on the recessed surface a' and is electrically connected directly or indirectly to the second conductivity-type semiconductor layer 23, and a first electrode 31 is disposed on the first conductivity-type semiconductor layer 21 and is electrically connected directly or indirectly to the first conductivity-type semiconductor layer 21; in some embodiments of the present invention, the top-view shape of the first electrode 31 and the second electrode 32 includes square or quasi-square (e.g. as shown in fig. 1), rectangular or quasi-rectangular (e.g. as shown in fig. 1D), circular, fan-shaped, horseshoe-shaped or elliptical, etc. in a top view of the led chip. It should be noted that, in order to conduct current and enhance current diffusion, to increase the light emitting efficiency of the led chip, the first electrode 31 and the second electrode 32 may also include an extension portion (not shown), and the shape of the extension portion may include a bar shape, a rectangular shape, a polygonal shape, or the like. In the embodiment shown in fig. 1, the second electrode 32 is omitted to effectively ensure that the light emitting area is larger, but the embodiment of the disclosure is not limited thereto.

The first electrode 31 and the second electrode 32 may be formed simultaneously using the same material in the same process, or may be formed in a distributed manner. For example, the first electrode 31 and the second electrode 32 may be metal electrodes, and nickel, gold, chromium, titanium, platinum, palladium, rhodium, iridium, aluminum, tin, indium, tantalum, copper, cobalt, iron, ruthenium, zirconium, tungsten, molybdenum, and combinations of one or more materials thereof may have the same layer structure as each other, but the embodiment of the present disclosure is not limited thereto.

Referring to fig. 1, fig. 1A and fig. 1C, a wavelength conversion layer 40 is formed and covers the first surface 20a of the semiconductor epitaxial stacked layer 20, and in the illustrated embodiment, the first surface 20 covers the upper surface, a part of the concave surface a ', a part of the inactive light emitting surface B', and a part of the sidewall of the semiconductor epitaxial stacked layer 20 of the first conductivity type semiconductor layer 21; the wavelength conversion layer 40 may absorb the first light emitted from the semiconductor epitaxial stack 20 and emit at least a second light having a second wavelength different from the first wavelength. The wavelength conversion layer 40 may be any combination of one or more of phosphor, phosphor glue. The wavelength conversion layer 40 is mainly phosphor powder or phosphor gel, and the thickness of the wavelength conversion layer 40 is in the range of 30 μm to 100 μm, but the embodiment of the disclosure is not limited thereto.

With continued reference to fig. 1, fig. 1A and fig. 1C, a first space D1 is provided between the second electrode 32 and the sidewall of the recessed region a, where the first space D1 is greater than or equal to 30 μm, so that enough space is reserved on the recessed surface a' when the wavelength conversion layer 40 is covered, and the wavelength conversion layer 40 fully covers the sidewall of the recessed region a, that is, the portion of the sidewall of the semiconductor epitaxial stack 20. Further, the first distance D1 is 50 μm or more. Further, the structural design of the first spacing D1 and the inactive light emitting region B with the first spacing D1 can avoid the light emitting diode chip from generating an offset of the wavelength conversion layer 40 in the lamination process, and the offset easily causes the defect of the wavelength conversion layer 40 in a part of the region on the first surface 20a of the semiconductor epitaxial lamination 20 after the film is cut, so that part of the semiconductor epitaxial lamination 20 leaks out, and the light emitted in the region of the leaking part is the first light with the first wavelength, but not the second light, thereby affecting the light emitting consistency of the light emitting diode; in this way, the non-active light emitting region B and the concave region a are disposed at the edge of the semiconductor epitaxial stacked layer 20 in an axisymmetric and/or centrosymmetric manner, so that the light leakage is avoided, and the light emitting diode chip has a larger light emitting area.

Referring to fig. 1C again, after the wavelength conversion layer 40 covers the sidewall of the recess region a, a portion of the wavelength conversion layer may extend to cover the recess surface a', but may also cover only the sidewall of the recess region a, in which case a distance D6 is provided between the wavelength conversion layer 40 and the second electrode 32, and the distance D6 may be greater than or equal to 0 μm and less than or equal to 100 μm, but the embodiment of the disclosure is not limited thereto.

Referring to fig. 2 and 2A, in some embodiments, in order to further improve the uniformity of light emission of the light emitting diode, the second distance D2 between the sidewall of the inactive light emitting region B and the electrode on the adjacent light emitting diode chip may be greater than or equal to the first distance D1, specifically, in this embodiment, the second distance D2 is formed by two parts, that is, the sum of the distance D21 from the electrode 230 to the scribe line 60 and the distance D22 from the scribe line 60 to the sidewall of the inactive light emitting region B of the adjacent light emitting diode chip. In some embodiments, the distance D21 from the electrode 230 to the scribe line 60 is about equal to the distance D22 from the scribe line 60 to the sidewall of the inactive light emitting region B of the adjacent led chip, and it should be noted that, of course, the "about equal" is considered to be within ±5% of the error that may exist in the production apparatus, and it is not excluded that the error of some of the apparatus may reach ±10%.

Fig. 3 is a top view of a light emitting diode chip according to another embodiment of the present invention, and fig. 3A is a top view of a light emitting diode array including 4 light emitting diode chips shown in fig. 3; fig. 3B is an enlarged schematic view of the structure shown in the dashed box of fig. 3A.

In the embodiment shown in fig. 3, the light emitting diode chip includes an electrode 330, and three non-active light emitting regions 3B1, 3B2, 3B3, where the three non-active light emitting regions 3B1, 3B2, 3B3 include a first non-active light emitting region 3B2 symmetrical to the center of the concave region, and a second non-active light emitting region 3B1, a third non-active light emitting region 3B3 symmetrical to the concave region respectively, and the area of the first non-active region 3B2 is less than or equal to 25% of the sum of the areas of the second non-active light emitting region 3B1 and the third non-active light emitting region 3B3, so that the light emitting diode chip has more light emitting area and avoids light leakage;

further, the area of the second inactive light emitting area 3B1 or the area of the third inactive light emitting area 3B3 is larger than the area of the first inactive area 3B2, so as to better improve the light emitting efficiency of the light emitting diode chip.

With continued reference to fig. 3A and 3B, the second distance D2 between the electrode 330 and the sidewall of the inactive light emitting region 3B on the adjacent led chip is greater than or equal to the first distance D1 between the electrode 330 and the sidewall of the recessed region 3A, specifically, the first distance D1 between the electrode 330 and the sidewall of the recessed region 3A has a first minimum distance D1', and the second distance D2 between the electrode 330 and the sidewall of the inactive light emitting region 3B1, 3B2, 3B3 on the adjacent led chip also has a second minimum distance D2'. In the enlarged schematic view of the embodiment shown in fig. 3B, the first minimum distance D1 'is approximately equal to the second minimum distance D2'; this can avoid the offset of the wavelength conversion layer 40 caused by the lamination process of the light emitting diode chip and the adjacent light emitting diode chip, and the offset easily causes the defect of the wavelength conversion layer 40 in a partial region on the first surface 320a of the semiconductor epitaxial stack 320 after the film cutting, so that part of the semiconductor epitaxial stack 20 leaks out, and the light emitted in the region of the leaking out part is the first light with the first wavelength, but not the second light, thereby affecting the light emitting uniformity of the light emitting diode.

Fig. 4 is a top view of a light emitting diode chip according to another embodiment of the present invention, and fig. 4A is a top view of a light emitting diode array including 4 light emitting diode chips shown in fig. 4; FIG. 4B is an enlarged schematic view of the structure shown in the dashed box of FIG. 4A; fig. 4C is a side cross-sectional view of the first row of 2 led chips of fig. 4A, shown with the 2 led chips along the Z-Z' line.

In the embodiment shown in fig. 4, the led chip includes two second electrodes 430A and 430B and two inactive light emitting regions 4B1 and 4B2 respectively disposed at four corners of the semiconductor epitaxial stacked layer 420, and the two second electrodes 430A and 430B are respectively disposed on the same side of the semiconductor epitaxial stacked layer 420.

With continued reference to fig. 4A and 4B, the second spacing D2 between the electrode 430A (left side), 430B (right side) and the sidewall of the inactive light emitting region 4B on the adjacent led chip is greater than or equal to the first spacing D1 between the electrode 430 and the sidewall of the recessed region a, specifically, the first spacing D1 between the electrode 430A, 430B and the sidewall of the recessed region 4A has a first minimum spacing D1', and the second spacing D2 between the electrode 430A, 430B and the sidewall of the inactive light emitting region 4B1, 4B2 of the adjacent led chip also has a second minimum spacing D2'. In the enlarged schematic view of the embodiment shown in fig. 4B, the first minimum distance D1' between the electrode 430B of the upper left-hand led chip and the sidewall of the recessed region 4A is approximately equal to the second minimum distance D2' between the electrode 430B of the upper left-hand led chip and the sidewall of the non-active light emitting region 4B of the lower left-hand led chip, and the distance between the electrode 430B of the upper left-hand led chip and the sidewall of the non-active light emitting region 4B of the upper right-hand led chip is significantly greater than the second minimum distance D2'; in some embodiments, referring to fig. 4, 4A and 4B again, the led chip of the embodiment shown in fig. 4 has a third minimum distance D3' between the electrode 430B of the upper left led chip and the electrode 430A of the upper right led chip, wherein D3' is approximately equal to D1'.

Fig. 5 is a top view of a light emitting diode chip according to another embodiment of the present invention, and fig. 5A is a top view of a light emitting diode array including 4 light emitting diode chips shown in fig. 5.

Referring to fig. 5 and 5A, in the embodiment shown in fig. 5, the led chip includes three electrodes 530A, 530B, 530C, and an inactive light emitting region 5B disposed at four corners of the semiconductor epitaxial stack 520, wherein the inactive light emitting region 5B is located at an upper left corner of the semiconductor epitaxial stack 520, and the three electrodes 530A, 530B, 530C are located at the remaining three corners of the semiconductor epitaxial stack 420.

Fig. 6 is a top view of a light emitting diode chip according to another embodiment of the present invention, and fig. 6A is a top view of a light emitting diode array including 4 light emitting diode chips shown in fig. 6.

Referring to fig. 6 and 6A, in the embodiment shown in fig. 6, the led chip includes an electrode 630 and an inactive light emitting region 6B, and the electrode 630 and the inactive light emitting region 6B are symmetrically disposed at non-corner positions on both sides of the semiconductor epitaxial stack 620 along a center line thereof.

Fig. 7 is a top view of a light emitting diode chip according to another embodiment of the present invention, and fig. 7A is a top view of a light emitting diode array including 4 light emitting diode chips shown in fig. 7.

Referring to fig. 7 and 7A, in the embodiment shown in fig. 7, the light emitting diode chip includes two second electrodes 730A and 730B and two inactive light emitting regions 7B1 and 7B2 respectively disposed at four corners of the semiconductor epitaxial layer 720, and the two second electrodes 730A and 730B and the two inactive light emitting regions 7B1 and 7B2 are respectively disposed diagonally.

FIG. 8 is a cross-sectional view of a light emitting diode chip according to another embodiment of the present invention; fig. 9 is a cross-sectional view of the led chip structure provided by the embodiment of fig. 8 covered with a wavelength conversion layer 40.

Referring to fig. 2, 8 and 9, in this embodiment, a light emitting diode chip, for example, a white light emitting diode, is provided, which includes a semiconductor epitaxial stack 820 including a first conductivity type semiconductor layer 821, a light emitting layer 822 and a second conductivity type semiconductor layer 823 in this order from top to bottom;

a first electrical connection layer 51 electrically connected to the first conductive type semiconductor layer 21;

a second electrical connection layer 52 electrically connected to the second conductivity type semiconductor layer 823 and partially exposed outside the semiconductor epitaxial stack 820;

the semiconductor epitaxial stack 820 has at least one recess 24, the recess 24 extending at least through the second conductivity type semiconductor layer 823, the light emitting layer 822 to the first conductivity type semiconductor layer 821;

The first electrical connection layer 51 is electrically connected to the first conductive type semiconductor layer 821 via the recess 24 and is electrically insulated from each other by an insulating layer and the light emitting layer 822, the second conductive type semiconductor layer 823, and the second electrical connection layer 52; in the embodiment shown in fig. 8, the second electrical connection layer 52 completely covers the second surface 20b of the semiconductor epitaxial stack 820, and the first electrical connection layer 51 completely covers the insulating layer for insulation from the first electrical connection layer 51 to constitute the first electrode 831. The materials of the first and second electrical connection layers 51 and 52 include, but are not limited to, metal, semiconductor, metal oxide, or any combination thereof, and in the present embodiment, it is preferable that the first electrical connection layer 51 is composed of a silicon substrate and a filler metal filled into the recess, and an electrical connection is established between the silicon substrate and the first conductive type semiconductor layer 821. In the present embodiment, the first conductive type semiconductor layer 821 includes an N type semiconductor layer, and the first conductive type semiconductor layer 822 includes a P type semiconductor layer

At least one electrode 830 disposed on the surface of the exposed portion of the second electrical connection layer 52 and electrically connected to the second conductive type semiconductor layer 823;

Taking the normal direction of the horizontal plane of the semiconductor epitaxial layer stack 820 as the overlooking direction, a first interval D1 is arranged between the electrode 830 and the side wall of the concave region A in the overlooking direction, and the first interval D1 is more than or equal to 50 mu m;

an inactive light emitting region B located at an edge of the semiconductor epitaxial stacked layer 820 and penetrating at least the first conductivity type semiconductor layer 821 and the light emitting layer 822 to expose an inactive light emitting surface B', such that a second distance D2 between an electrode on an adjacent light emitting diode chip and a sidewall 25 of the inactive light emitting region B is greater than or equal to the first distance D1;

the wavelength conversion layer 840 covers at least the upper region and the sidewall region of the semiconductor epitaxial stack 820. In the illustrated embodiment, a wavelength conversion layer 840 is formed over the first surface 820a of the semiconductor epitaxial stack 820, the first surface 820 covering the upper surface of the first conductivity type semiconductor layer 821, the partial recessed surface a ', the partial inactive light emitting surface B', and the partial sidewalls of the semiconductor epitaxial stack 820; the wavelength conversion layer 840 may absorb the first light emitted from the semiconductor epitaxial stack 820 and emit at least a second light having a second wavelength different from the first wavelength. The wavelength conversion layer 840 is mainly phosphor powder or phosphor glue, and the thickness of the wavelength conversion layer 840 is in the range of 30 μm to 100 μm, and when the wavelength conversion layer 840 is mainly phosphor ceramic, the thickness of the wavelength conversion layer 840 is in the range of 100 μm to 300 μm, but the embodiment of the disclosure is not limited thereto.

The electrode 830 has a first distance D1 between the electrode 830 and the sidewall of the recess area a, where the first distance D1 is greater than or equal to 30 μm, so that when the wavelength conversion layer 840 is covered, enough space is reserved on the recess surface a', so that the wavelength conversion layer 840 fully covers the sidewall of the recess area a, that is, the portion of the sidewall of the semiconductor epitaxial stack 820. Further, the first distance D1 is 50 μm or more. Further, the structural design of the first spacing D1 and the inactive light emitting region B with the first spacing D1 can avoid the light emitting diode chip from generating an offset of the wavelength conversion layer 840 in the lamination process, and the offset easily causes the defect of the wavelength conversion layer 840 in a part of the area on the first surface 820a of the semiconductor epitaxial lamination 820 after the film is cut, so that part of the semiconductor epitaxial lamination 820 leaks out, and the light emitted in the area of the leaking part is the first light with the first wavelength, but not the second light, thereby affecting the light emitting uniformity of the light emitting diode.

It should be noted that, in the technical solution of the led chip in the embodiment shown in fig. 8, the features of the foregoing embodiments may be obviously combined to form a new technical solution with the same function, for example, the positional relationship between the concave area a and the non-active light emitting area B may be further improved, so that the reliability of the led chip is further improved, and no excessive description is made again.

In addition, it should be understood by those skilled in the art that although many problems exist in the prior art, each embodiment or technical solution of the present invention may be modified in only one or several respects, without having to solve all technical problems listed in the prior art or the background art at the same time. Those skilled in the art will understand that nothing in one claim should be taken as a limitation on that claim.

Although terms such as a substrate, an upper surface, a lower surface, a semiconductor epitaxial layer stack, a first surface, a second surface, a first conductivity type semiconductor layer, a light emitting layer, a second conductivity type semiconductor layer, a recess, a first electrode, a second electrode, a wavelength conversion layer, a first electrical connection layer, a second electrical connection layer, a recess region, a recess surface, an inactive light emitting region, an inactive light emitting surface, a pitch, a distance, and the like are more used herein, the possibility of using other terms is not excluded. These terms are used merely for convenience in describing and explaining the nature of the invention; they are to be interpreted as any additional limitation that is not inconsistent with the spirit of the present invention; the terms first, second, and the like in the description and in the claims of embodiments of the invention and in the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A light emitting diode chip, characterized in that: the light emitting diode chip includes:

at least one electrode disposed on the recessed surface;

2. A light emitting diode chip as claimed in claim 1, wherein: the light emitting diode chip further comprises a first non-active light emitting area, and the first non-active light emitting area is centrally symmetrical with the concave area.

3. A light emitting diode chip as claimed in claim 1, wherein: the light emitting layer is for radiating first light having a first wavelength, and the wavelength conversion layer absorbs the first light emitted from the semiconductor epitaxial stack and radiates at least second light having a second wavelength, the second wavelength being different from the first wavelength.

4. A light emitting diode chip as claimed in claim 1, wherein: and a second interval between the side wall of the non-active light emitting area and the electrode on the adjacent light emitting diode chip is larger than or equal to the first interval.

5. A light emitting diode chip as recited in claim 4, wherein: the second interval is composed of two parts, wherein the first part is the distance from the electrode to the cutting channel, and the second part is the distance from the cutting channel to the side wall of the non-active light emitting area of the adjacent light emitting diode chip.

6. A light emitting diode chip as recited in claim 4, wherein: the first pitch is a minimum pitch between the electrode and a sidewall of the recessed region.

7. A light emitting diode chip as recited in claim 4, wherein: the second spacing is the minimum spacing between the electrode and the sidewall of the inactive light emitting region on the adjacent light emitting diode chip.

8. A light emitting diode chip as recited in claim 4, wherein: the first pitch is 50 μm or more, or the first pitch is 85 μm or more.

9. A light emitting diode chip as claimed in claim 1, wherein: the area of the first inactive region is 25% or less of the sum of the areas of the second inactive light emitting region and the third inactive light emitting region as viewed from the top view.

10. A light emitting diode chip as claimed in claim 1, wherein: the area of the second non-active light emitting region or the area of the third non-active light emitting region is larger than the area of the first non-active region.

11. A light emitting diode chip, characterized in that: the light emitting diode chip includes:

at least one electrode disposed on the recessed surface;

12. A light emitting device, characterized in that: a light emitting diode chip having any one of claims 1 to 11.