KR102223038B1 - Semiconductor light emitting device and semiconductor light emitting apparatus having the same - Google Patents

Abstract

A semiconductor light emitting device according to an embodiment of the present invention includes a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; A first insulating layer provided on the light emitting structure and having a first opening disposed on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; A barrier metal layer provided on the first insulating layer and electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, through the first openings; A second insulating layer provided on the barrier metal layer and having a second opening partially exposing the barrier metal layer; And an electrode provided on the barrier metal layer partially exposed through the second opening, and electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, through the barrier metal layer, , At least one of the first and second insulating layers and the barrier metal layer are disposed between the electrode and the light emitting structure.

Description

A semiconductor light emitting device and a semiconductor light emitting device having the same {SEMICONDUCTOR LIGHT EMITTING DEVICE AND SEMICONDUCTOR LIGHT EMITTING APPARATUS HAVING THE SAME}

The present invention relates to a semiconductor light emitting device and a semiconductor light emitting device having the same.

Light-emitting diodes (LEDs) are known as a next-generation light source with advantages such as long lifespan, low power consumption, fast response speed, and environmental friendliness compared to conventional light sources. It is attracting attention.

Among these light-emitting diodes, the flip-chip type is a bonding metal, which has the disadvantage of increasing the cost by using an alloy containing expensive metals such as AuSn, and the characteristic of melting at high temperature. There was a problem in that the scope of use was reduced due to the need for an expensive package composed of a material that is not available.

In addition, in the case of Sn solder, there is a problem that the solder spreads.

Accordingly, there is a need in the art to fundamentally block the diffusion of Sn solder.

However, the object of the present invention is not limited thereto, and even if not explicitly mentioned, the object or effect that can be grasped from the solutions or embodiments of the problems described below will be included therein.

A semiconductor light emitting device according to an embodiment of the present invention includes a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; A first insulating layer provided on the light emitting structure and having a first opening disposed on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; A barrier metal layer provided on the first insulating layer and electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, through the first openings; A second insulating layer provided on the barrier metal layer and having a second opening partially exposing the barrier metal layer; And an electrode provided on the barrier metal layer partially exposed through the second opening, and electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, through the barrier metal layer, , At least one of the first and second insulating layers and the barrier metal layer may be disposed between the electrode and the light emitting structure.

The second insulating layer may be provided on the barrier metal layer at a position corresponding to the first opening.

The first opening and the second opening may be arranged in a structure that does not overlap each other.

The light emitting structure may include an etched region in which the second conductive semiconductor layer, the active layer, and a portion of the first conductive semiconductor layer are etched, and a plurality of mesa regions partially partitioned by the etching region. .

The etching region may extend from one side of the light emitting structure toward the other side opposite to the light emitting structure, and a plurality of the etching regions may be provided in parallel with each other.

A first contact electrode disposed on an upper surface of the first conductive type semiconductor layer exposed to the etching region and connected to the first conductive type semiconductor layer, wherein the first contact electrode is formed through the barrier metal layer. It can be connected to the first electrode.

The first contact electrode may include a plurality of pad portions and a plurality of finger portions extending from the plurality of pad portions along the etching region, respectively.

The plurality of pad portions are exposed through the first opening and may be directly connected to the barrier metal layer.

A second contact electrode disposed on an upper surface of the plurality of mesa regions to be connected to the second conductivity type semiconductor layer, the second contact electrode may be connected to the second electrode through the barrier metal layer. .

The second contact electrode may include a reflective metal layer.

It may further include a coating metal layer covering the reflective metal layer.

A passivation layer provided on a side surface of the mesa region to cover the active layer exposed to the etching region may be further included.

The electrode includes a first electrode and a second electrode, and may be provided as a single electrode or a plurality of electrodes, respectively.

On the other hand, the semiconductor light emitting device according to an embodiment of the present invention has a stacked structure of a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, and the second conductivity type semiconductor layer, the active layer, and the first A light emitting structure including an etched region in which a part of the conductive semiconductor layer is etched, and a mesa region partially partitioned by the etched region; A first insulating layer provided on the light emitting structure; A barrier metal layer provided on the first insulating layer and electrically connected to the first conductive type semiconductor layer and the second conductive type semiconductor layer, respectively, through the first insulating layer; A second insulating layer provided on the barrier metal layer; And an electrode provided on a portion of the barrier metal layer exposed from the second insulating layer, and electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, through the barrier metal layer, The first insulating layer and the barrier metal layer or the barrier metal layer and the second insulating layer may be disposed between the electrode and the light emitting structure.

The first insulating layer has a first opening partially exposing each of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and the second insulating layer partially exposes the barrier metal layer. It has two openings, and the first opening and the second opening may be arranged in a structure that does not overlap each other.

A first contact electrode provided on the first conductivity type semiconductor layer defining a bottom surface of the etching region, and a second contact electrode provided on an upper surface of the mesa region, the first contact electrode and The second contact electrode may be connected to the barrier metal layer through the first opening.

The first contact electrode includes a plurality of pad portions and a plurality of finger portions respectively extending along the etching region from the plurality of pad portions, and the plurality of pad portions are exposed through the first opening, and the barrier metal layer And can be directly connected.

On the other hand, a semiconductor light emitting device according to an embodiment of the present invention includes a package body including a lead frame; And the semiconductor light emitting device disposed on the package body and connected to the lead frame.

The semiconductor light emitting device may be connected to the lead frame through solder interposed between the electrode and the lead frame.

An encapsulation part provided on the package body to cover the semiconductor light-emitting device may be further included, and the encapsulation part may contain a wavelength converting material for converting a wavelength of light generated from the semiconductor light-emitting device.

According to an embodiment of the present invention, a semiconductor light emitting device capable of fundamentally blocking diffusion of Sn solder and a semiconductor light emitting device having the same may be provided.

Various and beneficial advantages and effects of the present invention are not limited to the above-described contents, and may be more easily understood in the course of describing specific embodiments of the present invention.

1 is a schematic plan view of a semiconductor light emitting device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically showing a cross-section taken along the cut line A-A' of FIG. 1.
3 is an enlarged cross-sectional view of part B in FIG. 2.
4A to 10B are main step-by-step views schematically showing a method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention.
11A and 11B are plan views schematically showing modified arrangement structures of first and second electrodes, respectively.
12 is a schematic plan view of a semiconductor light emitting device according to another embodiment of the present invention.
13 is a cross-sectional view schematically showing a cross-section taken along the cut line C-C' of FIG. 12.
14 is an enlarged cross-sectional view of portion D in FIG. 13.
15A to 20B are main step-by-step views schematically showing a method of manufacturing a semiconductor light emitting device according to another embodiment of the present invention.
21A and 21B are cross-sectional views schematically illustrating an example in which a semiconductor light emitting device according to an embodiment of the present invention is applied to a package, respectively.
22 and 23 are cross-sectional views illustrating an example in which a semiconductor light emitting device according to an embodiment of the present invention is applied to a backlight unit.
24 and 25 are exploded perspective views showing an example in which a semiconductor light emitting device according to an embodiment of the present invention is applied to a lighting device.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, embodiments of the present invention are provided in order to more completely explain the present invention to those with average knowledge in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer description, and elements indicated by the same reference numerals in the drawings are the same elements.

A semiconductor light emitting device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic plan view of a semiconductor light emitting device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view schematically illustrating a cross-section taken along a cut line A-A' of FIG. 1.

1 and 2, the semiconductor light emitting device 10 according to an embodiment of the present invention includes a light emitting structure 100, a first insulating layer 200, a barrier metal layer 300, and a second insulating layer ( 400) and the electrode 500 may be included.

The light emitting structure 100 has a structure in which a plurality of semiconductor layers are stacked, and a first conductivity type semiconductor layer 110, an active layer 120, and a second conductivity type semiconductor layer 130 are sequentially stacked on the substrate 101. ) Can be included.

In this specification, terms such as'upper','upper','upper','lower','lower','lower', and'side' are based on drawings, and in reality, It may be different depending on the direction.

The substrate 101 may have an upper surface extending in the x and y directions. The substrate 101 may be provided as a substrate for semiconductor growth, and insulating, conductive, and semiconductor materials such as _{sapphire, Si, SiC, MgAl 2} O ₄ , MgO, LiAlO ₂ , LiGaO _{2, and GaN may be used.} Sapphire, which is widely used as a substrate for nitride semiconductor growth, is a crystal having electrical insulation and hexagonal-Rhombo (Hexa-Rhombo R3c) symmetry, and has a lattice constant of 13.001Å and 4.758Å in the c-axis and a-side directions, respectively, It has a (0001) plane, an A(1120) plane, and an R(1102) plane. In this case, the C-plane is mainly used as a substrate for nitride growth because it is relatively easy to grow a nitride thin film and is stable at high temperatures.

In addition, as shown in the drawing, a plurality of uneven structures 102 may be formed on the upper surface of the substrate 101, that is, the surface on which the semiconductor layers are grown, and the semiconductor layers are determined by the uneven structure 102. Performance, light emission efficiency, and the like can be improved. In the present embodiment, the uneven structure 102 is illustrated as having a dome-shaped convex shape, but is not limited thereto. For example, the uneven structure 102 may be formed in various shapes such as a square or a triangle. In addition, the uneven structure 102 may be selectively formed and provided, and thus may be omitted.

Meanwhile, the substrate 101 may be removed later depending on the embodiment. That is, after being provided as a growth substrate for growing the first conductivity type semiconductor layer 110, the active layer 120, and the second conductivity type semiconductor layer 130, they may be removed through a separation process. The separation of the substrate 101 may be separated from the semiconductor layer through a method such as laser lift off (LLO), chemical lift off (CLO), or the like.

Although not shown in the drawing, a buffer layer may be further provided on the upper surface of the substrate 101. The buffer layer is for mitigating lattice defects in the semiconductor layer grown on the substrate 101 and may be formed of an undoped semiconductor layer made of nitride or the like. The buffer layer, for example, mitigates the difference in lattice constant between the substrate 101 made of sapphire and the first conductivity type semiconductor layer 110 made of GaN stacked on the upper surface of the substrate 101, thereby reducing the crystallinity of the GaN layer. Can be increased. The buffer layer may be undoped GaN, AlN, InGaN, or the like, and may be formed by growing at a low temperature of 500° C. to 600° C. to a thickness of tens to hundreds of Å. Here, undoping means that the semiconductor layer is not subjected to a separate impurity doping process, and impurity concentration at the level originally present in the semiconductor layer, for example, a gallium nitride semiconductor, is deposited by metal organic chemical vapor deposition (MOCVD). In the case of growing by using, even if the Si used as a dopant is not intended, it may be included at a level of ^{about 10 14} ~ 10 ^{18 /cm 3.} However, such a buffer layer is not an essential element in the present embodiment and may be omitted depending on the embodiment.

The first conductivity-type semiconductor layer 110 stacked on the substrate 101 may be formed of a semiconductor doped with n-type impurities, and may be an n-type nitride semiconductor layer. In addition, the second conductivity-type semiconductor layer 130 may be formed of a semiconductor doped with p-type impurities, and may be a p-type nitride semiconductor layer. However, depending on the embodiment, the positions of the first and second conductivity-type semiconductor layers 110 and 130 may be changed and stacked. The first and second conductivity-type semiconductor layers 110 and 130 have Al _x In _y Ga _(1-xy) N composition formulas (here, 0≤x≤1, 0≤y≤1, 0≤x+y≤1) ), and, for example, materials such as GaN, AlGaN, InGaN, and AlInGaN may correspond to this.

The active layer 120 disposed between the first and second conductivity-type semiconductor layers 110 and 130 emits light having a predetermined energy by recombination of electrons and holes. The active layer 120 may include a material having an energy band gap smaller than that of the first and second conductivity type semiconductor layers 110 and 130. For example, when the first and second conductivity-type semiconductor layers 110 and 130 are GaN-based compound semiconductors, the active layer 120 may include an InGaN-based compound semiconductor having an energy band gap smaller than that of GaN. I can. In addition, the active layer 120 may have a multiple quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked, such as an InGaN/GaN structure. However, since the active layer 120 is not limited thereto, a single quantum well (SQW) structure may be used.

The light emitting structure 100 includes an etching region E in which a portion of the second conductivity type semiconductor layer 130, the active layer 120, and the first conductivity type semiconductor layer 110 is etched, and the etching region It may include a plurality of mesa regions (M) partially partitioned by (E).

The etched region E has a gap structure cut from one side of the light emitting structure 100 having a square shape toward the other side opposite to the other side to have a predetermined thickness and length, and a plurality of the light emitting structures 100 may be provided in parallel with each other. Accordingly, the plurality of mesa regions M are not physically completely separated by the etching region E, but may be connected to each other at the other side to form an integral part.

A first contact electrode 140 is disposed on an upper surface of the first conductivity type semiconductor layer 110 exposed to the etching region E to be connected to the first conductivity type semiconductor layer 110, and the plurality of A second contact electrode 150 may be disposed on an upper surface of the mesa region M to be connected to the second conductivity type semiconductor layer 130.

The first contact electrode 140 extends from the plurality of pad portions 141 in a form having a narrower width than that of a plurality of pad portions 141 as shown in FIG. 1 for uniform injection of the electrode. It includes a plurality of finger portions 142 to be formed, and may extend along the etched region E. The plurality of pad portions 141 may be disposed to be spaced apart from each other, and the plurality of finger portions 142 may connect the plurality of pad portions 141.

The second contact electrode 150 may include a reflective metal layer 151. In addition, a covering metal layer 152 covering the reflective metal layer 151 may be further included. However, the covering metal layer 152 may be selectively provided, and may be omitted depending on the embodiment. The second contact electrode 150 may be provided to cover an upper surface of the second conductivity type semiconductor layer 130 defining an upper surface of the mesa region M.

In order to increase the luminous efficiency of the light emitting structure 100, the first contact electrode 140 and the second contact electrode 150 may be disposed to have a structure that is alternately formed as a whole. However, the shapes and structures of the first and second contact electrodes 140 and 150 are exemplary and are not limited to those shown in the drawings.

Meanwhile, a passivation layer 200a made of an insulating material may be provided on a side surface of the mesa region M to cover the active layer 120 exposed to the etching region E. However, the passivation layer 200a is selectively provided and may be omitted depending on embodiments.

The first insulating layer 200 may be provided on the light emitting structure 100 to cover the light emitting structure 100 as a whole. The first insulating layer 200 may be formed of a material having basic insulating properties, and may be formed of an inorganic or organic material. For example, the first insulating layer 200 may be formed of an epoxy-based insulating resin. In addition, the first insulating layer 200 may include silicon oxide or silicon nitride, for example, SiO ₂ , SiN, SiO _x N _{y ,} TiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , It may be made of TiN, AlN, ZrO ₂ , TiAlN, TiSiN, and the like.

The first insulating layer 200 includes a first conductivity type semiconductor layer 110 exposed to the etching region E and a plurality of first openings 210 disposed on the second conductivity type semiconductor layer 130. Can be equipped. Specifically, the first opening 210 has a structure in which the first contact electrode 140 and the second contact electrode 150 are partially exposed on the first and second conductivity type semiconductor layers 110 and 130. It can be provided. In particular, in the case of the first contact electrode 140, the pad part 141 is exposed to the outside through the first opening 210, and thus, the first opening 210 is formed of the first conductive semiconductor layer ( On 110), it may be disposed at a position corresponding to the pad part 141.

The barrier metal layer 300 is provided on the first insulating layer 200, and the first conductivity type semiconductor layer 110 and the second conductivity type semiconductor layer 130 through the first opening 210 And can each be electrically connected.

As shown in FIG. 2, the barrier metal layer 300 is formed of the first and second conductivity-type semiconductor layers 110 by the first insulating layer 200 that entirely covers the upper surface of the light emitting structure 100. , 130) and can be insulated. In addition, the first and second conductive type semiconductor layers 110 and 130 are connected to the first contact electrode 140 and the second contact electrode 150 exposed to the outside through the first opening 210. Can be connected.

Electrical connection between the barrier metal layer 300 and the first and second conductivity type semiconductor layers 110 and 130 is variously controlled by the first opening 210 provided in the first insulating layer 200 Can be. For example, the electrical connection between the barrier metal layer 300 and the first and second conductivity-type semiconductor layers 110 and 130 may be variously changed according to the number and arrangement position of the first openings 210. I can.

The barrier metal layer 300 may be provided in at least one pair for electrical insulation between the first conductivity type semiconductor layer 110 and the second conductivity type semiconductor layer 130. That is, the first metal layer 310 is electrically connected to the first conductivity type semiconductor layer 110, the second metal layer 320 is electrically connected to the second conductivity type semiconductor layer 130, the The first and second metal layers 310 and 320 may be separated from each other and electrically insulated.

The barrier metal layer 300 may be made of, for example, a material including at least one of a material such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, Cr, and alloys thereof.

The second insulating layer 400 is provided on the barrier metal layer 300 and entirely covers and protects the barrier metal layer 300. In addition, the second insulating layer 400 may include a second opening 410 partially exposing the barrier metal layer 300.

A plurality of second openings 410 may be provided to partially expose the first metal layer 310 and the second metal layer 320, respectively. In this case, the second opening 410 may be disposed in a structure that does not overlap with the first opening 210 of the first insulating layer 200. That is, the second opening 410 is not positioned above the first opening 210 in a vertical direction.

In the present embodiment, three second openings 410 are provided and are exemplified as being arranged in an asymmetric structure, but the present invention is not limited thereto. The number and arrangement of the second openings 410 may be variously modified.

The second insulating layer 400 may be made of the same material as the first insulating layer 200.

The electrode 500 includes a first electrode 510 and a second electrode 520 and is formed on the first and second metal layers 310 and 320 partially exposed through the second opening 410. Each can be provided. In addition, each of the first conductivity-type semiconductor layer 110 and the second conductivity-type semiconductor layer 130 may be electrically connected to each other through the barrier metal layer 300.

The first electrode 510 and the second electrode 520 may be, for example, an under bump metallurgy (UBM) layer. And, each may be provided as a single or a plurality. In the present embodiment, two first electrodes 510 and a single second electrode 520 are provided, but are not limited thereto. The number and arrangement structure of the first and second electrodes 510 and 520 may be adjusted according to the second opening 410.

A groove in which a conductive adhesive, for example, Sn solder, is placed may be formed in the first and second electrodes 510 and 520.

Meanwhile, the first and second conductive semiconductor layers 110 and 130 are formed through the first opening 210 due to the arrangement structure of the first and second openings 210 and 410. On the barrier metal layer 300 connected to ), the second insulating layer 400 may be provided at a position corresponding to the first opening 210.

Accordingly, between the first electrode 510 and the second electrode 520 and the light emitting structure 100, the first insulating layer 200 and the barrier metal layer 300 or the barrier metal layer 300 2 A double barrier structure in which the insulating layers 400 are overlapped and disposed may be provided.

This double barrier structure will be described with reference to FIG. 3. 3 is an enlarged cross-sectional view of part B in FIG. 2.

As shown in FIG. 3, a barrier metal layer (specifically, a second metal layer 320) and an insulating dielectric are metal in the area where the Sn solder (S) and the second electrode 520, that is, the UBM are overlaid. The phosphorus first insulating layer 200 may be stacked and disposed. In addition, the double barrier structure composed of the second metal layer 320 and the first insulating layer 200 may block the diffusion of Sn solder S in a vertical direction toward the light emitting structure 100 as shown by an arrow. . Specifically, diffusion to the second contact electrode 150 including the reflective metal layer 151 may be blocked.

Specifically, the Sn solder alloy SAC (Sn _96.5 Ag _3.0 Cu _0.5 ) has the advantage of being relatively inexpensive and excellent in reliability. And there is a problem that the luminance decreases and the forward voltage (Vf, Voltage Forward) increases. In this embodiment, by implementing a double barrier structure, it is possible to solve a problem that occurs because it is not possible to block the diffusion of Sn solder to the light emitting structure in the conventional single barrier structure, that is, the problem of decrease in reflectivity and luminance due to contamination, and increase in forward voltage. have.

4A to 10B are main step-by-step views schematically showing a method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention. In FIGS. 4A to 10B, the same reference numerals as in FIGS. 1 to 3 denote the same members, and therefore, overlapping descriptions are omitted.

4A and 4B, FIG. 4A is a plan view of a light emitting structure formed on a substrate, and FIG. 4B is a cross-sectional view corresponding to a cut line A-A' of FIG. 4A. 5A to 10B below are also shown in the same manner.

First, the uneven structure 102 may be formed on the substrate 101. However, depending on the embodiment, the uneven structure 102 may be omitted. As described above, the substrate 101 may be a substrate made of a material such as sapphire, Si, SiC, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO _{2, and GaN.} Further, although not shown in the drawings, a buffer layer may be selectively provided on the substrate. The buffer layer may be made of a material such as undoped GaN, AlN, or InGaN.

Next, using a process such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydrogen Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), etc., the substrate 101 ) On the first conductivity type semiconductor layer 110, the active layer 120, and the second conductivity type semiconductor layer 130 are sequentially grown to form a light emitting structure 100 having a stacked structure of a plurality of semiconductor layers. Here, the first conductivity-type semiconductor layer 110 and the second conductivity-type semiconductor layer 130 may be an n-type semiconductor layer and a p-type semiconductor layer 130, respectively. In the light emitting structure 100, the positions of the first conductivity-type semiconductor layer 110 and the second conductivity-type semiconductor layer 130 may be changed, and the second conductivity-type semiconductor layer 130 is first on the substrate 101. Can be formed.

5A and 5B, a second conductivity type semiconductor layer 130, an active layer 120, and a portion of the first conductivity type semiconductor layer 110 so that at least a portion of the first conductivity type semiconductor layer 110 is exposed. Can be etched. Accordingly, the etching region E and a plurality of mesa regions M partially partitioned by the etching region E may be formed.

In the etching process, after forming a mask layer in a region other than the region where the first conductivity type semiconductor layer 110 is exposed, the mesa region M may be formed through a wet method or a dry method. Depending on the embodiment, an etching process may be performed so that only the top surface of the first conductivity type semiconductor layer 110 is not etched.

6A and 6B, a passivation layer 200a may be formed on a side surface of the mesa region M exposed to the etching region E by an etching process. The passivation layer 200a may include a top edge of the mesa region M and a bottom surface of the etch region E to cover a side surface of the mesa region M. Accordingly, the active layer 120 exposed to the etching region E may be covered so that it is not exposed to the outside by the passivation layer 200a. However, the passivation layer 200a is selectively formed and may be omitted depending on the embodiment.

7A and 7B, a first contact electrode 140 and a second contact electrode 150 may be formed on the etch region E and the mesa region M, respectively. The first contact electrode 140 may connect to a first conductivity type semiconductor layer 110 defining a bottom surface of the etching region E along the etching region E. In addition, the second contact electrode 150 may be connected to the second conductivity type semiconductor layer 130.

The first contact electrode 140 may include a plurality of pad portions 141 and a plurality of finger portions 142 extending from the pad portion 141. The second contact electrode 150 may include a reflective metal layer 151. In addition, a covering metal layer 152 covering the reflective metal layer 151 may be further included.

Referring to FIGS. 8A and 8B, a first insulating layer 200 may be provided on the light emitting structure 100 to cover the light emitting structure 100 as a whole. For example, the first insulating layer 200 may be formed of an epoxy-based insulating resin. In addition, the first insulating layer 200 may include silicon oxide or silicon nitride, for example, SiO ₂ , SiN, SiO _x N _{y ,} TiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , It may be made of TiN, AlN, ZrO ₂ , TiAlN, TiSiN, and the like.

In addition, the first contact electrode 140 and the second contact electrode 150 may be partially exposed on the first and second conductivity-type semiconductor layers 110 and 130 through the plurality of first openings 210. have.

9A and 9B, a barrier metal layer 300 may be formed on the first insulating layer 200. In addition, the first and second contact electrodes 140 and 150 are connected through the first opening 210 to be connected to the first and second conductive semiconductor layers 110 and 130. ) And each can be electrically connected.

The barrier metal layer 300 may be provided in at least one pair for electrical insulation between the first conductivity type semiconductor layer 110 and the second conductivity type semiconductor layer 130. That is, the first metal layer 310 is electrically connected to the first conductivity type semiconductor layer 110, the second metal layer 320 is electrically connected to the second conductivity type semiconductor layer 130, the The first and second metal layers 310 and 320 may be separated from each other and electrically insulated.

10A and 10B, a second insulating layer 400 may be formed on the barrier metal layer 300. In addition, the second insulating layer 400 may partially expose the barrier metal layer 300 through the second opening 410.

The second openings 410 are provided in plural to partially expose the first metal layer 310 and the second metal layer 320, respectively, and a first opening of the first insulating layer 200 ( 210) and may be arranged in a structure that does not overlap each other. That is, the second opening 410 is not positioned above the first opening 210 in a vertical direction. The second insulating layer 400 may be made of the same material as the first insulating layer 200.

Meanwhile, an electrode 500 including a first electrode 510 and a second electrode 520 on the first and second metal layers 310 and 320 partially exposed through the second opening 410, respectively Can be formed. The first electrode 510 and the second electrode 520 may be, for example, an under bump metallurgy (UBM) layer.

The number and arrangement structure of the first and second electrodes 510 and 520 may be variously adjusted. 11A and 11B are plan views schematically showing a modified arrangement structure of the first and second electrodes 510 and 520, respectively.

As shown in FIG. 11A, the first electrode 510 may be arranged in a ring shape in an edge region of the light emitting structure, and a second electrode 520 may be arranged in a central region thereof. In addition, as shown in FIG. 11B, the first electrode 510 and the second electrode 520 may have an arrangement structure opposite to that of FIG. 11A.

In this way, the arrangement structure in which the first electrode surrounds the center second electrode has the advantage that it is not necessary to mount the semiconductor light emitting device by limiting it to only a specific direction in consideration of the position of the electrode. For example, in mounting the semiconductor light emitting device, it is easy to mount because there is no need to consider whether the left and right positions of the first and second electrodes are changed or rotated at a predetermined angle.

A semiconductor light emitting device according to another embodiment of the present invention will be described with reference to FIGS. 12 and 13. 12 is a schematic plan view of a semiconductor light emitting device according to another embodiment of the present invention, and FIG. 13 is a cross-sectional view schematically showing a cross-section taken along the cut line C-C' of FIG. 12.

12 and 13, a semiconductor light emitting device 10' according to an embodiment of the present invention includes a light emitting structure 100', a first insulating layer 200', a barrier metal layer 300', and 2 It may be configured to include an insulating layer 400 ′ and an electrode 500 ′.

The light emitting structure 100 ′ has a structure in which a plurality of semiconductor layers are stacked, and a first conductivity type semiconductor layer 110 ′, an active layer 120 ′, and a second conductivity type sequentially stacked on the substrate 101 ′. A semiconductor layer 130 ′ may be included.

The substrate 101 ′ constituting the light emitting structure according to the present embodiment, and a first conductivity type semiconductor layer 110 ′, an active layer 120 ′, and a second conductivity type semiconductor layer stacked on the substrate 101 ′ Reference numeral 130' denotes a substrate 101 constituting the light emitting structure 100 shown in FIGS. 1 to 11, a first conductivity type semiconductor layer 110, an active layer 120, and a second conductivity type semiconductor layer 130. ) And each configuration and structure correspond to each other, and thus, a detailed description thereof will be omitted.

The light emitting structure 100 ′ includes an etching region E in which a portion of the second conductivity type semiconductor layer 130 ′, the active layer 120 ′, and the first conductivity type semiconductor layer 110 ′ is etched, , A plurality of mesa regions M partially partitioned by the etching region E may be included.

The etching region E may have a gap structure cut from one side of the light emitting structure 100 ′ having a square shape toward the other side opposite to the light emitting structure 100 ′ when viewed from the top to a predetermined thickness and length. In addition, a plurality of the light emitting structures 100 ′ may be arranged in parallel with each other inside the rectangular area. Accordingly, the plurality of etching regions E may be provided in a structure surrounded by the mesa region M.

A first contact electrode 140 ′ is disposed on an upper surface of the first conductivity type semiconductor layer 110 ′ exposed to the etching region E to be connected to the first conductivity type semiconductor layer 110 ′, A second contact electrode 150 ′ may be disposed on an upper surface of the plurality of mesa regions M to be connected to the second conductivity type semiconductor layer 130 ′.

The first contact electrode 140 ′ includes a plurality of pad portions 141 ′ as shown in FIG. 12, and a plurality of finger portions extending from the plurality of pad portions 141 ′ in a narrower width than this. It includes (142'), and may extend along the etching region (E). Further, a plurality of the first contact electrodes 140 ′ may be arranged at intervals so that a plurality of the first contact electrodes 140 ′ are uniformly distributed throughout the first conductivity type semiconductor layer 110 ′. Accordingly, the current injected into the first conductivity type semiconductor layer 110 ′ through the plurality of first contact electrodes 140 ′ may be uniformly injected throughout the first conductivity type semiconductor layer 110 ′. have.

The plurality of pad parts 141 ′ may be disposed to be spaced apart from each other, and the plurality of finger parts 142 ′ may respectively connect the plurality of pad parts 141 ′. The plurality of finger portions 142 ′ may have different widths. For example, as in the present embodiment, when the first contact electrode 140' has three finger portions 142', the finger portions 142 having a relatively different width of any one finger portion 142' Can be larger than the width of'). This may adjust the size of the width in consideration of the resistance of the current injected through the first contact electrode 140 ′.

The second contact electrode 150 ′ may include a reflective metal layer 151 ′. In addition, a coating metal layer 152 ′ covering the reflective metal layer 151 ′ may be further included. However, such a covering metal layer 152 ′ may be selectively provided, and may be omitted according to embodiments. The second contact electrode 150 ′ may be provided to cover an upper surface of the second conductivity type semiconductor layer 130 ′ defining an upper surface of the mesa region M.

A passivation layer 200a ′ made of an insulating material may be provided on the side of the mesa region M to cover the active layer 120 ′ exposed to the etching region E. However, the passivation layer 200a' is selectively provided, and may be omitted depending on embodiments.

The first insulating layer 200 ′ may be provided on the light-emitting structure 100 ′ in a structure that entirely covers the light-emitting structure 100 ′. The first insulating layer 200 ′ may be formed of a material having basic insulating properties, and may be formed using an inorganic or organic material. For example, the first insulating layer 200 ′ may be formed of an epoxy-based insulating resin. In addition, the first insulating layer 200 ′ may include silicon oxide or silicon nitride, for example, SiO ₂ , SiN, SiO _x N _{y ,} TiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiN, AlN, ZrO ₂ , TiAlN, TiSiN, and the like.

The first insulating layer 200 ′ may include a plurality of first openings 210 ′ respectively disposed on the first contact electrode 140 ′ and the second contact electrode 150 ′. Specifically, the plurality of first openings 210 ′ are provided at positions corresponding to the first contact electrode 140 ′ and the second contact electrode 150 ′, respectively, and The second contact electrode 150 ′ may be partially exposed.

In particular, a first opening 210 ′ disposed on the first contact electrode 140 ′ among the plurality of first openings 210 ′ is a pad portion 141 ′ of the first contact electrode 140 ′ The bay can be exposed to the outside. Accordingly, the plurality of first openings 210 ′ may be disposed on the first contact electrode 140 ′ at a position corresponding to the pad part 141 ′.

The barrier metal layer 300 ′ is provided on the first insulating layer 200 ′, and the first conductivity-type semiconductor layer 110 ′ and the second conductivity are formed through the plurality of first openings 210 ′. The type semiconductor layer 130 ′ may be electrically connected to each other.

13, the barrier metal layer 300' is formed of the first and second conductivity type semiconductors by the first insulating layer 200' covering the entire upper surface of the light emitting structure 100'. It may be insulated from the layers 110 ′ and 130 ′. In addition, the first and second conductivity-type semiconductor layers are connected to the first and second contact electrodes 140 ′ and 150 ′ partially exposed through the plurality of first openings 210 ′. 110', 130') can be electrically connected.

Electrical connection between the barrier metal layer 300 ′ and the first and second conductivity type semiconductor layers 110 ′ and 130 ′ is performed by the plurality of first openings 210 provided in the first insulating layer 200 ′. ') can be adjusted in various ways. For example, according to the number and arrangement positions of the plurality of first openings 210 ′, the barrier metal layer 300 ′ and the first and second conductivity type semiconductor layers 110 ′ and 130 ′ are electrically connected to each other. The connection can be varied in various ways.

The barrier metal layer 300 ′ may be provided in at least one pair including a first metal layer 310 ′ and a second metal layer 320 ′. That is, the first metal layer 310 ′ is electrically connected to the first conductivity type semiconductor layer 110 ′ through the first contact electrode 140 ′, and the second metal layer 320 ′ is It may be electrically connected to the second conductivity type semiconductor layer 130 ′ through the second contact electrode 150 ′. In this case, the first opening 210 ′ exposing the first contact electrode 140 ′ is disposed at a position overlapping the first metal layer 310 ′, and the second contact electrode 150 ′ The first opening 210 ′ exposing the is required to be disposed at a position overlapping with the second metal layer 320 ′. In addition, the first and second metal layers 310 ′ and 320 ′ may be separated from each other to be electrically insulated.

The barrier metal layer 300 ′ may be made of, for example, a material including at least one of a material such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, Cr, and alloys thereof.

Meanwhile, a first contact electrode 140 ′ disposed at a position overlapping the second metal layer 320 ′ with the second metal layer 320 ′ positioned on the first contact electrode 140 ′ In the case of, it is necessary to block electrical connection with the second metal layer 320 ′. To this end, the first insulating layer 200 ′ has a first opening 210 ′ exposing the pad portion 141 ′ of the first contact electrode 140 ′, and the second metal layer 320 ′ has an upper portion thereof. It may not be provided in the part located at.

Specifically, as shown in FIG. 12, when the first contact electrode 140' includes four pad portions 141' and three finger portions 142', the pad portion 141' is exposed. The first opening 210 ′ is provided only on the three pad portions 141 ′ disposed at a position overlapping the first metal layer 310 ′ and disposed at a position overlapping the second metal layer 320 ′ It is not provided on the remaining pad portion 141'. Accordingly, the pad portion 141 ′ of the first contact electrode 140 ′ positioned under the first metal layer 310 ′ is formed through the first opening 210 ′ to the first metal layer 310 ′. However, since the first opening 210 ′ is not provided on the pad part 141 ′ positioned under the second metal layer 320 ′, the pad part 141 ′ and the second metal layer 320 ′ are ') can be electrically insulated from each other. As a result, the first metal layer 310 ′ is formed through the arrangement structure of the plurality of first openings 210 ′ partially exposing the first contact electrode 140 ′ and the second contact electrode 150 ′, respectively. The contact electrode 140 ′ may be connected, and the second metal layer 320 ′ may be connected to the second contact electrode 150 ′.

The second insulating layer 400 ′ is provided on the barrier metal layer 300 ′, and completely covers and protects the barrier metal layer 300 ′. In addition, the second insulating layer 400 ′ may include a second opening 410 ′ partially exposing the barrier metal layer 300 ′.

A plurality of second openings 410 ′ may be provided to partially expose the first metal layer 310 ′ and the second metal layer 320 ′, respectively. In this case, some of the plurality of second openings 410 ′ may be disposed in a structure that does not overlap with some of the plurality of first openings 210 ′ of the first insulating layer 200 ′. For example, as shown in FIGS. 13 and 14, among the plurality of second openings 410 ′, a second opening 410 ′ partially exposing the second metal layer 320 ′ has the plurality of Among the first openings 210 ′ of, the first openings 210 ′ partially exposing the second contact electrode 150 ′ may not overlap each other. That is, the second opening 410 ′ is not positioned above the first opening 210 ′ in a vertical direction. In addition, the second opening 410 ′ partially exposing the first metal layer 310 ′ may partially overlap the first opening 210 ′ partially exposing the first contact electrode 140 ′. .

In the present embodiment, four second openings 410 ′ are provided and are exemplified as being arranged in a symmetrical structure, but the present invention is not limited thereto. The number and arrangement shape of the second openings 410 ′ may be variously modified.

The second insulating layer 400 ′ may be made of the same material as the first insulating layer 200 ′.

Meanwhile, the second insulating layer 400 ′ further includes an open region 430 ′ partially exposing the first and second metal layers 310 ′ and 320 ′, similar to the second opening 410 ′. can do. Such an open area 430 ′ may be provided as an area connected to a probe (not shown) so as to check whether the semiconductor light emitting device is operated or not before mounting the semiconductor light emitting device.

The electrode 500 ′ includes a first electrode 510 ′ and a second electrode 520 ′, and the first and second metal layers 310 ′ partially exposed through the second opening 410 ′. , 320') and may be respectively connected. In addition, each of the first conductivity type semiconductor layer 110 ′ and the second conductivity type semiconductor layer 130 ′ may be electrically connected to each other through the barrier metal layer 300 ′.

The first electrode 510 ′ and the second electrode 520 ′ may be, for example, an under bump metallurgy (UBM) layer. And, each may be provided as a single or a plurality. In the present embodiment, the first electrode 510 ′ and the second electrode 520 ′ are respectively provided as two, but the present embodiment is not limited thereto. The number and arrangement structure of the first and second electrodes 510 ′ and 520 ′ may be adjusted according to the second opening 410.

A groove in which a conductive adhesive, for example, Sn solder, is placed may be formed in the first and second electrodes 510 ′ and 520 ′.

Meanwhile, the second electrode 520 ′ may be provided in the second opening 410 ′ partially exposing the second metal layer 320 ′. Further, since the second opening 410 ′ does not overlap with the first opening 210 ′, the first insulating layer together with the second metal layer 320 ′ under the second electrode 520 ′ (200') may be located.

Accordingly, a double barrier structure in which the first insulating layer 200 ′ and the barrier metal layer 300 ′ are overlapped and disposed between the second electrode 520 ′ and the light emitting structure 100 ′ may be provided. .

This double barrier structure will be described with reference to FIG. 14. 14 is an enlarged cross-sectional view of portion D in FIG. 13.

As shown in FIG. 14, a barrier metal layer (specifically, a second metal layer 320 ′), which is a metal, in a region in which the Sn solder (S) and the second electrode 520 ′, that is, UBM is overlaid, and A first insulating layer 200 ′, which is an insulating dielectric, may be stacked and disposed. In addition, the double barrier structure composed of the second metal layer 320 ′ and the first insulating layer 200 ′ prevents Sn solder (S) from being diffused in a vertical direction toward the light emitting structure 100 ′ as shown in the arrow. Can be blocked. Specifically, diffusion to the second contact electrode 150 ′ including the reflective metal layer 151 ′ may be blocked.

15A to 20B are main step-by-step views schematically illustrating a method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention. In FIGS. 15A to 20B, the same reference numerals as those in FIGS. 12 to 14 denote the same members, and thus redundant descriptions will be omitted.

15A and 15B, FIG. 15A is a plan view of a light emitting structure formed on a substrate, and FIG. 15B is a cross-sectional view corresponding to a cut line C-C' of FIG. 15A. 16A to 20B below are also shown in the same manner.

First, an uneven structure 102 ′ may be formed on the substrate 101 ′. However, depending on the embodiment, the uneven structure 102 ′ may be omitted. As the substrate 101 ′, as described above, a substrate made of a material such _{as sapphire, Si, SiC, MgAl 2} O ₄ , MgO, LiAlO ₂ , LiGaO _{2, and GaN may be used.}

Next, using a process such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydrogen Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), etc., the substrate 101 A light emitting structure 100' having a stacked structure of a plurality of semiconductor layers by sequentially growing the first conductivity type semiconductor layer 110', the active layer 120', and the second conductivity type semiconductor layer 130'on'). ) To form. Here, the first conductivity type semiconductor layer 110 ′ and the second conductivity type semiconductor layer 130 ′ may be an n-type semiconductor layer and a p-type semiconductor layer, respectively. In the light emitting structure 100 ′, the positions of the first conductivity type semiconductor layer 110 ′ and the second conductivity type semiconductor layer 130 ′ may be interchanged, and the second conductivity type semiconductor layer 130 ′ is applied to the substrate 101. ') can be formed first.

16A and 16B, a second conductivity type semiconductor layer 130 ′, an active layer 120 ′, and a first conductivity type semiconductor layer 110 so that at least a portion of the first conductivity type semiconductor layer 110 ′ is exposed. ') can be etched. Accordingly, the etching region E and a plurality of mesa regions M partially partitioned by the etching region E may be formed.

In the etching process, after forming a mask layer in a region other than the region where the first conductivity type semiconductor layer 110 ′ is exposed, the mesa region M may be formed through a wet or dry method. Depending on the embodiment, an etching process may be performed so that only the top surface of the first conductivity type semiconductor layer 110 ′ is not etched.

Meanwhile, a passivation layer 200a ′ may be further formed on a side surface of the mesa region M exposed to the etching region E by the etching process. The passivation layer 200a ′ may be formed in a structure to cover a side surface of the mesa region M by partially including an upper surface edge of the mesa region M and a bottom surface of the etching region E. Accordingly, the active layer 120 ′ exposed to the etching region E may be covered so that it is not exposed to the outside by the passivation layer 200a ′. However, the passivation layer 200a' is selectively formed and may be omitted depending on the embodiment.

17A and 17B, a first contact electrode 140 ′ and a second contact electrode 150 ′ may be formed on the etch region E and the mesa region M, respectively. The first contact electrode 140 ′ extends along the etch region E and may connect to a first conductivity type semiconductor layer 110 ′ defining a bottom surface of the etch region E. In addition, the second contact electrode 150 ′ may be connected to the second conductivity type semiconductor layer 130 ′.

The first contact electrode 140 ′ may include a plurality of pad portions 141 ′ and a plurality of finger portions 142 ′ extending from the pad portion 141 ′. The second contact electrode 150 ′ may include a reflective metal layer 151 ′. In addition, a coating metal layer 152 ′ covering the reflective metal layer 151 ′ may be further included.

Referring to FIGS. 18A and 18B, a first insulating layer 200 ′ may be provided on the light-emitting structure 100 ′ in a structure that entirely covers the light-emitting structure 100 ′. For example, the first insulating layer 200 ′ may be formed of an epoxy-based insulating resin. In addition, the first insulating layer 200 ′ may include silicon oxide or silicon nitride, for example, SiO ₂ , SiN, SiO _x N _{y ,} TiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiN, AlN, ZrO ₂ , TiAlN, TiSiN, and the like.

In addition, the first contact electrode 140 ′ and the second contact electrode 150 ′ are formed on the first and second conductivity type semiconductor layers 110 ′ and 130 ′ through a plurality of first openings 210 ′. Can be partially exposed.

19A and 19B, a barrier metal layer 300 ′ may be formed on the first insulating layer 200 ′. In addition, the first and second contact electrodes 140 ′ and 150 ′ are connected to the exposed first and second contact electrodes 140 ′ and 150 ′ through the first opening 210 ′. Each of the semiconductor layers 130 ′ may be electrically connected.

The barrier metal layer 300 ′ may be provided in at least a pair for electrical insulation between the first conductivity type semiconductor layer 110 ′ and the second conductivity type semiconductor layer 130 ′. That is, the first metal layer 310 ′ is electrically connected to the first conductivity type semiconductor layer 110 ′ through the first contact electrode 140 ′, and the second metal layer 320 ′ is 2 It is electrically connected to the second conductivity type semiconductor layer 130 ′ through the contact electrode 150 ′, and the first and second metal layers 310 ′ and 320 ′ are separated from each other to be electrically insulated. have.

20A and 20B, a second insulating layer 400 ′ may be formed on the barrier metal layer 300 ′. In addition, the second insulating layer 400 ′ may partially expose the barrier metal layer 300 ′ through the second opening 410 ′.

A plurality of second openings 410 ′ may be provided to partially expose the first metal layer 310 ′ and the second metal layer 320 ′, respectively. In this case, some of the plurality of second openings 410 ′ may be disposed in a structure that does not overlap with some of the plurality of first openings 210 ′ of the first insulating layer 200 ′. For example, as shown in FIG., a second opening 410 ′ partially exposing the second metal layer 320 ′ among the plurality of second openings 410 ′ is the plurality of first openings Among 210 ′, the first opening 210 ′ partially exposing the second contact electrode 150 ′ may not overlap with each other. That is, the second opening 410 ′ is not positioned above the first opening 210 ′ in a vertical direction.

The second insulating layer 400 ′ may be made of the same material as the first insulating layer 200 ′.

Meanwhile, a first electrode 510 ′ and a second electrode 520 ′ are respectively included on the first and second metal layers 310 ′ and 320 ′ partially exposed through the second opening 410 ′. The electrode 500 ′ may be formed. The first electrode 510 ′ and the second electrode 520 ′ may be, for example, an under bump metallurgy (UBM) layer. The number and arrangement structure of the first electrodes 510 ′ and the second electrodes 520 ′ are not limited to the drawings and may be variously changed.

In addition, as shown in FIG. 20A, the second insulating layer 400 ′ is open to partially expose the first and second metal layers 310 ′ and 320 ′, similar to the second opening 410 ′. An area 430' may be further provided. The open area 430 ′ is for checking whether the manufactured semiconductor light emitting device is operated before being shipped as a product, and the first and second probe pins (not shown) are exposed to the open area 430 ′. The operation of the semiconductor light emitting device can be confirmed by supplying driving power by connecting to the metal layers 310 ′ and 320 ′.

21A and 21B are cross-sectional views schematically illustrating an example in which a semiconductor light emitting device according to an embodiment of the present invention is applied to a package, respectively.

Referring to FIG. 21A, the semiconductor light emitting device package 1000 may include a semiconductor light emitting device 1001 as a light source, a package body 1002, a pair of lead frames 1010, and an encapsulation portion 1005. Here, the semiconductor light emitting device 1001 may be the semiconductor light emitting device 10 of FIG. 1 or the semiconductor light emitting device 10 ′ of FIG. 12, and a description thereof will be omitted.

The semiconductor light emitting device 1001 may be mounted on the lead frame 1010 and electrically connected to the lead frame 1010 through a conductive adhesive material. As the conductive adhesive material, for example, Sn solder (S) may be used.

The pair of lead frames 1010 may include a first lead frame 1012 and a second lead frame 1014. Referring to FIG. 1, the first electrode 510 and the second electrode 520 of the semiconductor light emitting device 1001 are formed through Sn solder (S) interposed between the pair of lead frames 1010. It may be connected to the first lead frame 1012 and the second lead frame 1014, respectively.

The package body 1002 may be provided with a reflective cup to improve light reflection efficiency and light extraction efficiency, and an encapsulation portion 1005 made of a light-transmitting material may be formed in the reflective cup to encapsulate the semiconductor light emitting device 1001. I can.

Referring to FIG. 21B, the semiconductor light emitting device package 2000 may include a semiconductor light emitting device 2001, a mounting substrate 2010, and an encapsulation part 2005. Here, the semiconductor light emitting device 2001 may be the semiconductor light emitting device 10 of FIG. 1 or the semiconductor light emitting device 10 ′ of FIG. 12, and a description thereof will be omitted.

The semiconductor light emitting device 2001 may be mounted on the mounting substrate 2010 to be electrically connected to the first and second circuit patterns 2012 and 2014, respectively. And, it may be sealed by the sealing portion (2005). Through this, a chip on board (COB) type package structure can be implemented.

The mounting board 2010 may be provided as a board such as a PCB, MCPCB, MPCB, or FPCB, and the structure of the mounting board 2010 may be applied in various forms.

22 and 23 are cross-sectional views illustrating an example in which a semiconductor light emitting device according to an embodiment of the present invention is applied to a backlight unit.

Referring to FIG. 22, the backlight unit 3000 includes a light source 3001 mounted on a substrate 3002 and at least one optical sheet 3003 disposed thereon. As the light source 3001, a semiconductor light emitting device package having the structure described above with reference to FIGS. 21A and 21B or a structure similar thereto may be used, and the semiconductor light emitting device is directly mounted on the substrate 3002 (so-called COB type). You can also use it.

Unlike the light source 3001 in the backlight unit 3000 of FIG. 22 that emits light toward an upper portion on which the liquid crystal display is disposed, the backlight unit 4000 of another example shown in FIG. 23 is mounted on the substrate 4002. The light source 4001 emits light in a lateral direction, and the emitted light is incident on the light guide plate 4003 to be converted into a surface light source. Light passing through the light guide plate 4003 is emitted upward, and a reflective layer 4004 may be disposed on the lower surface of the light guide plate 4003 to improve light extraction efficiency.

24 and 25 are exploded perspective views showing an example in which a semiconductor light emitting device according to an embodiment of the present invention is applied to a lighting device.

Referring to FIG. 24, the lighting device 5000 is a bulb type lamp, and includes a light emitting module 5010, a driving unit 5020, and an external connection unit 5030. In addition, external structures such as external and internal housings 5040 and 5050 and a cover part 5060 may be additionally included.

The light emitting module 5010 includes a semiconductor light emitting device 5011 having the same or similar structure as the semiconductor light emitting devices 10 and 10 ′ of FIGS. 1 and 12 and a circuit board 5012 on which the semiconductor light emitting device 5011 is mounted. It may include. In the present embodiment, one semiconductor light emitting device 5011 is exemplified as being mounted on the circuit board 5012, but a plurality of semiconductor light emitting devices 5011 may be mounted if necessary. In addition, the semiconductor light emitting device 5011 is not directly mounted on the circuit board 5012, but may be mounted after being manufactured in a package form.

The outer housing 5040 may act as a heat dissipation unit, and includes a heat dissipation plate 5041 that directly contacts the light emitting module 5010 to improve a heat dissipation effect, and a heat dissipation fin 5042 surrounding a side surface of the outer housing 5040. I can. The cover part 5060 is mounted on the light emitting module 5010 and may have a convex lens shape. The driving unit 5020 may be mounted on the inner housing 5050 and connected to an external connection unit 5030 such as a socket structure to receive power from an external power source. In addition, the driving unit 5020 serves to convert and provide an appropriate current source capable of driving the semiconductor light emitting device 5011 of the light emitting module 5010. For example, the driving unit 5020 may be composed of an AC-DC converter or a rectifier circuit component.

In addition, although not shown in the drawings, the lighting device 5000 may further include a communication module.

Referring to FIG. 25, the lighting device 6000 is a bar-type lamp as an example, and may include a light emitting module 6010, a body part 6020, a cover part 6030, and a terminal part 6040. have.

The light emitting module 6010 may include a substrate 6012 and a plurality of semiconductor light emitting devices 6011 mounted on the substrate 6012. The semiconductor light emitting device 6011 may include the semiconductor light emitting devices 10 and 10 ′ of FIGS. 1 and 12 or the semiconductor light emitting device packages 1000 and 2000 of FIGS. 21A and 21B.

The body portion 6020 may be fixed by mounting the light emitting module 6010 on one surface of the light emitting module 6010 by the recess 6021, and the heat generated from the light emitting module 6010 may be discharged to the outside. Accordingly, the body part 6020 may include a heat sink as a type of support structure, and a plurality of heat dissipation fins 6022 for heat dissipation may protrude from both sides thereof.

The cover part 6030 is fastened to the locking groove 6023 of the body part 6020 and may have a semicircular curved surface so that light may be uniformly irradiated to the outside. On the bottom surface of the cover part 6030, a protrusion 6031 may be formed along the length direction to engage the locking groove 6023 of the body part 6020.

The terminal part 6040 may be provided on at least one side of the body part 6020 that is open at least one of both ends in the longitudinal direction to supply power to the light emitting module 6010, and may include an electrode pin 6041 protruding to the outside. have.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Therefore, various types of substitutions, modifications, and changes will be possible by those of ordinary skill in the art within the scope not departing from the technical spirit of the present invention described in the claims, and this also belongs to the scope of the present invention. something to do.

10, 10'... semiconductor light emitting device
101... board
200... first insulating layer
300... barrier metal layer
400... second insulating layer
500...electrodes

Claims (20)

A light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer;
A first insulating layer provided on the light emitting structure and having a first opening disposed on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer;
A barrier metal layer provided on the first insulating layer and electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, through the first openings;
A second insulating layer provided on the barrier metal layer and having a second opening partially exposing the barrier metal layer; And
First and second first and second conductive semiconductor layers provided on the barrier metal layer partially exposed through the second opening and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively, through the barrier metal layer. Including an electrode,
A semiconductor light emitting device, wherein at least one of the first and second insulating layers and the barrier metal layer are disposed between the first and second electrodes and the light emitting structure.
The method of claim 1,
The second insulating layer covers a part of an upper surface of the barrier metal layer disposed in the first opening.
The method of claim 1,
The semiconductor light emitting device, wherein the first opening and the second opening are arranged in a structure that does not overlap each other.
The method of claim 1,
The light-emitting structure includes an etched region in which a portion of the second conductivity type semiconductor layer, the active layer, and the first conductivity type semiconductor layer is etched, and a plurality of mesa regions partially partitioned by the etching region. A semiconductor light emitting device made of.
The method of claim 4,
The etching region extends from one side of the light emitting structure toward the other side opposite to the light emitting structure, and a plurality of the etching regions are provided in parallel with each other.
The method of claim 4,
Further comprising a first contact electrode disposed on an upper surface of the first conductivity type semiconductor layer exposed to the etching region and connected to the first conductivity type semiconductor layer,
The first contact electrode is a semiconductor light emitting device, characterized in that connected to the first electrode through the barrier metal layer.
The method of claim 6,
The first contact electrode includes a plurality of pad portions and a plurality of finger portions extending from the plurality of pad portions along the etching region, respectively.
The method of claim 7,
The plurality of pad portions are exposed through the first opening and are directly connected to the barrier metal layer.
The method of claim 7,
Further comprising a second contact electrode disposed on the upper surface of the plurality of mesa regions and connected to the second conductivity type semiconductor layer,
The second contact electrode is a semiconductor light emitting device, characterized in that connected to the second electrode through the barrier metal layer.
The method of claim 9,
A semiconductor light emitting device, wherein the second contact electrode includes a reflective metal layer.
The method of claim 10,
A semiconductor light emitting device further comprising a coating metal layer covering the reflective metal layer.
The method of claim 4,
The semiconductor light emitting device further comprising a passivation layer provided on a side surface of the mesa region to cover the active layer exposed to the etching region.
The method of claim 1,
A semiconductor light emitting device, characterized in that the first and second electrodes are provided in single or plural, respectively.
An etching region having a stacked structure of a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, wherein the second conductivity type semiconductor layer, the active layer, and a portion of the first conductivity type semiconductor layer are etched, and the etching A light emitting structure including a mesa region partially partitioned by the region;
A first insulating layer provided on the light emitting structure;
A barrier metal layer provided on the first insulating layer and electrically connected to the first conductive type semiconductor layer and the second conductive type semiconductor layer, respectively, through the first insulating layer;
A second insulating layer provided on the barrier metal layer; And
The first and second first and second conductive semiconductor layers are provided on portions of the barrier metal layer exposed from the second insulating layer and electrically connected to the first and second conductive semiconductor layers through the barrier metal layer. Including an electrode,
A semiconductor light emitting device, wherein the first insulating layer and the barrier metal layer or the barrier metal layer and the second insulating layer are disposed between the first and second electrodes and the light emitting structure.
The method of claim 14,
The first insulating layer has a first opening partially exposing each of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and the second insulating layer partially exposes the barrier metal layer. It has 2 openings,
The semiconductor light emitting device, wherein the first opening and the second opening are arranged in a structure that does not overlap each other.
The method of claim 15,
Further comprising a first contact electrode provided on the first conductivity type semiconductor layer defining a bottom surface of the etching region, and a second contact electrode provided on an upper surface of the mesa region,
The first contact electrode and the second contact electrode are connected to the barrier metal layer through the first opening.
The method of claim 16,
The first contact electrode includes a plurality of pad portions and a plurality of finger portions extending along the etching region from the plurality of pad portions, respectively,
The plurality of pad portions are exposed through the first opening and are directly connected to the barrier metal layer.
A package body having a lead frame; And
A semiconductor light emitting device comprising the semiconductor light emitting device according to any one of claims 1 to 17 disposed on the package body and connected to the lead frame.
The method of claim 18,
Wherein the semiconductor light emitting device is connected to the lead frame through solder interposed between the first and second electrodes and the lead frame.
The method of claim 18,
And an encapsulation part provided on the package body to cover the semiconductor light-emitting device, wherein the encapsulation part contains a wavelength converting material for converting a wavelength of light generated from the semiconductor light-emitting device.

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