JP2827795B2 - Semiconductor light emitting device and method of manufacturing the same - Google Patents

Abstract

PURPOSE:To prevent solder from attaching by moving a p-n junction part exposed in a mesa etching side surface of a GaP light emitting diode. CONSTITUTION:A wafer is prepared by forming an n-type first semiconductor region 11 and a p-type second semiconductor region 12 on an n-type semiconductor substrate 10 by an epitaxial growth method. A groove is formed along a division predetermined region of a surface at the side of the second semiconductor region 12 of the wafer. Then, p-type impurities are diffused to include the groove. After an anode electrode 18 and a cathode electrode 19 are formed, a light emitting diode is acquired by cutting by the groove. It is then adhered to a metal substrate 20 by solder 21 with the anode electrode 18 down.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor light emitting device such as a GaP light emitting diode and a method for manufacturing the same.

[0002]

2. Description of the Related Art A conventional green light emitting diode chip is shown in FIG.
As shown in FIG. 2, an n-type gallium phosphide (GaP) substrate (substrate) 1, an n-type GaP region 2 and a p-type GaP region 3 sequentially stacked thereon by a known liquid phase epitaxial method, It consists of electrodes 4 and 5. GaP
Has a band gap (forbidden band width) Eg of 2.24 eV and an emission wavelength λ of about 555 nm. However, since it is an indirect transition type, the emission efficiency is not so high. Therefore, generally, in addition to impurities (n-type tellurium and p-type zinc) that determine the conductivity type of the semiconductor region above the n-type GaP region 2, that is, in the vicinity of the pn junction 6 and the p-type GaP region 3. Doping with nitrogen (N) to be an isoelectronic trap. As a result, the emission wavelength is slightly larger (about 5
65 nm), but the luminous efficiency can be increased.

[0003]

By the way, this kind of G
In the aP light-emitting diode chip, it may be desired to mount the n-type substrate 1 side, that is, the region side where the cathode electrode is provided, as an upper surface because of the relationship with another circuit element. For this purpose, as shown in FIG. 2, when the anode electrode 6 provided on the p-type GaP region 3 is connected to the metal mounting base 7 by solder 8, the p-type GaP region 3 is thin, so that the solder 8 6, and the pn junction 6 may be short-circuited. Therefore, it is conceivable to form the p-type GaP region 3 thick as shown in FIG. However, this p-type GaP region 3
Is doped with nitrogen (N) in addition to zinc (Zn) as a conductivity type determining impurity, the pn junction 6 of the p-type region 3
The portion away from the pn junction 6 acts as a region (absorption edge) for absorbing light generated based on the recombination of carriers near the pn junction 6, and lowers luminous efficiency. As a means for solving this, it is conceivable that nitrogen is not doped into a portion of the p-type GaP region 3 remote from the pn junction. However, in this case, a lattice defect occurs in the region not doped with nitrogen, and as a result, the luminous efficiency is reduced. Can not be obtained very large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor light emitting device capable of keeping an exposed portion of a pn junction away from a mounting surface of a semiconductor chip and a method of manufacturing the same.

[0005]

According to the present invention, there is provided a first conductive type compound semiconductor comprising a first conductive type compound semiconductor.
A second semiconductor region comprising a second conductivity type compound semiconductor region having a thickness smaller than that of the first semiconductor region and disposed adjacent to the first semiconductor region; A third semiconductor region made of a second conductivity type compound semiconductor formed so as to cover the periphery of a pn junction between the first semiconductor region and the second semiconductor region;
An exposed portion of a pn junction between the third semiconductor region and the first semiconductor region is located on a side surface of a semiconductor chip including the first, second, and third semiconductor regions, and The distance between the exposed portion of the pn junction and the surface of the second semiconductor region is larger than the distance between the pn junction between the first and second semiconductor regions and the surface of the second semiconductor region. And a semiconductor light emitting device. Note that the first semiconductor region of the present invention corresponds to the first semiconductor region 11 of the embodiment or a combination of the first semiconductor region 11 and the substrate 10. The invention of a method for achieving the above object is to provide a first semiconductor region made of GaP of a first conductivity type and a second semiconductor region made of GaP of a second conductivity type on a GaP semiconductor substrate of a first conductivity type. Semiconductor regions are sequentially formed, and at least the second semiconductor region is doped with nitrogen, and the second semiconductor region has a total thickness of the semiconductor substrate and the first semiconductor region. Preparing a wafer that is formed thinner than that, and etching the wafer deeper than the pn junction between the first semiconductor region and the second semiconductor region from the second semiconductor region side of the wafer. Forming a groove in a region to be divided, and diffusing impurities of a second conductivity type into a region of the wafer where the groove is formed to form a third semiconductor region of the second conductivity type; ,
Cutting the wafer with the groove.

[0006]

The third semiconductor region in the present invention is p
It functions to keep the exposed portion of the n-junction away from the second semiconductor region. As a result, when the second semiconductor region side is fixed to the mounting base with a conductive adhesive such as solder, the conductive adhesive hardly adheres to the pn junction. If a groove is formed according to the method invention and a third semiconductor region is provided here, p
The movement of the exposed portion of the n-junction can be easily achieved.

[0007]

Next, a green GaP light emitting device, that is, a green light emitting diode (LED) according to an embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS.

First, as shown in FIG. 4, an n-type GaP (gallium-phosphorus) semiconductor substrate (hereinafter referred to as an n-type substrate) 1
A semiconductor in which a first semiconductor region 11 made of an n-type GaP semiconductor region is formed on the substrate 0 by a liquid phase epitaxial growth method, and a second semiconductor region 12 made of a p-type GaP semiconductor region is formed on the first semiconductor region 11 by an epitaxial growth method Wafer 13
Prepare The first semiconductor region 11 forming the pn junction 14 is doped with nitrogen in addition to Te (tellurium) as a conductivity type determining impurity, and the second semiconductor region 12 is doped with Zn ( In addition to zinc), nitrogen is doped. The first and second semiconductor regions 1
The thicknesses of 1 and 12 are much smaller than the thickness of the substrate 10.

Next, as shown in FIG. 5, a mesa-shaped etching groove 15 having a depth of about 80 μm is selectively etched from the surface of the wafer 13 on the side of the p-type second semiconductor region 12.
To form The groove 15 is provided so that the wafer 13 coincides with a boundary region (divided region) between the plurality of diode chip regions 13a, 13b, and 13c. Therefore, each of the diode chip regions 13a, 13b, 13c is an island region separated by the groove 15. The depth of the groove 15 is formed so as to be deeper than the second semiconductor region 12 and to reach the vicinity of the substrate 10. That is, the groove 15 is formed so as to cross the pn junction 14, and each diode chip region 1
3a, 13b and 13c are formed as deep as possible in a range where the connection can be maintained. The etching was performed in two stages in order to limit the width of the groove 15 from being increased by the lateral etching.

Next, the wafer 13 having the groove 15 formed therein is placed in a diffusion furnace, and Zn ₃ P ₂ is added at 0.1 to 0.45 mg / cc, P ₂
Is introduced in a smaller amount than Zn ₃ P ₂ ,
By performing a diffusion process for 10 to 100 hours, a third semiconductor region 16 made of a p + -type GaP semiconductor region shown in FIG. 6 is formed. By any amount introduce P ₂ in addition to Zn ₃ P ₂ in the diffusion step, the phosphorus from the wafer 13 (P)
Out-diffusion is suppressed. The third semiconductor region 16 is formed so as to cover the pn junction of the first and second semiconductor regions 11 and 12 exposed in the groove 15 in FIG. 5, and the third semiconductor region 16 and the first semiconductor region 1
A new pn junction 17 is formed between the substrate 1 and the substrate 10. When Zn is diffused without masking the main surface of the wafer 13 on the substrate 10 side, Zn is also diffused into the substrate 10. At this time, the inversion layer is removed by polishing or etching.

Next, as shown in FIG. 7, an anode electrode 18 is formed on the third semiconductor region 16 on one main surface of the wafer 13, and a cathode electrode 19 is formed on the substrate 10 on the other main surface by a known vacuum deposition. After the formation by the method, the wafer 13 is cut along the line L indicated by the groove 15 to obtain individual light emitting diode chips.

The light emitting diode chip thus formed is fixed to a conductive mounting base 20 made of a metal base or a substrate or a layer with a solder (conductive adhesive) 21 as shown in FIG. That is, the anode electrode 18 is fixed to the mounting base 20. When the anode electrode 18 is on the lower side, the light emitting element is arranged in an inverted mesa arrangement, and the solder 21 adheres to the inclined side surface 22 based on the groove 15 of the mesa etching. However, since the p-type third semiconductor region 16 is provided, the pn junction 14 between the first and second semiconductor regions 11 and 12 is
Junction 1 based on third semiconductor region 16 without being exposed to
7 is located higher than the pn junction 14 with respect to the mounting base 20, and the solder 2
Even if 1 rises, a short circuit of the pn junction does not occur.

Since the thickness of the p-type second semiconductor region 12 of the light emitting device of this embodiment is smaller than that of the structure of FIG. 3, the light emission efficiency does not decrease due to the absorption edge effect generated in the structure of FIG. . Therefore, relatively large luminance can be obtained despite the configuration in which the anode electrode 18 is on the lower side. Further, the chips divided by the line L in FIG. 7 are not limited to the inverted mesa arrangement in FIG. 8, but may be arranged with the anode electrode 18 on the upper side. That is, since the exposed portion of the pn junction 16 is located substantially at the center of the side surface of the chip, it does not matter which of the anode electrode 18 and the cathode electrode 19 is on the lower side.

[0014]

Next, a light emitting device according to another embodiment will be described with reference to FIG. However, in FIG. 9, portions common to FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted.
In this embodiment, a cathode electrode 19 is formed annularly along the periphery of the surface of the n-type substrate 10.
The substrate 10 is exposed inside the window, and a window region 10a is formed. One corner of the cathode electrode 19 is a wide lead connection region.

On the other hand, the anode electrode 18 is in contact with the center of the second semiconductor region 12 so as to fit into the window region 10a when viewed from above the chip. FIG.
In the light emitting diode of No. 3, the third semiconductor region 16 is formed in a portion corresponding to the inclined side surface 22 by selective diffusion, and is not formed on the lower surface side of the second semiconductor region 12. An insulating film 23 is formed on the inclined side surface 22 and the lower surface of the second semiconductor region 12. As shown in FIG. 11, an opening 23a is formed in the insulating film 23 at a portion corresponding to the central region on the lower surface of the second semiconductor region 12. The anode electrode 18 is connected to the opening 23a of the insulating film 23.
And is also formed on the insulating film 23. Since the anode electrode 18 is formed in a large area on the lower surface side of the chip, the mounting substrate 2
The fixation by the solder 21 to 0 becomes strong.

In the light emitting diode of FIG. 9, the third semiconductor region 16 is separated from the anode electrode 18 to prevent a channel current from flowing. Further, in the light emitting diode of FIG. 9, as can be seen from the current path indicated by the dotted line in the figure, a forward current flows over a wide area of the pn junction 14, and carrier recombination contributing to light emission can be generated abundantly. In particular, since the current flows intensively on the center side of the pn junction 14, the amount of light emission due to carrier recombination is large. In the light emitting diode of FIG.
Since the window region 10a is formed above the center side region of 4, the light can be effectively extracted outside the chip.

The differences between the light emitting diode of FIG. 8 and the light emitting diode of FIG. 9 will be described in further detail below. In the light emitting diode shown in FIG. 8, the anode 18 and the cathode 1
When a voltage for increasing the potential of the anode electrode 18 is applied between the anode electrode 9 and the anode electrode 9, a forward current flows from the anode electrode 18 to the cathode electrode 19. This forward current mainly flows through the first semiconductor region 12 passing through the second semiconductor region 12 via the pn junction.
And a second current passing through the third semiconductor region via the pn junction 17. Here, the second current is a leak current that causes a problem in voltage-current characteristics of the light emitting diode, and carrier recombination generated based on the second current is the first current.
Does not contribute to light emission as compared with the carrier recombination generated based on the electric current. Therefore, it is desirable that the second current does not flow as much as possible. According to the light emitting diode of FIG. 9, the second current is prevented. Of course, the light emitting diode of FIG.
As in the case of the light emitting diode of FIG. 8, the adhesion of the solder 21 to the pn junction can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a conventional light emitting device.

FIG. 2 is a cross-sectional view showing a state in which a conventional light emitting device has an anode attached to a lower side.

FIG. 3 is a cross-sectional view showing a conventional light emitting device having a thick p-type region.

FIG. 4 is a cross-sectional view illustrating a wafer for manufacturing a green GaP light emitting device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a state where a groove is formed in a wafer.

FIG. 6 is a sectional view showing a wafer on which a third semiconductor region is formed.

FIG. 7 is a sectional view showing a wafer on which electrodes are formed.

FIG. 8 is a cross-sectional view showing a state where the light emitting device according to the example is connected to the mounting base with the anode electrode facing down.

FIG. 9 is a central longitudinal sectional view of a light emitting diode of another embodiment.

FIG. 10 is a plan view of the light emitting diode of FIG. 9;

FIG. 11 is a bottom view showing a state in which an anode electrode of the light emitting diode of FIG. 9 is removed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 1st semiconductor region 12 2nd semiconductor region 16 3rd semiconductor region 21 Solder

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 33/00 H01L 21/301 H01L 21/52

Claims (2)

(57) [Claims] A first semiconductor region made of a compound semiconductor of a first conductivity type; and a first semiconductor region having a thickness smaller than that of the first semiconductor region.
A second semiconductor region composed of a compound semiconductor region of the second conductivity type, which is disposed adjacent to the first semiconductor region, and a periphery of a pn junction between the first semiconductor region and the second semiconductor region. A third semiconductor region made of a second conductivity type compound semiconductor formed in the semiconductor device, and a pn between the third semiconductor region and the first semiconductor region.
An exposed portion of the junction is located on a side surface of the semiconductor chip including the first, second and third semiconductor regions, and a distance between the exposed portion of the pn junction and a surface of the second semiconductor region. Is larger than a distance between a pn junction between the first and second semiconductor regions and a surface of the second semiconductor region. 2. A first semiconductor region made of GaP of a first conductivity type and a second semiconductor region made of GaP of a second conductivity type are sequentially formed on a GaP semiconductor substrate of a first conductivity type. And at least the second semiconductor region is doped with nitrogen, and the second semiconductor region is formed thinner than the total thickness of the semiconductor substrate and the first semiconductor region. Preparing a wafer; forming a groove in a region to be divided by etching deeper than a pn junction between the first semiconductor region and the second semiconductor region from the side of the second semiconductor region of the wafer; Forming a second conductive type third semiconductor region by diffusing a second conductive type impurity into a region of the wafer where the groove is formed; Cutting step A method for manufacturing a P semiconductor light emitting device.