JP2000277463A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor device or a chip-size package lessened in size to be improved in moisture resistance by a method wherein a groove is provided around a semiconductor chip and filled up with resin. SOLUTION: A base region 13 and an emitter region 14 are formed to form a semiconductor device. An annular groove 20 is formed around the active part of the device. A semiconductor chip 10 is sealed up with resin 21, filling the groove 20 with resin. As a moisture penetration path is elongated, the semiconductor device is improved in moisture resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having excellent moisture resistance.

[0002]

2. Description of the Related Art In the field of semiconductor devices, the demand for lighter, thinner and smaller devices is remarkable, and the thickness of a resin coating the periphery of a semiconductor chip tends to be reduced. FIG. 5 shows an example of a conventional semiconductor device.

Referring to FIG. 4, in this semiconductor device, a semiconductor chip 1 is fixed on an island 2 of a lead frame, and an electrode pad formed on the surface of the semiconductor chip 1 and a lead 3 are wire-bonded with a wire 4. The periphery of the semiconductor chip 1 is molded with a resin 5 so that the back surface of the island 2 is exposed. Exposing the back surface side of the island 2 means improving the heat dissipation of the semiconductor chip 1 and reducing the height (thickness) of the entire device.

[0004] Furthermore, in recent years, as a final form of light and thin,
Wafer-scale CSP capable of reducing external dimensions to dimensions that are equivalent to or approximate to the semiconductor chip size
(Chip size package) is starting to attract attention.

[0005] Referring to FIG. 5A, a semiconductor wafer 6 is subjected to various pretreatments such as diffusion to form a large number of semiconductor chips 1, and as shown in FIG. 6 is covered with a resin layer 7, electrodes 8 for external connection are led out to the surface of the resin layer 3, and then the semiconductor chip 1 is divided along a dicing line of the semiconductor wafer 6.
This is a completed product as shown in FIG. The resin layer 7 only covers the front surface of the semiconductor chip 1 (which may cover the back surface), and the silicon substrate is exposed on the side wall of the semiconductor chip 1. To mount the semiconductor device, the electrode 8 is bonded to the conductive pattern formed on the mounting board so as to face the conductive pattern (for example, see Japanese Patent Application Laid-Open No. 9-64).
No. 049).

Such a semiconductor device has an advantage that the package size of the device is equal to the chip size of the semiconductor chip, and the device can be bonded to the mounting substrate by opposing bonding, so that the area occupied by the mounting can be greatly reduced. Further, there is an advantage that the cost associated with the post-process can be significantly reduced.

[0007]

However, as a result of the reduced external dimensions, the distance between the interface between the lead frame and the resin layer 5 along the path indicated by reference numerals 9 and 10 in FIG. There is a disadvantage that moisture easily reaches the active portion on the surface of the semiconductor chip 1. The chip surface is the most important point for the element, and when moisture reaches the chip surface, the transistor characteristics are significantly deteriorated, such as an increase in leak current, and the reliability of the semiconductor chip 1 is significantly reduced. Such deterioration of the moisture resistance inevitably occurs not only in a device having an external shape in which the back surface side of the island is exposed, but also in an external shape pursuing miniaturization.

Further, the wafer scale CSP shown in FIG.
In this case, since the interface between the semiconductor substrate and the resin layer 7 is exposed on the side of the package, the path to the active portion is further shortened, and the moisture resistance is further deteriorated.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has a structure in which a diffusion region for forming at least one PN junction is formed on a surface of a semiconductor chip. A groove surrounding the periphery of the diffusion region is formed along a peripheral portion, and the semiconductor chip is resin-sealed so as to bury the inside of the groove.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below.
This will be described in detail using an NPN transistor as an example.

FIG. 1 is a sectional view (A) and a plan view (B) showing a peripheral portion of a chip of a semiconductor device according to the present invention. The semiconductor chip 10 has a rectangular shape as a whole, has an N + type high concentration layer 11 on the back surface side, and has an N type low concentration layer 12 serving as a substantial collector formed on the front side. N
A material in which an N + layer is diffused on both sides of a mold semiconductor substrate and the wafer is polished, or a material in which an N-type epitaxial layer is formed on an N + substrate is used.

As a pre-process, a P-type impurity such as boron is selectively diffused into the surface of the low concentration layer 12 to selectively diffuse the base region 1.
3 and a guard ring region 14, and an N-type impurity such as phosphorus is selectively diffused on the surface of the base region 13 to form an emitter region 15 and an N + annular ring region 16. Reference numeral 17 denotes a silicon oxide film. A contact hole exposing each diffusion region is formed in the oxide film 17, and an ohmic contact is made between the aluminum electrode 18 via the contact hole. The aluminum electrode 18 further forms base and emitter electrode pads on the oxide film 17.
In this transistor, the region including the base region 13 and the vicinity of the guard ring region 14 is an operationally active region, and the annular ring region 16 is arranged so as to surround this region.

A groove 20 having a bottom is formed in a region further surrounding the annular ring region 16 along the peripheral end of the semiconductor chip 10. The groove 20 is a trench groove formed by anisotropically dry-etching the silicon surface, or a cut groove formed by half-dicing the wafer after diffusion and electrode wiring processing in a lattice shape using a dicing blade. . The line width of the groove 20 is about 10 to 50 μm when formed by etching, and 50 μm to 300 μm depending on the thickness of the blade when formed by a dicing blade.

The periphery of the semiconductor chip 10 is covered with an epoxy resin 21. In the type using a lead frame, the semiconductor chip 10 is fixed to the island surface, so that the top and side surfaces of the chip are covered with the resin 21, and only the top surface of the chip is covered with the resin 21 in the CSP type. In either case, the resin 21 buries the inside of the groove 20.

FIG. 2 shows an apparatus of a type using a lead frame. The semiconductor chip 10 is fixed on the island 22 of the lead frame, and the electrode pad formed on the surface of the semiconductor chip 10 and the lead 23 are wire-bonded with the wire 24 so that the back surface of the island 22 is exposed. The periphery is molded with resin 21. In this apparatus, the lead frame metal surface and resin 2
Water enters from the interface with the semiconductor chip 1 and rises along the side wall of the semiconductor chip 10 to form a path that reaches the active portion. In addition, it hardly penetrates through the water resin 21 itself, and it is considered that most of the water penetrates along the interface between the resin 21 and another material.

Thus, the apparatus of the present invention described above
Since the bottomed groove 20 is formed in the peripheral portion of the semiconductor chip 10, the entered water enters through the inner wall of the groove 20, and the path 31 (see FIG. 1) can be lengthened. A semiconductor device having more excellent moisture resistance can be obtained.

FIG. 3 shows an example in which the present invention is applied to a wafer level CSP device. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. A groove 20 is formed in a peripheral portion of the semiconductor chip 10, only the surface of the semiconductor chip 10 is covered with the resin 21, and the resin 21 buries the inside of the groove 20. Reference numeral 30 denotes an electrode for leading each of the emitter, the collector, and the base. In the same manner as in the previous example, the path 31 is extended by an amount that enters along the inner wall of the groove 20.
Is increased, so that the moisture resistance can be greatly improved.

Although the semiconductor element has been described by taking a bipolar transistor as an example, it goes without saying that the present invention may be applied to an integrated circuit chip such as a BIP type or a MOS type in addition to a discrete type.

[0019]

As described above, according to the present invention, the groove 20 is provided around the semiconductor chip 10 so that the resin 2
Since it is buried with 1, the length of the path 31 has the advantage that the moisture resistance of the semiconductor device can be greatly improved.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view for explaining the present invention, and FIG.
It is a top view.

FIGS. 2A and 2B are cross-sectional views for explaining the present invention; FIGS.
It is a top view.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a diagram for explaining a conventional example.

FIG. 5 is a diagram for explaining a conventional example.

Claims (3)

[Claims] 1. A diffusion region forming at least one PN junction is formed on a surface of a semiconductor chip, a groove surrounding the periphery of the diffusion region is formed along a peripheral portion of the semiconductor chip, and the inside of the groove is buried. Wherein the semiconductor chip is sealed with a resin. 2. The semiconductor device according to claim 1, wherein said groove is formed by dicing. 3. The semiconductor device according to claim 1, wherein said groove is formed by etching.