JP2007073987A - Semiconductor module - Google Patents
Semiconductor module Download PDFInfo
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- JP2007073987A JP2007073987A JP2006311131A JP2006311131A JP2007073987A JP 2007073987 A JP2007073987 A JP 2007073987A JP 2006311131 A JP2006311131 A JP 2006311131A JP 2006311131 A JP2006311131 A JP 2006311131A JP 2007073987 A JP2007073987 A JP 2007073987A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
本発明は半導体装置に関し、特に半導体チップ裏面側を取り出し電極の１つとする２又は３端子素子における、小型化したパッケージに関する。 The present invention relates to a semiconductor device, and more particularly to a miniaturized package in a two- or three-terminal element having a semiconductor chip back surface as one of extraction electrodes.
従来の半導体装置の組立工程においては、ウェハからダイシングして分離した半導体チップをリードフレームに固着し、金型と樹脂注入によるトランスファーモールドによってリードフレーム上に固着された半導体チップを封止し、封止された半導体チップを個々の半導体装置毎に分離するという工程が行われている。リード端子が樹脂の外側に突出すること、トランスファーモールド金型の精度の問題などにより、外形寸法の縮小化には限界が見えていた。 In the assembly process of a conventional semiconductor device, a semiconductor chip diced and separated from a wafer is fixed to a lead frame, and the semiconductor chip fixed on the lead frame is sealed by a mold and transfer molding by resin injection, and sealed. A process of separating the stopped semiconductor chip for each semiconductor device is performed. Due to the fact that the lead terminal protrudes to the outside of the resin and the problem of the accuracy of the transfer mold, there has been a limit in reducing the outer dimensions.
近年、外形寸法を半導体チップサイズと同等あるいは近似した寸法にまで縮小する事が可能な、ウェハスケールＣＳＰ（チップサイズパッケージ）が注目され始めている。これは、図４（Ａ）を参照して、半導体ウェハ１に各種拡散などの前処理を施して多数の半導体チップ２を形成し、図４（Ｂ）に示すように半導体ウェハ１の上部を樹脂層３で被覆すると共に樹脂層３表面に外部接続用の電極４を導出し、その後半導体ウェハ１のダイシングラインに沿って半導体チップ１を分割して、図４（Ｃ）に示したような完成品としたものである。 In recent years, a wafer scale CSP (chip size package) that can reduce the outer dimensions to a size that is the same as or close to the size of a semiconductor chip has begun to attract attention. 4A, the semiconductor wafer 1 is subjected to various pretreatments such as diffusion to form a large number of semiconductor chips 2, and the upper portion of the semiconductor wafer 1 is formed as shown in FIG. As shown in FIG. 4C, the semiconductor layer 1 is coated with the resin layer 3 and an external connection electrode 4 is led out on the surface of the resin layer 3 and then the semiconductor chip 1 is divided along the dicing line of the semiconductor wafer 1. It is a finished product.
樹脂層３は半導体チップ１の表面（裏面を被覆する場合もある）を被覆するだけであり、半導体チップ１の側壁にはシリコン基板が露出する。電極４は樹脂層３下部に形成された集積回路網と電気的に接続されており、実装基板上に形成した導電パターンに対して電極４を対向接着することによりこの半導体装置の実装が実現する。 The resin layer 3 only covers the front surface (which may cover the back surface) of the semiconductor chip 1, and the silicon substrate is exposed on the side wall of the semiconductor chip 1. The electrode 4 is electrically connected to an integrated circuit network formed under the resin layer 3, and mounting of the semiconductor device is realized by adhering the electrode 4 to a conductive pattern formed on the mounting substrate. .
斯かる半導体装置は、装置のパッケージサイズが半導体チップのチップサイズと同等であり、実装基板に対しても対向接着で済むので、実装占有面積を大幅に減らすことが出来る利点を有する。また、後工程に拘わるコストを大幅に減じることが出来る利点を有するものである（例えば、特開平９-６４０４９号）。
しかしながら、基板をコレクタとするバイポーラ型トランジスタや、基板を共通ドレインとするパワーＭＯＳＦＥＴ装置等の３端子型の半導体素子や、基板をアノード又はカソードの一方とする２端子素子等の、半導体基板の裏面側を取り出し電極の一つとして動作電流を半導体チップの厚み方に流す素子では、前記コレクタやドレイン等を半導体チップの表面側に導出する手段がなく、この為にウェハスケールでのＣＳＰ装置を実現することが困難である欠点があった。 However, the back surface of a semiconductor substrate such as a bipolar transistor having a substrate as a collector, a three-terminal semiconductor element such as a power MOSFET device having a substrate as a common drain, or a two-terminal element having a substrate as one of an anode and a cathode. In an element in which the side is taken out as one of the electrodes and an operating current flows in the direction of the thickness of the semiconductor chip, there is no means for deriving the collector, drain, etc. to the surface side of the semiconductor chip. There were drawbacks that were difficult to do.
他の手法として、半導体チップをプリント基板上に直接実装するベアボンド実装も行われてはいるが、上記の問題は同様であるし、更にはベアチップであることの取り扱いの難しさが加わるという欠点があった。 As another method, bare bond mounting in which a semiconductor chip is directly mounted on a printed circuit board is also performed, but the above-mentioned problem is the same, and further, there is a drawback that handling difficulty of being a bare chip is added. there were.
本発明は上述した従来の欠点に鑑みて成されたものであり、
表面に２種類の電気的接続手段を有し、裏面に１種類の電気的接続手段を有した半導体チップと、
前記半導体チップの裏面が電気的に固着された搭載部と、
前記搭載部の周囲から上方に延在した延在部と、を備え、
前記半導体チップの裏面の電気的接続手段は、前記延在部に電気的に導出されており、
前記半導体チップの表面の電気的接続手段と前記延在部とが実装基板に電気的に対向接着されていることを特徴とする。
The present invention has been made in view of the above-mentioned conventional drawbacks,
A semiconductor chip having two types of electrical connection means on the front surface and one type of electrical connection means on the back surface;
A mounting portion on which the back surface of the semiconductor chip is electrically fixed;
An extending portion extending upward from the periphery of the mounting portion, and
The electrical connection means on the back surface of the semiconductor chip is electrically led to the extending portion,
The electrical connection means on the surface of the semiconductor chip and the extended portion are electrically opposed and bonded to the mounting substrate.
以上に説明したように、本発明によれば、実装面積がチップサイズに極めて近似する半導体装置得られる利点を有する。しかも、基板１６と第２の外部接続端子１７により半導体チップ１１の裏面側電極を低抵抗で導出できる利点を有するものである。更に、樹脂封止を廃止すれば、故障時の発煙・発火を防止できる利点を有するものである。 As described above, according to the present invention, there is an advantage that a semiconductor device whose mounting area is very close to the chip size can be obtained. In addition, the substrate 16 and the second external connection terminal 17 have the advantage that the back side electrode of the semiconductor chip 11 can be derived with low resistance. Furthermore, if the resin sealing is abolished, there is an advantage that it is possible to prevent smoke and ignition at the time of failure.
以下に本発明の実施の形態を、ＮＰＮトランジスタを例にして詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail by taking an NPN transistor as an example.
図１は、本発明の半導体装置を示す（Ａ）平面図、（Ｂ）断面図、（Ｃ）斜視図である。これらの図に於いて、１１はＮＰＮトランジスタを形成した半導体チップを示す。この半導体チップ１１は、裏面側にＮ＋型高濃度層を有し、表面側にＮ型の低濃度層を形成したもので、Ｎ型半導体基板の両面にＮ＋層を拡散した後にウェハを研磨した素材か、あるいはＮ＋基板の上にＮ型のエピタキシャル層を形成したものを用いる。そして、前記Ｎ型の低濃度層の表面に選択的にボロン等のＰ型不純物を選択拡散してベース領域を形成し、さらにベース領域表面にリン等のＮ型不純物を選択拡散してエミッタ領域等を形成したものである。前記Ｎ＋高濃度層／Ｎ型低濃度層がコレクタとなる。 1A is a plan view, FIG. 1B is a sectional view, and FIG. 1C is a perspective view showing a semiconductor device of the present invention. In these drawings, reference numeral 11 denotes a semiconductor chip on which an NPN transistor is formed. This semiconductor chip 11 has an N + type high concentration layer on the back surface side and an N type low concentration layer formed on the front surface side. After the N + layer is diffused on both sides of the N type semiconductor substrate, the wafer is polished. A material or an N + substrate formed with an N-type epitaxial layer is used. A base region is formed by selectively diffusing P-type impurities such as boron on the surface of the N-type low-concentration layer, and an N-type impurity such as phosphorus is selectively diffused on the surface of the base region. Etc. are formed. The N + high concentration layer / N type low concentration layer serves as a collector.
半導体チップ１１の表面はシリコン酸化膜、シリコン窒化膜等の絶縁膜１２によって被覆されており、その開口部に前記ベース・エミッタ領域と電気的に接続されたアルミパッド１３が露出する。このアルミパッド１３に対して半田バンプや半田ボール等の導電材料を接着して第１の外部接続端子１４としている。第１の外部接続端子１４の先端部は、半導体チップ１１の表面から０．０１〜０．３ｍｍ程度突出する。 The surface of the semiconductor chip 11 is covered with an insulating film 12 such as a silicon oxide film or a silicon nitride film, and an aluminum pad 13 electrically connected to the base / emitter region is exposed in the opening. A conductive material such as a solder bump or a solder ball is bonded to the aluminum pad 13 to form the first external connection terminal 14. The front end portion of the first external connection terminal 14 protrudes from the surface of the semiconductor chip 11 by about 0.01 to 0.3 mm.
半導体チップ１１は、半田、金などの導電性のプリフォーム剤１５によって平板状の基板１６に接着されている。基板１６は、鉄あるいは銅系の合金素材からなり、０．１〜０．３ｍｍ程度の板厚で１辺が０．８〜２．０ｍｍ程度の大きさを持つ。半導体チップ１１のチップサイズが０．５〜１．５ｍｍ程度であり、搭載する半導体チップ１１の大きさよりは若干大きい程度のものとする。 The semiconductor chip 11 is bonded to the flat substrate 16 with a conductive preform 15 such as solder or gold. The substrate 16 is made of iron or a copper-based alloy material, and has a thickness of about 0.1 to 0.3 mm and a side of about 0.8 to 2.0 mm. The chip size of the semiconductor chip 11 is about 0.5 to 1.5 mm, which is slightly larger than the size of the semiconductor chip 11 to be mounted.
基板１１の１側辺は半導体チップ１１側にＬ字型に折り曲げられ、その先端部は第１の外部接続端子１４の高さと同程度の高さまで達して、第２の外部接続端子１７を形成する。第２の外部接続端子１７は、基板１６に対して一体化したものでも、基板１６とは別個に形成したものを基板１６上に接着固定したものでも良い。そして、第２の外部接続端子１７は半導体チップ１１の裏面側の領域を導出する端子となる。第２の外部接続端子１７と半導体チップ１１とが併置されるので、基板１６の大きさは、主として半導体チップ１１と第２の外部接続端子１７との間隔をどこまで縮小できるかによってその最小寸法が決定される。 One side of the substrate 11 is bent in an L-shape toward the semiconductor chip 11, and the tip thereof reaches a height similar to the height of the first external connection terminal 14 to form the second external connection terminal 17. To do. The second external connection terminal 17 may be integrated with the substrate 16 or may be formed separately from the substrate 16 and bonded and fixed onto the substrate 16. The second external connection terminal 17 serves as a terminal for deriving a region on the back surface side of the semiconductor chip 11. Since the second external connection terminal 17 and the semiconductor chip 11 are juxtaposed, the size of the substrate 16 has a minimum dimension mainly depending on how far the interval between the semiconductor chip 11 and the second external connection terminal 17 can be reduced. It is determined.
半導体チップ１１の周辺部は樹脂封止されておらず、所謂ベアボンドに近い状態で供給する形となる。場合により封止するときは、半導体チップ１１の周辺部だけを樹脂のポッティング手法等により部分的に被覆し、第１の外部接続端子１４だけが露出するような形態とする。 The peripheral part of the semiconductor chip 11 is not sealed with resin and is supplied in a state close to a so-called bare bond. When sealing in some cases, only the peripheral portion of the semiconductor chip 11 is partially covered by a resin potting method or the like, and only the first external connection terminals 14 are exposed.
図２は、斯かる半導体装置を、リードフレームを用いて生産する方法を示したものである。即ち図２（Ａ）に示したように、複数個の基板１６を接続部１８によって１本の共通細条１９に接続したリードフレームを準備し、図２（Ｂ）に示したように、各々の基板１６上に第１の外部接続端子１４を形成した半導体チップ１１をダイボンドし、そして接続部１８をダイシングソー、レーザーなどの手法で切断することにより個々の半導体装置を製造する。基板１６に対して第２の外部接続端子１７を一体化する場合は、リードフレームを打ち抜きまたはエッチングによって加工した後にスタンピング加工等で基板１６の一側辺を折り曲げることで形成する。別個に形成した部材を後から固着する場合は、半導体チップ１１をダイボンドする前あるいは後に、前記部材を固着する工程を行う。 FIG. 2 shows a method for producing such a semiconductor device using a lead frame. That is, as shown in FIG. 2A, a lead frame in which a plurality of substrates 16 are connected to one common strip 19 by connecting portions 18 is prepared. As shown in FIG. Each semiconductor device is manufactured by die-bonding the semiconductor chip 11 having the first external connection terminal 14 formed on the substrate 16 and cutting the connection portion 18 by a technique such as a dicing saw or laser. When the second external connection terminal 17 is integrated with the substrate 16, the lead frame is formed by punching or etching and then bending one side of the substrate 16 by stamping or the like. When the separately formed member is fixed later, a step of fixing the member is performed before or after the semiconductor chip 11 is die-bonded.
図３は、斯かる装置を実装する際の状態を示す為の図である。供給時には図３（Ａ）の様に基板１６が上を向いて第１と第２の外部接続端子１４、１７が下方を向くようにして供給され、機種名などの標印は上を向いた基板１６の平坦面に印字する。そして図３（Ｂ）に示したように、基板１６の裏面側（半導体チップ１１を搭載した面に対して反対側の面）の端部を角錐吸着コレット２０に接触させるようにして、これを吸着・保持する。実装は、角錐吸着コレット２０で搬送した半導体装置を実装基板２１上に移送し、その表面に形成した配線２２に対して第１と第２の外部接続端子１４、１７を半田２３等により対向接着することで行われる。基板１６の裏面側で装置全体を吸着させるので、半導体チップ１１の大きさのばらつきによらず、搬送工程を安定化出来る。第１の外部接続端子１４は各々ベースとコレクタの電極、第２の外部接続端子１７はコレクタ端子となる。半導体チップ１１の表面（活性部分）をプリント基板上に対向接着するので、熱的にも電気的にも抵抗を小さくできる。また、基板１６は、搬送時と実装後に半導体チップ１１の保護板として機能する。 FIG. 3 is a diagram for illustrating a state when such a device is mounted. At the time of supply, as shown in FIG. 3A, the substrate 16 is supplied with the first and second external connection terminals 14 and 17 facing downward, and the marks such as the model name face upward. Printing is performed on the flat surface of the substrate 16. Then, as shown in FIG. 3B, the end of the back surface of the substrate 16 (the surface opposite to the surface on which the semiconductor chip 11 is mounted) is brought into contact with the pyramid adsorption collet 20, Adsorb and hold. For mounting, the semiconductor device conveyed by the pyramid adsorption collet 20 is transferred onto the mounting substrate 21, and the first and second external connection terminals 14 and 17 are bonded to the wiring 22 formed on the surface thereof by solder 23 or the like. It is done by doing. Since the entire apparatus is adsorbed on the back side of the substrate 16, the transfer process can be stabilized regardless of variations in the size of the semiconductor chip 11. The first external connection terminal 14 serves as a base and a collector electrode, and the second external connection terminal 17 serves as a collector terminal. Since the surface (active portion) of the semiconductor chip 11 is bonded to the printed circuit board, the resistance can be reduced both thermally and electrically. The substrate 16 functions as a protective plate for the semiconductor chip 11 during transportation and after mounting.
以上に説明した本発明の半導体装置は、半導体チップ１６よりは若干大きい程度の基板１６を用いるので、全体として実装面積の小さな半導体装置を得ることが出来るものである。そして、半導体チップ１１の裏面側の電極を第２の外部接続端子１７を介して導出したので、前記裏面側の電極の電気抵抗、熱抵抗を共に減じることが出来るものである。これはＮＰＮトランジスタにあってはコレクタ抵抗の増大を抑制し、パワーＭＯＳＦＥＴにあってはドレイン抵抗（オン抵抗ｒｄｓ）の増大を抑制するという効果をもたらす。更に、半導体チップ１１表面側の電極を第１の外部接続端子１４によって対向接着するので、これらの電気抵抗、熱抵抗をも減じることが出来る。 Since the semiconductor device of the present invention described above uses the substrate 16 that is slightly larger than the semiconductor chip 16, a semiconductor device having a small mounting area as a whole can be obtained. Since the electrode on the back surface side of the semiconductor chip 11 is led out via the second external connection terminal 17, both the electrical resistance and the thermal resistance of the electrode on the back surface side can be reduced. This has the effect of suppressing an increase in collector resistance in an NPN transistor and suppressing an increase in drain resistance (on resistance rds) in a power MOSFET. Furthermore, since the electrodes on the surface side of the semiconductor chip 11 are oppositely bonded by the first external connection terminals 14, these electric resistance and thermal resistance can also be reduced.
また、基板１６を用いることにより、ベアチップで提供するよりはその取り扱い性に優れ、基板１６に対して半導体チップ１１の保護板としての機能と、吸着コレット２０の吸着保持面としての機能と、裏面電極の取り出し電極としての機能を同時に持たせることが出来るものである。 Further, by using the substrate 16, the handleability is superior to that provided by a bare chip, the function as a protective plate of the semiconductor chip 11 with respect to the substrate 16, the function as the suction holding surface of the suction collet 20, and the back surface The electrode can have a function as an extraction electrode at the same time.
更に、半導体チップ１１の樹脂封止を廃止することが可能であるので、材料費を抑えると共に半導体素子の故障と暴走電流による装置の発火、発煙などの事故を防止できる。 Furthermore, since the resin sealing of the semiconductor chip 11 can be abolished, it is possible to reduce material costs and prevent accidents such as failure of the semiconductor element and ignition of the device due to runaway current.
なお、半導体素子としてはバイポーラ型トランジスタ、パワーＭＯＳＦＥＴ装置などの３端子型の場合は、第１の外部接続端子１４として２つ必要であるが、ダイオード素子などの２端子素子である場合は、１つの第１の外部接続端子１４を配置すれば良いことは言うまでもない。 In the case of a three-terminal type semiconductor element such as a bipolar transistor or a power MOSFET device, two first external connection terminals 14 are required, but in the case of a two-terminal element such as a diode element, 1 Needless to say, the first external connection terminals 14 may be arranged.
１１ 半導体チップ
１２ 絶縁膜
１３ アルミパッド
１４ 第１の外部接続端子
１５ プリフォーム剤
１６ 基板
１７ 第２の外部接続端子
１８ 接続部
１９ 共通細条
２０ 吸着コレット
２１ 実装基板
２２ 配線
２３ 半田
DESCRIPTION OF SYMBOLS 11 Semiconductor chip 12 Insulating film 13 Aluminum pad 14 1st external connection terminal 15 Preform agent 16 Board | substrate 17 2nd external connection terminal 18 Connection part 19 Common strip 20 Adsorption collet 21 Mounting board 22 Wiring 23 Solder
Claims (12)
前記半導体チップの裏面が電気的に固着された搭載部と、
前記搭載部の周囲から上方に延在した延在部と、を備え、
前記半導体チップの裏面の電気的接続手段は、前記延在部に電気的に導出されており、
前記半導体チップの表面の電気的接続手段と前記延在部とが実装基板に電気的に対向接着されていることを特徴とする半導体モジュール。 A semiconductor chip having two types of electrical connection means on the front surface and one type of electrical connection means on the back surface;
A mounting portion on which the back surface of the semiconductor chip is electrically fixed;
An extending portion extending upward from the periphery of the mounting portion, and
The electrical connection means on the back surface of the semiconductor chip is electrically led to the extending portion,
A semiconductor module, wherein the electrical connection means on the surface of the semiconductor chip and the extending part are electrically opposed and adhered to a mounting substrate.
前記半導体チップの表面における電気的接続手段は、前記開口部に露出するパッドと、前記パッドに導電材料が接着された外部接続端子と、からなることを特徴とする請求項１乃至請求項１０のいずれかに記載の半導体モジュール。 The surface of the semiconductor chip is covered with an insulating film having an opening,
11. The electrical connection means on the surface of the semiconductor chip comprises a pad exposed in the opening and an external connection terminal in which a conductive material is bonded to the pad. The semiconductor module in any one.
前記外部接続端子は、前記樹脂から露出していることを特徴とする請求項１１に記載の半導体モジュール。 The surface of the semiconductor chip is coated with a resin,
The semiconductor module according to claim 11, wherein the external connection terminal is exposed from the resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006311131A JP2007073987A (en) | 2006-11-17 | 2006-11-17 | Semiconductor module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006311131A JP2007073987A (en) | 2006-11-17 | 2006-11-17 | Semiconductor module |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08178699A Division JP3895884B2 (en) | 1999-03-25 | 1999-03-25 | Semiconductor device |
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| Publication Number | Publication Date |
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| JP2007073987A true JP2007073987A (en) | 2007-03-22 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8633060B2 (en) | 2010-02-01 | 2014-01-21 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device production method and semiconductor device |
| CN111587488A (en) * | 2018-01-17 | 2020-08-25 | 新电元工业株式会社 | Electronic module |
-
2006
- 2006-11-17 JP JP2006311131A patent/JP2007073987A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8633060B2 (en) | 2010-02-01 | 2014-01-21 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device production method and semiconductor device |
| CN111587488A (en) * | 2018-01-17 | 2020-08-25 | 新电元工业株式会社 | Electronic module |
| CN111587488B (en) * | 2018-01-17 | 2024-03-19 | 新电元工业株式会社 | Electronic module |
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