TW201828339A - 於半導體裝置製造中高品質氧化矽之低溫形成 - Google Patents

於半導體裝置製造中高品質氧化矽之低溫形成 Download PDF

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TW201828339A
TW201828339A TW106132721A TW106132721A TW201828339A TW 201828339 A TW201828339 A TW 201828339A TW 106132721 A TW106132721 A TW 106132721A TW 106132721 A TW106132721 A TW 106132721A TW 201828339 A TW201828339 A TW 201828339A
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凱文 Ｍ 麥克勞克林
艾米特 法基亞
卡蒲 瑟利西 瑞迪
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美商蘭姆研究公司
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Abstract

在低於約200℃的溫度下藉由PECVD來在半導體基板上沉積氧化矽層，並使用氦電漿處理氧化矽層以將所沉積層的應力降低至小於約80 MPa的絕對值。電漿處理減少氧化矽層中的氫含量，且導致亦可具有高密度與低粗糙度的低應力膜。在一些實施例中，膜係沉積在含有一或更多無法承受大於250℃的溫度之溫度敏感層的基板上，該溫度敏感層例如有機材料層或旋塗介電質層。在一些實施例中，氧化矽膜係沉積至約100-200 Å之間的厚度，且在半導體基板上之其他層的蝕刻期間用作為硬遮罩層。

Description

於半導體裝置製造中高品質氧化矽之低溫形成
本發明關於在半導體基板上形成材料層的方法。尤其，本發明關於藉由電漿輔助化學汽相沉積(PECVD)形成氧化矽層的方法。
半導體元件的製造典型地涉及若干層不同材料的沉積與圖案化。當若干層沉積於堆疊中時，因為高度應力的材料可能導致堆疊中的層的對齊破壞、彎曲、剝離，且最終導致圖案化不精確與半導體元件故障，所以所沉積層的應力特性變得特別重要。
由於外在因素(例如，熱膨脹係數不匹配)及/或內在因素(例如，晶格內的缺陷及/或移位)二者，多數膜沉積與在所沉積膜中的殘餘應力的導入有關。取決於例如基板的特性、沉積膜的類型、沉積膜的性質、沉積膜沉積的方式等等，應力可為壓縮的或者拉伸的。沉積膜中的壓縮應力可能導致膜的起泡或彎曲，而拉伸應力可能導致膜破裂。此外，由此等應力促發的晶圓變形可能造成其他元件層中的可靠性問題，且通常，不利地影響電子與光學的性能以及所製造的半導體元件的機械完整性。因此，在半導體元件製造中，膜應力為元件層積體化策略的主要考量。
氧化矽係作為介電層材料而廣泛使用於半導體元件製造中，且經常藉由電漿輔助化學汽相沉積(PECVD)來沉積。因為許多積體化方案涉及無法承受高溫PECVD之具有溫度敏感材料層(例如，有機介電層)之基板，所以目前存在藉由低溫PECVD沉積氧化矽的需求。然而，習知的低溫PECVD提供具有不可接受的高應力值的氧化矽膜。此外，在低溫下沉積的氧化矽PECVD膜係發現有高氫含量與相對低密度，這使得該膜作為硬遮罩不太有吸引力。
出乎意料地發現，藉由低溫PECVD所獲得之氧化矽膜的電漿處理且特別是氦電漿處理，改變該膜，且能降低膜應力至絕對值小於約80 MPa。進一步地，電漿處理增加所形成膜的密度使得可獲得具有至少2.05 g/cm3 的密度與至少2.1 g/cm3 的密度之低應力膜。
在一態樣中，提供用於處理半導體基板的方法，其中該方法包括：(a)提供半導體基板至PECVD製程腔室；(b)在低於約200℃(例如，在低於約180℃的溫度下)的溫度下藉由PECVD來在半導體基板上沉積氧化矽層，其中該沉積步驟包含使含矽前驅物、含氧反應物與可選的惰性氣體(例如氦)流入PECVD製程腔室內且形成電漿；(c)在沉積之後停止含矽前驅物的氣流；及(d)在溫度低於約200℃下使用電漿處理所沉積的氧化矽層，以從而改變所沉積層並降低所沉積層的應力至絕對值小於約80 MPa。具有應力絕對值低於約50 MPa且甚至低於約10 MPa的氧化矽層係可獲得。在一範例中，氧化矽層的沉積係藉由在約1.5-5 torr之間的壓力下之SiH4 (含矽前驅物)、CO2 (含氧反應物)與氦(惰性氣體)的混合物中形成電漿來執行。在一些實施例中，該方法涉及將用於電漿產生之功率從氧化矽層沉積中使用的第一功率位準，增加至所沉積層的電漿處理中使用的第二的、較大的功率位準。在一些實施例中，電漿處理步驟係在主要由氦構成之製程氣體中執行。電漿處理步驟可在與沉積步驟相同之壓力下或在不同的壓力下執行。在一範例中，電漿處理步驟在與沉積步驟相同的製程腔室中且在與沉積步驟實質上相同的壓力與溫度下執行。在一些實施例中，在氧化矽層的沉積之後、及在停止含矽前驅物流入製程腔室之前，電漿未加以熄滅。進一步，製程可包括沖洗製程腔室以在氧化矽的沉積之後、及電漿處理之前從製程腔室移除含矽前驅物。
有利地，製程可在含有一或更多層溫度敏感材料之基板上執行。例如，在一些實施例中，低應力氧化矽的沉積與電漿處理係在具有一或更多層對於250℃與更高的溫度敏感之溫度敏感材料之半導體基板上執行。溫度敏感材料的範例包括有機材料與旋塗介電質。
氧化矽層的電漿處理減少氧化矽層中的氫含量。在一些實施例中，電漿處理後獲得的氧化矽在IR光譜上2200-2300 cm-1 處不具有Si-H尖峰。
所描述的製程可在單一站或複數站設備中實施。在一實施例中，方法包括在複數站PECVD設備的第一站沉積與電漿處理部分的氧化矽、轉移基板至該複數站PECVD設備的第二站、及在該複數站PECVD設備的第二站重複沉積與電漿處理另一部分的氧化矽。
此處提供的方法可與圖案化方法整合。在一些實施例中，此處描述的製程更包括塗佈光阻劑至半導體基板；暴露光阻劑至光；圖案化光阻劑與轉移圖案至半導體基板；及從半導體基板選擇性移除光阻劑。
在另一態樣中，提供涉及UV處理之用以處理半導體基板的方法。該方法包括(a)提供半導體基板至PECVD製程腔室；(b)在低於約200℃的溫度下藉由PECVD來在半導體基板上沉積氧化矽層；(c)在沉積之後停止含矽前驅物的氣流；及(d)在溫度低於約200℃下使用具有180 nm或更短波長的UV光處理所沉積的氧化矽層，以從而改變所沉積層並降低所沉積層的應力至絕對值小於約80 MPa。
根據另一態樣，提供用於氧化矽膜的沉積與電漿處理之設備。設備包括PECVD製程腔室、配置以在PECVD製程腔室中形成電漿的產生器、及控制器。PECVD製程腔室包括用以在沉積期間將基板固持在適當位置的支撐件，及用於將反應物導入至製程腔室內的一或更多入口。控制器包括用於進行任何此處提供的沉積與電漿處理方法之程式指令。
根據另一態樣，提供用於氧化矽膜的沉積與UV處理之設備。設備包括PECVD製程腔室、配置以在PECVD製程腔室中或在專用於UV處理之不同的製程腔室中產生具有180 nm或更短波長的UV輻射之產生器、及控制器。PECVD製程腔室包括用以在沉積期間將基板固持在適當位置的基板支撐件，及用於將反應物導入至製程腔室內的一或更多入口。控制器包括用於進行任何此處提供的沉積與UV處理方法之程式指令。
根據另一態樣，於此處提供系統，其包括此處描述的任何設備與步進機。
根據另一態樣，提供非暫態電腦機器可讀媒體，其包括用於控制任何此處提供的設備之程式指令。該指令包括用於任何此處提供的沉積與處理方法之程式碼。
本發明的該等及其他特徵及優勢將於以下參考相關圖式更詳細加以描述。
前言與概觀
在低溫下高品質氧化矽的形成係藉由下列操作來實現：在低溫下藉由PECVD在半導體基板上沉積氧化矽層，隨後使用具有波長小於約180nm的電漿及/或UV輻射處理沉積層，以將沉積層的應力降低至小於約80MPa的絕對值。
用語「半導體基板」與「半導體晶圓」代表在基板的任何位置含有半導體材料且可含有例如導體與介電質之其他材料層的基板。
用語「氧化矽」代表由矽、氧及可選的氫所組成的材料。例如碳、氮、硼及氟之其他元素亦可作為低濃度的(例如，不含氫之上至約10%的原子百分比率)摻雜劑出現。「高品質氧化矽」代表具有一或任何下列特性的組合之氧化矽：絕對值小於約80 MPa的應力；大於約2.05 g/cm3 的密度；及小於約1.47的折射率。在一些實施例中，此處提供之高品質氧化矽膜具有所有以上所列之特性。
用語「低溫形成」或「低溫沉積」代表在低於約200℃的溫度之膜的形成。在一些實施例中，低溫膜係在例如約150-180℃之間之約100-180℃之間的溫度下形成。
如此處所使用之用語「PECVD」代表涉及沉積方法，其利用電漿輔助主要以整體型式使一或更多分子反應。此方法不同於原子層沉積(ALD)，ALD的反應主要發生在基板的表面上，而在製程腔室的容積中的反應係受到抑制。如此處所使用之用語「PECVD製程腔室」或「PECVD設備」代表能以PECVD模式進行反應的任何製程腔室或設備。
大致上，形成此處所提供之高品質氧化矽膜的低溫方法可在例如在邏輯元件製造中、記憶體元件的製造中、互補式金屬氧化物半導體(CMOS)影像感測元件等等之各式應用中使用。此等方法對於其中若干層材料(包括此處提供之一或更多層高品質氧化矽)以堆疊方式沉積在基板上、隨後圖案化該堆疊的一或更多層之應用尤其有用。在一些實施例中，高品質氧化矽係作為至少3層、至少5層或至少10層之平面堆疊的部分而沉積。低應力(絕對值小於約80 MPa，較佳是小於約50 MPa)與低粗糙度(小於約1.47的RI)的組合對於此等堆疊應用是特別有利的，因為堆疊變形效應將被最小化，且圖案化可高精度地執行。
在一些實施例中，此處所提供之高品質氧化矽係用作為硬遮罩或蝕刻停止層。在此等實施例中，高品質氧化矽除了低應力之外還具有高密度(至少約2.05 g/cm3 ，例如至少約2.1 g/cm3 ，或例如至少約2.15 g/cm3 )的特性。密度相關於蝕刻選擇性，較密集的材料比較低密度的材料更耐蝕刻，故因此，對於硬遮罩與蝕刻停止應用來說，高密度是特別理想的特性。硬遮罩層保護位於硬遮罩正下方的層不受蝕刻，而未受保護的材料係受到蝕刻以形成凹陷特徵部。在一些實施例中，此處所提供之高品質氧化矽用作為蝕刻停止層。例如，在位於其正上方之SiOC材料的蝕刻期間可將其用作為蝕刻停止層。
在一些實施例中，高品質氧化矽硬遮罩係沉積在第一層(例如，一層ULK介電質)上，圖案化硬遮罩使得在選定的位置移除硬遮罩材料，暴露該第一層，及在暴露的硬遮罩的存在下蝕刻該暴露的第一層。例如，可在暴露的硬遮罩的存在下使用基於氟的化學物(例如，使用CH2 F2 )蝕刻低密度SiOC。
在低溫下氧化矽膜的形成對於含有在高溫下可能在結構上或功能上劣化之溫度敏感材料的基板是特別理想的。在一些實施例中，用於沉積高品質氧化矽的基板包含一或更多層溫度敏感材料。在一些實施例中，此材料或複數材料在200℃及更高、或250℃及更高、或275℃及更高的情況下開始劣化。因此，所有對於此等基板的操作都應在較低的溫度下進行，以避免此等溫度敏感層之不欲見的劣化。溫度敏感材料的範例包括例如聚醯亞胺、聚降冰片烯(polynorbornenes)與基於苯並環丁烯的聚合物之有機介電質(其係典型地藉由旋塗方法來沉積)。
圖1A說明在高品質氧化矽層的形成之前半導體基板100的範例的橫剖面示意圖。基板100含有一層極低k值(ULK)介電質101，其中ULK介電質具有約2.2或更小之介電常數。ULK介電質可藉由CVD、PECVD或旋塗方法沉積在下方層(未顯示)上。在一些實施例中，ULK介電質為包括矽與氧之多孔的介電質。ULK層可位於下方金屬化層之上，該金屬化層可包括具有嵌入的金屬線路之另一層ULK介電質。層103位於ULK介電層101上方並與ULK介電層101接觸，且在所說明的實施例中，層103為含有在習知的PECVD所使用之溫度下(例如，在250℃及更高或300℃及更高)易於降解之有機旋塗的介電質之溫度敏感層。
圖1B說明在高品質氧化矽硬遮罩105的沉積之後半導體基板100的橫剖面示意圖。硬遮罩105使用此處所提供之低溫方法來形成於旋塗的介電層103上方及與旋塗的介電層103接觸。在一些實施例中，所形成的硬遮罩厚度為在約100-200Å之間。在硬遮罩層105的形成之後，一或更多平面層可沉積於硬遮罩層105之上，形成至少3層或至少5層的堆疊。在一些實施例中，此等上方層之中的一層為光阻層，其係接著受到圖案化，且該圖案係使用光微影成像技術轉移至硬遮罩層105。圖案化可在選定位置移除部分高品質氧化矽材料，從而暴露下方層103。接著，暴露的層103(與隨後暴露的ULK介電層101)可在暴露的硬遮罩105的存在下受到蝕刻。在一些實施例中，半導體處理方法包括在暴露的氧化矽的存在下，蝕刻一層在高品質氧化矽層上方或下方的材料，其中該氧化矽用作為硬遮罩或蝕刻停止層。
在此處所提供的方法的發展之前，在低溫下使用PECVD之低應力氧化矽的形成存在未解的問題，因為使用例如壓力、製程氣體組成與電漿產生中所使用的功率之PECVD參數的變化不可能將PECVD膜的應力降低至絕對值小於120 MPa。應力超過100 MPa的膜具有有限的實用性，特別在涉及圖案化的應用中，故因此需要在低溫下生產高品質氧化矽的基於PECVD的新方法。
圖2顯示一實驗圖表，該圖表說明在180℃下藉由習知的PECVD來沉積的氧化矽膜的應力和密度。該膜係使用SiH4 、CO2 與He的混合物作為製程氣體來沉積在300 mm晶圓上。電漿係使用在13.56 MHz下的高頻電漿產生來形成，且針對不同的膜，使用於電漿產生的功率在100W和400W之間變化。針對不同的膜，沉積壓力係在2.5 Torr與5 Torr之間變化，且針對不同的膜，製程氣體的組成之CO2 /SiH4 比率在100與200之間變化。可以從圖表見到，所有沉積的膜具有絕對值超過120 MPa的壓縮應力，且密度在約2.01至約2.14 g /cm3 的範圍內。在這項研究中，密度和膜應力表現為獨立的參數。
已經意外地發現用於將氧化矽膜的應力顯著降低至小於約80 MPa的方法，例如小於約50 MPa或甚至小於約30 MPa。根據一態樣，該方法涉及使用電漿(例如使用氦電漿)處理藉由低溫PECVD沉積的氧化矽，以從而改變氧化矽層並降低所形成的層的應力至絕對值小於約80 MPa。在另一態樣中，該方法涉及使用具有小於約180 nm的波長之UV輻射處理藉由低溫PECVD沉積的氧化矽，以從而改變氧化矽層並降低所形成的層的應力至絕對值小於約80 MPa。形成低應力氧化矽膜的方法
低溫下形成低應力氧化矽膜的方法係在圖3A中與圖3B中顯示之製程流程圖中說明。參照圖3A，製程在301中藉由提供基板至PECVD製程腔室而開始。基板典型地為半導體基板。在一些實施例中，基板為含有如圖1A中所說明之一或更多層溫度敏感材料的平面基板。PECVD製程腔室配置成在PECVD模式下進行反應，且典型地包括用以在沉積期間將基板固持在適當位置的支撐件、一或更多用於導入反應物(例如含矽前驅物與含氧反應物)的入口、及用於從製程腔室移除一或更多氣體的一出口。在一些實施例中，製程腔室配備有配置成在沉積期間加熱基板的加熱器。含有製程腔室的設備係配置成在製程腔室中產生電漿與在PECVD模式下進行反應。PECVD製程腔室亦可具有在不同模式下進行反應的能力，但當其用以進行PECVD反應時係稱為「PECVD製程腔室」。例如，當電漿輔助原子層沉積(PEALD)製程腔室用以在PECVD模式下進行反應時，其為此處所使用之「PECVD製程腔室」。
在基板已提供至PECVD製程腔室之後，在303中，一層氧化矽在低於約200℃的溫度下藉由PECVD沉積。沉積製程涉及提供含矽前驅物與含氧反應物至製程腔室且在製程腔室中形成電漿。合適的含矽前驅物的範例包括例如矽烷(SiH4 )、二矽烷(Si2 H6 )、三矽烷(Si3 H8 )與二氯基矽烷(SiH2 Cl2 )之無碳前驅物，及例如烷氧基矽烷、烷基矽烷、環矽氧烷、炔基矽烷與正矽酸鹽(例如，四乙氧基矽烷(tetraethylorthosilicate))之含碳前驅物。合適的含氧反應物的範例包括O2 、CO2 與N2 O。當含矽前驅物包括矽和氧兩者(例如，四乙氧基矽烷)時，如此的單一前驅物既可作為矽來源又可作為含氧反應物來使用。含有含矽前驅物與含氧反應物的沉積製程氣體係典型地與稀釋劑氣體一起流入製程腔室內(在某些情況下事先氣化液體反應物)，該稀釋劑氣體在一些實施例中為不參與PECVD反應的惰性氣體。稀釋劑氣體的範例包括N2 與例如氦、氬、氖與氪之鈍氣。
在沉積製程期間溫度係維持在低於約200℃。在一些實施例中沉積溫度為180℃或更低。例如，可在約100-180℃之間的溫度下沉積膜。在沉積期間的壓力可變化，且在一些實施例中為在於1-10 torr之間，更佳是在1.5-5 torr之間，例如3.5 torr。製程氣體的個別成分的流率取決於製程腔室的大小，且在一些實施例中可在約10-10,000 sccm之間的範圍內。在一些實施例中，含氧反應物流率和含矽前驅物流率的比率為小於約300，例如約200。在一範例中，CO2 流率和SiH4 流率的比率為小於約300。
在一些實施例中，僅使用高頻射頻(HF RF)電漿產生而進行沉積(單一頻率沉積)。在其他實施例中，高頻與低頻射頻(LF RF)電漿產生兩者都被使用(雙頻率沉積)。HF電漿使用例如13.56 MHz之在約1.8 MHz與2.45 GHz之間的頻率而產生。低頻電漿使用例如400 kHz之在約50 kHz與900 kHz之間的頻率而產生。在一些實施例中，氧化矽的沉積係在單一頻率HF沉積中使用相對低功率來執行。例如，對於在單一300 mm晶圓上的沉積，用以產生電漿的功率可在約100-500W的範圍內，對應於在約0.14 W/cm2 至約0.71 W/cm2 之間的功率密度。
沉積係執行直到在基板上形成所欲量的氧化矽。在一些實施例中，在單一步驟中沉積具有厚度約100-200 Å的氧化矽層。在其他實施例中，沉積部分的氧化矽並處理之，且該製程係重複直到達成氧化矽的所欲厚度。
緊接在沉積之後的氧化矽膜通常具有低品質，且具有相對高的氫含量與高應力的特性。如此膜的IR光譜在約2250 cm-1 處展現突出的Si-H尖峰，且應力值的絕對值係典型地超過100 MPa(膜為壓縮性的)。
在此等低品質膜已藉由低溫PECVD沉積之後，在操作305中，所沉積的膜在沒有含矽前驅物的存在下使用電漿處理，以降低所沉積膜的應力至絕對值小於約80 MPa。在一些實施例中，含矽前驅物與含氧反應物的氣流係在已經沉積氧化矽膜之後停止，而剩餘的含矽前驅物係從製程腔室藉由沖洗及/或排空來移除。接著，提供例如氦之電漿處理氣體至製程腔室內，並使用電漿處理基板。在一些實施例中，電漿處理在基本上由氦組成的電漿處理製程氣體中執行。
沉積操作303與處理操作305可有利地在相同PECVD製程腔室中執行。在一些實施例中，電漿在沉積完成後並未熄滅且維持在從沉積、沖洗到電漿處理步驟的期間。在其他實施例中，電漿可在已經完成沉積之後熄滅，並接著在電漿處理期間再次激發。在又一其他的實施例中，電漿處理305與氧化矽沉積303在不同的製程腔室中執行或甚至在不同設備上執行。在一較佳的實施例中，電漿處理在完成沉積之後不久便執行，例如在已經完成沉積之後約5分鐘內或約1分鐘內。
在一些實施例中(尤其當沉積303與處理305在沒有真空中止的單一腔室內執行時)，電漿處理製程氣體(例如氦)和沉積303期間以及沉積303之後的處理腔室的沖洗期間使用之稀釋劑氣體為相同的氣體。在一些實施例中，在電漿處理期間之電漿處理氣體(例如，氦)的流率為沉積期間稀釋劑氣體的流率的至少1.5倍，例如至少2倍。例如，在一些實施例中，沉積303期間的氦流率(作為稀釋劑氣體)為約1000 sccm，且此流率在電漿處理步驟305中增加至約2500，其中氦作為電漿處理製程氣體使用。進一步地，在電漿處理步驟305期間用於電漿產生的功率大於在沉積步驟303期間用於電漿產生的功率。在一些實施例中，在電漿處理步驟期間使用的功率為在沉積步驟期間使用的功率之至少2倍，例如至少3倍。
在電漿處理步驟期間的溫度較佳是維持在低於約200℃，例如在100-180℃。在一些實施例中，電漿處理期間的壓力在約1-10 torr之間的範圍，例如約1-5 torr之間。在一些實施例中，沉積步驟303期間的溫度與壓力與電漿處理305期間的溫度與壓力相同。在其他實施例中，僅此等參數其中之一者維持不變。在沉積303和電漿處理305期間使用相同的壓力及/或溫度增加製程的整體穩定性。
電漿處理的持續時間典型地在約6秒與20秒之間的範圍內，且為可改變以調整所形成的氧化矽層的應力的參數之一。
本發明的另一態樣為調整氧化矽的應力至所欲水準的方法。該方法涉及調整選自由下列組成的群組之一或更多參數：電漿處理壓力、電漿處理持續時間、及電漿處理期間電漿產生所使用的功率位準。
在不希望受到特定操作理論束縛的情況下，吾人推測，至少部分地由於形成在氦電漿中的UV輻射與所沉積的氧化矽層之間的交互作用，因而觀察到氦電漿處理之後獲得的應力改善。在氦電漿中形成的UV輻射具有小於180 nm的波長。在本發明的另一態樣中，提供在低溫下使用具有小於約180 nm的波長之UV輻射來形成高品質氧化矽的方法。此方法的製程流程圖係在圖3B中呈現。步驟307與309等同於圖3A中顯示之步驟301與303。在已經藉由低溫PECVD沉積氧化矽層之後，在311中使用具有小於約180 nm的波長之UV輻射處理氧化矽層，以降低氧化矽層的應力至絕對值小於80 MPa。UV處理較佳是在低於200℃的溫度下執行。UV輻射的合適來源包括利用H、He、Ar、O2 等等的激發(如在電漿中)之來源。
使用氦電漿處理以降低PECVD氧化矽的應力之製程的具體範例係在圖4中說明。圖4提供示意地說明在沉積步驟401、沖洗步驟403與電漿處理步驟405期間製程氣體成分的流率以及電漿功率位準之時序圖。應瞭解，該圖未依比例繪製而提供製程的大致概觀。在步驟401中，將主要由SiH4 、CO2 與He組成之製程氣體提供至製程腔室，並使用在製程氣體中用13.56 MHz頻率與第一功率位準形成的HF RF電漿來沉積氧化矽。
沉積步驟401的具體製程條件係提供在表1中。參數係針對在單一300 mm晶圓基板上的沉積而提供，且應瞭解，電漿功率位準與流率可對於任何所欲基板或複數基板進行縮放。例如，當在具有四個處理站的設備中同時處理四個晶圓時，電漿功率與氣體的流率應為表1-3中所列之參數的四倍。 [表1] 300 mm基板上氧化矽的沉積。
接著，在沖洗步驟403，僅使氦流入製程腔室中且其將矽烷與二氧化碳沖洗出製程腔室。在此步驟期間電漿並未熄滅且電漿功率沒有改變。表2列出在沖洗步驟403期間所使用的製程參數。 [表2] 在300 mm基板上氧化矽的沉積之後的沖洗。
在完成沖洗後，於步驟405中使用氦電漿處理所沉積的氧化矽膜。在此步驟期間，電漿功率與氦流率增加。表3列出用於電漿處理步驟的製程參數。 [表3] 在300 mm基板上氧化矽的電漿處理。 設備
本發明可由容許在PECVD模式下沉積氧化矽之許多不同類型的設備來實施。通常，設備將包括收容一或更多晶圓且合適於處理晶圓之一或更多腔室或「反應器」(有時包括複數站)。各腔室可容納一或更多晶圓以供處理。一或更多腔室將晶圓保持在定義的位置或複數位置(在該位置內有或沒有移動，例如，旋轉、振動或其擾動)。在一實施例中，經受沉積與電漿處理的晶圓在製程期間從反應器中的一站轉移至反應器中的另一站。例如在一些實施例中，部分的氧化矽藉由PECVD沉積在晶圓上，且在PECVD設備的第一站受到電漿處理；晶圓接著轉移到PECVD設備的第二站，其中額外部分的氧化矽藉由PECVD沉積並受到處理。在一實施例中，所欲厚度的高品質氧化矽層的形成在四站中進行沉積，其中各站沉積與處理四分之一的層厚度。例如，如果100 Å為該層的目標厚度，各站沉積與處理25 Å厚的氧化矽膜。
在製程之時，各晶圓藉由基座、晶圓卡盤及/或其他晶圓固持設備來固持在定位。針對其中加熱晶圓的某些操作，設備可包括例如加熱面板的加熱器。在本發明的一實施例中，PECVD系統都使用於膜的沉積與處理二者。當處理為UV處理時，具有小於180 nm的波長之UV輻射來源可併入至PECVD設備中。在其他實施例中，單獨的製程腔室或甚至單獨的設備可用於沉積與處理步驟。
圖5提供簡潔的方塊圖，該圖描繪配置成實施本發明之不同的PECVD反應器元件。如所示，反應器500包括製程腔室524，其圍起反應器的其他元件並用以容納電漿，該電漿藉由包括與接地的加熱器塊520一起運作之噴淋頭514的電容器類型系統來產生。高頻RF產生器502與可選的低頻RF產生器504係連接至匹配網路506，且接著連接至噴淋頭514。
在反應器之內，晶圓基座518支撐基板516。基座518典型地包括卡盤、叉桿或升降銷以在沉積反應期間與沉積反應之間固持並轉移基板。卡盤可為靜電卡盤、機械卡盤或可在工業及/或研究中使用之不同的其他類型的卡盤。
製程氣體係經由入口512導入。複數來源氣體管線510係連接至歧管508。氣體可預先混合或不混合。採用適當的閥調與質量流量控制機制以確保在沉積、沖洗與電漿處理、製程的多個階段期間輸送正確的氣體。在(複數)化學前驅物以液體形式輸送的情況下，採用液體流量控制機制。在到達沉積腔室前，液體接著在其於加熱至高過其氣化點的歧管中之輸送期間，受到氣化並與其他製程氣體混合。
製程氣體經由出口522排出腔室500。真空泵浦526(例如，一或二階段機械乾式泵浦及/或渦輪分子泵浦)典型地抽出製程氣體，並藉由例如節流閥或鐘擺閥之封閉迴路控制的流量限制裝置來在反應器內維持合適低壓。
控制器530係與PECVD反應器500相關且可包括用於執行任何此處所述製程的程式指令。例如，控制器530可指定下列操作之必要參數：用於在低溫下執行PECVD氧化矽的沉積、用於沖洗製程腔室以移除含矽前驅物、以及用於電漿處理所沉積的氧化矽層以降低氧化矽層應力。
在複數實施例中之一者中，複數站設備可用於PECVD沉積與處理。複數站反應器容許在一腔室環境中同時運行不同的製程，從而增加晶圓處理的效率。如此設備的一範例係描繪於圖6中。俯視圖的示意呈現係加以顯示。設備腔室601包含四站603-609。通常，在複數站設備的單一腔室內，任何數目的站為可能的。站603用於基板晶圓的裝載與卸載。分度平面611用以在各站之間分度晶圓。控制器613可包含用於此處所述製程之指令。站603-609可具有相同或不同的功能。例如，有些站可致力於PECVD沉積，而其他站可僅用於所沉積膜的電漿處理。在複數實施例中之一者中，個別的站可在不同的製程條件下操作且可實質上與其他站彼此隔離。在另一實施例中，各站配置成執行PECVD沉積與所沉積膜的處理。
根據上述複數實施例中之一者，所有的站603-609配置成執行相同功能，且各站配置成用於氧化矽的PECVD沉積與用於所沉積層的處理二者。分度面板611用以抬升基板離開基座且在下個處理站準確地定位基板。在晶圓基板裝載於站603之後，其係分度至站605，高品質氧化矽膜的形成(包括PECVD沉積與處理)係在站605執行。晶圓接著移至站607，額外部分的氧化矽係在該處受到沉積與處理。基板進一步分度至站609，在該處進一步執行氧化矽膜的沉積與處理，且接著分度至站603以沉積與處理更多的擴散氧化矽層。例如，各站可沉積與處理25 Å的氧化矽以形成100 Å厚的氧化矽層，或者各站可沉積與處理50 Å的氧化矽以形成200 Å厚的氧化矽層。處理過的晶圓係在站603卸載，而該模組係裝填新的晶圓。在正常操作期間，單獨的基板佔據各站，且每次重複製程時將基板移至新站。因此，具有四站603、605、607與609的設備容許同時處理四晶圓。因為增加了晶圓間沉積的再現性，涉及將膜形成拆解成實質上相同的複數階段之此類型的處理為特別有利的，其中各階段包括部分膜的沉積與處理。
製程條件與製程流量本身可藉由控制器單元613來控制，該控制器單元613包含用於監控、維持及/或調整例如RF電漿功率、氣體流率與時間、溫度、壓力等等之特定製程變數的程式指令。例如，可包括針對氧化矽沉積來指定矽烷與CO2 流率的指令。根據上述方法，指令可指定所有的參數以執行操作。例如，指令可包括PECVD沉積、沖洗與電漿處理的參數。控制器可包含用於不同設備站之不同的或相同的指令，因此容許設備站獨立地或同步地操作。
在一些實施例中，控制器為系統的一部分，系統可為上述範例的一部分。如此系統可包含半導體處理設備，包括處理工具或複數工具、腔室或複數腔室、用於處理的平台或複數平台及/或特定的處理元件(晶圓基座、氣體流量系統等等)。此等系統可與在半導體晶圓或基板的處理之前、期間、與之後用於控制其操作的電子元件整合。電子元件可稱為「控制器」，其可控制不同的元件、或者系統或複數系統的子部分。取決於處理需求及/或系統的類型，控制器可程式化以控制此處所接露的任何製程，包括處理氣體的輸送、溫度設定(例如，加熱及/或冷卻)、壓力設定、真空設定、功率設定、射頻(RF)產生器設定、RF匹配電路設定、頻率設定、流率設定、流體輸送設定、定位與操作設定、晶圓轉移進出工具及連接至或介接至特定系統的其他轉移工具及/或負載閘。
廣泛地講，控制器可界定為具有用以接收指令、發佈指令、控制操作、啟動清洗操作、啟動終點量測以及類似者之諸多積體電路、邏輯、記憶體、及/或軟體的電子設備。積體電路可包含：儲存程式指令之韌體形式的晶片、數位訊號處理器(DSP，digital signal processor)、界定為特殊用途積體電路(ASIC，application specific integrated circuit)的晶片、及/或一或更多微處理器、或執行程式指令(例如，軟體)的微控制器。程式指令可為以不同的單獨設定(或程式檔案)之形式而傳達至控制器或系統的指令，該單獨設定(或程式檔案)為實行特定的製程(在半導體晶圓上，或針對半導體晶圓)界定操作參數。在一些實施例中，操作參數可為由製程工程師為了在一或更多以下者的製造期間實現一或更多處理步驟而界定之配方的一部分：層、材料、金屬、氧化物、矽、二氧化矽、表面、電路、及/或晶圓的晶粒。
在一些實施例中，控制器可為電腦的一部分，或耦接至電腦，該電腦係與系統整合、耦接至系統、以其他網路的方式接至系統、或其組合的方式而接至系統。舉例而言，控制器可在能容許遠端存取晶圓處理之「雲端」或廠房主機電腦系統的全部、或部分中。電腦可使系統能夠遠端存取，以監控製造操作的目前進度、檢查過去製造操作的歷史、自複數的製造操作而檢查趨勢或效能度量，以改變目前處理的參數、設定目前處理之後的處理步驟、或開始新的製程。在一些範例中，遠端電腦(例如，伺服器)可通過網路提供製程配方至系統，該網路可包含局域網路或網際網路。遠端電腦可包含使得可以進入參數及/或設定、或對該參數及/或設定進行程式設計的使用者介面，然後該參數及/或設定自遠端電腦而傳達至系統。在一些範例中，控制器以資料的形式接收指令，該指令為即將於一或更多操作期間進行之處理步驟的每一者指定參數。應理解，參數可特定地針對待執行之製程的類型、及控制器與之接合或加以控制之工具的類型。因此，如上所述，控制器可為分散式，例如藉由包含以網路的方式接在一起、且朝向共同之目的(例如，本文所描述之製程及控制)而運作的一或更多分離的控制器。用於如此目的之分散式控制器的範例將是腔室上與位於遠端的一或更多積體電路(例如，在作業平臺層次處、或作為遠端電腦的一部分)進行通訊的一或更多積體電路，兩者相結合以控制腔室上的製程。
例示性系統可包含但不限於以下者：電漿蝕刻腔室或模組、沉積腔室或模組、旋轉淋洗腔室或模組、金屬電鍍腔室或模組、清洗腔室或模組、斜角緣部蝕刻腔室或模組、物理氣相沉積(PVD)腔室或模組、化學氣相沉積(CVD)腔室或模組、原子層沉積(ALD)腔室或模組、原子層蝕刻(ALE)腔室或模組、離子植入腔室或模組、軌道腔室或模組、及可在半導體晶圓的製造及/或加工中相關聯、或使用的任何其他半導體處理系統。
如以上所提及，取決於待藉由工具而執行之(複數)製程步驟，控制器可與半導體製造工廠中之一或更多的以下者進行通訊：其他工具電路或模組、其他工具元件、叢集工具、其他工具介面、鄰近的工具、相鄰的工具、遍及工廠而分布的工具、主電腦、另一控制器、或材料輸送中使用之工具，該材料輸送中使用之工具將晶圓容器帶至工具位置及/或裝載埠，或自工具位置及/或裝載埠帶來晶圓容器。含有用於控制根據本發明之製程操作的機器可讀媒體可耦接至系統控制器。
於上文所述之設備/製程可結合微影圖案化工具或製程一起使用，其例如用以製作或製造半導體裝置、顯示器、LED、太陽光電板及類似者。通常(儘管非必需)，如此之工具/製程會在一共同製造設備中一起使用或實施。膜的微影圖案化通常包含下列步驟的部分或全部(使用一些適當工具來實施各步驟)：(1)利用旋塗或噴塗工具將光阻塗布在工作件（即基板）上；(2)利用熱板或加熱爐或UV固化工具使光阻固化；(3)利用例如晶圓步進機之工具，使光阻曝露至可見光或UV光或x光；(4)使光阻顯影以選擇性移除光阻，並從而利用例如濕式工作臺之工具使其圖案化；(5)藉由利用乾式或電漿輔助蝕刻工具，使光阻圖案轉移至下方膜或工作件內；及(6)利用例如RF或微波電漿光阻剝除器之工具，將光阻移除。
所描述之方法與裝置的若干實施例現將藉由具體範例說明。實驗範例
範例1，具有低應力與高密度之氧化矽膜的形成。
在可從Lam Research Corporation, Fremont CA獲得的Vector PECVD反應器中，在溫度180℃下、與2.5 Torr-3.5 Torr的壓力，於平面300 mm晶圓上藉由PECVD，沉積若干氧化矽膜。沉積期間使用的製程氣體由SiH4 (以30sccm提供)、CO2 (以4200 sccm)與He組成。電漿係使用在100-400W的功率位準下、在13.56 MH下的HF RF產生而在該製程氣體中產生。沉積持續進行5秒；接著流入製程腔室之SiH4 與CO2 的氣流停止，同時保留電漿與氦氣流5秒以將SiH4 與CO2 沖洗出製程腔室。接著，電漿功率增加至500-1000W且氦氣流增加至1000-4000 sccm，而沉積的氧化矽膜係在此等條件下受到持續6-20秒的電漿處理。對於整個製程期間的各膜，溫度與壓力維持不變。流率與電漿功率位準係針對單一晶圓上的處理而給定。膜係沉積至400 Å的厚度以促進應力的準確量測。沉積之後，量測所形成之膜的應力與密度。應力係使用Si晶圓基板的彎曲度改變與膜厚度橢圓偏振之量測來計算。密度係藉由Si基板上的質量改變與膜厚度橢圓偏振來計算。所形成的膜的密度值與應力值係在顯示於圖7中之圖表中說明。可以見到，獲得具有應力絕對值小於80 MPa且甚至小於50 MPa的膜。一些膜展現小於30 MPa的應力值。所形成的膜具有大於2.05 g/cm3 的密度。一些膜具有大於2.1 g/cm3 的密度。可從圖7見到，因為較低的應力(絕對值)與較低的密度有關，密度與應力趨勢之間存在相關性。儘管如此，提供的方法生產具有適用於硬遮罩應用之可接受的應力與密度值之膜。相反，在沒有電漿處理的情況下，在低溫下形成的PECVD氧化矽膜具有超過100 MPa的應力絕對值。
範例2，所形成之低應力膜的結構。
獲取低應力氧化矽材料的FT IR光譜。使用下列製程參數，如在範例1中所述形成該膜：180℃的溫度、3.5 Torr的壓力、100W的電漿功率(在13.56 MHz下產生)、30 sccm的SiH4 流率、4200 sccm的CO2 流率與1250 sccm的He流率。所形成的膜具有小於-40 MPa的應力。可以見到，FT IR光譜在2250 cm-1 處不具有Si-H尖峰，其係典型地存在於沒有電漿後處理之藉由低溫PECVD沉積的氧化矽膜中。這表示電漿後處理降低所形成的膜中的氫濃度。
範例3，藉由電漿後處理改善的應力、密度與RI。
對比的氧化矽膜係藉由低溫PECVD沉積至厚度411 Å，且量測其應力、密度與RI。該沉積係在180℃的溫度下與3.5Torr的壓力下使用100W的電漿功率(13.56 MHz)、30 sccm的SiH4 流率、4200 sccm的CO2 流率與1250 sccm的He流率來進行。
另一氧化矽膜係使用如同前文對比膜的沉積中所用之相同製程條件藉由低溫PECVD來沉積，並接著在180℃的溫度下、3.5Torr的壓力下、使用500W的電漿功率(13.56MHz)與1000 sccm的He流率受到電漿處理。量測經處理的膜的應力、密度與RI。
針對對比膜與針對經處理的膜之參數係提供於表4中。 [表4] 電漿處理之後的應力、密度與RI的改善。
應注意，獲得大於1.47的RI係由於薄膜的計量偏移。RI使用橢圓偏振量測。
範例4，在處理階段使用壓力之應力的調變。
如範例1所述，四個膜使用氦電漿沉積與處理。使用下列的條件：180℃的溫度、100W的電漿功率(13.56MHz)、30 sccm的SiH4 流率、4200 sccm的CO2 流率與1250 sccm的He流率。對於所有的四個膜，沉積期間的壓力不變且為3.5 Torr。電漿處理步驟期間的壓力係在1.5 torr、2.5 torr、3.5 torr與5.5 torr之間變化。處理壓力為在膜形成期間唯一變化的製程參數。圖9A提供作為處理壓力的函數之4個膜的應力值之圖表。可以見到，應力的絕對值隨著壓力增加而從約50 MPa降低至約35 MPa。
範例5，使用電漿處理時間之應力的調變。
具有不同厚度的若干膜係使用如此處所述之氦來沉積與電漿處理。研究電漿處理步驟的持續時間對膜應力的影響並顯示於圖9B中。隨著處理的持續時間從3秒增加至12秒，50 Å膜(曲線a)展現應力的絕對值從約50 MP降低至約10 MPa。對於處理持續時間的改變，33 Å膜(曲線b)與25 Å膜(曲線c)某種程度上反應較差。
範例6，針對不同厚度的膜使用電漿處理時間之應力的調變。
具有不同厚度的若干膜係使用如此處所述之氦來沉積與電漿處理。研究電漿處理步驟的持續時間對膜應力的影響並顯示於圖9C中。隨著處理的持續時間從6秒增加至12秒，使用500W電漿功率的50 Å膜(曲線a)展現應力絕對值的降低。隨著處理的持續時間從12秒增加至20秒，使用500W電漿功率處理之具有100 Å厚度的膜(曲線b)亦展現應力絕對值的降低。
儘管各種細節為清楚之目的予以省略，然可實施各種設計替代例。因此，本範例應視為說明性而非限制性，且本發明不受限於本文所提出之細節，而是可在隨附請求項之範圍中進行變更。
100‧‧‧基板
101‧‧‧介電質/介電層
103‧‧‧層
105‧‧‧硬遮罩
301‧‧‧步驟
303‧‧‧步驟
305‧‧‧步驟
307‧‧‧步驟
309‧‧‧步驟
311‧‧‧步驟
401‧‧‧步驟
403‧‧‧步驟
405‧‧‧步驟
500‧‧‧反應器
502‧‧‧高頻RF產生器
504‧‧‧低頻RF產生器
506‧‧‧匹配網路
508‧‧‧歧管
510‧‧‧來源氣體管線
512‧‧‧入口
514‧‧‧噴淋頭
516‧‧‧基板
518‧‧‧晶圓基座
520‧‧‧加熱器塊
522‧‧‧出口
524‧‧‧製程腔室
526‧‧‧真空泵浦
530‧‧‧控制器
601‧‧‧設備腔室
603‧‧‧站
605‧‧‧站
607‧‧‧站
609‧‧‧站
611‧‧‧平面
613‧‧‧控制器
圖1A-1B顯示經受使用此處提供的方法來處理之例示性半導體元件的示意橫剖面。
圖2為在沒有後處理情況下使用低溫PECVD所沉積的膜之應力對密度的實驗圖表。
圖3A-3B呈現根據此處提供的實施例之氧化矽形成製程的製程流程圖。
圖4根據此處提供的一些實施例，顯示氧化矽形成製程的示意時序圖。
圖5根據本發明的一些實施例，為合適於形成氧化矽膜之PECVD設備的示意圖。
圖6根據本發明的一些實施例，為合適於形成氧化矽膜之複數站設備的一範例的示意圖。
圖7根據此處提供的實施例，為在具有後處理情況下使用低溫PECVD所沉積的膜之應力對密度的實驗圖表。
圖8為藉由此處揭露的實施例所提供而獲得之低應力氧化矽膜的FT IR光譜。
圖9A為膜應力對於此處提供的氧化矽膜的電漿處理期間之壓力的相依性之實驗圖表。
圖9B為膜應力對於此處提供的氧化矽膜之電漿處理的持續時間的相依性之實驗圖表。
圖9C為膜應力對於此處提供的不同厚度的氧化矽膜之電漿處理的持續時間的相依性之實驗圖表。

Claims (28)

  1. 一種處理半導體基板的方法，該方法包含： (a)提供一半導體基板至一PECVD製程腔室； (b)在低於約200℃的溫度下藉由PECVD來在該半導體基板上沉積一層氧化矽，其中該沉積步驟包含使一含矽前驅物與一含氧反應物流入該PECVD製程腔室內且形成一電漿； (c)在沉積之後停止該含矽前驅物的氣流；及 (d)在低於約200℃的溫度下使用一電漿來處理該氧化矽的沉積層，以從而改變該沉積層及降低該沉積層的應力至小於約80 MPa的一絕對值。
  2. 如申請專利範圍第1項之處理半導體基板的方法，其中該方法包含將用於電漿產生之功率從一第一功率位準增加至一第二、較大的功率位準，其中該第一功率位準係在(b)中使用且該第二功率位準係在(d)中使用。
  3. 如申請專利範圍第1項之處理半導體基板的方法，其中(d)包含使用在主要由氦組成之一處理氣體中形成的一電漿來處理該氧化矽的沉積層。
  4. 如申請專利範圍第1項之處理半導體基板的方法，其中在(a)中提供之該半導體基板包含一或更多層對250℃與更高的溫度敏感之溫度敏感材料。
  5. 如申請專利範圍第4項之處理半導體基板的方法，其中該溫度敏感材料為一有機材料。
  6. 如申請專利範圍第4項之處理半導體基板的方法，其中該溫度敏感材料為一旋塗介電質。
  7. 如申請專利範圍第1項之處理半導體基板的方法，其中該氧化矽層的該沉積係在低於約180℃的溫度下執行。
  8. 如申請專利範圍第1項之處理半導體基板的方法，其中在(d)之後獲得的該氧化矽層的應力的絕對值係小於約50 MPa。
  9. 如申請專利範圍第1項之處理半導體基板的方法，其中在(d)之後獲得的該氧化矽層的應力的絕對值係小於約10 MPa。
  10. 如申請專利範圍第1項之處理半導體基板的方法，其中在(d)中之該氧化矽層的該電漿處理降低該氧化矽層中的氫含量。
  11. 如申請專利範圍第1項之處理半導體基板的方法，其中在(d)中之電漿處理之後獲得的該氧化矽在一IR光譜上2200-2300 cm-1 處不具有一Si-H尖峰。
  12. 如申請專利範圍第1項之處理半導體基板的方法，其中該方法包含在(b)之後與(c)之前維持該電漿。
  13. 如申請專利範圍第1項之處理半導體基板的方法，更包含在(b)之後與(c)之前沖洗該PEVCD製程腔室，以從該製程腔室移除該含矽前驅物。
  14. 如申請專利範圍第1項之處理半導體基板的方法，其中(b)更包含使一惰性氣體流入該PECVD製程腔室內。
  15. 如申請專利範圍第14項之處理半導體基板的方法，其中該含矽前驅物為SiH4 、該含氧反應物為CO2 及該惰性氣體為He。
  16. 如申請專利範圍第1項之處理半導體基板的方法，其中(b)係在約1.5-5 Torr之間的壓力下執行。
  17. 如申請專利範圍第1項之處理半導體基板的方法，其中(b)與(c)係在相同的PECVD製程腔室中、在實質上相同的壓力與溫度下執行。
  18. 如申請專利範圍第1項之處理半導體基板的方法，其中(b)-(d)係在一複數站PECVD設備的一第一站執行，其中該方法更包含在(d)之後將該半導體基板轉移至該複數站PECVD設備的一第二站，且在該複數站PECVD設備的該第二站中重複(b)-(d)。
  19. 如申請專利範圍第1項之處理半導體基板的方法，更包含： 塗佈光阻劑至該半導體基板； 暴露該光阻劑至光； 圖案化該光阻劑且轉移該圖案至該半導體基板；及 選擇性地從該半導體基板移除該光阻劑。
  20. 一種處理半導體基板的方法，該方法包含： (a)提供一半導體基板至一PECVD製程腔室； (b)在低於約200℃的溫度下藉由PECVD來在該半導體基板上沉積一層氧化矽； (c)在沉積之後停止該含矽前驅物的氣流；及 (d)在低於約200℃的溫度下使用具有180 nm或更短波長的UV光來處理該氧化矽的沉積層，以改變該沉積層及降低該沉積層的應力至小於約80 MPa的一絕對值。
  21. 一種用於半導體基板上之氧化矽膜的沉積與電漿處理的設備，該設備包含： (a)一PECVD製程腔室，其包含用以在沉積期間將該半導體基板固持在適當位置的一基板支撐件； (b)一電漿產生器，其用以產生用於該PECVD製程腔室的一電漿；及 (c)一控制器，其包含用於下列操作的程式指令： (i)在低於約200℃的溫度下，在該PECVD製程腔室中之該半導體基板上沉積一層氧化矽，其中用於沉積之該程式指令包含用於使一含矽前驅物與一含氧反應物流入該PECVD製程腔室內且形成一電漿之指令； (ii)在沉積之後停止該含矽前驅物的氣流；及 (iii)在低於約200℃的溫度下使用一電漿來處理該氧化矽的沉積層，以從而改變該沉積層及降低該沉積層的應力至小於約80 MPa的一絕對值。
  22. 如申請專利範圍第21項之用於半導體基板上之氧化矽膜的沉積與電漿處理的設備，其中該程式指令包含用於將用於電漿產生之功率從一第一功率位準增加至一第二、較大的功率位準的指令，其中該第一功率位準係在(i)中使用且該第二功率位準係在(iii)中使用。
  23. 一種用於半導體基板上之氧化矽膜的沉積與UV處理的設備，該設備包含： (a)一PECVD製程腔室，其包含用以在沉積期間將該半導體基板固持在適當位置的一基板支撐件； (b)一電漿產生器，其用以產生用於該PECVD製程腔室的一電漿； (c)一產生器，其配置成產生具有180 nm波長之UV輻射；及 (d)一控制器，其包含用於下列操作的程式指令： (i)在低於約200℃的溫度下、在該PECVD製程腔室中之該半導體基板上沉積一層氧化矽，其中用於沉積之該程式指令包含用於使一含矽前驅物與一含氧反應物流入該PECVD製程腔室內且形成一電漿之指令； (ii)在沉積之後停止該含矽前驅物的氣流；及 (iii)在低於約200℃的溫度下使用具有180 nm 或更短波長的UV光來處理該氧化矽的沉積層，以改變該沉積層及降低該沉積層的應力至小於約80 MPa的一絕對值。
  24. 如申請專利範圍第23項之用於半導體基板上之氧化矽膜的沉積與UV處理的設備，其中配置成產生UV輻射的該產生器係位在該PECVD製程腔室中。
  25. 如申請專利範圍第23項之用於半導體基板上之氧化矽膜的沉積與UV處理的設備，其中配置成產生UV輻射的該產生器係位在不同於該PECVD製程腔室之一製程腔室中。
  26. 一種包含申請專利範圍第21項或第23項的一設備及一步進機的系統。
  27. 一種非暫態電腦機器可讀媒體，包含用於下列者的程式碼： (i)在低於約200℃的溫度下、在一PECVD製程腔室中的一半導體基板上沉積一層氧化矽，其中用於沉積之該程式碼包含用於使一含矽前驅物與一含氧反應物流入該PECVD製程腔室內且形成一電漿的程式指令； (ii)在沉積之後停止該含矽前驅物的氣流；及 (iii)在低於約200℃的溫度下使用具有180 nm或更短波長之UV光來處理該氧化矽的沉積層，以改變該沉積層及降低該沉積層的應力至小於約80 MPa的一絕對值。
  28. 一種非暫態電腦機器可讀媒體，包含用於下列者的程式碼： (i)在低於約200℃的溫度下、在該PECVD製程腔室中的該半導體基板上沉積一層氧化矽，其中用於沉積之該程式碼包含用於使一含矽前驅物與一含氧反應物流入該PECVD製程腔室內且形成一電漿的程式指令； (ii)在沉積之後停止該含矽前驅物的氣流；及 (iii)在低於約200℃的溫度下使用具有180 nm或更短波長之UV光來處理該氧化矽的沉積層，以改變該沉積層及降低該沉積層的應力至小於約80 MPa的一絕對值。
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