KR960032775A - 반도체 장치 제조 방법 - Google Patents

반도체 장치 제조 방법 Download PDF

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KR960032775A
KR960032775A KR1019960003814A KR19960003814A KR960032775A KR 960032775 A KR960032775 A KR 960032775A KR 1019960003814 A KR1019960003814 A KR 1019960003814A KR 19960003814 A KR19960003814 A KR 19960003814A KR 960032775 A KR960032775 A KR 960032775A
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substrate
forming
insulating film
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silicon film
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순페이 야마자끼
야스유키 아라이
사토시 데라모토
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순페이 야마자끼
가부시키가이샤 한도오따이 에네루기 켄큐쇼
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Abstract

본 발명의 반도체 장치 제조 방법은, 제1기판상에 제1절연막을 형성하는 단계; 그 제1절연막상에 제2절연막을 형성하는 단계; 그 제2절연막상에 비정질 규소막을 형성하는 단계; 규소의 결정화를 조장하는 금속 원소를 비정질 규소막의 표면에 접촉시켜 유지하는 단계; 가열 처리에 의해 비정질 규소막을 결정화시켜 결정성 규소막을 얻는 단계; 그 결정성 규소막을 사용하여 박막 트랜지스터를 형성하는 단계; 그 박막 트랜지스터를 밀봉하는 밀봉층을 형성하는 단계; 반투명 성질을 가지는 제2기판을 밀봉층에 접합하는 단계; 및 제1기판을 박리하기 위해 제1절연막을 제거하는 단계를 포함한다.

Description

반도체 장치 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1(A)도∼제1(D)도는 본 발명의 일 실시예에 따른 액정 패널을 제조하는 공정을 나타내는 도면.

Claims (27)

  1. 제1기판상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 제2절연막을 형성하는 단계; 상기 제2절연막상에 비정질 규소막을 형성하는 단계; 규소의 결정화 조장하는 금속 원소를 상기 비정질 규소막의 표면에 접촉시켜 유지하는 단계; 결정성 규소막을 얻기 위해 가열 처리에 의해 상기 비정질 규소막을 결정화시키는 단계; 상기 결정성 규소막을 사용하여 박막 트랜지스터를 형성하는 단계; 상기 박막 트랜지스터를 밀봉하는 밀봉층을 형성하는 단계; 반투명 성질을 가지는 제2기판을 상기 밀봉층에 접합하는 단계; 및 상기 제1기판을 박리하기 위해 상기 제1절연막을 제거하는 단계를 포함하는 반도체 장치 제조 방법.
  2. 제1항에 있어서, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu 및 Au으로부터 선택된 1종류 또는 다수 종류의 원소가 규소의 결정화를 조장하는 상기 금속 원소로 사용되는 반도체 장치 제조 방법.
  3. 제1항에 있어서, 상기 결정성 규소막이 규소의 결정화를 조장하는 상기 금속 원소를 1×1014∼5×1018원자㎝-3의 밀도로 함유하고, 소수 및/또는 할로겐을 0.0005∼5원자%의 밀도로 함유하는 반도체 장치 제조 방법.
  4. 제1항에 있어서, 상기 제1기판이 유리 기판이나 석영 기판으로 형성된 반도체 장치 제조 방법.
  5. 제1항에 있어서, 상기 제2기판이 반투명 성질을 가지며, 가요성 수지 기판을 형성된 반도체 장치 제조 방법.
  6. 제3항에 있어서, 상기 할로겐이 불소, 염소 또는 브롬인 반도체 장치 제조 방법.
  7. 표면에 홈이 형성된 제1기판상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 제2절연막을 형성하는 단계; 상기 제2절연막상에 비정질 규소막을 형성하는 단계; 규소의 결정화 조장하는 금속 원소를 상기 비정질 규소막의 표면에 접촉시켜 유지하는 단계; 결정성 규소막을 얻기 위해 가열 처리에 의해 상기 비정질 규소막을 결정화시키는 단계; 상기 결정성 규소막을 사용하여 박막 트랜지스터를 형성하는 단계; 상기 박막 트랜지스터를 밀봉하는 밀봉층을 형성하는 단계; 반투명 성질을 가지는 제2기판을 상기 밀봉층에 접합하는 단계; 및 상기 제1기판을 박리하기 위해 에칭 용매를 사용하여 상기 제1절연막을 제거하는 단계를 포함하는 반도체 장치 제조 방법.
  8. 제7항에 있어서, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu 및 Au으로부터 선택된 1종류 또는 다수 종류의 원소가 규소의 결정화를 조장하는 상기 금속 원소로 사용되는 반도체 장치 제조 방법.
  9. 제7항에 있어서, 상기 결정성 규소막이 규소의 결정화를 조장하는 상기 금속 원소를 1×1014∼5×1018원자㎝-3의 밀도로 함유하고, 소수 및/또는 할로겐을 0.0005∼5원자%의 밀도로 함유하는 반도체 장치 제조 방법.
  10. 제7항에 있어서, 상기 제1기판이 유리 기판이나 석영 기판으로 형성된 반도체 장치 제조 방법.
  11. 제7항에 있어서, 상기 제2기판이 반투명 성질을 가지며, 가요성 수지 기판으로 형성된 반도체 장치 제조 방법.
  12. 표면에 홈이 형성된 제1기판상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 제2절연막을 형성하는 단계; 상기 제2절연막상에 비정질 규소막을 형성하는 단계; 규소의 결정화 조장하는 금속 원소를 상기 비정질 규소막의 표면에 접촉시켜 유지하는 단계; 결정성 규소막을 얻기 위해 가열 처리에 의해 상기 비정질 규소막을 결정화시키는 단계; 상기 결정성 규소막을 사용하여 박막 트랜지스터를 형성하는 단계; 상기 박막 트랜지스터를 밀봉하는 밀봉층을 형성하는 단계; 반투명 성질을 가지는 제2기판을 상기 밀봉층에 접합하는 단계; 및 상기 제1기판을 박리하기 위해 에칭 용매를 사용하여 상기 제1절연막을 제거하는 단계를 포함하고, 상기 홈의 바닥 부분과 상기 제1절연막 사이에 간극이 형성되고, 상기 에칭 용매가 상기 간극에 들어가는 반도체 장치 제조 방법.
  13. 제12항에 있어서, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu 및 Au으로부터 선택된 1종류 또는 다수 종류의 원소가 규소의 결정화를 조장하는 상기 금속 원소로 사용되는 반도체 장치 제조 방법.
  14. 제12항에 있어서, 상기 결정성 규소막이 규소의 결정화를 조장하는 상기 금속 원소를 1×1014∼5×1018원자㎝-3의 밀도로 함유하고, 소수 및/또는 할로겐을 0.0005∼5원자%의 밀도로 함유하는 반도체 장치 제조 방법.
  15. 제12항에 있어서, 상기 제1기판이 유리 기판이나 석영 기판으로 형성된 반도체 장치 제조 방법.
  16. 제12항에 있어서, 상기 제2기판이 반투명 성질을 가지며, 가요성 수지 기판으로 형성된 반도체 장치 제조 방법.
  17. 제14항에 있어서, 상기 할로겐이 불소, 염소 또는 브롬인 반도체 장치 제조 방법.
  18. 제1기판상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 제2절연막을 형성하는 단계; 상기 제2절연막상에 비정질 규소막을 형성하는 단계; 규소의 결정화를 조장하는 금속 원소를 상기 비정질 규소막의 표면에 접촉시켜 유지하는 단계; 상기 비정질 규소막에 레이저 비임을 조사하여, 그 레이저 비임이 조사된 영역을 단결정과 닮은 영역 또는 사실상 단결정과 닮은 영역으로 변경시키는 단계; 상기 단결성과 닮은 영역 또는 사실상 단결정과 닮은 영역을 활성층으로 사용하여 박막 트랜지스터를 형성하는 단계; 상기 박막 트랜지스터를 밀봉하는 밀봉층을 형성하는 단계; 반투명 성질을 가지는 제2기판을 상기 밀봉층에 접합하는 단계; 및 상기 제1기판을 박리하기 위해 상기 제1절연막을 제거하는 단계를 포함하는 반도체 장치 제조 방법.
  19. 제18항에 있어서, 상기 제2기판이 반투명 성질과 가요성을 가지는 수지 기판을 포함하고, 상기 활성층내의 응력이 레이저 비임의 조사 후 가열 처리를 행함으로써 완화되는 반도체 장치 제조 방법.
  20. 단결정과 닮은 영역 또는 사실상 단결정과 닮은 영역이 결정입계를 사실상 포함하지 않고, 결함을 보상하기 위한 수소 원자 및/또는 할로겐 원자를 1×1015∼1×1020원자㎝-3의 밀도로 함유하며, 탄소 원자와 질소 원자를 1×1016∼5×10|18원자㎝-3의 밀도로 함유하고, 산소 원자를 1×1017∼5×1019원자㎝-3의 밀도로 함유하는 반도체 장치 제조 방법.
  21. 제1기판상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 제2절연막을 형성하는 단계; 상기 제2절연막상에 비정질 규소막을 형성하는 단계; 규소의 결정화를 조장하는 금속 원소를 상기 비정질 규소막의 표면에 접촉시켜 유지하는 단계; 상기 비정질 규소막에 레이저 비임을 조사하여, 그 레이저 비임이 조사된 영역을 결정성을 가지는 영역으로 변경시키는 단계; 상기 결정성을 가지는 영역을 활성층으로 사용하여 박막 트랜지스터를 형성하는 단계; 상기 박막 트랜지스터를 밀봉하는 밀봉층을 형성하는 단계; 반투명 성질을 가지는 제2기판을 상기 밀봉층에 접합하는 단계; 및 상기 제1기판을 박리하기 위해 상기 제1절연막을 제거하는 단계를 포함하는 반도체 장치 제조 방법.
  22. 제21항에 있어서, 상기 제2기판이 가용성을 가지는 수지 기판을 포함하고, 상기 활성층내의 응력이 레이저 비임의 조사 후 가열 처리를 행함으로써 완화되는 반도체 장치 제조 방법.
  23. 석영을 포함하는 제1기판상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 제2절연막을 형성하는 단계; 상기 제2절연막상에 비정질 규소막을 형성하는 단계; 규소의 결정화를 조장하는 금속 원소를 상기 비정질 규소막이 표면에 접촉시켜 유지하는 단계; 결정성 규소막을 얻기 위해 가열 처리에 의해 상기 비정질 규소막을 결정화시키는 단계; 상기 결정성 규소막의 표면에 열산화막을 형성하도록, 그리고 상기 결정성 규소막에 존재하는 상기 금속 원소를 제거 또는 감소시키기 위해 상기 금속 원소를 상기 열산화 막내로 게터링하도록, 할로겐 원소를 함유하는 산화 분위기에서 상기 결정성 규소막에 열 처리를 행하는 단계; 상기 열산화막을 제거하는 단계; 상기 결정성 규소막을 사용하여 박막 트랜지스터를 형성하는 단계; 상기 박막 트랜지스터를 밀봉하는 밀봉층을 형성하는 단계; 반투명 성질을 가지는 제2기판을 상기 밀봉층에 접합하는 단계; 및 상기 제1기판을 박리하기 위해 상기 제1절연막을 제거하는 단계를 포함하는 반도체 장치 제조 방법.
  24. 제23항에 있어서, 박막 트랜지스터를 형성하는 상기 단계가, 상기 결정성 규소막을 패터닝하여 상기 박막 트랜지스터의 활성층으로 되게 하고; 상기 활성층의 표면에 상기 열산화막을 형성하는 것을 포함하는 반도체 장치 제조 방법.
  25. 제23항에 있어서, Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu 및 Au으로 이루어진 군으로부터 선택된 1종류 또는 다수 종류의 원소가 상기 금속 원소로 사용되는 반도체 장치 제조 방법.
  26. 제23항에 있어서, 상기 산화 분위기가 HCI, HF, HBr, Cl2, F2및 Br2로 이루어진 군으로부터 선택된 1종류 또는 다수 종류의 가스를 포함하는 반도체 장치 제조 방법.
  27. 제23항에 있어서, 상기 제2기판이 반투명이 가용성 수지 기판을 포함하는 반도체 장치 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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US5821138A (en) 1998-10-13
US6998282B1 (en) 2006-02-14
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US20080309585A1 (en) 2008-12-18
JPH08288522A (ja) 1996-11-01
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US8497509B2 (en) 2013-07-30
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US20050162578A1 (en) 2005-07-28
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US7425931B1 (en) 2008-09-16
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US6376333B1 (en) 2002-04-23
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