KR940022915A - 트랜지스터 및 그 제조방법 - Google Patents
트랜지스터 및 그 제조방법 Download PDFInfo
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- KR940022915A KR940022915A KR1019940005917A KR19940005917A KR940022915A KR 940022915 A KR940022915 A KR 940022915A KR 1019940005917 A KR1019940005917 A KR 1019940005917A KR 19940005917 A KR19940005917 A KR 19940005917A KR 940022915 A KR940022915 A KR 940022915A
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- 238000004519 manufacturing process Methods 0.000 title description 2
- 229910052782 aluminium Inorganic materials 0.000 claims abstract 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract 10
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims abstract 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract 9
- 239000010703 silicon Substances 0.000 claims abstract 9
- 239000010410 layer Substances 0.000 claims abstract 8
- 238000005530 etching Methods 0.000 claims abstract 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract 6
- 239000011229 interlayer Substances 0.000 claims abstract 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract 2
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims 13
- 239000004065 semiconductor Substances 0.000 claims 12
- 239000000758 substrate Substances 0.000 claims 7
- 239000012212 insulator Substances 0.000 claims 4
- 239000000203 mixture Substances 0.000 claims 4
- 238000007743 anodising Methods 0.000 claims 3
- 239000012535 impurity Substances 0.000 claims 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 239000002253 acid Substances 0.000 claims 1
- 230000003213 activating effect Effects 0.000 claims 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 239000010408 film Substances 0.000 abstract 1
- 238000005224 laser annealing Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 239000011259 mixed solution Substances 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
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- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명에 따른 박막 트랜지스터는 99.5% 이상의 고순도 알루미늄을 함유하는 하층과 0.5이상의 규소를 함유하는 알루미늄으로 형성한 상층을 포함하는 게이트 전극을 가진다. 이와는 달리, Ⅲa 족 원소를 Ⅲb족 원소에 첨가하여 형성한 게이트 전극도 가진다. 규소 함유 알루미늄 게이트 전극을 에칭함으로써 제조되는 잔류부는 불화수소산, 질산 및 아세트산의 혼합 용액으로 에칭된다. 접촉 구멍을 층간 절연막내에 형성한 후에, 레이저 어닐링이 수행되고 나서 금속 전극이 접촉 구멍내에 형성된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 1C도는 본 발명에 따른 TFT의 게이트 구조의 실시예의 설명도, 제3A도 내지 제3E도는 본 발명의 제1실시예에 따른 제조방법을 도시하는 단면도.
Claims (20)
- 기판상에 제공되는 반도체 막과 그 반도체 막상에 제공되는 게이트 전극을 포함하는 트랜지스터로서, 상기 게이트 전극은 반도체 막상에 제공되는 순도 99.5%이상의 알루미늄을 함유하는 하층과 그 하층상에 제공되는 알루미늄과 농도 0.5%이상인 규소를 포함하는 상층을 포함하는 것을 특징으로 하는 트랜지스터.
- 제1항에 있어서, 상기 게이트 전극의 적어도 한 측면에 제공되는 게이트 전극의 재료인 양극 산화물을 더 포함하는 것을 특징으로 하는 트랜지스터.
- 제1항에 있어서, 상층은 농도 2% 이상의 규소를 포함하는 것을 특징으로 하는 트랜지스터.
- 제1항에 있어서, 상층의 두께는 하층 두께의 5배 이상인 것을 특징으로 하는 트랜지스터.
- 아이스랜드(island)반도체 영역을 기판상에 형성하는 단계와, 절연막을 아이슬랜드 반도체 영역 위에 형성하는 단계와, 순도 99.5% 이상의 알루미늄을 함유하는 제1막을 형성하는 단계와, 알루미늄과 농도 0.5%이상의 규소를 함유하는 제2막을 제1막 위에 형성하는 단계 및, 제1 및 제2막을 패턴닝함으로써 게이트 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 제조방법.
- 제5항에 있어서, 게이트 전극 형성 단계 전에, 비결정질 규소를 함유하는 막을 제2막 위에 형성하는 단계를 더 포함하는 것을 특징으로 하는 트랜지스터 제조방법.
- 제5항에 있어서, 게이트 전극을 양극 산화하는 단계를 더 포함하는 것을 특징으로 하는 트랜지스터 제조방법.
- 제5항에 있어서, 패터닝은 인상을 사용하는 에칭에 의해 수행되는 것을 특징으로 하는 트랜지스터 제조방법.
- 아이슬랜드 반도체 영역을 기판상에 형성하는 단계와, 절연막을 아이슬랜드 반도체 영역위에 형성하는 단계 0.5% 이상의 규소를 함유하는 알루미늄 막을 절연막상에 형성하는 단계와, 알루미늄 막을 에칭함으로써 게이트 전극을 형성하는 단계 및, 상기 게이트 전극 형성 단계에 의해 제조되는 불화수소산, 절산 및 아세트산을 함유하는 혼합물에 의해 에칭되는 규소 함유 잔류부를 에칭하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 제조방법.
- 제9항에 있어서, 혼합물내의 불화수소산:질산:아세트산의 몰비가 1:100 내지 400:100 내지 300인 것을 특징으로 하는 트랜지스터 제조방법.
- 제9항에 있어서, 알루미늄 막은 2%잇앙의 규소를 함유하는 것을 특징으로 하는 트랜지스터 제조방법.
- 제9항에 있어서, 상기 잔류부 에칭 단계후에, 게이트 전극을 양극 산화하는 단계를 더 포함하는 것을 특징으로 하는 트랜지스터 제조방법.
- 제9항에 있어서, 알루미늄 막의 에칭은 인산에 의해 수행되는 것을 특징으로 하는 트랜지스터 제조방법.
- 제9항에 있어서, 상기 잔류부의 에칭은 기판을 상기 혼합물내에 침지함으로써 수행되는 것을 특징으로 하는 트랜지스터 제조방법.
- 제14항에 있어서, 상기 기판은 상기 혼합물내에 30 내지 90초 동안 침지되는 것을 특징으로 하는 트랜지스터 제조방법.
- 아이슬랜드 반도체 영역을 기판상에 형성하는 단계와 절연막을 아이슬랜드 반도체 영역위에 형성하는 단계와, 게이트 전극을 절연막상에 형성하는 단계와, 마스크로서의 게이트 전극과 함께 아이슬랜드 반도체 영역 내부로 불순물을 도입하는 단계와, 충간 절연체를 게이트 전극 위에 형성하는 단계와, 접촉 구멍을 층간 절연체를 통해 내부에 불순물이 도입되어 있는 아이슬랜드 반도체 영역부상에 형성하는 단계 및, 층간 절연체와 접촉 구멍을 통해 아이슬랜드 반도체 영역으로 광선을 조사함으로써 불순물을 활성화 하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 제조방법.
- 제16항에 있어서, 광선은 레이저 광선 또는 레이저 광선과 동등한 광선인 것을 특징으로 하는 트랜지스터 제조방법.
- 제16항에 있어서, 상기 도입 단계전에, 게이트 전극을 양극 산화하는 단계를 더 포함하는 것을 특징으로 하는 트랜지스터 제조방법.
- 제16항에 있어서, 기판은 광선을 조사중에 100 내지 450℃의 온도로 가열되는 것을 특징으로 하는 트랜지스터 제조방법.
- 제16항에 있어서, 상기 층간 절연체 형성 단계는 상기 도입 단계후에 수행되는 것을 특징으로 하는 트랜지스터 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP93-86752 | 1993-03-22 | ||
JP08675093A JP3315190B2 (ja) | 1993-03-22 | 1993-03-22 | 薄膜トランジスタの作製方法 |
JP08675293A JP3315191B2 (ja) | 1993-03-22 | 1993-03-22 | 薄膜トランジスタの作製方法 |
JP93-86751 | 1993-03-22 | ||
JP93-86750 | 1993-03-22 | ||
JP08675193A JP3396504B2 (ja) | 1993-03-22 | 1993-03-22 | 薄膜トランジスタの作製方法 |
JP5263024A JP2940653B2 (ja) | 1993-09-27 | 1993-09-27 | 半導体装置およびその作製方法 |
JP93-263024 | 1993-09-27 |
Publications (2)
Publication Number | Publication Date |
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KR940022915A true KR940022915A (ko) | 1994-10-22 |
KR0166397B1 KR0166397B1 (ko) | 1999-01-15 |
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Application Number | Title | Priority Date | Filing Date |
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KR1019940005917A KR0166397B1 (ko) | 1993-03-22 | 1994-03-22 | 트랜지스터 및 그 제조방법 |
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US (1) | US5580800A (ko) |
KR (1) | KR0166397B1 (ko) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
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KR0131179B1 (ko) * | 1993-02-22 | 1998-04-14 | 슌뻬이 야마자끼 | 전자회로 제조프로세스 |
JP3335757B2 (ja) * | 1994-03-17 | 2002-10-21 | 株式会社半導体エネルギー研究所 | 陽極酸化方法 |
US5985690A (en) * | 1995-01-30 | 1999-11-16 | Nec Corporation | Method of manufacturing contact image sensor |
JPH08250743A (ja) * | 1995-03-07 | 1996-09-27 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP3759999B2 (ja) * | 1996-07-16 | 2006-03-29 | 株式会社半導体エネルギー研究所 | 半導体装置、液晶表示装置、el装置、tvカメラ表示装置、パーソナルコンピュータ、カーナビゲーションシステム、tvプロジェクション装置及びビデオカメラ |
JPH10163501A (ja) * | 1996-11-29 | 1998-06-19 | Semiconductor Energy Lab Co Ltd | 絶縁ゲイト型トランジスタ |
US5861335A (en) | 1997-03-21 | 1999-01-19 | Advanced Micro Devices, Inc. | Semiconductor fabrication employing a post-implant anneal within a low temperature high pressure nitrogen ambient to improve channel and gate oxide reliability |
US5994156A (en) * | 1997-09-12 | 1999-11-30 | Sharp Laboratories Of America, Inc. | Method of making gate and source lines in TFT LCD panels using pure aluminum metal |
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JPH01268840A (ja) * | 1988-04-19 | 1989-10-26 | Sumitomo Metal Mining Co Ltd | 流電陽極用アルミニウム合金 |
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JP2794678B2 (ja) * | 1991-08-26 | 1998-09-10 | 株式会社 半導体エネルギー研究所 | 絶縁ゲイト型半導体装置およびその作製方法 |
JPH05152573A (ja) * | 1991-11-29 | 1993-06-18 | Nec Corp | 薄膜トランジスタ及びその製造方法 |
JPH05299655A (ja) * | 1992-04-08 | 1993-11-12 | Nec Corp | 薄膜トランジスタ |
JPH06267959A (ja) * | 1993-03-16 | 1994-09-22 | Nippon Steel Corp | 半導体装置の製造方法 |
-
1994
- 1994-03-15 US US08/213,060 patent/US5580800A/en not_active Expired - Lifetime
- 1994-03-22 KR KR1019940005917A patent/KR0166397B1/ko not_active IP Right Cessation
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KR0166397B1 (ko) | 1999-01-15 |
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