KR940006285A - 박막형 반도체 장치 및 그 제작방법 - Google Patents

박막형 반도체 장치 및 그 제작방법 Download PDF

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KR940006285A
KR940006285A KR1019930012642A KR930012642A KR940006285A KR 940006285 A KR940006285 A KR 940006285A KR 1019930012642 A KR1019930012642 A KR 1019930012642A KR 930012642 A KR930012642 A KR 930012642A KR 940006285 A KR940006285 A KR 940006285A
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film
thin film
semiconductor device
silicon
forming
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KR970010652B1 (ko
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순페이 야마자끼
장홍용
야스히코 다케무라
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순페이 야마자끼
가부시키가이샤 한도오따이 에네루기 겐큐쇼
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Abstract

절연기판상에 박막 트랜지스터(TFT)를 형성하는 공정에 있어서, 아모르퍼스 반도체 피막을 형성한 후, 레이저광에 대해서 투명한 보호피막을 형성하고, 이에 레이저 광을 조사해서 반도체 피막의 결정성을 개선시킨 후, 상기 보호피막을 제거하고 반도체 피막의 표면을 노출시켜, 새롭게 게이트 절연막이 되는 피막을 형성한 후, 게이트 전극을 형성하는 것을 특징으로 하는 박막형 반도체장치의 제작 방법 및 상기 방법에 의해 얻어진 박막형 반도장치.
또한, 절연기판상에 박막 트랜지스터(TFT)등의 반도체영역 장치를 형성한 공정에 있어서, 질화 알루미늄을 주성분으로 하는 제1피막을 형성한 후, 산화규소등을 주성분으로 하는 제2피막을 구성하고 이 기초 막상에 TFT의 반도체 장치나 회로를 형성한다.

Description

박막형 반도체 장치 및 그 제작방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 TFT의 제작방법,
제2도는 본 발명에 의한 TFT의 제작방법,
제3도는 본 발명에 의한 TFT의 제작방법.

Claims (24)

  1. 절연기판상에 반도체 피막을 형성하는 공정과, 상기 반도체 피막상에 투명한 보호피막을 형성하는 공정과, 상기 보호 피막을 제거하여 반도체 피막의 표면을 노출시키는 공정과, 상기 반도체 피막에 펄스레이저광 또는 그것과 동일한 강광(强光)을 조사함에 의해 결정화시키는 공정과, 상기 반도체 피막상에 게이트 절열막으로서 기능하는 절연피막을 형성하는 공정과, 상기 절연피막상에 금속원소를 주성분으로 하는 제1의 배선을 형성하는 공정과, 상기 제1의 배선을 주된 마스크로하여 자기 정합적으로 고속 이온을 조사하는 공정과, 상기 이온 조사후, 상기 제1의 배선을 주된 마스크로하여 펄스 레이저광 또는 그것과 동일한 강한 광을 조사하는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  2. 제1항에 있어서, 절연기판과 반도체 피막의 사이에는 질화규소 또는 산화 알루미늄 또는 질화 알루미늄을 주된 성분으로 하는 절연 피막이 형성되어 있는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  3. 제1항에 있어서, 절연기판이 소다 유리 또는 무알칼리 유리 또는 코닝 7059유리인 것을 특징으로 하는 박막형 반도체장치의 제작방법
  4. 제1항에 있어서, 제1의 배선에 전해 용액중에서 통전하는 것에 의해 양극산화막을 형성하는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  5. 제1항에 있어서, 절연기판과 반도체 피막의 사이에는 질화규소, 산화 알루미늄 및 질화 알루미늄으로 부터 선택된 재료로 이루어지는 절연피막과 산화규소막의 다층의 형성되어 있는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  6. 제5항에 있어서, 상기 질화규소 산화 알루미늄 및 질화 알루미늄으로 부터 선택된 재료로 이루어지는 절연피막은 300∼3000Å의 두께인 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  7. 제5항에 있어서, 상기 산화규소막은 300∼3000Å의 두께인 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  8. 제1항에 있어서, 상기 강광이 할로겐 적외선 램프광인 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  9. 절연기판상에 형성되고 알루미늄을 주성분으로 하는 금속재료를 게이트 전극ㆍ배선으로서 갖는 복수의 박막 트랜지스터를 갖는 액티브 매트릭스 회로에서, 상기 액티브 매트릭스부 중의 박막 트랜지스터의 활성영역은 펄스 레이저광 또는 그것과 동일한 강광이 조사되어서 결정화되고 또는 소스/드레인 영역은 P형의 도전형이며, 또한 P형 불순물 도입후 펄스 레이저광이 조사된 것을 특징으로 하는 박막형 반도체장치.
  10. 제9항에 있어서, 절연기판은 적어도 질화규소 혹은 산화 알루미늄 또는 질화 알루미늄으로 이루어지는 층을 갖는 피막에 의하여 피복된 소다 유리 또는 무알칼리 유리인 것을 특징으로 하는 박막형 반도체장치.
  11. 제7항에 있어서, 상기 강광이 할로겐 적외선 램프광인 것을 특징으로 하는 박막형 반도체장치.
  12. 절연기판상에 형성되고 알루미늄을 주성분으로 하는 금속재료를 게이트 전극 배선으로서 갖는 복수의 박막 트랜지스터를 갖는 액티브 매트릭스 회로 및 주변 구동회로를 갖는 장치에 있어서, 상기 주변 구동회로 중의 박막 트랜지스터의 활성영역은 펄스 레이저광 또는 그것과 동등한 강광이 조사된 결정성 실리콘이며, 액티브 매트릭스 회로중의 박막 트랜지스터의 활성 영역은 아모르퍼스 혹은 그것과 동등한 낮은 결정성 또는 주변회로와 비교하여 낮은 정도의 결정성을 갖는 것을 특징으로 하는 박막형 반도체장치.
  13. 절연기판상에 아모르퍼스 흑은 그것과 동등한 결정성이 낮은 실리콘막을 형성하는 공정과, 상기 실리콘막에 선택적으로 레이저광 또는 그것과 동일한 강광을 조사하는 것에 의해 상기 실리콘막 일부의 결정성을 높이는 공정과 알루미늄을 주성분으로하는 게이트 전극을 형성하는 공정과, 상기 게이트 전극을 마스크로하여 레이저 광 또는 그것과 동일한 강광을 조사하여 결정성이 높은 실리콘막을 얻는 공정을 거치는 것에 의해, 1매의 기판상에 아모르퍼스 실리 TFT와 결정성 실리콘 TFT를 동시에 얻는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  14. 제13항에 있어서, 상기 강광이 할로겐 적외선 램프광인 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  15. 절연기판상에 형성되고, 알루미늄을 주성분으로 하는 금속재료를 게이트 전극으로 하여 펄스 레이저광 또는 그것과 등등한 펄스광을 조사하는 것에 의해 얻어진 게이트 전극하의 활성층과 그것에 인접된 불순물 영역을 갖는 박막 트랜지스터를 적어도 둘을 갖는 회로에서, 상기 박막 트랜지스터는 아모르퍼스 혹은 그것과 동등한 낮은 결정성을 갖는 실리콘 반도체에 의하여 분리되어 있는 것을 특징으로 하는 박막형 반도체장치.
  16. 제15항에 있어서, 상기 동일한 펄스광이 할로겐 적외선 램프광인 것을 특징으로 하는 박막형 반도체장치.
  17. 절연기판상에 아모르퍼스 또는 그것과 동등한 결정성이 낮은 실리콘막을 형성하는 공정과, 상기 실리콘막에 선택적으로 레이저광 또는 그것과 동일한 강광을 조사하는 것에 의해 상기 실리콘막의 일부의 결정성을 높이는 공정과, 알루미늄을 주성분으로 하는 게이트 전극을 형성하는 공정과, 상기 게이트 전극 및 패터닝된 마스크재를 마스크로 하여 선택적으로 N형 또는 P형의 한쪽, 또는 쌍방의 불순물을 주입하는 공정과 상기 불순물이 주입된 영역과 실질적으로 동일영역에만 레이저광 또는 그것과 동일의 강광을 조사하여 결정성이 높은 실리콘막을 얻는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치.
  18. 제17항에 있어서, 상기 강광이 적외선 램프광인 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  19. 제18항에 있어서, 상기 레이저광 또는 상기 강광을 조사할 때에, 상기 기판을 100∼500℃에서 가열하는 것을 특징으로 하는 박막형 반도체장치의 제직방법.
  20. 절연기판상에 아모르퍼스 혹은 그것과 동등한 결정성이 낮은 실리콘막을 형성하는 공정과, 상기 실리콘막 상에 두꺼운 절연막을 형성하는 공정과, 상기 절연막을 선택적으로 에칭하여 상기 절연막이 제거된 또는 상기 절연막이 얇은 영역을 형성하는 공정과, 레이저광 또는 그것과 동일한 강광을 조사하는 것에 의하여 상기 절연막이 제거된 혹은 영역 하부의 상기 실리콘막의 결정성을 높이는 공정과, 알루미늄 주성분으로 하는 게이트 전극을 형성하는 공정과, 상기 게이트 전극 및 상기 두꺼운 절연막을 마스크로 하여 선택적으로 N형 또는 P형의 한쪽 혹은 쌍방의 불순물을 주입하는 공정과, 레이저광 또는 동일한 강광을 조사하여 상기 불순물이 주입된 영역의 활성화를 행하는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  21. 제20항에 있어서, 상기 강광이 할로겐 적외선 램프광인 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  22. 기판상에 질화 알루미늄을 주성분으로 하는 제1의 피막을 형성하는 공정과, 상기 제1의 피막상에 직접 또는 간접으로 실리콘을 주성분으로 하는 제2의 피막을 형성하는 공정과, 상기 제2의 피막상에 직접 또는 간접으로 금속 혹은 반도체의 배선을 형성하는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  23. 기판상에 질화 알루미늄 주성분으로 하는 제1의 피막과, 상기 제1의 피막상에 직접 또는 간접으로 실리콘을 주성분으로 하는 제2의 피막과, 상기 제2의 피막상에 직접 또는 간접으로 금속 혹은 반도체의 배선을 갖는 것을 특징으로 하는 박막형 반도체장치.
  24. 기판상에 산화규소막과 산화규소상에 박막 트랜지스터를 갖는 것을 특징으로 하는 박막형 반도체 장치에 있어서, 산화규소에 비하여 높은 열전도를 갖는 투광성 피막을 그 기판과 그 산화규소의 사이에 갖는 것을 특징으로 하는 박막형 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930012642A 1992-07-06 1993-07-06 박막형 반도체 장치 및 그 제작방법 KR970010652B1 (ko)

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