JP5549962B2 - メモリアレイ。 - Google Patents
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- JP5549962B2 JP5549962B2 JP2013514178A JP2013514178A JP5549962B2 JP 5549962 B2 JP5549962 B2 JP 5549962B2 JP 2013514178 A JP2013514178 A JP 2013514178A JP 2013514178 A JP2013514178 A JP 2013514178A JP 5549962 B2 JP5549962 B2 JP 5549962B2
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- 239000000463 material Substances 0.000 claims description 44
- 210000001520 comb Anatomy 0.000 claims description 21
- 239000000203 mixture Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000003491 array Methods 0.000 description 4
- 238000013500 data storage Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 150000004770 chalcogenides Chemical class 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910001245 Sb alloy Inorganic materials 0.000 description 1
- 229910001215 Te alloy Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
- G01R33/44—Arrangements or instruments for measuring magnetic variables involving magnetic resonance using nuclear magnetic resonance [NMR]
- G01R33/48—NMR imaging systems
- G01R33/58—Calibration of imaging systems, e.g. using test probes, Phantoms; Calibration objects or fiducial markers such as active or passive RF coils surrounding an MR active material
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/12—Measuring magnetic properties of articles or specimens of solids or fluids
- G01R33/1284—Spin resolved measurements; Influencing spins during measurements, e.g. in spintronics devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
- H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
- H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
- G01R33/24—Arrangements or instruments for measuring magnetic variables involving magnetic resonance for measuring direction or magnitude of magnetic fields or magnetic flux
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/10—Resistive cells; Technology aspects
- G11C2213/18—Memory cell being a nanowire having RADIAL composition
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- High Energy & Nuclear Physics (AREA)
- Semiconductor Memories (AREA)
Description
Claims (14)
- 第一の水平方向に沿って伸長する複数のグローバルビット線であって、前記複数のグローバルビット線は、第一の高度レベルにおける第一系列と、前記第一の高度レベルとは異なる第二の高度レベルにおける第二系列とを含み、前記第一系列の前記複数のグローバルビット線は、前記第二系列の前記複数のグローバルビット線と互い違いに存在する、複数のグローバルビット線と、
前記複数のグローバルビット線と垂直に伸長する複数の垂直ローカルビット線と、
前記第一の水平方向とは垂直な第二の水平方向に沿って伸長する複数のワード線であって、前記複数のワード線は、複数の垂直列と複数の水平行とを含む二次元アレイに積層され、前記ワード線アレイの前記複数の垂直列は、二つ以上のワード線を含み、前記複数の垂直ローカルビット線は、複数の垂直ローカルビット線が、前記ワード線アレイの隣接する複数の垂直列の間に存在するように、前記ワード線アレイを通って伸長する、複数のワード線と、
前記複数のワード線と前記複数の垂直ローカルビット線との直間のメモリセル材料であって、前記メモリセル材料は、ワード線/グローバルビット線の組み合わせによって一意的にアドレスされる複数のメモリセルを形成する、メモリセル材料と、
を含む、ことを特徴とするメモリアレイ。 - 前記第一系列の前記複数のグローバルビット線は、前記第二系列の前記複数のグローバルビット線とは逆の側の前記複数のワード線上に存在する、ことを特徴とする請求項1に記載のメモリアレイ。
- 前記第一系列の前記複数のグローバルビット線は、前記第二系列の前記複数のグローバルビット線の真上に存在する、ことを特徴とする請求項2に記載のメモリアレイ。
- 前記第一系列の前記複数のグローバルビット線は、前記第二系列の前記複数のグローバルビット線の真上には存在しない、ことを特徴とする請求項2に記載のメモリアレイ。
- 前記第一系列の前記複数のグローバルビット線は、前記第二系列の前記複数のグローバルビット線と共通の側の前記複数のワード線上に存在する、ことを特徴とする請求項1に記載のメモリアレイ。
- 複数のビット線コームであって、前記複数の個々のコームは、水平に伸長するグローバルビット線と、前記グローバルビット線に電気的に接続され、垂直に伸長する複数のビット線ピラーとを含み、前記複数のビット線コームは、第一系列および第二系列を含み、前記第二系列は、前記第一系列に対して垂直にオフセットされ、前記第一系列の前記複数のビット線コームは、前記第二系列の前記複数のビット線コームと互い違いになって、垂直に伸長する複数のビット線ピラーの千鳥状配列を形成し、前記水平に伸長する複数のグローバルビット線は、お互いに対して平行である、複数のビット線コームと、
前記複数のグローバルビット線に直交して伸長する複数のワード線であって、前記複数のワード線は、複数の垂直列と複数の水平行とを含む二次元アレイに積層され、前記ワード線アレイの前記複数の垂直列は、二つ以上のワード線を含み、複数のビット線ピラーが前記ワード線アレイの隣接する複数の垂直列の間にあるように、前記複数のビット線ピラーは、前記ワード線アレイを通って伸長する、複数のワード線と、
前記複数のワード線と前記複数のビット線ピラーとの直間のメモリセル材料であって、前記メモリセル材料は、ワード線/グローバルビット線の組み合わせによって一意的にアドレスされる複数のメモリセルを形成する、メモリセル材料と、
を含む、ことを特徴とするメモリアレイ。 - 前記第一系列の複数のビット線コームの前記複数の垂直ピラーは、前記複数のグローバルビット線から下方へ伸長し、前記第二系列の複数のビット線コームの前記複数の垂直ピラーは、前記複数のグローバルビット線から上方へ伸長する、ことを特徴とする請求項6に記載のメモリアレイ。
- 前記第一系列の複数のビット線コームの個々の複数のグローバルビット線は、前記第二系列の複数のビット線コームの個々の複数のグローバルビット線の真上にある、ことを特徴とする請求項7に記載のメモリアレイ。
- 前記第一系列の複数のビット線コームの個々の複数のグローバルビット線は、前記第二系列の複数のビット線コームの個々の複数のグローバルビット線の真上からオフセットされる、ことを特徴とする請求項7に記載のメモリアレイ。
- 前記第一系列および前記第二系列の複数のビット線コームの前記複数の垂直ピラーは、前記複数のグローバルビット線から上方へ伸長する、ことを特徴とする請求項6に記載のメモリアレイ。
- 前記複数のビット線コームの前記複数の垂直ピラーは、電圧の増加に対して非線形に応答する複数のアクセスデバイスを介して、前記複数のグローバルビット線に接続される、ことを特徴とする請求項6に記載のメモリアレイ。
- 前記複数のビット線コームの前記複数の垂直ピラーは、複数のオボニック閾値スイッチを介して、前記複数のグローバルビット線に接続される、ことを特徴とする請求項6に記載のメモリアレイ。
- 個々の垂直ピラーに関連付けられた複数のメモリセルの前記メモリセル材料は、前記垂直ピラーの表面に隣接していない、ことを特徴とする請求項6に記載のメモリアレイ。
- 個々の垂直ピラーに関連付けられた複数のメモリセルの前記メモリセル材料は、前記垂直ピラーの表面に隣接する、ことを特徴とする請求項6に記載のメモリアレイ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/795,565 US8289763B2 (en) | 2010-06-07 | 2010-06-07 | Memory arrays |
US12/795,565 | 2010-06-07 | ||
PCT/US2011/035601 WO2011156069A2 (en) | 2010-06-07 | 2011-05-06 | Memory arrays |
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JP2013531887A JP2013531887A (ja) | 2013-08-08 |
JP5549962B2 true JP5549962B2 (ja) | 2014-07-16 |
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JP2013514178A Expired - Fee Related JP5549962B2 (ja) | 2010-06-07 | 2011-05-06 | メモリアレイ。 |
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US (11) | US8289763B2 (ja) |
EP (1) | EP2577668B1 (ja) |
JP (1) | JP5549962B2 (ja) |
KR (1) | KR101417568B1 (ja) |
CN (1) | CN102939632B (ja) |
SG (1) | SG186189A1 (ja) |
TW (1) | TWI517304B (ja) |
WO (1) | WO2011156069A2 (ja) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8289763B2 (en) | 2010-06-07 | 2012-10-16 | Micron Technology, Inc. | Memory arrays |
CN102881317B (zh) * | 2011-07-13 | 2015-08-12 | 华邦电子股份有限公司 | 三维存储器阵列 |
US8835990B2 (en) * | 2011-08-12 | 2014-09-16 | Winbond Electronics Corp. | 3D memory array |
KR101957897B1 (ko) * | 2012-04-26 | 2019-03-13 | 에스케이하이닉스 주식회사 | 가변 저항 메모리 장치 및 그 제조 방법 |
US8841649B2 (en) * | 2012-08-31 | 2014-09-23 | Micron Technology, Inc. | Three dimensional memory array architecture |
US8729523B2 (en) * | 2012-08-31 | 2014-05-20 | Micron Technology, Inc. | Three dimensional memory array architecture |
KR20140054975A (ko) * | 2012-10-30 | 2014-05-09 | 에스케이하이닉스 주식회사 | 가변 저항 메모리 장치 |
KR20140113024A (ko) * | 2013-03-15 | 2014-09-24 | 에스케이하이닉스 주식회사 | 저항 변화 메모리 장치 및 그 구동방법 |
US9728584B2 (en) * | 2013-06-11 | 2017-08-08 | Micron Technology, Inc. | Three dimensional memory array with select device |
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